CN115904677A

CN115904677A - Memory allocation method, device, computer readable storage medium and program product

Info

Publication number: CN115904677A
Application number: CN202110932961.6A
Authority: CN
Inventors: 付新荣
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-08-13
Filing date: 2021-08-13
Publication date: 2023-04-04

Abstract

The embodiment of the disclosure provides a memory allocation method, a memory allocation device, a computer readable storage medium and a program product, and relates to the field of computers. The method comprises the following steps: determining whether the number of pages of a memory linked list corresponding to a target processor in the multiprocessor system is lower than a threshold number, wherein each processor in the multiprocessor system has a corresponding memory linked list; and submitting the work task to a work queue of the target processor if the number of pages is below the threshold number. The work tasks include: a predetermined number of pages in the memory manager are set to an available state and added to a memory linked list corresponding to the target processor. Therefore, each processor is provided with the corresponding memory linked list, so that the low efficiency caused by competitive access can be avoided, and the processing efficiency of each processor is ensured. In addition, the page is added to the memory linked list by the work tasks in the work queue, and the current process is not affected, so that the normal operation of the current process is ensured.

Description

Memory allocation method, device, computer readable storage medium and program product

Technical Field

The present disclosure relates to the field of computers, and more particularly, to a memory allocation method, apparatus, computer-readable storage medium, and program product.

Background

With the development of computer technology, operating systems have been rapidly developed and applied to various electronic products. With the help of an operating system, a large number of applications can be used. When running on an operating system, an application program needs to use a memory, so the memory allocation efficiency directly affects the experience of a user using an electronic product. However, the current memory allocation scheme is inefficient and cannot meet the actual requirements.

Disclosure of Invention

Embodiments of the present disclosure provide an efficient memory allocation scheme.

In a first aspect, a method for memory allocation is provided. The method comprises the following steps: determining whether the number of pages of a memory linked list corresponding to a target processor in a multiprocessor system is lower than a threshold number, wherein each processor in the multiprocessor system has a corresponding memory linked list; and if it is determined that the number of pages is below the threshold number, submitting the work task to a work queue of the target processor. The work tasks include: setting a predetermined number of pages in a memory manager corresponding to the multiprocessor system to an available state; and adding a predetermined number of pages of the available state to a memory linked list corresponding to the target processor.

Therefore, in the embodiment of the disclosure, each processor has a corresponding memory linked list, so that the inefficiency caused by competitive access can be avoided, and the processing efficiency of each processor is ensured. In addition, the page is added to the memory linked list by the work tasks in the work queue, so that the current process is not influenced, and the normal operation of the current process is ensured.

In some embodiments of the first aspect, further comprising: and if the current process of the target processor is determined to have the page missing exception, extracting the page from the memory linked list corresponding to the target processor to continue the current process.

Therefore, in the embodiment of the disclosure, when the current process extracts the page from the memory linked list, the page zero clearing operation is not required to be executed, so that the time of the system staying in the kernel state is shortened, the process is ensured to be recovered as soon as possible, the interruption time is shortened, and the processing efficiency is improved.

In some embodiments of the first aspect, determining whether the number of pages is below a threshold number comprises: and if the extracted page is the last page in the memory linked list corresponding to the target processor, determining that the number of the pages is lower than the threshold number.

In some embodiments of the first aspect, the threshold number is a water line value for the subject processor.

In some embodiments of the first aspect, the predetermined number of pages are set to an available state by performing a clear operation.

Therefore, in the embodiment of the disclosure, the pages in the memory linked list are all the pages which have been cleared, so that when the page fault exception occurs in the current process, the pages can be directly extracted and the process can be recovered, the interrupt time is shortened, and the processing efficiency is improved.

In some embodiments of the first aspect, the work task and the current process of the target processor are executed asynchronously.

Therefore, the work tasks in the work queue asynchronously add the cleared pages into the memory linked list, so that the current process is not affected, and the normal operation of the current process is ensured.

In a second aspect, a memory allocation apparatus is provided. The device includes: a determining module configured to determine whether a number of pages of a memory linked list corresponding to a target processor in a multiprocessor system, each processor in the multiprocessor system having a corresponding memory linked list, is below a threshold number; and a task submission module configured to submit the work task to a work queue of the target processor if the number of pages is determined to be below the threshold number. The work tasks include: setting a predetermined number of pages in a memory manager corresponding to the multiprocessor system to an available state; and adding a predetermined number of pages of the available state to a memory linked list corresponding to the target processor.

In some embodiments of the second aspect, further comprising a page extraction module configured to: and if the current process of the target processor is determined to have the page missing exception, extracting the page from the memory linked list corresponding to the target processor to continue the current process.

In some embodiments of the second aspect, the determination module is configured to: and if the extracted page is the last page in the memory linked list corresponding to the target processor, determining that the number of the pages is lower than the threshold number.

In some embodiments of the second aspect, the threshold number is a water line value for the target processor.

In some embodiments of the second aspect, the predetermined number of pages are set to an available state by performing a clear operation.

In some embodiments of the second aspect, the work task and the current process of the target processor are executed asynchronously.

In a third aspect, there is provided a computing device comprising a processor and a memory, the memory having stored thereon instructions for execution by the processor, the instructions when executed by the processor causing the computing device to carry out the operations of the method of the first aspect or any embodiment thereof.

In a fourth aspect, there is provided a computer-readable storage medium having stored thereon computer-executable instructions that, when executed by a processor, carry out operations according to the method of the first aspect above or any embodiment thereof.

In a fifth aspect, a chip or chip system is provided. The chip or chip system comprises processing circuitry configured to perform operations according to the method of the first aspect described above or any embodiment thereof.

In a sixth aspect, a computer program or computer program product is provided. The computer program or computer program product is tangibly stored on a computer-readable medium and comprises computer-executable instructions that, when executed, implement the operations according to the method of the first aspect described above or any embodiment thereof.

Drawings

The above and other features, advantages and aspects of various embodiments of the present disclosure will become more apparent by referring to the following detailed description when taken in conjunction with the accompanying drawings. The same or similar reference numbers in the drawings identify the same or similar elements, of which:

FIG. 1 illustrates a schematic diagram of an example environment in which embodiments of the present disclosure may be implemented;

FIG. 2 illustrates a schematic diagram of a multiprocessor system in which embodiments of the present disclosure may be implemented;

FIG. 3 shows a schematic flow chart diagram of a process of memory allocation according to an embodiment of the present disclosure;

FIG. 4 shows a schematic flow chart diagram of the operational procedures required to be performed by a work task according to an embodiment of the present disclosure;

FIG. 5 shows a schematic block diagram of a memory allocation apparatus according to an embodiment of the present disclosure; and

FIG. 6 illustrates a schematic block diagram of an example device that can be used to implement embodiments of the present disclosure.

Detailed Description

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure are shown in the drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the disclosure are for illustration purposes only and are not intended to limit the scope of the disclosure.

In describing embodiments of the present disclosure, the terms "include" and its derivatives should be interpreted as being inclusive, i.e., "including but not limited to. The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first," "second," and the like may refer to different or the same object. Other explicit and implicit definitions are also possible below.

Memory management is one of the core subsystems of an operating system, and the performance experience of the whole product is directly influenced by the memory allocation efficiency. Anonymous page memory is the main form of memory used by Applications (APPs), and the distribution efficiency directly affects the operating efficiency of all applications running on an operating system.

In view of this, embodiments of the present disclosure provide a memory allocation scheme, which can improve the efficiency of memory allocation. Embodiments of the present disclosure are directed to a multiprocessor system in which each processor has a corresponding memory linked list, each memory linked list including one or more pages. It should be understood that in the context of the present disclosure, the term "page" may also be referred to as a memory page or a physical page, etc., to which the present disclosure is not limited.

FIG. 1 illustrates a schematic diagram of an example environment 100 in which embodiments of the present disclosure may be implemented. The environment 100 may be implemented, for example, by a computing device running a computer program, comprising essentially three levels: a hardware layer 110, an operating system layer 130, and an application layer 150.

The hardware layer 110 includes a processing unit 111, a memory 112, a storage device 113, an Input/Output (I/O) device 114, and a display 115. The processing unit 111 may have one or more processors, and the processing unit 111 executes codes or instructions of a computer program loaded from the memory 112. The memory 112 stores resources required for the computer to run, including, for example, assembly code, variables, heap, stack, and the like, which are obtained by compiling a computer program. Depending on the environment, the assembly code is assembly code that may be an architecture such as an Advanced Reduced Instruction Set Computing Machine (Advanced RISC (Reduced Instruction Set Computing) Machine, ARM), x86, microprocessor with Interlocked Pipelined Microprocessors (MIPS), or various variants thereof. The storage device 113 may be used for persistent storage of data. Input/output (I/O) devices may include, for example, a mouse, a keyboard, a Universal Serial Bus (USB) device, and the like. Display 115 may be used to present program execution results or other information related to the program to a user. It should be understood that hardware layer 110 may include more or fewer hardware devices described above, as well as other hardware devices not described herein, and the like.

The operating system layer 130 interfaces between the hardware layer 110 and the application layer 150, providing an interface for user interaction with the hardware. The application layer 150 may access various modules in the operating system through a system call interface 151. The operating system layer 130 includes a software support layer 121, a function implementation layer 133, and a kernel subsystem 141. The software support layer 121 includes an architecture module 122, a memory manager 126, a file system 127, a block device management 128, a character device management 129, a network subsystem 131, and a network interface 132. The functional implementation layer 133 includes multitasking 134, virtual memory 135, file/directory 136, tty/device access 137, and interconnectivity 138. The kernel subsystem 141 includes process management 141, memory management 142, file system 143, device control, network 145, and the like. It should be understood that operating system layer 130 may include more or fewer modules described above, as well as other modules not described herein, and the like.

The processing unit 111 in fig. 1 may be implemented as a multiprocessor system. The multiprocessor system includes a plurality of processors, all the processors in the multiprocessor system share hardware devices such as a memory, and the entire hardware system including the multiprocessor system and the shared hardware devices is controlled by a unified operating system. The Processor in the embodiments of the present disclosure may include one or more of a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a Digital Signal Processor (DSP), and the like. For simplicity of description, a multi-processor system is described as an example of a multi-CPU system.

FIG. 2 illustrates a schematic diagram of a multiprocessor system 200 in which embodiments of the present disclosure may be implemented. Fig. 2 shows a first CPU 210 and a second CPU 220, a first PCP (per _ CPU _ pages) memory allocator 212 corresponding to the first CPU 210 and a second PCP memory allocator 222 corresponding to the second CPU 220, and a memory manager 230.

The memory manager 230 may be used to manage physical memory, the memory manager 230 includes a plurality of free _ area linked lists, and the memory manager 230 may also be referred to as a partner system.

A first PCP memory allocator 212 may be configured to allocate pages for corresponding CPUs 210 and a second PCP memory allocator 222 may be configured to allocate pages for corresponding CPUs 220. The first PCP memory allocator 212 may have a linked list of a plurality of different allocation functions. Similarly, the second PCP memory allocator 222 may have a number of linked lists of different allocation functions. Pages are included in the linked list and come from memory manager 230.

As shown in fig. 2, first PCP Memory Allocator 212 includes an unmovable linked list 2121, a movable linked list 2122, a recyclable linked list 2123, a Continuous Memory Allocator (CMA) linked list 2124, and a pre-cleared linked list 2125. Second PCP memory allocator 222 includes an unmovable linked list 2221, a movable linked list 2222, a recyclable linked list 2223, a CMA linked list 2224, and a pre-clear linked list 2225.

As shown in fig. 2, the pre-clear linked list 2125 corresponds to the first CPU 210, and the pre-clear linked list 2225 corresponds to the second CPU 220, that is, a single pre-clear linked list is not shared by a plurality of different CPUs, so that inefficiency caused by contention access can be avoided.

It should be noted that although only 2 CPUs are shown in FIG. 2, embodiments of the present disclosure are not so limited, e.g., a multiprocessor system may include a greater number of CPUs. In addition, the linked list included in the PCP memory allocator in fig. 2 is only an exemplary one, and a greater or lesser number of linked lists may be included in an actual scenario, which is not limited in this disclosure.

The scheme of memory allocation in the embodiments of the present disclosure will be described below in conjunction with fig. 2, and for the sake of brevity, the following description is made only for a single processor (target processor) in a multiprocessor system, it being understood that the memory allocation scheme for any one processor is similar.

Fig. 3 shows a schematic flow diagram of a process 300 of memory allocation according to an embodiment of the present disclosure. Process 300 may be performed by a computing device implementing environment 100 as shown in fig. 1, and process 300 may be directed to memory allocation for any of the CPUs in multiprocessor system 200 as shown in fig. 2.

At block 310, a determination is made whether the number of pages of a memory linked list corresponding to a target processor in the multiprocessor system is below a threshold number.

As described in connection with fig. 2, each processor in a multiprocessor system may have a corresponding memory linked list for storing pages. The memory linked list may be preprocessed, for example, implemented as a pre-clear linked list.

The target processor refers to a processor, such as the first CPU 210 shown in fig. 2, among the plurality of processors of the multiprocessor system, for which memory is to be allocated.

In some embodiments, the memory linked list corresponding to the target processor may be a pre-cleared linked list of the target CPU. Referring to fig. 2, assuming that the target processor is the first CPU 210, the memory linked list is the pre-clear linked list 2125 in the first PCP memory allocator 212 corresponding to the first CPU 210.

The determination at block 310 may be performed in a periodic manner or an event-triggered manner. For example, the number of pages of the memory linked list corresponding to the target processor may be determined periodically at preset time intervals. For example, the number of pages of the memory linked list corresponding to the target processor may be determined based on a trigger for a fetch operation of the pages in the memory linked list.

Illustratively, if the current process of the target processor has a page fault exception, the page can be extracted from the memory linked list corresponding to the target processor to continue the current process. A page fault exception (page fault) may also be referred to as a page miss, a page fault, a page seek miss, a page fault, a hard interrupt, a page fault interrupt, etc., which is not limited by this disclosure.

Specifically, the system may be in a user state and run the current process, when a page fault exception occurs, the system may be converted into a kernel state, and extract one page from a memory linked list corresponding to the target processor, and then the system may be converted into the user state again to continue executing the current process.

Taking Linux system as an example, the user mode may also be referred to as user space, which provides a space for running the application program, so that the application program can access resources managed by the kernel, such as CPU, memory, and the like. The kernel state, which may also be referred to as a kernel space, controls hardware resources of the computing device, such as coordinating CPU resources, allocating memory resources, etc., and may provide a stable environment for the application to run.

In some embodiments, after one page in the memory linked list is fetched, it may be determined whether the number of pages of the memory linked list after the page fetch is below a threshold number. The threshold number may be a preset positive integer.

And if the extracted page is the last page in the memory linked list, determining that the number of the pages in the memory linked list is lower than the threshold number. In other words, if there are no more pages in the memory linked list after a page fetch, the number of pages is determined to be below the threshold number. That is, by page fetching, the last page in the memory linked list is allocated, so that the number of pages in the memory linked list after page fetching is 0.

In some embodiments, the threshold number may be a watermark value (watermark) for the target processor. Illustratively, a water line value may be set when designing a PCP memory allocator for the target processor. The waterline value may be a LOW waterline (WMARK _ LOW) or a minimum waterline (WMARK _ MIN), which is not limited by this disclosure.

At block 320, if it is determined that the number of pages is below the threshold number, a work task is submitted to the work queue of the target processor, the work task including: setting a predetermined number of pages in a memory manager corresponding to the multiprocessor system to an available state; and adding a predetermined number of pages of the available state to a memory linked list corresponding to the target processor.

That is, when the job task is executed, a predetermined number of pages in the memory manager can be caused to be set to an available state, and the predetermined number of pages of the available state can be added to the memory linked list corresponding to the target processor.

It should be understood that embodiments of the present disclosure are not limited to a particular number of values, and in some embodiments, the predetermined number depends on the chunk (chunk) or batch (batch) set for the PCP memory allocator corresponding to the target processor. For example, in conjunction with FIG. 2, if the target processor is the first CPU 210 and the lot set for the first PCP memory allocator 212 is equal to 31, then the predetermined number may be equal to 31.

In some embodiments, a predetermined number of pages may be set to an available state by performing a clear operation. FIG. 4 shows a schematic flow chart diagram of an operational procedure 400 required for the performance of a work task in accordance with an embodiment of the present disclosure.

At block 410, a predetermined number of pages are retrieved from the memory manager. For example, in connection with the example shown in fig. 2, 31 pages may be obtained from the memory manager 130.

At block 420, a predetermined number of pages are cleared. With continued reference to fig. 2, for example, a clear operation may be performed for the 31 pages retrieved from the memory manager 130.

At block 430, the cleared predetermined number of pages is added to the memory linked list corresponding to the target processor. In some embodiments, assuming the target processor is the first CPU 210, then the cleared 31 pages may be added to the pre-cleared linked list 2125.

Thus, through the process 400, the work task may be executed with the pre-cleared pages added to the memory linked list. After that, when the process of the target processor extracts the page from the memory chain table, the zero clearing operation is not required to be executed.

In embodiments of the present disclosure, work tasks in the work queue are executed asynchronously with the current process of the target processor. That is, the process 400 executed by the work tasks in the work queue is asynchronous with respect to the current process, so that the current process is not affected and normal operation of the current process is ensured.

If the current process of the target processor is in page fault exception, the page can be extracted from the memory linked list corresponding to the target processor, and then the current process can be continued. Specifically, the system is in a user mode and runs the current process, when a page fault abnormality occurs, the system can be switched to a kernel mode, one page is extracted from a memory linked list corresponding to the target processor, and then the system can be switched to the user mode again to continue to execute the current process. It can be seen that, since the zero-cleared pages are added to the memory linked list corresponding to the target processor by the job tasks in the job queue through the execution process 400, no page zero-clearing operation needs to be executed when the current process running on the system extracts the pages from the memory linked list, so that the time of the system staying in the kernel state is shortened, the process is ensured to be recovered as soon as possible, the interruption time is shortened, and the processing efficiency is improved.

Fig. 5 shows a schematic block diagram of a memory allocation arrangement 500 according to an embodiment of the present disclosure. The apparatus 500 may be implemented by software, hardware or a combination of both. In some embodiments, apparatus 500 may be a software or hardware apparatus to implement some or all of the functionality in environment 100 shown in FIG. 1 or multiprocessor system 200 shown in FIG. 2.

As shown in FIG. 5, the apparatus 500 includes a determination module 510 and a task submission module 520. Optionally, the apparatus 500 may further include a page extraction module 530.

The determining module 510 may be configured to determine whether a number of pages of a memory linked list corresponding to a target processor in the multiprocessor system, each processor in the multiprocessor system having a corresponding memory linked list, is below a threshold number. The task submission module 520 may be configured to submit the work task to the work queue of the target processor if the number of pages is determined to be below the threshold number. The work tasks include: setting a predetermined number of pages in a memory manager corresponding to the multiprocessor system to an available state; and adding a predetermined number of pages of the available state to a memory linked list corresponding to the target processor.

The page extraction module 530 may be configured to: and if the current process of the target processor is determined to have the page missing exception, extracting the page from the memory linked list corresponding to the target processor to continue the current process.

In some embodiments, the determination module 510 may be configured to: and if the extracted page is the last page in the memory linked list corresponding to the target processor, determining that the number of the pages is lower than the threshold number.

The specific value of the threshold number is not limited in the embodiments of the present disclosure. For example, the threshold number may be a water line value for the target processor.

A page of available status may refer to a page that is cleared to zero. Accordingly, the predetermined number of pages may be set to an available state by performing a clear operation.

It is understood that the work task and the current process of the target processor are executed asynchronously. That is, after submitting a work task to the work queue, the work task may not be executed immediately, which can ensure the processing effect of the current process.

In some embodiments, the apparatus 500 may include an acquisition unit, a clearing unit, and an addition unit to perform the aforementioned work tasks. The acquisition unit is configured to acquire a predetermined number of pages from the memory manager, the clearing unit is configured to clear the acquired predetermined number of pages, and the adding unit is configured to add the cleared predetermined number of pages to a memory linked list corresponding to the target processor.

In the embodiments of the present disclosure, division of a module or a unit is schematic, and is only a logical function division, and in actual implementation, there may be another division manner, and in addition, each functional unit in the embodiments of the present disclosure may be integrated in one unit, may also exist alone physically, or may also be integrated in one unit by two or more units. The integrated unit may be implemented in the form of hardware, or may also be implemented in the form of a software functional unit.

The apparatus 500 in fig. 5 can be used to implement the processes described above in conjunction with fig. 3 to 4, and for brevity, will not be described again here.

Fig. 6 illustrates a schematic block diagram of an example device 600 that can be used to implement embodiments of the present disclosure. The device 600 may be implemented as or included in the environment 100 of fig. 1.

As shown, the device 600 includes a Central Processing Unit (CPU) 601, a Read-Only Memory (ROM) 602, and a Random Access Memory (RAM) 603. The CPU 601 may perform various appropriate actions and processes according to computer program instructions stored in the RAM 602 and/or the RAM 603 or computer program instructions loaded from the storage unit 608 into the ROM 602 and/or the RAM 603. In the ROM 602 and/or RAM 603, various programs and data required for the operation of the device 600 can also be stored. The CPU 601 and the ROM 602 and/or the RAM 603 are connected to each other via a bus 604. An input/output (I/O) interface 605 is also connected to bus 604.

A number of components in the device 600 are connected to the I/O interface 605, including: an input unit 606 such as a keyboard, a mouse, and the like; an output unit 607 such as various types of displays, speakers, and the like; a storage unit 608, such as a magnetic disk, optical disk, or the like; and a communication unit 609 such as a network card, modem, wireless communication transceiver, etc. The communication unit 609 allows the device 600 to exchange information/data with other devices via a computer network such as the internet and/or various telecommunication networks.

CPU 601 may be a variety of general and/or special purpose processing components with processing and computing capabilities. Some examples that may be implemented include, but are not limited to, graphics Processing Units (GPUs), various specialized Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital Signal Processors (DSPs), and any suitable processors, controllers, microcontrollers, etc., which may be referred to as computing units accordingly. CPU 601 performs the various methods and processes described above, such as process 300 or process 400. For example, in some embodiments, process 300 or process 400 may be implemented as a computer software program tangibly embodied in a computer-readable medium, such as storage unit 608. In some embodiments, part or all of a computer program may be loaded onto and/or installed onto device 600 via ROM 602 and/or RAM 603 and/or communication unit 609. When the computer program is loaded into ROM 602 and/or RAM 603 and executed by CPU 601, one or more steps of the process described above may be performed. Alternatively, in other embodiments, CPU 601 may be configured to perform

processes

300 or 400 in any other suitable manner (e.g., by way of firmware).

Illustratively, the apparatus 600 in fig. 6 may be implemented as a computing device, or may be implemented as a chip or chip system in a computing device, to which embodiments of the present disclosure are not limited.

Embodiments of the present disclosure also provide a computing device comprising a memory and a multiprocessor system. Each processor system in the multiprocessor system has a corresponding memory linked list, and the memory linked list includes at least a threshold number of pages that have been cleared. The memory has stored therein computer instructions or a computer program. The memory allocation method described in the foregoing embodiments can be implemented when computer instructions or a computer program in the memory are executed.

Embodiments of the present disclosure also provide a chip that may include an input interface, an output interface, and a processing circuit. In the embodiment of the present disclosure, the interaction of signaling or data can be completed by the input interface and the output interface, and the generation and processing of signaling or data information can be completed by the processing circuit.

Embodiments of the present disclosure also provide a chip system including a processor for supporting a computing device to implement the functions recited in any of the above embodiments. In one possible design, the system on chip may further include a memory for storing necessary program instructions and data, which when executed by the processor, cause the device on which the system on chip is installed to implement the method as claimed in any of the above embodiments. Illustratively, the chip system may be composed of one or more chips, and may also include chips and other discrete devices.

Embodiments of the present disclosure also provide a processor coupled with a memory, the memory storing instructions that, when executed by the processor, cause the processor to perform the methods and functions recited in any of the above embodiments.

Embodiments of the present disclosure also provide a computer program product containing instructions which, when run on a computer, cause the computer to perform the methods and functions referred to in any of the embodiments described above.

Embodiments of the present disclosure also provide a computer-readable storage medium having stored thereon computer instructions, which, when executed by a processor, cause the processor to perform the methods and functions recited in any of the above embodiments.

In general, the various embodiments of the disclosure may be implemented in hardware or special purpose circuits, software, logic or any combination thereof. Some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software, which may be executed by a controller, microprocessor or other computing device. While various aspects of the embodiments of the disclosure are illustrated and described as block diagrams, flow charts, or using some other pictorial representation, it is well understood that the blocks, apparatus, systems, techniques or methods described herein may be implemented in, as non-limiting examples, hardware, software, firmware, special purpose circuits or logic, general purpose hardware or controller or other computing devices, or some combination thereof.

The present disclosure also provides at least one computer program product tangibly stored on a non-transitory computer-readable storage medium. The computer program product comprises computer executable instructions, such as instructions included in program modules, which are executed in a device on a real or virtual processor of the target to perform the processes/methods as described above with reference to the figures. Generally, program modules include routines, programs, libraries, objects, classes, components, data structures, etc. that perform particular tasks or implement particular abstract data types. In various embodiments, the functionality of the program modules may be combined or split between program modules as desired. Machine-executable instructions for program modules may be executed within local or distributed devices. In a distributed facility, program modules may be located in both local and remote memory storage media.

Computer program code for implementing the methods of the present disclosure may be written in one or more programming languages. These computer program code may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the program code, when executed by the computer or other programmable data processing apparatus, causes the functions/acts specified in the flowchart and/or block diagram to be performed. The program code may execute entirely on the computer, partly on the computer, as a stand-alone software package, partly on the computer and partly on a remote computer or entirely on the remote computer or server.

In the context of the present disclosure, computer program code or related data may be carried by any suitable carrier to enable a device, apparatus or processor to perform various processes and operations described above. Examples of a carrier include a signal, computer readable medium, and so forth. Examples of signals may include electrical, optical, radio, acoustic, or other forms of propagated signals, such as carrier waves, infrared signals, and the like.

The computer readable medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination thereof. More detailed examples of a computer-readable storage medium include an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical storage device, a magnetic storage device, or any suitable combination thereof.

Further, while the operations of the methods of the present disclosure are depicted in the drawings in a particular order, this does not require or imply that these operations must be performed in this particular order, or that all of the illustrated operations must be performed, to achieve desirable results. Rather, the steps depicted in the flowcharts may change the order of execution. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions. It should also be noted that the features and functions of two or more devices according to the present disclosure may be embodied in one device. Conversely, the features and functions of one apparatus described above may be further divided into embodiments by a plurality of apparatuses.

The foregoing has described implementations of the present disclosure, and the above description is illustrative, not exhaustive, and not limited to the implementations disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described implementations. The terminology used herein was chosen in order to best explain the principles of various implementations, the practical application, or improvements to the technology in the marketplace, or to enable others of ordinary skill in the art to understand various implementations disclosed herein.

Claims

1. A memory allocation method comprises the following steps:

determining whether a page number of a memory linked list corresponding to a target processor in a multiprocessor system is lower than a threshold number, each processor in the multiprocessor system having a corresponding memory linked list; and

if the number of pages is determined to be lower than the threshold number, submitting a work task to a work queue of the target processor, wherein the work task comprises:

setting a predetermined number of pages in a memory manager corresponding to the multiprocessor system to an available state; and

adding the predetermined number of pages of the available state to a memory linked list corresponding to the target processor.

2. The method of claim 1, further comprising:

and if the current process of the target processor is determined to have the page missing exception, extracting the page from the memory linked list corresponding to the target processor to continue the current process.

3. The method of claim 2, wherein determining whether the number of pages is below a threshold number comprises:

and if the extracted page is the last page in the memory linked list corresponding to the target processor, determining that the number of the pages is lower than the threshold number.

4. The method of claim 1 or 2, wherein the threshold number is a water line value for the target processor.

5. The method according to any one of claims 1 to 4, wherein the predetermined number of pages are set to an available state by performing a clear operation.

6. The method of any of claims 1-5, wherein the work task and a current process of the target processor are executed asynchronously.

7. A memory allocation apparatus, comprising:

a determining module configured to determine whether a number of pages of a memory linked list corresponding to a target processor in a multiprocessor system is below a threshold number, each processor in the multiprocessor system having a corresponding memory linked list; and

a task submission module configured to submit a work task to a work queue of the target processor if it is determined that the number of pages is below the threshold number, the work task comprising:

8. The apparatus of claim 7, further comprising a page extraction module configured to:

and if the current process of the target processor is determined to have a page fault exception, extracting pages from a memory linked list corresponding to the target processor to continue the current process.

9. The method of claim 8, wherein the determination module is configured to:

10. The apparatus of claim 7 or 8, wherein the threshold number is a water line value for the target processor.

11. The apparatus according to any one of claims 7 to 11, wherein the predetermined number of pages are set to an available state by performing a clear operation.

12. The apparatus of any of claims 7 to 12, wherein the work task and a current process of the target processor are executed asynchronously.

13. A computer-readable storage medium storing computer-executable instructions that, when executed by a processor, implement the method of any one of claims 1 to 6.

14. A computer program product having computer-executable instructions embodied thereon that, when executed, implement the method of any one of claims 1 to 6.