KR102563648B1 - Multi-processor system and method of operating the same - Google Patents

Abstract

A multiprocessor system includes a plurality of processors, a scheduler and a selector. The plurality of processors are each included in at least one of three or more domains defined according to a hierarchical domain structure. A scheduler receives and manages at least one task performed by a plurality of processors. When at least one task is received, the selector allocates at least one task by selecting one of a plurality of domains based on the states of the plurality of domains, and the state of processors included in the selected domain among the plurality of processors. At least one processor is selected based on and assigned at least one task.

Description

Multi-processor system and its driving method {MULTI-PROCESSOR SYSTEM AND METHOD OF OPERATING THE SAME}

The present invention relates to a computing system, and more particularly, to a multi-processor system including a plurality of processors and a method for driving the multi-processor system.

An operating system (OS) executed in a computing system serves to manage all hardware resources and software resources in the computing system. In order to complete a series of tasks, the OS manages a processing sequence between tasks and resources required for the tasks, and a processor such as a central processing unit (CPU) processes most of the tasks occurring in the OS. Recently, as the performance of a computing system has improved, a computing system including a plurality of processors or processor cores has been developed, and various methods capable of optimizing the performance and power consumption of the plurality of processors or processor cores have been studied. there is.

One object of the present invention is to provide a multi-processor system capable of efficiently managing performance and power consumption of a plurality of processors.

Another object of the present invention is to provide a method for driving a multi-processor system capable of efficiently managing performance and power consumption of a plurality of processors.

In order to achieve the above object, a multi-processor system according to embodiments of the present invention includes a plurality of processors, a scheduler, and a selector. Each of the plurality of processors is included in at least one of three or more domains defined according to a hierarchical domain structure. The scheduler receives and manages at least one task performed by the plurality of processors. When the at least one task is received, the selector allocates the at least one task by selecting one of the plurality of domains based on the state of the plurality of domains, and the selected one of the plurality of processors. At least one processor is selected based on states of processors included in the domain and assigned to the at least one task.

In order to achieve the above other object, in a method for driving a multi-processor system including a plurality of processors according to embodiments of the present invention, at least three or more of a plurality of domains defined according to a hierarchical domain structure. When at least one task performed by the plurality of processors each included in one is received, one of the plurality of domains is selected based on the state of the plurality of domains, and the at least one task is received. assign tasks Among the plurality of processors, at least one processor is selected based on states of processors included in the selected domain, and the at least one task is assigned.

In the multi-processor system and method of driving the same according to the embodiments of the present invention as described above, a plurality of domains of three or more are defined according to a hierarchical domain structure, and a received task is processed in two stages by using a task packing algorithm. By assigning specific domains and specific processors, tasks performed by a plurality of processors can be efficiently scheduled and managed. Accordingly, performance and power consumption can be efficiently managed in a multi-cluster environment having various characteristics, and power consumption can be reduced while performance of a multi-processor system is improved.

1 is a flowchart illustrating a method of driving a multi-processor system according to embodiments of the present invention.
2 is a block diagram illustrating a multi-processor system according to embodiments of the present invention.
FIG. 3 is a flowchart illustrating an example of a step of defining the hierarchical domain structure of FIG. 1 .
4a, 4b, 4c, 5a and 5b are diagrams for explaining an operation of defining the hierarchical domain structure of FIG. 3 .
6 and 7 are flowcharts illustrating an example of selecting one domain of FIG. 1 and allocating at least one task.
8 and 9 are flowcharts illustrating examples of selecting at least one processor of FIG. 1 and allocating at least one task.
10A, 10B, 11 and 12 are diagrams illustrating performance of a multi-processor system and a method for driving the same according to embodiments of the present invention.
13 and 14 are flowcharts illustrating a method of driving a multi-processor system according to embodiments of the present invention.
15 is a block diagram illustrating a multi-core processing device according to embodiments of the present invention.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in more detail. The same reference numerals are used for the same components in the drawings, and redundant descriptions of the same components are omitted.

1 is a flowchart illustrating a method of driving a multi-processor system according to embodiments of the present invention.

Referring to FIG. 1 , in a method of driving a multi-processor system according to embodiments of the present invention, first information representing characteristics of a plurality of processors included in the multi-processor system and a plurality of domains of three or more Based on the second information for , a hierarchical domain structure may be defined such that each of the plurality of processors is included in at least one domain (step S100). The structure of the multi-processor system and the hierarchical domain structure will be described later in detail with reference to FIG. 2 and the like.

At least one task performed by the plurality of processors may be received (step S200). An application or program such as a video, game, web browser, etc. executed on an operating system (OS) is called a process, and dividing such a process into schedulable units is called a task. In other words, one process includes a series of tasks, and at least one of the series of tasks may be received in step S200.

When the at least one task is received, one of the plurality of domains is selected based on the state of the plurality of domains and the at least one task is allocated (step S300). In other words, one domain for performing the at least one task may be determined first.

After the at least one task is received and one domain for performing the at least one task is selected, selecting at least one processor based on the state of processors included in the selected domain among the plurality of processors The at least one task is assigned (step S400). In other words, the at least one processor for performing the at least one task may be determined within the selected domain.

The at least one task may be performed by the selected domain and the selected at least one processor (step S500). The at least one task performed by the plurality of processors may be efficiently scheduled and managed using the hierarchical domain structure and the two-step task allocation of steps S300 and S400. The operations of steps S300 and S400 may be referred to as a task allocation algorithm or a task packing algorithm.

Depending on the embodiment, step S100 may be omitted. In this case, the hierarchical domain structure may be predefined, and steps S200, S300, S400, and S500 may be performed by loading the predefined hierarchical domain structure and using it.

2 is a block diagram illustrating a multi-processor system according to embodiments of the present invention.

Referring to FIG. 2, the multi-processor system 100 includes a plurality of processors P1, P2, P3, P4, P5, P6, ..., P(N-1), PN), a scheduler 120 ) and a selector 130. The multi-processor system 100 may further include a plurality of clusters CLU1, CLU2, ..., CLUM, a domain definer 110, and a memory 140.

A plurality of processors (P1, P2, P3, P4, P5, P6, ..., P(N-1), PN) execute various functions, such as specific calculations or tasks. In one embodiment, each of the plurality of processors (P1, P2, P3, P4, P5, P6, ..., P(N-1), PN) may include a central processing unit (CPU), a microprocessor, and the like. can In another embodiment, each of the plurality of processors (P1, P2, P3, P4, P5, P6, ..., P (N-1), PN) is a graphic processing unit (GPU), an image signal processor (ISP) , a digital signal processor (DSP), a display processor, a communication processor, a multimedia processor, and the like.

Each of the plurality of processors (P1, P2, P3, P4, P5, P6, ..., P (N-1), PN) is a plurality of clusters (CLU1, CLU2, ..., CLUM) can be included in either. For example, in FIG. 2 , N (N is a natural number greater than or equal to 3) processors and M (M is a natural number greater than or equal to 3) clusters are shown, and the processors P1, P2, P3, and P4 are a first cluster CLU1. ), the processors P5 and P6 are included in the second cluster CLU2, and the processors P(N−1) and PN are included in the Mth cluster CLUM.

A plurality of clusters (CLU1, CLU2, ..., CLUM) may be hardware- and physically separated from each other, and one cluster forms one power domain that is hardware- and physically-connected to individually power You can control it. For example, the first cluster CLU1 forms a first power domain, and the processors P1, P2, P3, and P4 may belong to the first power domain. The second cluster CLU2 forms a second power domain physically separated from the first power domain, and the processors P5 and P6 are physically separated from the processors P1, P2, P3, and P4. It may belong to the second power domain. In other words, the plurality of clusters (CLU1, CLU2, ..., CLUM) or the power domains may represent a physical division of processors.

In one embodiment, one cluster includes at least one processor, and accordingly, the number of the plurality of clusters (CLU1, CLU2, ..., CLUM) is a plurality of processors (P1, P2, P3, P4, It may be smaller than or equal to the number of P5, P6, ..., P(N-1), PN) (ie, M≤N).

Meanwhile, although not shown, each of the plurality of processors (P1, P2, P3, P4, P5, P6, ..., P(N-1), PN) may include an L1 (level 1) cache, Each of the plurality of clusters (CLU1, CLU2, ..., CLUM) may include a level 2 (L2) cache. In this case, the multi-processor system 100 may further include a component for managing caches such as a cache coherent interface (not shown).

Each of the plurality of processors P1, P2, P3, P4, P5, P6, ..., P(N-1), PN includes three or more plurality of domains DM1, defined according to a hierarchical domain structure. DM2, ..., DMK) are each included in at least one. For example, in FIG. 2 , K domains (where K is a natural number equal to or greater than 3) are shown. In the K domains, the second domain DM2 includes the first domain DM1 and the Kth domain DMK includes the remaining domains. It may be hierarchically configured to include DM1 and DM2. Also, as shown by thick dotted lines in FIG. 2 , the processors P1 , P2 , P3 , and P4 are included in the first domain DM1 , and the processors P5 and P6 correspond to the second domain DM2 . And, the processors P(N-1) and PN may configure and define the hierarchical domain structure to correspond to the K-th domain DMK.

Unlike the plurality of clusters (CLU1, CLU2, ..., CLUM) or the power domains, the plurality of domains (DM1, DM2, ..., DMK) are a plurality of processors (P1, P2, P3, P4 , P5, P6, ..., P(N-1), PN) may represent functional/conceptual divisions for processors to suit the processes and/or tasks performed by them. In other words, in the present specification, the plurality of domains (DM1, DM2, ..., DMK) defined according to the hierarchical domain structure are concepts distinct from power domains, and may be referred to as work domains, processor domains, and the like. .

In one embodiment, one domain includes at least one processor, and accordingly, the number of the plurality of domains (DM1, DM2, ..., DMK) is a plurality of processors (P1, P2, P3, P4, It may be less than or equal to the number of P5, P6, ..., P(N-1), PN) (ie, K≤N).

Depending on the embodiment, the number of the plurality of domains (DM1, DM2, ..., DMK) may be the same as or different from the number of the plurality of clusters (CLU1, CLU2, ..., CLUM). The hierarchical domain structure may be defined to correspond to a configuration of a plurality of clusters (CLU1, CLU2, ..., CLUM) or the power domains, and a plurality of clusters (CLU1, CLU2, ..., CLUM) Alternatively, the hierarchical domain structure may be defined regardless of the configuration of the power domains.

The domain definer 110 includes first information (PINF) indicating characteristics of a plurality of processors (P1, P2, P3, P4, P5, P6, ..., P(N-1), PN) and a plurality of Based on the second information (DINF) for the domains (DM1, DM2, ..., DMK), a plurality of domains (DM1, DM2, ..., DMK) are hierarchically configured and a plurality of processors The hierarchical domain structure may be defined so that each of (P1, P2, P3, P4, P5, P6, ..., P(N-1), PN) is included in at least one domain. For example, the first information PINF and the second information DINF may be provided in the form of a device tree including hardware characteristic information. The domain definer 110 may generate third information HDINF representing the hierarchical domain structure.

In one embodiment, the domain definer 110 may receive the first user setting signal USS1. When the first user set signal USS1 is received, the domain definer 110 may change the predefined hierarchical domain structure based on the first user set signal USS1. In other words, the hierarchical domain structure may be changeable by the domain definer 110 based on a user setting signal.

The scheduler 120 receives and manages at least one task TKS performed by a plurality of processors P1, P2, P3, P4, P5, P6, ..., P(N-1), PN do. When at least one task TKS is received, the selector 130 selects the plurality of domains DM1, DM2, ..., based on the states of the plurality of domains DM1, DM2, ..., DMK. , DMK) to assign at least one task (TKS), and among a plurality of processors (P1, P2, P3, P4, P5, P6, ..., P(N-1), PN) At least one processor is selected based on the state of the processors included in the selected domain and at least one task (TKS) is allocated. The scheduler 120 and the selector 130 may schedule, manage, and allocate at least one task TKS based on the third information HDINF representing the hierarchical domain structure.

The processor selected by the selector 130 from among the plurality of processors P1, P2, P3, P4, P5, P6, ..., P(N-1), PN performs at least one task TKS. can

In one embodiment, the selector 130 may receive the second user setting signal USS2. When the second user setting signal USS2 is received, the selector 130 is inactivated and does not perform the above-mentioned two-step task assignment. At this time, the scheduler 120 selects an arbitrary processor according to a general procedure and At least one task (TKS) can be assigned. In other words, the selector 130 may be deactivated based on the second user setting signal USS2.

The memory 140 may store first information PINF, second information DINF, and third information HDINF. For example, the memory 140 may include volatile memory such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), static random access memory (SRAM), flash memory, phase change random access memory (PRAM), and the like. ), resistance random access memory (RRAM), nano floating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), and the like. can include Also, according to embodiments, the memory 140 may be in the form of a storage device such as a solid state drive (SSD), an embedded SSD (eSSD), a multimedia card (MMC), an embedded MMC (eMMC), or a universal flash storage (UFS). may be implemented.

The method of driving the multi-processor system according to the embodiments of the present invention shown in FIG. 1 may be performed by the multi-processor system 100 of FIG. 2 . For example, step S100 in FIG. 1 is performed by the domain definer 110, step S200 is performed by the scheduler 120, steps S300 and S400 are performed by the selector 130, and step S500 is performed by the selector 130. It may be performed by at least one of a plurality of processors (P1, P2, P3, P4, P5, P6, ..., P(N-1), PN).

In one embodiment, the multi-processor system 100 may be implemented in the form of a system on chip (SOC). In this case, although not shown, the multi-processor system 100 may include a plurality of functional blocks.

Meanwhile, although not shown, a plurality of processors (P1, P2, P3, P4, P5, P6, ..., P(N-1), PN) included in the multi-processor system 100, a domain definer ( 110), the scheduler 120, the selector 130, and the memory 140 may exchange signals and/or data through a bus. In one embodiment, the bus is an Advanced Microcontroller Bus Architecture (AMBA), an Advanced High-performance Bus (AHB), an Advanced Peripheral Bus (APB), an Advanced eXtensible Interface (AXI), an Advanced System Bus (ASB), or a combination thereof. can be implemented

FIG. 3 is a flowchart illustrating an example of a step of defining the hierarchical domain structure of FIG. 1 .

1 and 3, in defining the hierarchical domain structure (step S100), the plurality of processors and the plurality of domains may be analyzed (step S110). For example, as shown in FIG. 2 , first information PINF indicating characteristics of the plurality of processors P1, P2, P3, P4, P5, P6, ..., P(N-1), PN ) and the plurality of processors P1, P2, P3, P4, P5, P6, ..., P based on the second information DINF for the plurality of domains DM1, DM2, ..., DMK. (N-1), PN) and a plurality of domains (DM1, DM2, ..., DMK) can be analyzed.

The plurality of domains may be hierarchically arranged (step S120), and each of the plurality of processors may be arranged to be included in at least one of the plurality of domains (step S130). For example, as shown in FIG. 2, a plurality of domains DM1, DM2, ..., DMK and a plurality of processors P1, P2, P3, P4, P5, P6, ..., P( N-1), the hierarchical domain structure including PN) may be configured and defined. For example, the plurality of domains (DM1, DM2, ..., DMK) may be sequentially arranged from the first domain (DM1) to the last domain (DMK), and the plurality of processors (P1, P2, P3) , P4, P5, P6, ..., P(N-1), PN) may be sequentially arranged from the first processor P1 to the last processor PN.

In one embodiment, steps S110, S120 and S130 of FIG. 3 may be performed by domain definer 110 of FIG. 2 .

4a, 4b, 4c, 5a and 5b are diagrams for explaining an operation of defining the hierarchical domain structure of FIG. 3 .

Referring to FIG. 4A , eight processors P11, P12, P13, P14, P15, P16, P17, and P18 are divided into three clusters CLU11, CLU12, and CLU13. The first cluster CLU11 forms a first power domain and may include the first to fourth processors P11, P12, P13, and P14. The second cluster CLU12 forms a second power domain and may include fifth and sixth processors P15 and P16. The third cluster CLU13 forms a third power domain and may include seventh and eighth processors P17 and P18.

Referring to FIG. 4B, the eight processors P11, P12, P13, P14, P15, P16, P17, and P18 of FIG. 4A are hierarchically configured into three domains DM11, An example of arrangement in DM12 and DM13) is shown. The first domain DM11 may be included in the second domain DM12, and the second domain DM12 may be included in the third domain DM13. The first to fourth processors P11, P12, P13, and P14 are included in the first domain DM11, and the first to sixth processors P11, P12, P13, P14, P15, and P16 are included in the second domain DM11. It is included in the domain DM12, and the first to eighth processors P11, P12, P13, P14, P15, P16, P17, and P18 may be included in the third domain DM13.

In the example of FIG. 4B , the configuration of domains DM11 , DM12 , and DM13 may correspond to the configuration of clusters CLU11 , CLU12 , and CLU13 and power domains. For example, the processors P11, P12, P13, and P14 included only in the first domain DM11 are included in the first cluster CLU11, and the processors P15 and P16 included only in the second domain DM12. ) may be included in the second cluster CLU12, and processors P17 and P18 included only in the third domain DM13 may be included in the third cluster CLU13. In addition, the first domain DM11 corresponds to all of the first power domains, the second domain DM12 corresponds to all of the first and second power domains, and the third domain DM13 corresponds to the first power domain. It may correspond to all of the first, second and third power domains. In other words, the first domain DM11 may correspond to one power domain, and the second and third domains DM12 and DM13 may correspond to two or more different power domains, respectively.

Referring to FIG. 4C, the eight processors P11, P12, P13, P14, P15, P16, P17, and P18 of FIG. 4A are hierarchically configured into three domains DM11' according to embodiments of the present invention. , DM12', DM13') shows another example. The first domain DM11' may be included in the second domain DM12', and the second domain DM12' may be included in the third domain DM13'. The first, second, fifth, and sixth processors P11, P12, P15, and P16 are included in the first domain DM11', and the first, second, third, fifth, sixth, and sixth processors are included in the first domain DM11'. The seven processors P11, P12, P13, P15, P16, and P17 are included in the second domain DM12', and the first to eighth processors P11, P12, P13, P14, P15, P16, P17, P18) may be included in the third domain DM13'.

In the example of FIG. 4C , the configuration of the domains DM11', DM12', and DM13' may not correspond to the configuration of the clusters CLU11, CLU12, and CLU13 and the power domains. For example, the processors P11, P12, P13, and P14 included in the first cluster CLU11 are included in the first to third domains DM11', DM12', and DM13', and the second cluster ( The processors P15 and P16 included in CLU12 are included only in the first domain DM11', and the processors P17 and P18 included in the third cluster CLU13 are included in the second and third domains DM12. ', DM13'). In addition, the first domain DM11' corresponds to parts of the first and second power domains, the second domain DM12' corresponds to parts of the first, second, and third power domains. The third domain DM13' may correspond to all of the first, second, and third power domains.

Referring to FIG. 5A , eight processors (P21, P22, P23, P24, P25, P26, P27, and P28) are divided into four clusters (CLU21, CLU22, CLU23, and CLU24). The first cluster CLU21 forms a first power domain and may include first and second processors P21 and P22. The second cluster CLU22 forms a second power domain and may include third and fourth processors P23 and P24. The third cluster CLU23 forms a third power domain and may include fifth and sixth processors P25 and P26. The fourth cluster CLU24 forms a fourth power domain and may include seventh and eighth processors P27 and P28.

Referring to FIG. 5B, three domains (DM21, An example of arrangement in DM22 and DM23) is shown. The first domain DM21 may be included in the second domain DM22, and the second domain DM22 may be included in the third domain DM23. The first to fourth processors P21, P22, P23, and P24 are included in the first domain DM21, and the first to sixth processors P21, P22, P23, P24, P25, and P26 are included in the second domain DM21. It is included in the domain DM22, and the first to eighth processors P21, P22, P23, P24, P25, P26, P27, and P28 may be included in the third domain DM23.

In the example of FIG. 5B , the configuration of domains DM21 , DM22 , and DM23 may partially correspond to the configuration of clusters CLU21 , CLU22 , CLU23 , and CLU24 and power domains. In other words, except that the first domain DM21 corresponds to all of the first and second power domains, the configuration of the domains DM21, DM22, and DM23 includes clusters CLU21, CLU22, CLU23, and CLU24. and configuration of power domains.

In defining a hierarchical domain structure according to embodiments of the present invention, the following criteria may be applied. First, a plurality of domains must be configured in a hierarchical structure. Each processor must be included in at least one domain, and each domain must have at least one processor included only in the corresponding domain. Each processor may be included redundantly in all domains. Domains may be defined to correspond to or not correspond to the configuration of power domains, and two or more different power domains may be defined as one domain. In this case, defining domains based on power domains may be advantageous in terms of power consumption management.

Although the hierarchical domain structure according to the embodiments of the present invention has been described based on the examples of FIGS. 4B, 4C, and 5B, the present invention is not limited thereto, and each of the processors of FIGS. 4A and 5A uses at least one Can be placed in a domain. In addition, although a hierarchical domain structure according to embodiments of the present invention has been described based on a specific number of processors, clusters (or power domains), and domains, the present invention may not be limited thereto. 4a, 4b, and 4c illustrate cases in which the number of domains is equal to the number of clusters (or power domains), and cases in which the number of domains is less than the number of clusters (or power domains) in FIGS. 5a and 5b. , but the present invention is not limited thereto, and may be applied even when the number of domains is greater than the number of clusters (or power domains).

6 and 7 are flowcharts illustrating an example of selecting one domain of FIG. 1 and allocating at least one task.

1 and 6, in assigning the at least one task by selecting one of the plurality of domains (step S300), first, based on a case in which a first task, which is one task, is received in step S200 An operation of allocating the first task will be described.

After the first task is received, it may first be determined whether the first task is received or generated for the first time (step S310).

If the first task is not the first received task (step S310: No), that is, if there is a current domain performing or processing a task other than the first task, the state of the current domain may be checked. Yes (step S320). For example, the state of the current domain may include at least one of utilization and load (eg, workload) of the current domain, and other various factors such as power/load. It may include at least one of the variables.

If it is determined that the first job can be sufficiently processed in the current domain (step S330: Yes), the first job can be assigned to the current domain (step S340). If it is determined that the first job cannot be processed in the current domain (step S330: No), the first job may be assigned to a domain other than the current domain among the plurality of domains (step S350). . In other words, the existing domain may be maintained or a new domain may be selected according to the determination result of step S330.

In one embodiment, the other domain in step S350 may be one of the domains including the current domain, and in particular, may be the immediately following domain directly including the current domain. For example, as shown in FIG. 2, when the first domain DM1 among the plurality of domains DM1, DM2, ..., DMK is the current domain, One of the domains DM2, ..., DMK may be the other domain, and in particular, the second domain DM2 may be the other domain.

In one embodiment, in step S330, it may be determined whether the first job can be processed in the current domain based on at least one of the state of the current domain, the usage amount and priority of the first job. For example, the amount of use of the first task may indicate the amount of processor resource used by the first task and/or the amount of processor resource used by the first task.

Meanwhile, when the first task is the first received task (step S310: Yes), that is, when the current domain does not exist, the first task may be assigned to the smallest domain among the plurality of domains. Yes (step S360). In general, since the first received task does not have a large amount of work, it may be allotted to the smallest domain. For example, as shown in FIG. 2 , the first task may be assigned to the smallest first domain DM1 among the plurality of domains DM1, DM2, ..., DMK.

1 and 7, in assigning the at least one task by selecting one of the plurality of domains (step S300), first, based on a case in which a first task, which is one task, is received in step S200 An operation of allocating the first task will be described.

After the first job is received, states of all of the plurality of domains may be checked (step S325), and the first job is allocated to an optimal domain capable of processing the first job among the plurality of domains. It can be done (step S245). Unlike the embodiment of FIG. 6 in which only the state of the current domain among the plurality of domains is checked, in the embodiment of FIG. 7 , the state of all of the plurality of domains can be checked.

In an embodiment, in step S345, an optimal domain capable of processing the first job may be selected based on at least one of states of all of the plurality of domains, amount of usage and priority of the first job.

In one embodiment, steps S310, S320, S330, S340, S350, and S360 of FIG. 6 and steps S325 and S345 of FIG. 7 may be performed by the selector 130 of FIG. 2 .

8 and 9 are flowcharts illustrating examples of selecting at least one processor of FIG. 1 and allocating at least one task.

1 and 8, in selecting the at least one processor and allocating the at least one task (step S400), first, when a first task is received in step S200 and one in step S300. An operation of allocating the first task based on a case in which the first domain, which is the domain of , is selected will be described.

After the first task is received, the first domain is selected, and the first task is allocated, states of first processors included in the first domain among the plurality of processors may be checked (step S410). . For example, as shown in FIG. 2 , when the first task is allocated to a first domain DM1 among a plurality of domains DM1, DM2, ..., DMK, the first domain DM1 The states of the processors P1, P2, P3, and P4 included in may be checked. For example, the state of the first processors may include at least one of whether the first processors are in use, usage, and load, and may include at least one of various other factors/variables.

If there is an idle processor in an idle state among the first processors (step S420: Yes), the first task may be assigned to the idle processor (step S430). The idle state is a concept opposite to the active state, and may also be referred to as a sleep state, a standby state, and the like.

When the idle processor does not exist among the first processors (step S420: No), that is, when all of the first processors are in the active state rather than the idle state, the load of the first processors is checked. can If there is a least loaded processor having the least load among the first processors (step S440: Yes), the first task may be assigned to the least loaded processor (step S450).

When the idle processor does not exist (step S420: No), and when the minimum load processor does not exist (step S440: No), that is, when all of the first processors have the same load, the first processor Among the processors, the first task may be assigned to a processor defined first in the first domain (step S460). For example, as shown in FIG. 2 , when the first processor P1 is sequentially defined or arranged, the first task may be assigned to the first processor P1.

1 and 9, in selecting the at least one processor and allocating the at least one task (step S400), the embodiment of FIG. 8 is more specifically determined to sequentially determine all of the first processors. An example for this is shown. Hereinafter, a description overlapping with that of FIG. 8 will be omitted.

Among the first processors included in the first domain, an X (X is a natural number)-th defined processor may be set as a current processor (step S415). At the beginning of the operation, X = 1, and the decision can be started from the first defined processor.

When the current processor is in the idle state (step S425: Yes) or when the current processor has the least load (step S445: Yes), the first task may be assigned to the current processor (step S445: Yes). S435). Steps S425 and S445 of FIG. 9 may be similar to steps S420 and S440 of FIG. 8 , respectively.

When the current processor is not in the idle state (step S425: No), and when the current processor does not have the least load (step S445: No), it is checked whether the determination of all of the first processors is completed. can

Specifically, when the total number of the first processors is Y (Y is a natural number), X and Y may be compared. If X is not equal to Y (Y is a natural number) (step S455: No), that is, if X is smaller than Y, increase X by 1 (step S465), and repeat steps S415, S425, S445 and S455. can do. If X is equal to Y (step S455: Yes), this means that all of the first processors have the same load, and therefore the first processor defined first in the first domain among the first processors has the same load. A task can be assigned (step S460). Step S460 of FIG. 9 may be substantially the same as step S460 of FIG. 8 .

In one embodiment, steps S410, S420, S430, S440, S450 and S460 of FIG. 8 and steps S415, S425, S435, S445, S455, S460 and S465 of FIG. 9 are performed by selector 130 of FIG. can

In one embodiment, in selecting the at least one processor and allocating the at least one task (step S400), at least one of various algorithms widely used in the past as well as the algorithm described above with reference to FIGS. 8 and 9 can also be used.

10A, 10B, 11 and 12 are diagrams illustrating performance of a multi-processor system and a method for driving the same according to embodiments of the present invention.

Referring to FIG. 10A , frequency of use of processors is shown when a video is reproduced using eight processors (CPU0, CPU1, CPU2, CPU3, CPU4, CPU5, CPU6, CPU7) according to the prior art. In the example of FIG. 10A , processors CPU0 , CPU1 , CPU2 , CPU3 , CPU4 , and CPU5 are included in a first domain with relatively low power and low performance, and processors CPU6 and CPU7 have relatively high power and high performance. It is included in the second domain, and the first domain and the second domain are not hierarchically configured but configured separately. In the prior art, tasks are equally allocated to the processors (CPU0, CPU1, CPU2, CPU3, CPU4, and CPU5) included in the first domain.

Referring to FIG. 10B , frequency of use of processors is shown when a video is played using 8 processors (CPU0, CPU1, CPU2, CPU3, CPU4, CPU5, CPU6, CPU7) according to embodiments of the present invention. . In the example of FIG. 10B , the first domain is included in the second domain and the second domain is hierarchically configured to be included in the third domain, and the processors CPU0, CPU1, CPU2, and CPU3 are included in the first domain. and the processors (CPU0, CPU1, CPU2, CPU3, CPU4, and CPU5) are included in the second domain, and the processors (CPU0, CPU1, CPU2, CPU3, CPU4, CPU5, CPU6, and CPU7) are included in the third domain. included in the domain. In addition, the video was reproduced under the same conditions as in the example of FIG. 10A except for the hierarchical domain structure. According to embodiments of the present invention, tasks are preferentially allocated to the processors (CPU0, CPU1, CPU2, and CPU3) included in the first domain, and tasks are assigned to the processors (CPU4, CPU5) only in a period in which usage increases. additionally allocated. Therefore, compared to the prior art, the processors CPU4 and CPU5 can be deactivated for a long period of time, and power consumption can be reduced.

11 and 12, CASE1 represents a case of executing various scenarios according to the prior art described above with reference to FIG. 10A, and CASE2 represents various scenarios according to the embodiments of the present invention described above with reference to FIG. 10B. Indicates when to run. As shown in FIG. 11, the power consumption of the present invention is generally reduced in various scenarios such as address book execution, music application execution, screen touch, 3D game, gallery application execution, video playback, music playback, standby screen, etc. You can check. For example, power consumption can be reduced by about 2.19 mW on average. In addition, as shown in FIG. 12, it can be confirmed that the execution speed of the present invention is generally fast in a web browsing scenario in which various web pages (WEBPAGE1, WEBPAGE2, WEBPAGE3, WEBPAGE4, WEBPAGE5, WEBPAGE6, WEBPAGE7, WEBPAGE8) are executed. . For example, it can increase execution speed by about 7.4% on average.

13 and 14 are flowcharts illustrating a method of driving a multi-processor system according to embodiments of the present invention. Hereinafter, a description overlapping with that of FIG. 1 will be omitted.

Referring to FIG. 13 , the embodiment of FIG. 13 may be substantially the same as the embodiment of FIG. 1 except that step S100 is omitted and step S600 is added.

In the method for driving a multi-processor system according to embodiments of the present invention, the hierarchical domain structure may be predefined. Before steps S200, S300, S400, and S500 are performed, the predefined hierarchical domain structure may be changed based on a user setting signal (step S600). For example, as shown in FIG. 2 , when the first user set signal USS1 is received, the domain definer 110 determines the hierarchical domain defined in advance based on the first user set signal USS1. structure can be changed. In other words, the hierarchical domain structure may be changeable according to external settings.

Steps S200, S300, S400 and S500 may be performed based on the hierarchical domain structure changed in step S600.

Referring to FIG. 14 , the embodiment of FIG. 14 may be substantially the same as the embodiment of FIG. 1 except for the addition of step S700.

After steps S100 and S200 are performed, it may be determined whether a task allocation algorithm or a task packing algorithm according to embodiments of the present invention is activated.

When the task allocation algorithm or the task packing algorithm is activated (step S700: YES), the two-step task allocation of steps S300 and S400 is performed, and step S500 is performed by the selected domain and the selected at least one processor. can be performed

If the task allocation algorithm or the task packing algorithm is inactivated (step S700: No), steps S300 and S400 can be omitted. For example, as shown in FIG. 2 , when the second user setting signal USS2 is received, the selector 130 is inactivated and may not perform the above-described two-step task allocation. In other words, the task allocation algorithm or the task packing algorithm may be selectively turned on/off according to external settings.

When the task allocation algorithm or the task packing algorithm is inactivated, the scheduler 120 may select an arbitrary processor according to a general procedure, and step S500 may be performed by the selected processor.

In the multi-processor system and its driving method according to embodiments of the present invention, a plurality of processors having various characteristics are implemented in a multi-cluster environment, and three or more domains are hierarchically managed to efficiently manage the plurality of processors. It is defined according to the domain structure, and each of the plurality of processors may be included in at least one domain. In addition, tasks performed by a plurality of processors can be efficiently scheduled and managed by allocating received tasks to specific domains and specific processors in two steps using a task packing algorithm. Accordingly, performance and power consumption of the multi-processor system can be efficiently managed, and power consumption can be reduced while performance of the multi-processor system is improved.

Meanwhile, the method of driving a multi-processor system according to embodiments of the present invention may be implemented in the form of a product including a computer-readable program code stored in a computer-readable medium. The computer readable program code may be provided to processors of various computers or other data processing devices. The computer-readable medium may be a computer-readable signal medium or a computer-readable recording medium. The computer-readable recording medium may be any tangible medium capable of storing or including a program in or connected to an instruction execution system, equipment, or device.

15 is a block diagram illustrating a multi-core processing device according to embodiments of the present invention. Hereinafter, a description overlapping with that of FIG. 2 will be omitted.

Referring to FIG. 15, the multi-core processing apparatus 200 includes a plurality of processor cores (PC1, PC2, PC3, PC4, PC5, PC6, ..., PC(N-1), PCN), a scheduler 220 and selector 230 . The multi-core processing device 200 may further include a domain definer 210 and a memory 240 .

A plurality of processors (P1, P2, P3, P4, P5, P6, ..., P(N-1), PN) a plurality of processor cores (PC1, PC2, PC3, PC4, PC5, PC6, . .., PC(N-1), PCN), the multi-core processing device 200 of FIG. 15 may be substantially the same as the multi-processor system 100 of FIG. The domain definer 210, scheduler 220, selector 230, and memory 240 are each substantially the same as the domain definer 110, scheduler 120, selector 130, and memory 140 of FIG. It is the same and can operate according to the embodiments of the present invention. In this case, the driving method of the multi-processor system according to the embodiments of the present invention may be referred to as a driving method of the multi-core processing device.

In one embodiment, at least one of the domain definer 210 and the memory 240 may be disposed outside the multi-core processing device 200 .

Depending on embodiments, some or all of the domain definers 110 and 210, the schedulers 120 and 220, and the selectors 130 and 230 of FIGS. 2 and 15 may be implemented in the form of hardware or software (i.e., It may be implemented in the form of a program) and stored in a storage device.

Embodiments of the present invention can be usefully used in any electronic device and system including a multi-processor system. For example, embodiments of the present invention may be used in computers, laptops, cellular, smart phones, MP3 players, personal digital assistants (PDAs), portable multimedia players (PMPs), digital TV, digital camera, portable game console, navigation device, wearable device, internet of things (IoT) device, VR (virtual reality) device, AR (augmented reality) device It can be usefully applied to various electronic devices such as

Although the above has been described with reference to preferred embodiments of the present invention, those skilled in the art can variously modify and change the present invention without departing from the spirit and scope of the present invention described in the claims below. you will understand that you can

Claims (10)

a plurality of processors each included in at least one of a plurality of three or more domains defined according to a hierarchical domain structure;
a scheduler for receiving and managing at least one task performed by the plurality of processors; and
When the at least one task is received, the at least one task is allocated by selecting one of the plurality of domains based on the state of the plurality of domains, and being included in the selected domain among the plurality of processors. Selecting at least one processor based on the state of the processors to allocate the at least one task, and selecting another domain including the current domain when it is determined that the at least one task cannot be processed in the current domain A multi-processor system with a selector. The method of claim 1, wherein the selector,
When a first task is received, the status of the current domain among the plurality of domains is checked, and when it is determined that the first task can be processed in the current domain, the first task is assigned to the current domain. and allocating the first task to the other domain including the current domain among the plurality of domains when it is determined that the first task cannot be processed in the current domain. According to claim 2,
The state of the current domain includes at least one of utilization and load of the current domain;
The multi-processor system of claim 1 , wherein the selector determines whether the first task can be processed in the current domain based on at least one of a state of the current domain, usage and priority of the first task. The method of claim 1, wherein the selector,
After a first task is received and the first task is allocated to a first domain among the plurality of domains, states of first processors included in the first domain among the plurality of processors are checked, and 1. A multi-processor system, wherein the first task is assigned to an idle processor among processors in an idle state. The method of claim 4, wherein the selector,
When all of the first processors are not in the idle state, the first task is allocated to a least loaded processor having the smallest load among the first processors. The method of claim 5, wherein the selector,
When all of the first processors are not in the idle state and when all of the first processors have the same load, a processor defined first in the first domain among the first processors performs the first task. Multi-processor system, characterized in that for allocating. According to claim 1,
Domain definition for defining the hierarchical domain structure so that each of the plurality of processors is included in at least one domain, based on the first information representing the characteristics of the plurality of processors and the second information about the plurality of domains. A multi-processor system further comprising a definer. According to claim 7,
The plurality of domains include first, second and third domains,
The plurality of processors include first, second and third processors,
In the domain definer, the second domain includes the first domain, the third domain includes the second domain, the first processor is included in the first domain, and the first and second processors are included in the first domain. 2 domains and defining the hierarchical domain structure so that the first, second and third processors are included in the third domain. As a driving method of a multi-processor system including a plurality of processors,
When at least one task performed by the plurality of processors each included in at least one of three or more domains defined according to a hierarchical domain structure is received, the plurality of assigning the at least one task by selecting one of the plurality of domains based on a state of the domains; and
Selecting at least one processor from among the plurality of processors based on states of processors included in the selected domain and allocating the at least one task;
and selecting another domain including the current domain when it is determined that the at least one task cannot be processed in the current domain. According to claim 9,
Defining the hierarchical domain structure so that each of the plurality of processors is included in at least one domain, based on first information indicating characteristics of the plurality of processors and second information about the plurality of domains. A method of driving a multi-processor system, characterized in that it further comprises.

Images