CN115904418A - System and method for burning firmware of PCIE (peripheral component interface express) cascade chip - Google Patents
System and method for burning firmware of PCIE (peripheral component interface express) cascade chip Download PDFInfo
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Abstract
A system for burning firmware of PCIE cascade chips comprises a plurality of chips cascaded by PCIE and a memory corresponding to each chip, wherein a first-stage chip is provided with an upper computer interface and is used for communicating with an upper computer; the first-stage chip is configured to sequentially receive a first data packet sent to each chip by an upper computer through an upper computer interface; each chip is configured to match the chip identifier in the first data packet with the identifier of the chip, if the matching fails, the first data packet is forwarded to the next-level chip, and if the matching succeeds, the downloading agent program in the first data packet is operated, and a first response is returned to the upper computer; and the chip corresponding to the first response acquires the second data packet and burns the firmware in the second data packet into the corresponding memory. The application also provides a method for burning the PCIE cascade chip firmware, which can realize the burning of each cascade chip firmware by only using one upper computer interface, thereby saving the upper computer interface.
Description
Technical Field
The present application relates to the field of data processing, and in particular, to a system and method for firmware burning of PCIE cascade chips.
Background
High computational demand scenarios such as autopilot, AI calculations, sometimes may not be able to meet the demand on a single chip, requiring two or even more chips to be cascaded, each chip requiring independent loading of firmware for operation. In order to facilitate circuit layout, software package management and production procedures, the reserved interface of the circuit board is communicated with an upper computer and used for downloading all chip firmware or other operations. At present, a common method is to reserve an upper computer interface for each chip to write respective firmware, each chip has a memory and firmware of the chip, and if the upper computer is connected with the chip through the upper computer interface of each chip to write the firmware, the following problems exist: the consumption of chip pins is increased, so that the number of available pins is reduced, the complexity of circuit wiring is increased, the software version management difficulty is increased, and the production procedures are increased.
Disclosure of Invention
In order to solve at least one problem in the prior art, the present application aims to provide a method and a system for burning firmware of PCIE cascade chips, which can realize burning of the other chip firmware by using only one upper computer interface, and communicate and receive the firmware sent by the upper computer by using a high-speed interconnect PCIE interface, thereby saving the upper computer interface, reducing the production processes, and facilitating software version management.
In order to achieve the above object, the system for burning the firmware of the PCIE cascade chip provided in the present application includes a plurality of chips cascaded by PCIE and a memory corresponding to each of the chips, where a first-stage chip is configured with an upper computer interface for communicating with an upper computer;
the first-level chip is configured to sequentially receive a first data packet sent to each chip by the upper computer through the upper computer interface;
each chip is configured to match the chip identifier in the first data packet with the identifier of the chip based on the chip identifier, if the matching fails, the first data packet is forwarded to a next-stage chip, and if the matching succeeds, a downloading agent program in the first data packet is operated, and a first response is returned to the upper computer;
the chip corresponding to the first response is configured to acquire a second data packet sent by the upper computer and burn the firmware in the second data packet into the corresponding memory.
Further, the chip corresponding to the first response is also configured to return a second response to the upper computer after the burning is finished;
and the upper computer sends the second data packet of the chip of the next level based on the second response.
Further, the first-stage chip is further configured to sequentially send the first response returned by each chip to the upper computer through the upper computer interface, and sequentially send the second response returned by each chip to the upper computer through the upper computer interface.
Further, the first-stage chip is configured to start up an interface of an upper computer, the other chips are configured to start up PCIE interfaces, an output-side PCIE interface of the first-stage chip is configured to be in a root complex mode, an input-side PCIE interface of the last-stage chip is configured to be in an endpoint mode, an input-side PCIE interface of each intermediate-stage chip is configured to be in the endpoint mode, and an output-side PCIE interface of each intermediate-stage chip is configured to be in the root complex mode.
Further, each of the chips includes a random access memory for temporarily storing and running the download agent and temporarily storing the firmware.
Further, after power-on, the random access memories in the chips other than the first-level chip are configured to be mapped to the output PCIE interface of the upper-level chip.
Further, the first data packet includes the chip identifier and the download agent, and the second data packet includes the chip identifier and the firmware.
Further, the second data packet is transmitted in a fast start command format.
Further, the first-level chip is configured to transmit the second packet through a first-in-first-out queue mode.
In order to achieve the above object, the present application further provides a method for burning firmware of a PCIE cascade chip, including:
the first-level chip sequentially receives a first data packet sent to each chip by the upper computer through the upper computer interface;
each chip is matched with the own identifier based on the chip identifier in the first data packet, if the matching fails, the first data packet is forwarded to a next-level chip, and if the matching succeeds, a downloading agent program in the first data packet is operated, and a first response is returned to the upper computer;
and the chip corresponding to the first response acquires a second data packet sent by the upper computer, and burns the firmware in the second data packet into a corresponding memory.
Further, the step of returning the first response to the upper computer includes:
if the chip sending the first response is the first-level chip, sending the first response to the upper computer through the upper computer interface;
and if the chip sending the first response is not the first-level chip, sending the first response to the upper-level chip until the first-level chip receives the first response, and sending the first response to the upper computer through the upper computer interface.
Further, after the step of burning the firmware in the second data packet into the corresponding memory, the method further includes:
returning a second response to the upper computer after the burning is finished;
and the upper computer sends the second data packet of the chip of the next level based on the second response.
Further, the step of returning a second response to the upper computer includes:
if the chip sending the second response is the first-level chip, sending the second response to the upper computer through the upper computer interface;
and if the chip sending the second response is not the first-level chip, sending the second response to the upper-level chip until the first-level chip receives the second response, and sending the second response to the upper computer through the upper computer interface.
In order to achieve the above object, the present application further provides a chip, on which the system for firmware burning of PCIE cascade chips as described above is integrated.
In order to achieve the above object, the present application also provides a circuit board including the chip as described above.
In order to achieve the above object, the present application further provides a vehicle device, including the chip as described above.
In order to achieve the above object, the present application further provides an electronic device, which includes a memory and a processor, and is characterized in that the memory stores computer instructions, and the processor is configured to execute the instructions to execute the steps of the method for firmware burning of PCIE cascade chips as described above.
In order to achieve the above object, the present application further provides a computer readable storage medium, on which computer instructions are stored, and when the computer instructions are executed, the steps of the method for burning the firmware of the PCIE cascade chip as described above are executed.
According to the method and the system for burning the firmware of the PCIE cascade chips, the first-level chip receives the downloading agent program from the upper computer, each chip downloads the downloading agent program matched with the chip to the internal RAM of the chip for operation, the downloading agent program receives the firmware matched with the chip and burns the firmware to the corresponding memory, burning of the firmware of each cascade chip can be realized by only one upper computer interface, the PCIE interface with high speed interconnection is used for communication and receiving the firmware sent by the upper computer, the upper computer interface is saved, production procedures are reduced, and software version management is facilitated.
Additional features and advantages of the present application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the present application.
Drawings
The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application and not limit the application. In the drawings:
fig. 1 is a block diagram of a system for firmware burning of PCIE cascade chips according to another embodiment of the present application;
fig. 2 is a flowchart of a method for firmware burning of PCIE cascade chips according to an embodiment of the present application;
fig. 3 is a flowchart of a method for firmware burning of PCIE cascade chips according to another embodiment of the present application;
FIG. 4 is a schematic diagram of a chip structure according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a circuit board structure according to an embodiment of the present application;
fig. 6 is a schematic diagram of a vehicle machine structure according to an embodiment of the application.
Detailed Description
Embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided for a more thorough and complete understanding of the present application. It should be understood that the drawings and embodiments of the present application are for illustration purposes only and are not intended to limit the scope of the present application.
It should be understood that the various steps recited in the method embodiments of the present application may be performed in a different order, and/or performed in parallel. Moreover, method embodiments may include additional steps and/or omit performing the illustrated steps. The scope of the present application is not limited in this respect.
The term "include" and variations thereof as used herein are open-ended, i.e., "including but not limited to". The term "based on" is "based, at least in part, on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Relevant definitions for other terms will be given in the following description.
It should be noted that the references to "first", "second", etc. in this application are only used for distinguishing different devices, modules, units or data, and are not used for limiting the order or interdependence of the functions performed by these devices, modules, units or data.
It is noted that references to "a", "an", and "the" modifications in this application are intended to be illustrative rather than limiting, and that those skilled in the art will recognize that reference to "one or more" unless the context clearly dictates otherwise. "plurality" is to be understood as two or more.
Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings.
Firmware: firmware refers to a program written in EROM (Erasable ROM) and EEPROM (Electrically Erasable Programmable ROM), that is, a device "driver" stored inside the device;
burning: the method is a process of writing a written program into a chip after the program is compiled into an HEX or BIN file;
DA: download Agent, download Agent;
PCIE: the Peripheral Component Interconnect express is a high-speed serial computer expansion bus standard;
RAM: random Access Memory, random Access Memory;
RC: root Complex, root Complex device, a component in the PCIe protocol;
EP: endpoint, PCIe protocol;
USB: universal Serial Bus, a standard for external Bus, is used to standardize the connection and communication between computer and external devices;
fastboot, which is a firmware communication protocol for a computer to flash, erase/format, debug, and transmit various instructions to the mobile phone firmware through a USB data line;
FIFO, first Input First Output, first in First out, first in command is completed and retired, then the second command is executed.
Example 1
Fig. 1 is a block diagram of a system structure for firmware burning of PCIE cascade chips according to an embodiment of the present application. Referring to fig. 1, a system 10 for burning firmware of PCIE cascade chips in the embodiment of the present application includes a plurality of chips 11 cascaded by PCIE and a memory 12 corresponding to each of the chips, where the chips 11 include: the memory 12 comprises a memory 1 and a memory 2, wherein the memory 1 is connected with the corresponding first-stage chip, the memory 2 is connected with the corresponding second-stage chip, and the memory N is connected with the corresponding N-stage chip, wherein only the first-stage chip is provided with an upper computer interface and is used for communicating with an upper computer;
the first-stage chip is configured to sequentially receive, through the upper computer interface, a first data packet sent to each chip 11 by the upper computer;
each chip 11 is configured to match the chip identifier in the first data packet with its own identifier, forward the first data packet to a next-stage chip if matching fails, run a download agent in the first data packet if matching succeeds, and return a first response to the upper computer;
the chip 11 corresponding to the first response is configured to acquire a second data packet sent by the upper computer, and burn the firmware in the second data packet to the corresponding memory 12.
Further, in this embodiment of the application, the chip corresponding to the first response is further configured to return a second response to the upper computer after the burning is completed;
and the upper computer sends the second data packet of the next-level chip based on the second response.
Specifically, the first data packet is created and sent by an upper mechanism, the first data packet includes a chip identifier and a download agent, the first-stage chip is a chip directly connected with an upper computer through an upper computer interface, the upper computer interface of the first-stage chip directly receives the first data packet sent by the upper computer, and the upper computer interface is an interface through which the first-stage chip can communicate with the upper computer, such as a USB interface.
Further, in this application embodiment, the first-level chip is further configured to send the first response to the upper computer through the upper computer interface, and send the second response to the upper computer through the upper computer interface.
That is to say, the upper computer needs to send the download agent of each chip 11 in sequence, for example, the upper computer sends the download agent of the first-level chip through the upper computer interface first, after the first-level chip is successfully matched, the upper computer returns a first response to the upper computer through the upper computer interface, the upper computer sends the download agent of the second-level chip to the first-level chip through the upper computer interface, the first-level chip receives the download agent and forwards the download agent to the second-level chip after the matching fails, the second-level chip receives the first response sent to the upper computer by the first-level chip after the matching of the download agent is successful, and the first-level chip receives the first response and then sends the first response to the upper computer; the upper computer sends a downloading agent program of a third-level chip after receiving a first response returned by the second-level chip, and so on, when the upper computer sends the downloading agent program of the last chip and receives the first response returned by the last chip, namely the Nth-level chip, the upper computer starts to send the firmware of each chip 11 in sequence, for example, the upper computer sends the firmware of the first-level chip through an upper computer interface, after the first-level chip is successfully matched, the DA of the first-level chip receives and writes the firmware to a memory 1 corresponding to the first-level chip, the upper computer returns a second response to the upper computer through the upper computer interface, the upper computer sends the firmware of the second-level chip to the first-level chip through the upper computer interface, after the first-level chip is failed to be matched, the firmware is forwarded to the second-level chip, after the second-level chip receives the firmware and writes the firmware to a memory 2 corresponding to the second-level chip, the DA of the second-level chip sends a second response to the upper computer, and after the first-level chip receives the second response, the firmware sends the firmware to the upper computer; and the upper computer sends the firmware of the third-level chip after receiving the second response returned by the second-level chip, and so on until the upper computer sends the firmware of the last chip, namely the Nth-level chip, and the upper computer receives the second response returned by the last chip, namely the Nth-level chip, and then the operation is finished.
Further, in this embodiment of the application, the first data packet includes the chip identifier and the download agent, and the second data packet includes the chip identifier and the firmware.
Specifically, the chip identification is a code of the chip, and the code of the chip can ensure the uniqueness of the identity information of the chip according to information such as a manufacturer, a chip type, a chip name, a chip order, chip verification and the like, so as to ensure that different chips can have different chip identifications.
Specifically, the first data packet includes the chip identifier, and the chip parses the first data packet, extracts a chip identifier field therein, and obtains the chip identifier;
the self identification refers to the code of the chip at the level, and the chip can directly read the self identification when the chip leaves a factory and is programmed in the chip;
the successful matching means that the chip identification extracted from the first data packet is completely the same as the identification of the chip;
the matching failure means that the chip identifier extracted from the first data packet is different from the identifier of the chip itself.
The first-stage chip runs a downloading agent program and is used for initializing an upper computer interface and initializing a PCIE port, the initialized upper computer interface is ready to receive data sent by the upper computer and send a response to the upper computer, and the initialized PCIE port is ready to send data to the next-stage chip;
and the other chips run the download agent program and have the functions of initializing the PCIE ports, preparing to receive the data sent by the upper-level chip through the initialized PCIE ports and sending the data to the lower-level chip.
After each chip receives the second data packet sent to itself, the downloading agent program is used for receiving the firmware and burning the firmware into the memory 12 corresponding to the chip.
The second data packet is established and sent by an upper mechanism, the second data packet comprises chip identifiers and firmware, and the first-level chip sequentially receives the second data packet sent to each chip by the upper computer through an upper computer interface;
each chip is matched with the own identifier based on the chip identifier of the second data packet, and if the matching fails, the second data packet is forwarded to a next-stage chip; if the matching is successful, the downloading agent program receives the firmware in the second data packet, burns the firmware into the corresponding memory 12, and returns a second response to the upper computer after the burning is finished.
Further, the second data packet is transmitted in a fast start fastpool command format.
For example, the command format of the second data packet may be: FWx, chip denotes the chip, FWx denotes which firmware of the chip, e.g. the nth chip is programmed, using the fastboot command: system, which represents the system firmware for burning the nth chip.
Specifically, the chip identifier is a code of the chip, and the code of the chip can ensure the uniqueness of the identity information of the chip according to information such as a manufacturer, a chip type, a chip name, a chip order, chip verification and the like, thereby ensuring that different chips can have different chip identifiers.
Specifically, the second data packet includes the chip identification information, the second data packet is analyzed, a chip identification field in the second data packet is extracted, and a chip identification is obtained;
the self identification refers to the code of the chip, and the chip can directly read the self identification when the chip leaves a factory and is burnt in the chip;
the successful matching means that the chip identification information extracted from the second data packet is completely the same as the identification information of the chip;
the matching failure means that the chip identification information extracted from the second data packet is different from the identification information of the chip itself.
Specifically, the chips are connected step by step through PCIE, specifically, a mode in which the chip and the complex RC are directly connected to an end point EP of the next chip is used.
Specifically, the first-stage chip is configured to activate an interface of an upper computer, the other chips are configured to activate PCIE interfaces, an output-side PCIE interface of the first-stage chip is configured to be in an RC mode, an input-side PCIE interface of the last-stage chip is configured to be in an EP mode, an input-side PCIE interface of each stage of chip in the middle is configured to be in the EP mode, and an output-side PCIE interface of each stage of chip is configured to be in the RC mode.
That is to say, the PCIE interface at the output end of the chip may become an RC end, and the PCIE interface at the input end of the chip may be referred to as an EP end. The RC end of the chip can send data to the EP end of the next-level chip, and then communication between the RC end of the chip and EP end equipment is achieved.
Further, in the embodiment of the present application, each chip 11 includes a random access memory RAM, respectively, and the RAM is used for temporarily storing and operating the DA, and temporarily storing the firmware.
When each chip 11 receives the DA, the DA is temporarily stored in its own RAM, matching is performed based on the chip identifier in the first data packet and its own identifier, if matching is successful, the DA is run in the RAM, and if matching is failed, the DA is taken out from its own RAM and forwarded to the next-stage chip, that is, temporarily stored in the RAM of the next-stage chip;
when each chip 11 receives the firmware, the firmware is temporarily stored in its own RAM, and if the firmware is not the firmware matched with the chip, the firmware is taken out from its own RAM and forwarded to the next chip, that is, the firmware is temporarily stored in the RAM of the next chip; if the firmware is matched with the chip, the DA takes the firmware out of the RAM and burns the firmware into the corresponding memory 12.
Further, in this embodiment of the application, the RAMs in the chips other than the first-level chip are configured to be mapped to the PCIE interface at the output end of the upper-level chip.
Further, in this embodiment of the application, the upper computer interface may be a USB interface.
Further, in this embodiment of the application, the first-stage chip is configured to transmit the second data packet in a FIFO queue mode, for example, when the first-stage chip receives the firmware of the second-stage chip sent by the upper computer through the USB interface, and when the firmware is sent to the second-stage chip through the PCIE, the USB interface of the first-stage chip can continue to receive the firmware of the third-stage chip sent by the upper computer, so that it is ensured that the PCIE and the upper computer interface can work simultaneously, and the efficiency is improved.
According to the system for burning the PCIE cascade chip firmware, the first-level chip receives the downloading agent program from the upper computer, each chip downloads the downloading agent program matched with the chip to the internal RAM of the chip for operation, the downloading agent program receives the firmware matched with the chip and burns the firmware to the corresponding memory, burning of the firmware of each cascade chip can be achieved by only one upper computer interface, the PCIE interface with high speed interconnection is used for communication and receiving the firmware sent by the upper computer, the upper computer interface is saved, production procedures are reduced, and software version management is facilitated.
Example 2
Fig. 2 is a flowchart of a method for burning PCIE cascade chip firmware according to an embodiment of the present application, and the method for burning PCIE cascade chip firmware according to the present application is described in detail below with reference to fig. 2.
It should be noted that the method for burning the firmware of the PCIE cascade chip of the present application is applied to a plurality of chips that are cascaded through the PCIE, where a first-stage chip is configured with an upper computer interface for communicating with an upper computer;
in step 201, the first-level chip sequentially receives a first data packet sent to each chip by the upper computer through the upper computer interface;
in step 202, each chip matches the chip identifier in the first data packet with its own identifier, if the matching fails, the first data packet is forwarded to the next-stage chip, and if the matching succeeds, the downloading agent in the first data packet is run, and a first response is returned to the upper computer;
in step 203, the chip corresponding to the first response acquires a second data packet, and burns the firmware in the second data packet into a corresponding memory;
specifically, the step of returning a first response to the upper computer includes:
if the chip sending the first response is the first-level chip, sending the first response to the upper computer through the upper computer interface;
and if the chip sending the first response is not the first-level chip, sending the first response to the upper-level chip until the first-level chip receives the first response, and sending the first response to the upper computer through the upper computer interface.
Further, after the step of burning the firmware in the second data packet into the corresponding memory, the method further includes:
returning a second response to the upper computer;
and the upper computer sends the second data packet of the chip of the next level based on the second response.
Specifically, the step of returning a second response to the upper computer includes:
if the chip corresponding to the second response is the first-level chip, sending the second response to the upper computer through the upper computer interface;
and if the chip corresponding to the second response is not the first-level chip, sending the second response to the upper-level chip until the first-level chip receives the second response, and sending the second response to the upper computer through the upper computer interface.
The first-stage chip sends the first response returned by each chip to the upper computer through the upper computer interface in sequence, and sends the second response returned by each chip to the upper computer through the upper computer interface in sequence.
It should be noted that the explanation of the system for burning the PCIE cascade chip firmware in the foregoing embodiment is also applicable to the method for burning the PCIE cascade chip firmware in the foregoing embodiment, and details are not described here.
According to the method for burning the firmware of the PCIE cascade chips, the first-level chip receives the downloading agent program from the upper computer, each chip downloads the downloading agent program matched with the chip to the internal RAM of the chip for operation, the downloading agent program receives the firmware matched with the chip and burns the firmware to the corresponding memory, burning of the firmware of each cascade chip can be achieved by only one upper computer interface, the PCIE interface with high speed interconnection is used for communication and receiving the firmware sent by the upper computer, the upper computer interface is saved, production procedures are reduced, and management of software versions is facilitated.
Example 3
The present application is further explained and illustrated below by means of a specific embodiment.
Fig. 3 is a flowchart of a method for burning PCIE cascade chip firmware according to an embodiment of the present application, and the method for burning PCIE cascade chip firmware according to the present application is described in detail below with reference to fig. 3.
The method for burning the firmware of the PCIE cascade chip is applied to N chips which are cascaded through the PCIE, wherein a first-stage chip is provided with an upper computer interface and is used for communicating with an upper computer, and the method comprises the following steps:
in step 301, the upper computer sends a download agent DA of the chip 1 to the chip 1 through an upper computer interface;
in step 302, after receiving the DA, the chip 1 determines that the DA is the DA sent to the chip 1 by matching, runs the DA, initializes an upper computer interface, initializes a PCIE port, and returns a first response ACK to the upper computer;
in step 303, the upper computer sends the DA of the chip 2 to the chip 1 through the upper computer interface;
in step 304, after receiving the DA, the chip 1 determines that the DA is not the DA sent to itself through matching, and forwards the DA to the chip 2, and the chip 2 receives the DA, determines that the DA is the DA sent to itself through matching, runs the DA, initializes the PCIE port, and returns a first response ACK to the upper computer;
in step 305, the upper computer sends the DA of each chip to the chip 1 successively through the upper computer interface, and after each chip receives the DA sent to the chip 1 and the chip N, the PCIE ports are initialized respectively, and first response ACKs are returned to the upper computer respectively.
In step 306, after the upper computer receives the first responses returned by all the chips, the upper computer sends the firmware of the chip 1 to the chip 1 through the interface of the upper computer;
in step 307, after receiving the firmware, the chip 1 confirms that the firmware is sent to the chip 1 by matching, and then the DA receives the firmware, burns the firmware into the memory 1 corresponding to the chip 1, and returns a second response ACK to the upper computer after burning is completed;
in step 308, the upper computer sends the firmware of the chip 2 to the chip 1 through the upper computer interface;
in step 309, after receiving the firmware, the chip 1 confirms that the firmware is not sent to the chip 1 by matching, and forwards the firmware to the chip 2, and when the chip 2 receives the firmware, confirms that the firmware is sent to the chip 2 by matching, the DA receives the firmware, burns the firmware into the memory 2 corresponding to the chip 2, returns a second response to the chip 1, and sends a second response ACK to the upper computer by the chip 1;
in step 310, the upper computer sequentially sends the firmware of each chip to the chip 1 through the upper computer interface, and after each chip receives the firmware sent to the upper computer interface, the chip receives the firmware through the DA, burns the firmware into the memory corresponding to the chip, and respectively sends a second response to the upper chip until the chip 1 receives a second response ACK and sends the second response ACK to the upper computer interface.
According to the method for burning the firmware of the PCIE cascade chips, the first-level chip receives the downloading agent program from the upper computer, each chip downloads the downloading agent program matched with the chip to the internal RAM of the chip for operation, the downloading agent program receives the firmware matched with the chip and burns the firmware to the corresponding memory, burning of the firmware of each cascade chip can be achieved by only one upper computer interface, the PCIE interface with high speed interconnection is used for communication and receiving the firmware sent by the upper computer, the upper computer interface is saved, production procedures are reduced, and management of software versions is facilitated.
Example 4
Fig. 4 is a schematic diagram of a chip structure according to an embodiment of the present application. Referring to fig. 4, the system 30 for firmware burning of PCIE cascade chips as described above is integrated on the chip 40.
Example 5
Fig. 5 is a schematic diagram of a circuit board structure according to an embodiment of the present application. Referring to fig. 5, the circuit board 50 includes the chip 40 thereon as described above.
Example 6
Fig. 6 is a schematic diagram of a vehicle machine structure according to an embodiment of the application. Referring to fig. 6, the cart machine 60 includes the chip 40 as described above.
Example 7
In one embodiment of the present application, there is also provided a computer-readable storage medium, which may be included in the system described in the above embodiment; or may exist separately and not be assembled into the system. The computer-readable storage medium carries one or more computer instructions which, when executed, implement the steps of the FIFO buffer control method of the embodiments.
In embodiments of the present application, the computer-readable storage medium may be a non-volatile computer-readable storage medium, which may include, for example but is not limited to: a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this application, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
Those of ordinary skill in the art will understand that: although the present application has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments described above, or equivalents may be substituted for elements thereof. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (18)
1. A system of PCIE cascade chips is characterized by comprising a plurality of chips which are cascaded through PCIE and a memory corresponding to each chip, wherein a first-stage chip is provided with an upper computer interface and is used for communicating with an upper computer;
the first-stage chip is configured to sequentially receive a first data packet sent to each chip by the upper computer through the upper computer interface;
each chip is configured to match the chip identifier in the first data packet with the identifier of the chip based on the chip identifier, if the matching fails, the first data packet is forwarded to a next-stage chip, and if the matching succeeds, a downloading agent program in the first data packet is operated, and a first response is returned to the upper computer;
the chip corresponding to the first response is configured to acquire a second data packet sent by the upper computer and burn the firmware in the second data packet into the corresponding memory.
2. The system of claim 1, wherein the chip corresponding to the first response is further configured to return a second response to the upper computer after completion of the burning;
and the upper computer sends the second data packet of the chip of the next level based on the second response.
3. The system of claim 2, wherein the first level chips are further configured to send the first response returned by each chip to the host computer through the host computer interface in sequence, and send the second response returned by each chip to the host computer through the host computer interface in sequence.
4. The system of claim 1, wherein the first-stage chip is configured to be activated by an upper computer interface, the other chips are configured to be activated by PCIE interfaces, an output PCIE interface of the first-stage chip is configured to be in a root complex mode, an input PCIE interface of the last-stage chip is configured to be in an endpoint mode, an input PCIE interface of each intermediate-stage chip is configured to be in the endpoint mode, and an output PCIE interface of each intermediate-stage chip is configured to be in the root complex mode.
5. The system of claim 1, wherein each of the chips comprises a random access memory for temporarily storing and running the download agent and for temporarily storing the firmware.
6. The system of claim 5, wherein after power-on, the random access memories in the chips other than the first-level chip are configured to be mapped to the output PCIE interface of the upper-level chip.
7. The system of claim 1, wherein the first data packet includes the chip identifier and the download agent, and wherein the second data packet includes the chip identifier and the firmware.
8. The system of claim 1, wherein the second data packet is transmitted in a fast start command format.
9. The system of claim 1, wherein the first level chip is configured to transmit the second packet via a first-in-first-out queuing mode.
10. A method for firmware burning of PCIE cascade chips, which is applied to the system according to any one of claims 1 to 9, and the method includes:
the first-level chip sequentially receives a first data packet sent to each chip by the upper computer through the upper computer interface;
each chip is matched with the own identifier based on the chip identifier in the first data packet, if the matching fails, the first data packet is forwarded to the next-level chip, and if the matching succeeds, a downloading agent program in the first data packet is operated, and a first response is returned to the upper computer;
and the chip corresponding to the first response acquires a second data packet sent by the upper computer, and burns the firmware in the second data packet into a corresponding memory.
11. The method of claim 10, wherein the step of returning a first response to the host computer comprises:
if the chip sending the first response is the first-level chip, sending the first response to the upper computer through the upper computer interface;
and if the chip sending the first response is not the first-level chip, sending the first response to the upper-level chip until the first-level chip receives the first response, and sending the first response to the upper computer through the upper computer interface.
12. The method of claim 10, further comprising, after the step of burning the firmware in the second data packet into the corresponding memory:
after the burning is finished, a second response is returned to the upper computer;
and the upper computer sends the second data packet of the chip of the next stage based on the second response.
13. The method of claim 12, wherein the step of returning a second response to the host computer comprises:
if the chip sending the second response is the first-level chip, sending the second response to the upper computer through the upper computer interface;
and if the chip for sending the second response is not the first-level chip, sending the second response to the upper-level chip until the first-level chip receives the second response, and sending the second response to the upper computer through the upper computer interface.
14. A chip, wherein the system for firmware burning of PCIE cascade chips as claimed in any one of claims 1 to 9 is integrated on the chip.
15. A circuit board comprising the chip of claim 14.
16. A vehicle machine, characterized in that said vehicle machine comprises the chip of claim 14.
17. An electronic device comprising a memory and a processor, wherein the memory has stored therein computer instructions, and the processor is configured to execute the instructions to perform the steps of the method for PCIE cascade chip firmware burning as recited in any one of claims 10 to 13.
18. A computer-readable storage medium having stored thereon computer instructions which, when executed, perform the method for firmware burning of PCIE cascade chips as claimed in any one of claims 10 to 13.
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| CN202310156381.1A CN115904418A (en) | 2023-02-23 | 2023-02-23 | System and method for burning firmware of PCIE (peripheral component interface express) cascade chip |
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| CN202310156381.1A CN115904418A (en) | 2023-02-23 | 2023-02-23 | System and method for burning firmware of PCIE (peripheral component interface express) cascade chip |
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Application publication date: 20230404 |