CN115904418A - A system and method for burning PCIE cascade chip firmware - Google Patents

Abstract

A system for burning firmware of PCIE cascade chips comprises a plurality of chips cascaded by PCIE and a memory corresponding to each chip, wherein a first-stage chip is provided with an upper computer interface and is used for communicating with an upper computer; the first-stage chip is configured to sequentially receive a first data packet sent to each chip by an upper computer through an upper computer interface; each chip is configured to match the chip identifier in the first data packet with the identifier of the chip, if the matching fails, the first data packet is forwarded to the next-level chip, and if the matching succeeds, the downloading agent program in the first data packet is operated, and a first response is returned to the upper computer; and the chip corresponding to the first response acquires the second data packet and burns the firmware in the second data packet into the corresponding memory. The application also provides a method for burning the PCIE cascade chip firmware, which can realize the burning of each cascade chip firmware by only using one upper computer interface, thereby saving the upper computer interface.

Description

A system and method for burning PCIE cascade chip firmware

technical field

The present application relates to the field of data processing, in particular to a system and method for programming firmware of PCIE cascaded chips.

Background technique

Scenarios with high computing power requirements, such as autonomous driving and AI computing, sometimes the computing power of a single chip may not meet the demand, thus requiring two or more chips to be cascaded, and each chip needs to be independently loaded with firmware to run. In order to facilitate circuit layout, software package management and production process, the circuit board reserves an interface to communicate with the host computer to download all chip firmware or other operations. At present, the commonly used method is to reserve the host computer interface for each chip to program their own firmware. Each chip has its own memory and firmware. If the host computer is connected to the chip through the host computer interface of each chip to burn Writing firmware, there will be the following problems: increasing the consumption of chip pins, resulting in a decrease in available pins, increasing the complexity of circuit wiring, increasing the difficulty of software version management, and increasing the production process.

Contents of the invention

In order to solve at least one problem existing in the prior art, the purpose of this application is to provide a method and system for programming PCIE cascaded chip firmware, which can realize the programming of other chip firmware with only one host computer interface. The high-speed interconnection PCIE interface communicates and receives the firmware sent by the upper computer, thus saving the upper computer interface, reducing the production process, and facilitating software version management.

In order to achieve the above object, the application provides a PCIE cascade chip firmware programming system, the PCIE cascade chip firmware programming system includes a plurality of chips cascaded through PCIE and a memory corresponding to each chip , wherein the first-level chip is configured with a host computer interface for communicating with the host computer;

The first-level chip is configured to sequentially receive the first data packet sent by the host computer to each of the chips through the host computer interface;

Each of the chips is configured to match the chip identification in the first data packet with its own identification, if the matching fails, forward the first data packet to the next-level chip, and if the matching is successful, Then run the download agent program in the first data packet, and return the first response to the host computer;

The chip corresponding to the first response is configured to obtain the second data packet sent by the host computer, and burn the firmware in the second data packet to the corresponding memory.

Further, the chip corresponding to the first response is further configured to return a second response to the host computer after the programming is completed;

The host computer sends the second data packet of the chip at the next level based on the second response.

Further, the first-level chip is also configured to sequentially send the first response returned by each chip to the host computer through the host computer interface, and sequentially send each response to the host computer through the host computer interface. The second response returned by the chip is sent to the host computer.

Further, the first-level chip is configured to start the host computer interface, and other chips are configured to start the PCIE interface, the output PCIE interface of the first-level chip is configured as the root complex mode, and the last-level chip The input PCIE interface of the chip is configured as an endpoint mode, the input PCIE interface of each intermediate chip is configured as an endpoint mode, and the output PCIE interface is configured as a root complex mode.

Further, each of the chips includes a random access memory, and the random access memory is used for temporarily storing and running the download agent program, and temporarily storing the firmware.

Further, after power-on, random access memories in other chips except the first-level chip are configured to be mapped to the output PCIE interface of the upper-level chip.

Further, the first data packet includes the chip identification and the download agent program, and the second data packet includes the chip identification and the firmware.

Further, the second data packet is transmitted in a quick start command format.

Further, the first-level chip is configured to transmit the second data packet in a first-in-first-out queue mode.

In order to achieve the above purpose, the present application also provides a method for burning PCIE cascade chip firmware, including:

The first-level chips sequentially receive the first data packets sent by the host computer to each of the chips through the host computer interface;

Each of the chips performs matching based on the chip identification in the first data packet and its own identification, if the matching fails, the first data packet is forwarded to the next-level chip, and if the matching is successful, the Download the agent program in the first data packet, and return the first response to the host computer;

The chip corresponding to the first response obtains the second data packet sent by the host computer, and burns the firmware in the second data packet into the corresponding memory.

Further, the step of returning the first response to the host computer includes:

If the chip sending the first response is the first-level chip, sending the first response to the host computer through the host computer interface;

If the chip that sends the first response is not the first-level chip, then send the first response to the upper-level chip until the first-level chip receives the first response, and through the host computer The interface sends the first response to the host computer.

Further, after the step of burning the firmware in the second data package to the corresponding memory, it also includes:

Returning a second response to the host computer after the burning is completed;

The host computer sends the second data packet of the chip at the next level based on the second response.

Further, the step of returning the second response to the host computer includes:

If the chip sending the second response is the first-level chip, sending the second response to the host computer through the host computer interface;

If the chip that sends the second response is not the first-level chip, then send the second response to the upper-level chip until the first-level chip receives the second response, and through the host computer The interface sends the second response to the host computer.

To achieve the above purpose, the present application also provides a chip on which the above-mentioned PCIE cascade chip firmware programming system is integrated.

In order to achieve the above purpose, the present application also provides a circuit board, including the above-mentioned chip.

In order to achieve the above purpose, the present application also provides a car machine, including the above-mentioned chip.

To achieve the above object, the present application also provides electronic equipment, including a memory and a processor, wherein computer instructions are stored in the memory, and the processor is configured to run the instructions to perform the above-mentioned The steps of the method for burning PCIE cascade chip firmware.

To achieve the above object, the present application also provides a computer-readable storage medium, on which computer instructions are stored, and when the computer instructions are executed, the steps of the method for burning the firmware of the PCIE cascade chip as described above are executed.

A kind of PCIE cascading chip firmware burning method and system of the present application, receive download agent program from upper computer through first-level chip, each chip downloads the download agent program that matches itself to the internal RAM operation of chip, and then The download agent program receives the firmware that matches itself and writes it to the corresponding memory. It can realize the programming of each cascaded chip firmware with only one host computer interface, and use the high-speed interconnection PCIE interface to communicate and receive the firmware sent by the host computer. , thus saving the host computer interface, reducing the production process, and facilitating software version management.

Additional features and advantages of the application will be set forth in the description which follows, and, in part, will be obvious from the description, or may be learned by practice of the application.

Description of drawings

The accompanying drawings are used to provide a further understanding of the present application, and constitute a part of the description, and together with the embodiments of the present application, are used to explain the present application, and do not constitute a limitation to the present application. In the attached picture:

Fig. 1 is a system structure block diagram of PCIE cascade chip firmware burning according to another embodiment of the present application;

Fig. 2 is a flow chart of a method for burning PCIE cascade chip firmware according to an embodiment of the present application;

Fig. 3 is a flow chart of a method for burning PCIE cascade chip firmware according to another embodiment of the present application;

FIG. 4 is a schematic diagram of a chip structure according to an embodiment of the present application;

FIG. 5 is a schematic structural diagram of a circuit board according to an embodiment of the present application;

Fig. 6 is a schematic structural diagram of a car machine according to an embodiment of the present application.

Detailed ways

Embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present application are shown in the drawings, it should be understood that the application may be embodied in various forms and should not be construed as limited to the embodiments set forth herein; A more thorough and complete understanding of the application. It should be understood that the drawings and embodiments of the present application are for exemplary purposes only, and are not intended to limit the protection scope of the present application.

It should be understood that the various steps described in the method implementations of the present application may be executed in different orders, and/or executed in parallel. Additionally, method embodiments may include additional steps and/or omit performing illustrated steps. The scope of the application is not limited in this respect.

As used herein, the term "comprise" and its variations are open-ended, ie "including but not limited to". The term "based on" is "based at least in part on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one further embodiment"; the term "some embodiments" means "at least some embodiments." Relevant definitions of other terms will be given in the description below.

It should be noted that the "first", "second", etc. mentioned in this application are only used to distinguish different devices, modules, units or data, and are not used to limit the implementation of these devices, modules, units or data. The sequence or interdependence of functions.

It should be noted that the modifications of "one" and "multiple" mentioned in this application are illustrative and not restrictive. Those skilled in the art should understand that unless the context clearly indicates otherwise, it should be understood as "one or more" multiple". "Plurality" should be understood as two or more.

Hereinafter, embodiments of the present application will be described in detail with reference to the drawings.

Firmware: Firmware refers to the program written in EROM (Erasable ROM, erasable read-only memory) and EEPROM (Electrically Erasable Programmable ROM, electrically erasable programmable read-only memory), that is, the device "driver" stored inside the device program";

Burning: It is the process of writing the program into the chip after compiling the written program to form a HEX or BIN file;

DA: Download Agent, download agent;

PCIE: Peripheral Component Interconnect express, is a high-speed serial computer expansion bus standard;

RAM: Random Access Memory, random access memory;

RC: Root Complex, a root complex device, a component in the PCIe protocol;

EP: Endpoint, an endpoint, a component in the PCIe protocol;

USB: Universal Serial Bus, Universal Serial Bus, is an external bus standard used to regulate the connection and communication between computers and external devices;

Fastboot, fast boot, is a firmware communication protocol for a computer to flash, erase/format, debug, and transmit various instructions to the phone firmware through a USB data cable;

FIFO, First Input First Output, first in first out, the command entered first is completed and retired first, and then the second command is executed.

Example 1

Fig. 1 is a system structure diagram of PCIE cascade chip firmware programming according to an embodiment of the present application. Referring to Fig. 1, the system 10 of PCIE cascade chip firmware burning in the embodiment of the present application includes a plurality of chips 11 cascaded through PCIE and a memory 12 corresponding to each chip, and the chip 11 includes: a first First-level chips, second-level chips...Nth-level chips, each chip is cascaded through PCIE, and the memory 12 includes memory 1, memory 2...memory N, wherein memory 1 and The corresponding first-level chip is connected, the memory 2 is connected with the corresponding second-level chip...the memory N is connected with the corresponding Nth-level chip, and only the first-level chip is equipped with a host computer interface for communicating with The upper computer communicates;

The first-level chip is configured to sequentially receive the first data packet sent to each chip 11 by the host computer through the host computer interface;

Each of the chips 11 is configured to match the chip identification in the first data packet with its own identification, if the matching fails, forward the first data packet to the next-level chip, and if the matching is successful , then run the download agent program in the first data packet, and return the first response to the host computer;

The chip 11 corresponding to the first response is configured to obtain the second data packet sent by the host computer, and burn the firmware in the second data packet to the corresponding memory 12 .

Further, in the embodiment of the present application, the chip corresponding to the first response is further configured to return a second response to the host computer after the programming is completed;

The host computer sends the second data packet of the next-level chip based on the second response.

Specifically, the first data packet is constructed and sent by the host computer, and the first data packet includes a chip identification and a download agent program, and the first-level chip refers to a chip directly connected to the host computer through an interface of the host computer , the host computer interface of the first-level chip directly receives the first data packet sent by the host computer, and the host computer interface refers to an interface through which the first-level chip can communicate with the host computer, such as a USB interface.

Further, in the embodiment of the present application, the first-level chip is further configured to send the first response to the host computer through the host computer interface, and send the first response to the host computer through the host computer interface. The second response is sent to the upper computer.

That is to say, the host computer needs to send the download agent program of each chip 11 in turn. For example, the host computer first sends the download agent program of the first-level chip through the host computer interface. The computer returns the first response, and the host computer sends the download agent program of the second-level chip to the first-level chip through the host computer interface. After the first-level chip receives the download agent program and fails to match, it forwards it to the second-level chip. After receiving the successful matching of the download agent program, the second-level chip sends the first response to the upper computer to the first-level chip. After receiving the first response, the first-level chip sends it to the upper computer; the upper computer receives the second-level chip and returns Send the download agent program of the third-level chip after the first response of After the first response, the host computer starts to send the firmware of each chip 11 in turn. For example, the host computer first sends the firmware of the first-level chip through the interface of the host computer. After the first-level chip is successfully matched, the DA of the first-level chip receives and Burn the firmware to the memory 1 corresponding to the first-level chip, return the second response to the upper computer through the host computer interface, and then send the firmware of the second-level chip to the first-level chip through the upper computer interface, and the first-level chip matches After the failure, it is forwarded to the second-level chip. After the second-level chip receives the firmware and matches successfully, the DA of the second-level chip receives and writes the firmware to the corresponding memory 2 of the second-level chip, and sends it to the first-level chip to the upper The second response of the computer, the first-level chip sends it to the host computer after receiving the second response; the host computer sends the firmware of the third-level chip after receiving the second response returned by the second-level chip... By analogy, until the host computer finishes sending the firmware of the last chip, that is, the Nth-level chip, and receives the second response returned by the last chip, that is, the Nth-level chip.

Further, in the embodiment of the present application, the first data packet includes the chip identification and the download agent program, and the second data packet includes the chip identification and the firmware.

Specifically, the chip identification is the code of the chip, and the code of the chip can ensure the uniqueness of the identity information of the chip according to information such as the manufacturer, chip type, chip name, chip sequence, and chip verification, thereby ensuring that different chips can have different chip codes. logo.

Specifically, the first data packet includes the chip identification, and the chip parses the first data packet, extracts the chip identification field therein, and obtains the chip identification;

The self-identification refers to the code of the chip at this level. When the chip leaves the factory and is programmed inside the chip, the chip can directly read its own identification;

The successful matching means that the chip identification extracted in the first data packet is completely the same as the identification of the chip itself;

The matching failure means that the chip identifier extracted in the first data packet is different from the chip's own identifier.

The first-level chip runs the download agent program, which is used to initialize the host computer interface and initialize the PCIE port. The initialized host computer interface is ready to receive the data sent by the host computer and send a response to the host computer. The initialized PCIE port is ready to send to the host computer. The next-level chip sends data;

Other chips run the download agent program to initialize the PCIE port, and the initialized PCIE port is ready to receive the data sent by the upper level chip and send data to the lower level chip.

After each chip receives the second data packet sent to itself, the function of the download agent program is to receive the firmware and burn the firmware into the memory 12 corresponding to the chip.

The second data packet is constructed and sent by the host computer, the second data packet includes chip identification and firmware, and the first-level chip receives the second data sent to each chip by the host computer in turn through the interface of the host computer. data pack;

Each of the chips matches the chip identification of the second data packet with its own identification. If the matching fails, the second data packet is forwarded to the next-level chip; The agent program receives the firmware in the second data packet, burns the firmware into the corresponding memory 12, and returns a second response to the host computer after the burning is completed.

Further, the second data packet is transmitted in the Fastboot command format.

For example, the command format of the second data packet can be: chipid:FWx, chipid indicates which chip, and FWx indicates which firmware of the chip. Write the system firmware of the Nth chip.

Specifically, the chip identification is the code of the chip, and the code of the chip can ensure the uniqueness of the identity information of the chip according to information such as the manufacturer, chip type, chip name, chip sequence, and chip verification, thereby ensuring that different chips can have different chip codes. logo.

Specifically, the second data packet includes the chip identification information, the second data packet is parsed, and the chip identification field is extracted to obtain the chip identification;

The self-identification refers to the code of the chip. When the chip leaves the factory and is programmed inside the chip, the chip can directly read its own identification;

The successful matching means that the chip identification information extracted in the second data packet is completely the same as the identification information of the chip itself;

The matching failure means that the identification information of the chip extracted in the second data packet is different from the identification information of the chip itself.

Specifically, the chips are connected step by step through PCIE, specifically, the link complex RC of the chip is directly connected to the endpoint EP of the next-level chip.

Specifically, the first-level chip is configured to start the host computer interface, and other chips are configured to start the PCIE interface. The output PCIE interface of the first-level chip is configured as RC mode, and the input of the last-level chip The terminal PCIE interface is configured in EP mode, the input PCIE interface of each intermediate chip is configured in EP mode, and the output PCIE interface is configured in RC mode.

That is to say, the PCIE interface at the output end of the chip can be called an RC end, and the PCIE interface at the input end of the chip can be called an EP end. The RC end of the chip can send data to the EP end of the next-level chip, and then realize the communication with the EP end device.

Further, in the embodiment of the present application, each chip 11 includes a random access memory RAM, and the RAM is used for temporarily storing and running the DA, and temporarily storing the firmware.

When each chip 11 receives the DA, it will temporarily store the DA in its own RAM, based on the chip identification in the first data packet and its own identification to match, if the matching is successful, then run the DA in the RAM, if If the matching fails, the DA is taken out from its own RAM and forwarded to the next-level chip, that is, it is temporarily stored in the RAM of the next-level chip;

When each chip 11 receives the firmware, it will temporarily store the firmware in its own RAM. If it is not the firmware that matches this chip, it will take out the firmware from its own RAM and forward it to the next-level chip, that is, temporarily store it in the next-level chip. If it matches the firmware of the chip, the DA takes the firmware out of the RAM and burns it into the corresponding memory 12.

Further, in the embodiment of the present application, the RAMs in other chips except the first-level chip are configured to be mapped to the output PCIE interface of the upper-level chip.

Further, in the embodiment of the present application, the host computer interface may be a USB interface.

Further, in the embodiment of the present application, the first-level chip is configured to transmit the second data packet through the first-in-first-out FIFO queue mode, for example, when the first-level chip receives the second packet sent by the host computer through the USB interface. The firmware of the first-level chip, while sending the firmware to the second-level chip through PCIE, the USB interface of the first-level chip can continue to receive the firmware of the third-level chip sent by the host computer, ensuring that the PCIE and the host computer interface can work at the same time, Improve efficiency, so the use of FIFO queues can keep full load transmission on the host computer interface.

According to the system of a kind of PCIE cascading chip firmware burning of the present application, the download agent program is received from the upper computer through the first-level chip, and each chip downloads the download agent program matched with itself to the internal RAM of the chip to run, and then the The download agent program receives the firmware that matches itself and writes it to the corresponding memory. It can realize the firmware programming of each cascaded chip with only one host computer interface, and use the high-speed interconnection PCIE interface to communicate and receive the firmware sent by the host computer. Thus saving the host computer interface, reducing the production process, and facilitating software version management.

Example 2

FIG. 2 is a flow chart of a method for burning PCIE cascade chip firmware according to an embodiment of the present application. The method for burning PCIE cascade chip firmware of the present application will be described in detail below with reference to FIG. 2 .

It should be noted that the PCIE cascade chip firmware programming method of the present application is applied to multiple chips cascaded through PCIE, wherein the first-level chip is configured with a host computer interface for communicating with the host computer;

In step 201, the first-level chip sequentially receives the first data packet sent by the host computer to each of the chips through the host computer interface;

In step 202, each chip performs matching based on the chip identification in the first data packet and its own identification, if the matching fails, the first data packet is forwarded to the next-level chip, if the matching is successful, Then run the download agent program in the first data packet, and return the first response to the host computer;

In step 203, the chip corresponding to the first response obtains a second data packet, and burns the firmware in the second data packet into a corresponding memory;

Specifically, the step of returning the first response to the host computer includes:

If the chip sending the first response is the first-level chip, sending the first response to the host computer through the host computer interface;

If the chip that sends the first response is not the first-level chip, then send the first response to the upper-level chip until the first-level chip receives the first response, and through the host computer The interface sends the first response to the host computer.

Further, after the step of burning the firmware in the second data package to the corresponding memory, it also includes:

returning a second response to the host computer;

The host computer sends the second data packet of the next-level chip based on the second response.

Specifically, the step of returning the second response to the host computer includes:

If the chip corresponding to the second response is the first-level chip, sending the second response to the host computer through the host computer interface;

If the chip corresponding to the second response is not the first-level chip, send the second response to the upper-level chip until the first-level chip receives the second response. The host computer interface sends the second response to the host computer.

The first-level chips sequentially send the first responses returned by each chip to the host computer through the host computer interface, and sequentially send the second responses returned by each chip through the host computer interface. The response is sent to the host computer.

It should be noted that, the explanations of the system for burning the firmware of the PCIE cascade chip in the above embodiment are also applicable to the method for burning the firmware of the PCIE cascade chip in the above embodiment, and will not be repeated here.

According to a kind of PCIE cascade chip firmware burning method of the present application, receive download agent program from upper computer by first-level chip, each chip downloads the download agent program that matches itself to the internal RAM operation of chip, then by The download agent program receives the firmware that matches itself and writes it to the corresponding memory. It can realize the firmware programming of each cascaded chip with only one host computer interface, and use the high-speed interconnection PCIE interface to communicate and receive the firmware sent by the host computer. Thus saving the host computer interface, reducing the production process, and facilitating software version management.

Example 3

The present application will be further explained and illustrated through a specific embodiment below.

FIG. 3 is a flowchart of a method for burning PCIE cascade chip firmware according to an embodiment of the present application. The method for burning PCIE cascade chip firmware of the present application will be described in detail below with reference to FIG. 3 .

The PCIE cascade chip firmware burning method of the embodiment of the present application is applied to N chips cascaded through PCIE, wherein the first-level chip is configured with a host computer interface for communicating with the host computer. The method includes the following steps :

In step 301, the host computer sends the download agent program DA of chip 1 to chip 1 through the interface of the host computer;

In step 302, chip 1 receives the DA and confirms that it is the DA sent to itself through matching, runs the DA, initializes the host computer interface, initializes the PCIE port, and returns the first response ACK to the host computer;

In step 303, the host computer sends the DA of chip 2 to chip 1 through the interface of the host computer;

In step 304, chip 1 receives the DA and confirms that it is not the DA for itself through matching, and forwards the DA to chip 2. After receiving the DA, chip 2 confirms that it is the DA for itself after matching, runs the DA, and initializes the PCIE port. And return the first response ACK to the upper computer;

In step 305, the host computer sends the DA of each chip to chip 1 successively through the host computer interface, from chip 1 to chip N. After each chip receives the DA sent to itself, it initializes the PCIE port respectively and returns to the host computer respectively. First response ACK.

In step 306, after the host computer receives the first responses returned by all chips, it sends the firmware of chip 1 to chip 1 through the interface of the host computer;

In step 307, after the chip 1 receives the firmware, it is confirmed by matching that it is the firmware sent to itself, then the DA receives the firmware, burns the firmware into the memory 1 corresponding to the chip 1, and returns it to the host computer after the burning is completed. The second response ACK;

In step 308, the host computer sends the firmware of chip 2 to chip 1 through the interface of the host computer;

In step 309, after receiving the firmware, chip 1 confirms that it is not the firmware for itself through matching, and forwards the firmware to chip 2, and chip 2 receives the firmware and confirms that it is the firmware for itself after matching, then DA receives the firmware , burn the firmware into the memory 2 corresponding to the chip 2, and return a second response to the chip 1, and then the chip 1 sends the second response ACK to the upper computer;

In step 310, the host computer sends the firmware of each chip to chip 1 in turn through the host computer interface, from chip 1 to chip N, after each chip receives the firmware sent to itself, its DA receives the firmware and transfers the Burn the above firmware into the memory corresponding to the chip, and send the second response to the upper-level chip respectively until the chip 1 receives the second response ACK and sends it to the host computer.

According to a kind of PCIE cascade chip firmware burning method of the present application, receive download agent program from upper computer by first-level chip, each chip downloads the download agent program that matches itself to the internal RAM operation of chip, then by The download agent program receives the firmware that matches itself and writes it to the corresponding memory. It can realize the firmware programming of each cascaded chip with only one host computer interface, and use the high-speed interconnection PCIE interface to communicate and receive the firmware sent by the host computer. Thus saving the host computer interface, reducing the production process, and facilitating software version management.

Example 4

FIG. 4 is a schematic diagram of a chip structure according to an embodiment of the present application. As shown in FIG. 4 , the chip 40 is integrated with the PCIE cascade chip firmware programming system 30 as described above.

Example 5

FIG. 5 is a schematic structural diagram of a circuit board according to an embodiment of the present application. Referring to FIG. 5 , the circuit board 50 includes the above-mentioned chip 40 .

Example 6

Fig. 6 is a schematic structural diagram of a car machine according to an embodiment of the present application. Referring to FIG. 6 , the vehicle machine 60 includes the above-mentioned chip 40 .

Example 7

In one embodiment of the present application, a computer-readable storage medium is also provided, and the computer-readable storage medium may be contained in the system described in the above-mentioned embodiments; or it may exist independently without being assembled into the system middle. The above-mentioned computer-readable storage medium carries one or more computer instructions, and when the one or more computer instructions are executed, the steps of the FIFO buffer control method of the above-mentioned embodiments are realized.

In the embodiment of the present application, the computer-readable storage medium may be a non-volatile computer-readable storage medium, such as may include but not limited to: portable computer disk, hard disk, random access memory (RAM), read-only memory (ROM), Erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

Those of ordinary skill in the art can understand that: the above is only a preferred embodiment of the application, and is not intended to limit the application. Although the application has been described in detail with reference to the foregoing embodiments, for those skilled in the art, it still The technical solutions described in the foregoing embodiments may be modified, or some technical features thereof may be equivalently replaced. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this application shall be included within the protection scope of this application.

Claims (18)

1. A system of PCIE cascaded chips, characterized in that, comprises a plurality of chips cascaded by PCIE and a memory corresponding to each said chip, wherein the first-level chip is configured with a host computer interface for communicating with the host machine to communicate; The first-level chip is configured to sequentially receive the first data packet sent by the host computer to each of the chips through the host computer interface; Each of the chips is configured to match the chip identification in the first data packet with its own identification, if the matching fails, forward the first data packet to the next-level chip, and if the matching is successful, Then run the download agent program in the first data packet, and return the first response to the host computer; The chip corresponding to the first response is configured to obtain the second data packet sent by the host computer, and burn the firmware in the second data packet to the corresponding memory. 2. The system according to claim 1, wherein the chip corresponding to the first response is further configured to return a second response to the host computer after programming is completed; The host computer sends the second data packet of the chip at the next level based on the second response. 3. The system according to claim 2, wherein the first-level chips are further configured to sequentially send the first responses returned by each chip to the host computer through the host computer interface , and sequentially sending the second response returned by each chip to the host computer through the host computer interface. 4. system according to claim 1, is characterized in that, described first-level chip is configured to host computer interface and starts, and other each chip is configured to start with PCIE interface, and the output end PCIE interface of described first-level chip It is configured as root complex mode, the input PCIE interface of the last chip is configured as endpoint mode, the input PCIE interface of each intermediate chip is configured as endpoint mode, and the output PCIE interface is configured as root complex mode . 5. The system according to claim 1, wherein each of the chips includes a random access memory, and the random access memory is used for temporarily storing and running the download agent program, and temporarily storing the firmware. 6. The system according to claim 5, wherein after power-on, random access memories in other chips except the first-level chip are configured to be mapped to the output PCIE interface of the upper-level chip. 7. The system according to claim 1, wherein the first data packet includes the chip identification and the download agent program, and the second data packet includes the chip identification and the firmware. 8. The system according to claim 1, wherein the second data packet is transmitted in a quick start command format. 9. The system according to claim 1, wherein the first-level chip is configured to transmit the second data packet in a first-in first-out queue mode. 10. A method for burning PCIE cascade chip firmware, applied to the system according to any one of claims 1 to 9, the method comprising: The first-level chips sequentially receive the first data packets sent by the host computer to each of the chips through the host computer interface; Each of the chips performs matching based on the chip identification in the first data packet and its own identification, if the matching fails, the first data packet is forwarded to the next-level chip, and if the matching is successful, the Download the agent program in the first data packet, and return the first response to the host computer; The chip corresponding to the first response obtains the second data packet sent by the host computer, and burns the firmware in the second data packet into the corresponding memory. 11. The method according to claim 10, wherein the step of returning the first response to the host computer comprises: If the chip sending the first response is the first-level chip, sending the first response to the host computer through the host computer interface; If the chip that sends the first response is not the first-level chip, then send the first response to the upper-level chip until the first-level chip receives the first response, and through the host computer The interface sends the first response to the host computer. 12. The method according to claim 10, characterized in that, after the step of burning the firmware in the second data package to the corresponding memory, further comprising: Returning a second response to the host computer after the burning is completed; The host computer sends the second data packet of the chip at the next level based on the second response. 13. The method according to claim 12, wherein the step of returning a second response to the host computer comprises: If the chip sending the second response is the first-level chip, sending the second response to the host computer through the host computer interface; If the chip that sends the second response is not the first-level chip, then send the second response to the upper-level chip until the first-level chip receives the second response, and through the host computer The interface sends the second response to the host computer. 14. A chip, characterized in that the chip is integrated with the PCIE cascade chip firmware programming system according to any one of claims 1-9. 15. A circuit board, characterized in that the circuit board comprises the chip according to claim 14. 16. An on-board machine, characterized in that the on-board machine comprises the chip according to claim 14. 17. An electronic device, comprising a memory and a processor, wherein computer instructions are stored in the memory, and the processor is configured to run the instructions to perform any one of claims 10-13 The steps of the method for burning the firmware of the PCIE cascade chip. 18. A computer-readable storage medium, characterized in that computer instructions are stored thereon, and when the computer instructions run, the method for burning the PCIE cascade chip firmware according to any one of claims 10-13 is executed.

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