TWI774255B - Bridge circuit and computer system - Google Patents

Bridge circuit and computer system Download PDF

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TWI774255B
TWI774255B TW110107558A TW110107558A TWI774255B TW I774255 B TWI774255 B TW I774255B TW 110107558 A TW110107558 A TW 110107558A TW 110107558 A TW110107558 A TW 110107558A TW I774255 B TWI774255 B TW I774255B
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nvme
tcp
data
circuit
storage
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TW110107558A
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TW202143035A (en
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賴瑾
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威盛電子股份有限公司
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Priority to US17/234,751 priority patent/US11442882B2/en
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Abstract

A bridge circuit includes an NVMe device controller, a network subsystem, and a data transfer circuit. The NVMe device controller is used to communicate with a host via a PCIe bus. The network subsystem is used to communicate with an NVMe-TCP device via a network. The data transfer circuit is coupled between the NVMe device controller and the network subsystem, and is used to deal with data transfer associated with the NVMe-TCP device without intervention of the host.

Description

橋接電路與電腦系統 Bridging circuits and computer systems

本發明係有關於資料處理,尤指一種可於PCIe-NVMe協定與NVMe-TCP協定之間提供轉換的橋接電路與採用此橋接電路的電腦系統。 The present invention relates to data processing, especially to a bridge circuit that can provide conversion between PCIe-NVMe protocol and NVMe-TCP protocol and a computer system using the bridge circuit.

NVMe(Non-Volatile Memory Express)是一種非揮發性記憶體的主機控制介面規格,專門搭配使用PCIe(Peripheral Component Interconnect Express)匯流排的快閃記憶體裝置而設計的通訊協定,例如電腦主機可透過PCIe-NVMe協定來將資料寫入具有PCIe介面的固態硬碟(solid-state drive,SSD),以及可透過PCIe-NVMe協定來讀取具有PCIe介面的固態硬碟中所儲存的資料,相較於採用其它輸入/輸出介面的固態硬碟,具有PCIe介面的固態硬碟可藉由PCIe-NVMe協定而具備更快的讀寫速度。然而,由於電腦主機需要透過PCIe匯流排來存取固態硬碟,因此標準的PCIe-NVMe協定無法適用於遠端儲存設備的資料存取,故近年來出現了NVMe-oF(NVMe-over-Fabrics)方案以支持資料中心的網路儲存,其中NVMe-TCP(NVMe-over-TCP)協定可以在現有的網路基礎設施上運作,不需要特殊的交換機、路由器與網路卡,因此透過NVMe-TCP協定可簡單實現遠端儲存設備的部署。 NVMe (Non-Volatile Memory Express) is a host control interface specification for non-volatile memory. It is a communication protocol specially designed for flash memory devices using PCIe (Peripheral Component Interconnect Express) bus. The PCIe-NVMe protocol is used to write data into a solid-state drive (SSD) with a PCIe interface, and the data stored in a solid-state drive with a PCIe interface can be read through the PCIe-NVMe protocol. For SSDs using other I/O interfaces, SSDs with PCIe interface can have faster read and write speeds through the PCIe-NVMe protocol. However, since the computer host needs to access the SSD through the PCIe bus, the standard PCIe-NVMe protocol cannot be used for data access of remote storage devices, so NVMe-oF (NVMe-over-Fabrics) ) solution to support network storage in data centers, in which the NVMe-TCP (NVMe-over-TCP) protocol can operate on existing network infrastructure without special switches, routers and network cards. The TCP protocol can easily implement the deployment of remote storage devices.

然而,對於主機端而言,NVMe-TCP協定本身的複雜度會大幅增加中央處理器的運算負載,此外,為了存取NVMe-TCP裝置(例如連接至區域網路的固態硬碟),主機端另需要安裝新的驅動程式,由於需要不同的驅動程式來分別 處理PCIe-NVMe協定以及NVMe-TCP協定,也必然會增加系統複雜度。 However, for the host side, the complexity of the NVMe-TCP protocol itself will greatly increase the computing load of the CPU. In addition, in order to access NVMe-TCP devices (such as solid-state drives connected to the local area network), the host side In addition, a new driver needs to be installed, because different drivers are required to separate Dealing with the PCIe-NVMe protocol and the NVMe-TCP protocol will inevitably increase the system complexity.

因此,本發明的目的之一在於提出一種可於PCIe-NVMe協定與NVMe-TCP協定之間提供轉換的橋接電路與採用此橋接電路的電腦系統。 Therefore, one of the objectives of the present invention is to provide a bridge circuit that can provide conversion between the PCIe-NVMe protocol and the NVMe-TCP protocol and a computer system using the bridge circuit.

在本發明的一個實施例中,揭露一種橋接電路。該橋接電路包含有一NVMe裝置控制器、一網路子系統以及一資料轉送電路。該NVMe裝置控制器用以透過一PCIe匯流排來與一電腦主機進行溝通。該網路子系統用以透過一網路來與一NVMe-TCP裝置進行溝通。該資料轉送電路耦接於該NVMe裝置控制器與該網路子系統之間,並用以在無須該電腦主機的介入之下,處理有關該NVMe-TCP裝置的資料轉送。 In one embodiment of the present invention, a bridge circuit is disclosed. The bridge circuit includes an NVMe device controller, a network subsystem, and a data transfer circuit. The NVMe device controller is used to communicate with a computer host through a PCIe bus. The network subsystem is used to communicate with an NVMe-TCP device through a network. The data transfer circuit is coupled between the NVMe device controller and the network subsystem, and is used for processing data transfer related to the NVMe-TCP device without the intervention of the computer host.

在本發明的另一個實施例中,揭露一種電腦系統。該電腦系統包含有一電腦主機以及一橋接電路。該橋接電路包含有一NVMe裝置控制器、一網路子系統以及一資料轉送電路。該NVMe裝置控制器用以透過一PCIe匯流排來與該電腦主機進行溝通。該網路子系統用以透過一網路來與一NVMe-TCP裝置進行溝通。該資料轉送電路耦接於該NVMe裝置控制器與該網路子系統之間,並用以處理有關該NVMe-TCP裝置的資料轉送。該橋接電路會讓該NVMe-TCP裝置被該電腦主機視為一PCIe-NVMe裝置來進行存取。 In another embodiment of the present invention, a computer system is disclosed. The computer system includes a computer host and a bridge circuit. The bridge circuit includes an NVMe device controller, a network subsystem, and a data transfer circuit. The NVMe device controller is used to communicate with the computer host through a PCIe bus. The network subsystem is used to communicate with an NVMe-TCP device through a network. The data transfer circuit is coupled between the NVMe device controller and the network subsystem, and is used for processing data transfer related to the NVMe-TCP device. The bridge circuit allows the NVMe-TCP device to be accessed by the computer host as a PCIe-NVMe device.

在本發明的另一個實施例中,揭露一種電腦系統。該電腦系統包含有一電腦主機以及一橋接電路。該橋接電路包含有一NVMe裝置控制器、一網路子系統以及一資料轉送電路。該NVMe裝置控制器用以透過一PCIe匯流排來與該 電腦主機進行溝通。該網路子系統用以透過一網路來與一NVMe-TCP裝置進行溝通。該資料轉送電路耦接於該NVMe裝置控制器與該網路子系統之間,並用以處理有關該NVMe-TCP裝置的資料轉送。該電腦主機載入並執行PCIe-NVMe驅動程式來控制該電腦主機與該NVMe裝置控制器之間的溝通,且無須具備NVMe-TCP驅動程式。 In another embodiment of the present invention, a computer system is disclosed. The computer system includes a computer host and a bridge circuit. The bridge circuit includes an NVMe device controller, a network subsystem, and a data transfer circuit. The NVMe device controller is used to communicate with the communicate with the host computer. The network subsystem is used to communicate with an NVMe-TCP device through a network. The data transfer circuit is coupled between the NVMe device controller and the network subsystem, and is used for processing data transfer related to the NVMe-TCP device. The computer host loads and executes the PCIe-NVMe driver to control the communication between the computer host and the NVMe device controller, and does not need to have the NVMe-TCP driver.

本發明所揭示的橋接電路可將NVMe-TCP的處理自主機端處理器卸載出來,因而大幅降低主機端處理器的運算負載,另外,主機端處理器僅需執行PCIe-NVMe驅動程式即可藉由本發明所揭示的橋接電路來完成NVMe-TCP裝置的資料存取,無須安裝並執行NVMe-TCP驅動程式,故可降低系統複雜度。 The bridge circuit disclosed in the present invention can offload the processing of NVMe-TCP from the host-side processor, thereby greatly reducing the computing load of the host-side processor. In addition, the host-side processor only needs to execute the PCIe-NVMe driver. The bridge circuit disclosed in the present invention completes the data access of the NVMe-TCP device without installing and executing the NVMe-TCP driver, so the system complexity can be reduced.

100:電腦系統 100: Computer System

102:電腦主機 102: Computer host

103:PCIe匯流排 103: PCIe bus

104:PCIe介面卡 104: PCIe interface card

105:網路 105: Internet

106:NVMe-TCP裝置 106: NVMe-TCP device

112:中央處理器 112: CPU

114:系統儲存裝置 114: System Storage Device

116:提交佇列 116:Submit Queue

118:完成佇列 118: Complete the queue

122,200:橋接電路 122,200: Bridge circuit

124:本地儲存裝置 124: local storage device

132:非揮發性記憶體 132: non-volatile memory

201:晶片 201: Wafer

202,300:NVMe裝置控制器 202,300: NVMe Device Controller

204,400:資料轉送電路 204,400: Data transfer circuit

206,500:網路子系統 206,500: Network Subsystem

302:PCIe控制器 302: PCIe Controller

304:主機控制器 304: Host Controller

306:提交佇列處理電路 306: Submission queue processing circuit

308:完成佇列處理電路 308: Complete the queue processing circuit

310:儲存位址處理電路 310: storage address processing circuit

312,314,316,318:功能區塊 312, 314, 316, 318: Functional Blocks

402:資料存取電路 402: Data access circuit

404,406,408:儲存元件 404, 406, 408: Storage elements

410:查找表 410: Lookup Table

412,414:鏈接串列 412, 414: Linked Sequence

502:卸載引擎 502: Unload engine

504:NVMe-TCP控制器 504: NVMe-TCP Controller

第1圖為本發明採用橋接電路之電腦系統的示意圖。 FIG. 1 is a schematic diagram of a computer system using a bridge circuit according to the present invention.

第2圖為根據本發明一實施例之橋接電路的示意圖。 FIG. 2 is a schematic diagram of a bridge circuit according to an embodiment of the present invention.

第3圖為根據本發明一實施例之NVMe裝置控制器的示意圖。 FIG. 3 is a schematic diagram of an NVMe device controller according to an embodiment of the present invention.

第4圖為根據本發明一實施例之資料轉送電路的示意圖。 FIG. 4 is a schematic diagram of a data transfer circuit according to an embodiment of the present invention.

第5圖為根據本發明一實施例之網路子系統的示意圖。 FIG. 5 is a schematic diagram of a network subsystem according to an embodiment of the present invention.

第1圖為本發明採用橋接電路之電腦系統的示意圖。電腦系統100包含電腦主機102、PCIe介面卡104以及至少一NVMe-TCP裝置106,為了簡潔起見,第1圖僅繪示出一個NVMe-TCP裝置106,然而,於實際應用時,電腦系統100可根據應用需求而設置複數個NVMe-TCP裝置106。電腦主機102包含中央處理器112 與系統儲存裝置114,例如系統儲存裝置114可以是記憶體。另外,系統儲存裝置114中設置有提交佇列(submission queue,SQ)116與完成佇列(completion queue,CQ)118,其中提交佇列116用以儲存電腦主機102所發出的命令,而完成佇列118會與提交佇列116配對,用來儲存該命令的完成資訊。PCIe介面卡104上設置有橋接電路122與可供橋接電路122使用的本地儲存裝置124,例如本地儲存裝置124可以是記憶體。PCIe介面卡104可安裝於電腦主機102上的PCIe插槽,因此,橋接電路122便可透過PCIe匯流排103來跟電腦主機102進行溝通。本實施例中,橋接電路122與NVMe-TCP裝置106均連接至網路105,例如網路105為區域網路。NVMe-TCP裝置106包含非揮發性記憶體132,例如NVMe-TCP裝置106為採用NVMe-TCP協定的固態硬碟。本實施例中,橋接電路122可於PCIe-NVMe協定與NVMe-TCP協定之間提供轉換,換言之,橋接電路122透過PCIe-NVMe協定來跟電腦主機102溝通,並透過NVMe-TCP協定來跟NVMe-TCP裝置106進行溝通,因此,電腦主機102本身無須處理NVMe-TCP協定堆疊(stack),故電腦主機102僅需載入並執行PCIe-NVMe驅動程式DRV_NVMe來控制電腦主機102與橋接電路122之間的溝通,實際上無須具備NVMe-TCP驅動程式,進一步來說,橋接電路104可讓NVMe-TCP裝置106被電腦主機102視為PCIe-NVMe裝置來進行存取。 FIG. 1 is a schematic diagram of a computer system using a bridge circuit according to the present invention. The computer system 100 includes a computer host 102, a PCIe interface card 104 and at least one NVMe-TCP device 106. For the sake of brevity, only one NVMe-TCP device 106 is shown in FIG. 1. However, in practical applications, the computer system 100 A plurality of NVMe-TCP devices 106 may be provided according to application requirements. The computer host 102 includes a central processing unit 112 As with system storage 114, for example, system storage 114 may be memory. In addition, the system storage device 114 is provided with a submission queue (SQ) 116 and a completion queue (CQ) 118 , wherein the submission queue 116 is used for storing commands issued by the computer host 102 to complete the queues. Column 118 is paired with commit queue 116 to store completion information for the command. A bridge circuit 122 and a local storage device 124 that can be used by the bridge circuit 122 are disposed on the PCIe interface card 104 . For example, the local storage device 124 may be a memory. The PCIe interface card 104 can be installed in a PCIe slot on the computer host 102 , so the bridge circuit 122 can communicate with the computer host 102 through the PCIe bus bar 103 . In this embodiment, the bridge circuit 122 and the NVMe-TCP device 106 are both connected to the network 105, for example, the network 105 is a local area network. The NVMe-TCP device 106 includes a non-volatile memory 132, for example, the NVMe-TCP device 106 is a solid state drive using the NVMe-TCP protocol. In this embodiment, the bridge circuit 122 can provide conversion between the PCIe-NVMe protocol and the NVMe-TCP protocol. In other words, the bridge circuit 122 communicates with the computer host 102 through the PCIe-NVMe protocol, and communicates with the NVMe through the NVMe-TCP protocol -Communicate with the TCP device 106, therefore, the computer host 102 itself does not need to process the NVMe-TCP protocol stack, so the computer host 102 only needs to load and execute the PCIe-NVMe driver DRV_NVMe to control the communication between the computer host 102 and the bridge circuit 122 In fact, there is no need for an NVMe-TCP driver to communicate with each other. Further, the bridge circuit 104 allows the NVMe-TCP device 106 to be accessed by the computer host 102 as a PCIe-NVMe device.

第2圖為根據本發明一實施例之橋接電路的示意圖。第1圖所示之橋接電路122可由第2圖所示之橋接電路200來實現。如第2圖所示,橋接電路200包含NVMe裝置控制器202、資料轉送電路204以及網路子系統206。本實施例中,NVMe裝置控制器202、資料轉送電路204以及網路子系統206均設置於同一晶片201中。NVMe裝置控制器202用以透過PCIe匯流排103來與電腦主機102進行溝通。網路子系統206用以透過網路(例如區域網路)105來與NVMe-TCP裝置106進行溝通。資料轉送電路204具備直接記憶體存取(direct memory access,DMA)的能 力,並耦接於NVMe裝置控制器202與網路子系統206之間,用以在無須電腦主機102的介入之下,處理有關NVMe-TCP裝置106的資料轉送(包含透過NVMe裝置控制器202與網路子系統206來將電腦主機102的資料轉送至NVMe-TCP裝置106中的非揮發性記憶體132,以及透過NVMe裝置控制器202與網路子系統206來將NVMe-TCP裝置106的非揮發性記憶體132所儲存的資料轉送至電腦主機102)。 FIG. 2 is a schematic diagram of a bridge circuit according to an embodiment of the present invention. The bridge circuit 122 shown in FIG. 1 can be implemented by the bridge circuit 200 shown in FIG. 2 . As shown in FIG. 2 , the bridge circuit 200 includes an NVMe device controller 202 , a data transfer circuit 204 and a network subsystem 206 . In this embodiment, the NVMe device controller 202 , the data transfer circuit 204 and the network subsystem 206 are all disposed in the same chip 201 . The NVMe device controller 202 is used to communicate with the computer host 102 through the PCIe bus 103 . The network subsystem 206 is used to communicate with the NVMe-TCP device 106 through the network (eg, a local area network) 105 . The data transfer circuit 204 is capable of direct memory access (DMA) It is coupled between the NVMe device controller 202 and the network subsystem 206 for processing data transfers related to the NVMe-TCP device 106 (including through the NVMe device controller 202 and the network subsystem 206) without the intervention of the computer host 102. The network subsystem 206 transfers data from the computer host 102 to the non-volatile memory 132 in the NVMe-TCP device 106 , and through the NVMe device controller 202 and the network subsystem 206 to transfer the non-volatile memory of the NVMe-TCP device 106 The data stored in the memory 132 is forwarded to the computer host 102).

第3圖為根據本發明一實施例之NVMe裝置控制器的示意圖。第2圖所示之NVMe裝置控制器202可由第3圖所示之NVMe裝置控制器300來實現。如第3圖所示,NVMe裝置控制器300包含PCIe控制器302、主機控制器304、提交佇列處理電路306、完成佇列處理電路308以及儲存位址處理電路310。PCIe控制器302用以存取PCIe匯流排103。主機控制器304包含複數個功能區塊,其中功能區塊(標示為DNTRFC)312用以控制PCIe匯流排103的下行資料處理(downstream transaction),功能區塊(標示為UPTRFC)314用以控制PCIe匯流排103的上行資料處理(upstream transaction),功能區塊(標示為PCIe_cfg)316包含有暫存器以儲存PCIe組態設定,以及功能區塊(標示為NVMe_cfg)318包含有暫存器以儲存NVMe組態設定。 FIG. 3 is a schematic diagram of an NVMe device controller according to an embodiment of the present invention. The NVMe device controller 202 shown in FIG. 2 may be implemented by the NVMe device controller 300 shown in FIG. 3 . As shown in FIG. 3 , the NVMe device controller 300 includes a PCIe controller 302 , a host controller 304 , a commit queue processing circuit 306 , a completion queue processing circuit 308 , and a storage address processing circuit 310 . The PCIe controller 302 is used to access the PCIe bus 103 . The host controller 304 includes a plurality of functional blocks, wherein the functional block (marked as DNTRFC) 312 is used to control the downstream transaction of the PCIe bus 103, and the functional block (marked as UPTRFC) 314 is used to control the PCIe For the upstream transaction of the bus 103, the functional block (labeled as PCIe_cfg) 316 includes registers to store PCIe configuration settings, and the functional block (labeled as NVMe_cfg) 318 includes registers to store NVMe configuration settings.

提交佇列處理電路306用以讀取並處理電腦主機102之提交佇列116中的命令(例如寫入命令或讀取命令),例如,當電腦主機102將命令(例如寫入命令或讀取命令)寫入提交佇列116之後,電腦主機102會通知NVMe裝置控制器300,而提交佇列處理電路306後續便會將此命令(例如寫入命令或讀取命令)自提交佇列116中擷取出來。完成佇列處理電路308用以將該命令(例如寫入命令或讀取命令)的完成資訊寫入電腦主機102之完成佇列118中,例如,當資料轉送電路204已經將寫入命令所指示的主機端資料傳送至NVMe-TCP裝置106中的非揮發性記憶 體132,則完成佇列處理電路308會將此寫入命令的完成資訊寫入至完成佇列118中;同樣地,當資料轉送電路204已經將讀取命令所指示的裝置端資料傳送至主機裝置102中的系統儲存裝置114,則完成佇列處理電路308會將此讀取命令的完成資訊寫入至完成佇列118中。 The submission queue processing circuit 306 is used to read and process commands (eg, write commands or read commands) in the submission queue 116 of the host computer 102. After the command) is written to the commit queue 116, the computer host 102 will notify the NVMe device controller 300, and the commit queue processing circuit 306 will subsequently send the command (such as a write command or a read command) from the commit queue 116 Extract it. The completion queue processing circuit 308 is used to write the completion information of the command (such as a write command or a read command) into the completion queue 118 of the computer host 102, for example, when the data transfer circuit 204 has indicated the write command host-side data transfer to non-volatile memory in NVMe-TCP device 106 body 132, the completion queue processing circuit 308 will write the completion information of the write command into the completion queue 118; similarly, when the data transfer circuit 204 has transmitted the device-side data indicated by the read command to the host In the system storage device 114 in the device 102 , the completion queue processing circuit 308 writes the completion information of the read command into the completion queue 118 .

儲存位址處理電路310用以擷取該命令(例如寫入命令或讀取命令)所附帶的儲存位址資訊,並可根據該儲存位址資訊來設定資料轉送電路204,例如該儲存位址資訊會指定系統儲存裝置114中的儲存位址,當提交佇列116中所要處理的命令是寫入命令時,要被寫入至NVMe-TCP裝置106中非揮發性記憶體132的主機端資料會位於該儲存位址資訊所指定的儲存位址,另外,當提交佇列116中所要處理的命令是讀取命令時,要從NVMe-TCP裝置106中非揮發性記憶體132讀取出來的裝置端資料會寫入至該儲存位址資訊所指定的儲存位址。本實施例中,該儲存位址資訊可利用分散聚合表(Scatter Gather List,SGL)的資料結構來紀錄,然而,本發明並不以此為限,於其它實施例中,該儲存位址資訊亦可利用物理區域頁(Physical Region Page,PRP)的資料結構來紀錄。由於NVMe命令(例如寫入命令或讀取命令)所附帶的該儲存位址資訊會指定系統儲存裝置114中的儲存位址,因此,儲存位址處理電路310可據此來設定資料轉送電路204,以使資料轉送電路204可正確處理有關NVMe-TCP裝置106的資料轉送作業。 The storage address processing circuit 310 is used for retrieving the storage address information attached to the command (such as a write command or a read command), and can set the data transfer circuit 204 according to the storage address information, such as the storage address The information specifies the storage address in the system storage device 114 to be written to the host-side data of the non-volatile memory 132 in the NVMe-TCP device 106 when the command to be processed in the submission queue 116 is a write command will be located at the storage address specified by the storage address information. In addition, when the command to be processed in the submission queue 116 is a read command, it will be read from the non-volatile memory 132 of the NVMe-TCP device 106 Device-side data will be written to the storage address specified by the storage address information. In this embodiment, the storage address information can be recorded by using the data structure of the Scatter Gather List (SGL). However, the present invention is not limited to this. In other embodiments, the storage address information The data structure of Physical Region Page (PRP) can also be used to record. Since the storage address information attached to the NVMe command (eg, write command or read command) specifies the storage address in the system storage device 114 , the storage address processing circuit 310 can configure the data transfer circuit 204 accordingly. , so that the data transfer circuit 204 can correctly process the data transfer operation related to the NVMe-TCP device 106 .

第4圖為根據本發明一實施例之資料轉送電路的示意圖。第2圖所示之資料轉送電路204可由第4圖所示之資料轉送電路400來實現。如第4圖所示,資料轉送電路400包含資料存取電路402與複數個儲存元件(例如記憶體)404、406、408。儲存元件406用以儲存一鏈接串列(linked list)412,其中鏈接串列412中的每一節點會紀錄系統儲存裝置114中的一儲存位址,例如鏈接串列412的複數節點分 別紀錄系統儲存裝置114中的複數個儲存位址ADDR_A1、ADDR_A2、ADDR_A3、ADDR_A4。儲存元件408則用以儲存另一鏈接串列414,其中鏈接串列414中的每一節點會紀錄本地儲存裝置124中的一儲存位址,例如鏈接串列414的複數節點分別紀錄本地儲存裝置124中的複數個儲存位址ADDR_B1、ADDR_B2、ADDR_B3、ADDR_B4。儲存元件404則用以儲存一查找表410,其中查找表410會紀錄鏈接串列412中第一節點(本實施例為紀錄儲存位址ADDR_A1的節點)於儲存元件406中的儲存位址PTR_1以及鏈接串列414中第一節點(本實施例為紀錄儲存位址ADDR_B1的節點)於儲存元件408中的儲存位址PTR_2。資料存取電路402用以依據查找表410來讀取鏈接串列412及鏈接串列414,以處理電腦主機102與NVMe-TCP裝置106之間的資料轉送作業。 FIG. 4 is a schematic diagram of a data transfer circuit according to an embodiment of the present invention. The data transfer circuit 204 shown in FIG. 2 can be realized by the data transfer circuit 400 shown in FIG. 4 . As shown in FIG. 4 , the data transfer circuit 400 includes a data access circuit 402 and a plurality of storage elements (eg, memories) 404 , 406 and 408 . The storage element 406 is used for storing a linked list 412 , wherein each node in the linked list 412 records a storage address in the system storage device 114 , for example, a plurality of nodes in the linked list 412 . The plurality of storage addresses ADDR_A1 , ADDR_A2 , ADDR_A3 , and ADDR_A4 in the system storage device 114 are respectively recorded. The storage element 408 is used to store another link series 414, wherein each node in the link series 414 records a storage address in the local storage device 124, for example, a plurality of nodes in the link series 414 respectively record the local storage device A plurality of storage addresses ADDR_B1, ADDR_B2, ADDR_B3, ADDR_B4 in 124. The storage element 404 is used for storing a look-up table 410, wherein the look-up table 410 records the storage address PTR_1 and The first node in the chain 414 (in this embodiment, the node recording the storage address ADDR_B1 ) is connected to the storage address PTR_2 in the storage element 408 . The data access circuit 402 is used for reading the link string 412 and the link string 414 according to the lookup table 410 to process the data transfer operation between the computer host 102 and the NVMe-TCP device 106 .

當電腦主機102將NVMe命令(例如寫入命令或讀取命令)寫入至提交佇列116,該NVMe命令會具有相對應的NVMe命令識別碼HID,此外,透過網路105,橋接電路122會藉由TCP連線識別碼(TCP session ID)SID來與NVMe-TCP裝置106進行溝通,並會基於該PCIe-NVMe命令來產生並傳送NVMe-TCP命令(例如寫入命令或讀取命令)至NVMe-TCP裝置106,而該NVMe-TCP命令同樣會具有相對應的命令識別碼CID,本實施例中,NVMe命令識別碼HID會綁定相對應的一對TCP連線識別碼SID與NVMe-TCP命令識別碼CID來作為查找表410的索引,如第4圖所示,查找表410會將一組NVMe命令識別碼HID、TCP連線識別碼SID與NVMe-TCP命令識別碼CID映射至鏈接串列412中第一節點於儲存元件406中的儲存位址PTR_1以及鏈接串列414中第一節點於儲存元件408中的儲存位址,因此,資料存取電路402便可依據該組NVMe命令識別碼HID、TCP連線識別碼SID與NVMe-TCP命令識別碼CID來自查找表410讀取出有關鏈接串列起始點的指標(包含鏈接串列412中第一節點於儲存元件406中的儲存位址PTR_1以及鏈接串列414 中第一節點於儲存元件408中的儲存位址PTR_2)。 When the computer host 102 writes an NVMe command (such as a write command or a read command) to the submission queue 116, the NVMe command will have a corresponding NVMe command identifier HID. In addition, through the network 105, the bridge circuit 122 will Communicates with the NVMe-TCP device 106 through the TCP session ID (TCP session ID) SID, and generates and transmits NVMe-TCP commands (such as write commands or read commands) based on the PCIe-NVMe commands to the NVMe-TCP device 106, and the NVMe-TCP command will also have a corresponding command identifier CID. In this embodiment, the NVMe command identifier HID will be bound to a corresponding pair of TCP connection identifiers SID and NVMe- The TCP command identifier CID is used as an index of the lookup table 410. As shown in FIG. 4, the lookup table 410 maps a set of NVMe command identifiers HID, TCP connection identifiers SID and NVMe-TCP command identifiers CID to links The storage address PTR_1 of the first node in the string 412 in the storage element 406 and the storage address of the first node in the link string 414 in the storage element 408, therefore, the data access circuit 402 can follow the set of NVMe commands The identification code HID, the TCP connection identification code SID and the NVMe-TCP command identification code CID come from the lookup table 410 to read out the index about the starting point of the link sequence (including the first node in the link sequence 412 in the storage element 406 ) Storage address PTR_1 and link string 414 The first node in the storage element 408 is at the storage address PTR_2).

根據電腦主機102所發出的NVMe命令(例如寫入命令或讀取命令),資料存取電路402可以參照所要存取的命名空間(namespace)來決定網路105上哪個NVMe-TCP裝置要被存取,假若所要存取的是NVMe-TCP裝置106,則資料存取電路402會將橋接電路122與NVMe-TCP裝置106之間的TCP連線跟NVMe-TCP裝置106的命名空間進行綁定,而當橋接電路122將NVMe-TCP命令傳送至NVMe-TCP裝置106時,資料存取電路402便會建立對照表410並根據儲存位址處理電路310所提供的資訊(亦即NVMe命令所附帶的儲存位址資訊)來設定儲存元件406中的鏈接串列412與儲存元件408中的鏈接串列414。 According to the NVMe command (such as a write command or a read command) issued by the computer host 102, the data access circuit 402 can refer to the namespace to be accessed to determine which NVMe-TCP device on the network 105 is to be stored Take, if the NVMe-TCP device 106 is to be accessed, the data access circuit 402 will bind the TCP connection between the bridge circuit 122 and the NVMe-TCP device 106 to the namespace of the NVMe-TCP device 106, When the bridge circuit 122 transmits the NVMe-TCP command to the NVMe-TCP device 106, the data access circuit 402 will create the look-up table 410 and process the information provided by the circuit 310 according to the storage address (that is, the information attached to the NVMe command). storage address information) to configure link string 412 in storage element 406 and link string 414 in storage element 408.

假如電腦主機102所發出的NVMe命令是寫入命令,則資料存取電路402依據鏈接串列412中第一節點於儲存元件406中的儲存位址PTR_1來開始讀取鏈接串列412所紀錄的儲存位址ADDR_A1~ADDR_A4,以從系統儲存裝置114讀取一筆資料(從儲存位址ADDR_A1~ADDR_A4讀取),並依據鏈接串列414中第一節點於儲存元件408中的儲存位址PTR_2來開始讀取鏈接串列414所紀錄的儲存位址ADDR_B1~ADDR_B4,來將該筆資料寫入至本地儲存裝置124(寫入至儲存位址ADDR_B1~ADDR_B4)。之後,資料存取電路402再依據鏈接串列414中第一節點於儲存元件408中的儲存位址PTR_2來開始讀取鏈接串列414所紀錄的儲存位址ADDR_B1~ADDR_B4,以自本地儲存裝置124讀取該筆資料(從儲存位址ADDR_B1~ADDR_B4讀取),並透過網路子系統206來將該筆資料傳送至NVMe-TCP裝置106以寫入至非揮發性記憶體132。 If the NVMe command issued by the computer host 102 is a write command, the data access circuit 402 starts to read the data recorded in the link string 412 according to the storage address PTR_1 of the first node in the link string 412 in the storage element 406 . The storage addresses ADDR_A1~ADDR_A4 are used to read a piece of data from the system storage device 114 (read from the storage addresses ADDR_A1~ADDR_A4), and according to the storage address PTR_2 of the first node in the link string 414 in the storage element 408 Start to read the storage addresses ADDR_B1 ˜ADDR_B4 recorded in the link string 414 to write the data to the local storage device 124 (write to the storage addresses ADDR_B1 ˜ADDR_B4 ). After that, the data access circuit 402 starts to read the storage addresses ADDR_B1-ADDR_B4 recorded in the link string 414 according to the storage address PTR_2 of the first node in the link string 414 in the storage element 408, so as to obtain the data from the local storage device. 124 reads the data (read from storage addresses ADDR_B1 to ADDR_B4 ), and transmits the data to the NVMe-TCP device 106 through the network subsystem 206 for writing to the non-volatile memory 132 .

假如電腦主機102所發出的NVMe命令是讀取命令,則網路子系統206 會自NVMe-TCP裝置106接收一筆資料,另外,資料存取電路402便依據鏈接串列414中第一節點於儲存元件408中的儲存位址PTR_2來開始讀取鏈接串列414所紀錄的儲存位址ADDR_B1~ADDR_B4,以將該筆資料寫入至本地儲存裝置124(寫入至儲存位址ADDR_B1~ADDR_B4)。之後,資料存取電路402會再依據鏈接串列414中第一節點於儲存元件408中的儲存位址PTR_2來開始讀取鏈接串列414所紀錄的儲存位址ADDRB1~ADDR_B4,以自本地儲存裝置124讀取該筆資料(從儲存位址ADDR_B1~ADDR_B4讀取),並且會依據鏈接串列412中第一節點於儲存元件406中的儲存位址PTR_1來開始讀取鏈接串列412所紀錄的儲存位址ADDR_A1~ADDR_A4,以將該筆資料寫入至系統儲存裝置114(寫入至儲存位址ADDR_A1~ADDR_A4)。 If the NVMe command issued by the computer host 102 is a read command, the network subsystem 206 A piece of data is received from the NVMe-TCP device 106. In addition, the data access circuit 402 starts to read the storage recorded in the link string 414 according to the storage address PTR_2 of the first node in the link string 414 in the storage element 408 Addresses ADDR_B1 to ADDR_B4 are used to write the data to the local storage device 124 (write to storage addresses ADDR_B1 to ADDR_B4). Afterwards, the data access circuit 402 will start to read the storage addresses ADDRB1-ADDR_B4 recorded in the link string 414 according to the storage address PTR_2 of the first node in the link string 414 in the storage element 408 to store the data locally The device 124 reads the data (read from the storage addresses ADDR_B1 to ADDR_B4), and starts to read the record in the link string 412 according to the storage address PTR_1 of the first node in the link string 412 in the storage element 406 to write the data to the system storage device 114 (write to the storage addresses ADDR_A1 to ADDR_A4).

如前所述,網路子系統206會透過網路(例如區域網路)105來與NVMe-TCP裝置106進行溝通,例如,網路子系統206透過網路105來將命令傳遞至NVMe-TCP裝置106、將寫入資料傳遞至NVMe-TCP裝置106,以及自NVMe-TCP裝置106接收讀取資料。第5圖為根據本發明一實施例之網路子系統的示意圖。第2圖所示之網路子系統206可由第5圖所示之網路子系統500來實現。如第5圖所示,網路子系統500包含卸載引擎502以及NVMe-TCP控制器504。卸載引擎502是專門用以處理網路子系統500與NVMe-TCP裝置106之間的傳輸控制協定/網際網路協定堆疊(TCP/IP stack)的硬體,因此,橋接電路122/200無須處理器介入傳輸控制協定/網際網路協定堆疊的處理。NVMe-TCP控制器504用以觸發資料轉送電路204/400來自電腦主機102讀取資料以透過卸載引擎502傳送至NVMe-TCP裝置106,以及觸發資料轉送電路204/400來將卸載引擎502自NVMe-TCP裝置106所接收之資料傳送至電腦主機102。另外,NVMe-TCP控制器504亦可根據NVMe命令識別碼HID來將TCP連線識別碼SID與NVMe-TCP命令識別碼CID編碼至網路封包 中,以及另對NVMe-TCP資料(包含寫入命令或讀取指令)進行編碼並加入相對應循環冗餘校驗(Cyclic Redundancy Check)資料至網路封包;以及NVMe-TCP控制器504亦可對網路封包進行解碼來得到NVMe-TCP資料(包含寫入命令的完成資訊或讀取命令的完成資訊),並根據相對應循環冗餘校驗資料來進行資料正確性檢查與錯誤更正。 As previously mentioned, the network subsystem 206 communicates with the NVMe-TCP device 106 through the network (eg, a local area network) 105 , eg, the network subsystem 206 passes commands to the NVMe-TCP device 106 through the network 105 , pass write data to NVMe-TCP device 106 , and receive read data from NVMe-TCP device 106 . FIG. 5 is a schematic diagram of a network subsystem according to an embodiment of the present invention. The network subsystem 206 shown in FIG. 2 may be implemented by the network subsystem 500 shown in FIG. 5 . As shown in FIG. 5 , the network subsystem 500 includes an offload engine 502 and an NVMe-TCP controller 504 . The offload engine 502 is dedicated hardware for handling the Transmission Control Protocol/Internet Protocol stack (TCP/IP stack) between the network subsystem 500 and the NVMe-TCP device 106, so the bridge circuit 122/200 does not require a processor Involves the processing of the Transmission Control Protocol/Internet Protocol stack. The NVMe-TCP controller 504 is used to trigger the data transfer circuit 204/400 to read data from the computer host 102 for transmission to the NVMe-TCP device 106 through the offload engine 502, and to trigger the data transfer circuit 204/400 to transfer the offload engine 502 from the NVMe - The data received by the TCP device 106 is transmitted to the computer host 102 . In addition, the NVMe-TCP controller 504 can also encode the TCP connection identifier SID and the NVMe-TCP command identifier CID into the network packet according to the NVMe command identifier HID. , and also encode the NVMe-TCP data (including write commands or read commands) and add the corresponding Cyclic Redundancy Check (Cyclic Redundancy Check) data to the network packet; and the NVMe-TCP controller 504 can also Decode the network packets to obtain NVMe-TCP data (including the completion information of the write command or the completion information of the read command), and perform data correctness checking and error correction according to the corresponding CRC data.

綜上所述,本發明所揭示的橋接電路可將NVMe-TCP的處理自主機端處理器卸載出來,因而大幅降低主機端處理器的運算負載,另外,主機端處理器僅需執行PCIe-NVMe驅動程式即可藉由本發明所揭示的橋接電路來完成NVMe-TCP裝置的資料存取,無須安裝並執行NVMe-TCP驅動程式,故可降低系統複雜度。 To sum up, the bridge circuit disclosed in the present invention can offload the processing of NVMe-TCP from the host-side processor, thereby greatly reducing the computing load of the host-side processor. In addition, the host-side processor only needs to execute PCIe-NVMe The driver can complete the data access of the NVMe-TCP device through the bridge circuit disclosed in the present invention, and there is no need to install and execute the NVMe-TCP driver, so the system complexity can be reduced.

以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。 The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

100:電腦系統 100: Computer Systems

102:電腦主機 102: Computer host

103:PCIe匯流排 103: PCIe bus

104:PCIe介面卡 104: PCIe interface card

105:網路 105: Internet

106:NVMe-TCP裝置 106: NVMe-TCP device

112:中央處理器 112: CPU

114:系統儲存裝置 114: System Storage Device

116:提交佇列 116:Submit Queue

118:完成佇列 118: Complete the queue

122:橋接電路 122: Bridge circuit

124:本地儲存裝置 124: local storage device

132:非揮發性記憶體 132: non-volatile memory

Claims (12)

一種橋接電路,包含有:一NVMe裝置控制器,用以透過一PCIe匯流排來與一電腦主機進行溝通;一網路子系統,用以透過一網路來與一NVMe-TCP裝置進行溝通;以及一資料轉送電路,耦接於該NVMe裝置控制器與該網路子系統之間,用以在無須該電腦主機的介入之下,處理有關該NVMe-TCP裝置的資料轉送;其中該NVMe裝置控制器、該網路子系統以及該資料轉送電路均設置於同一晶片。 A bridge circuit includes: an NVMe device controller for communicating with a computer host through a PCIe bus; a network subsystem for communicating with an NVMe-TCP device through a network; and A data transfer circuit, coupled between the NVMe device controller and the network subsystem, is used to process data transfer about the NVMe-TCP device without the intervention of the computer host; wherein the NVMe device controller , the network subsystem and the data transfer circuit are all arranged on the same chip. 如申請專利範圍第1項所述之橋接電路,其中該NVMe裝置控制器包含有:一PCIe控制器,用以存取該PCIe匯流排;一主機控制器,耦接於該PCIe控制器,用以控制該PCIe匯流排的上行資料處理與下行資料處理、NVMe組態設定以及PCIe組態設定;一提交佇列處理電路,耦接於該主機控制器,用以讀取並處理該電腦主機之一提交佇列中的命令;一完成佇列處理電路,耦接於該主機控制器,用以將該命令的完成資訊寫入該電腦主機之一完成佇列中;以及一儲存位址處理電路,耦接於該主機控制器,用以擷取該命令所附帶的儲存位址資訊,並根據該儲存位址資訊來設定該資料轉送電路。 The bridge circuit of claim 1, wherein the NVMe device controller comprises: a PCIe controller for accessing the PCIe bus; a host controller coupled to the PCIe controller for To control the upstream data processing and downstream data processing of the PCIe bus, NVMe configuration settings and PCIe configuration settings; a submission queue processing circuit, coupled to the host controller, for reading and processing the computer host. a command in the submission queue; a completion queue processing circuit, coupled to the host controller, for writing the completion information of the command into a completion queue of the computer host; and a storage address processing circuit , which is coupled to the host controller and used for retrieving the storage address information attached to the command and setting the data transfer circuit according to the storage address information. 如申請專利範圍第1項所述之橋接電路,其中該網路子系統包含有:一卸載引擎,用以處理該網路子系統與該NVMe-TCP裝置之間的傳輸控制協定/網際網路協定堆疊;以及 一NVMe-TCP控制器,用以觸發該資料轉送電路來自該電腦主機讀取資料以透過該卸載引擎傳送至該NVMe-TCP裝置,以及觸發該資料轉送電路來將該卸載引擎自該NVMe-TCP裝置所接收之資料傳送至該電腦主機。 The bridge circuit of claim 1, wherein the network subsystem comprises: an offload engine for processing TCP/IP stacking between the network subsystem and the NVMe-TCP device ;as well as an NVMe-TCP controller for triggering the data transfer circuit to read data from the computer host to transmit to the NVMe-TCP device through the offload engine, and triggering the data transfer circuit to read data from the NVMe-TCP by the offload engine The data received by the device is transmitted to the computer host. 如申請專利範圍第1項所述之橋接電路,其中該資料轉送電路包含有:一第一儲存元件,用以儲存一第一鏈接串列,該第一鏈接串列中的每一節點紀錄該電腦主機之一系統儲存裝置中的一儲存位址;一第二儲存元件,用以儲存一第二鏈接串列,該第二鏈接串列中的每一節點紀錄可供該橋接電路使用之一本地儲存裝置中的一儲存位址;一第三儲存元件,用以儲存一查找表,該查找表紀錄該第一鏈接串列中第一節點於該第一儲存元件中的儲存位址以及該第二鏈接串列中第一節點於該第二儲存元件中的儲存位址;以及一資料存取電路,用以依據該查找表來讀取該第一鏈接串列以及該第二鏈接串列,以處理該電腦主機與該NVMe-TCP裝置之間的資料轉送。 The bridge circuit as described in claim 1, wherein the data transfer circuit comprises: a first storage element for storing a first link series, and each node in the first link series records the a storage address in a system storage device of the computer host; a second storage element for storing a second link string, each node record in the second link string can be used by the bridge circuit a storage address in the local storage device; a third storage element for storing a look-up table, the look-up table records the storage address of the first node in the first link string in the first storage element and the The storage address of the first node in the second link string in the second storage element; and a data access circuit for reading the first link string and the second link string according to the look-up table , to handle data transfer between the computer host and the NVMe-TCP device. 如申請專利範圍第4項所述之橋接電路,其中該查找表另紀錄一組NVMe命令識別碼、TCP連線識別碼與NVMe-TCP命令識別碼係映射至該第一鏈接串列中第一節點於該第一儲存元件中的儲存位址以及該第二鏈接串列中第一節點於該第二儲存元件中的儲存位址;以及該資料存取電路另用以依據該組NVMe命令識別碼、TCP連線識別碼與NVMe-TCP命令識別碼來自該查找表讀取出該第一鏈接串列中第一節點於該第一儲存元件中的儲存位址以及該第二鏈接串列中第一節點於該第二儲存元件中的儲存位址。 The bridge circuit as described in claim 4, wherein the lookup table further records a set of NVMe command identifiers, TCP connection identifiers and NVMe-TCP command identifiers, which are mapped to the first one in the first link sequence the storage address of the node in the first storage element and the storage address of the first node in the second link string in the second storage element; and the data access circuit is further used for identifying according to the set of NVMe commands code, TCP connection ID and NVMe-TCP command ID from the look-up table to read the storage address of the first node in the first link string in the first storage element and the second link string The storage address of the first node in the second storage element. 如申請專利範圍第4項所述之橋接電路,其中該資料存取電路依據該第一鏈接串列中第一節點於該第一儲存元件中的儲存位址來開始讀取該第一鏈接串列,以自該系統儲存裝置讀取一筆資料,並依據該第二鏈接串列中第一節點於該第二儲存元件中的儲存位址來開始讀取該第二鏈接串列,以將該筆資料寫入至該本地儲存裝置。 The bridge circuit as described in claim 4, wherein the data access circuit starts to read the first link string according to the storage address of the first node in the first link string in the first storage element row, to read a piece of data from the system storage device, and start reading the second link string according to the storage address of the first node in the second link string in the second storage element, so as to Pen data is written to the local storage device. 如申請專利範圍第6項所述之橋接電路,其中該資料存取電路另依據該第二鏈接串列中第一節點於該第二儲存元件中的儲存位址來開始讀取該第二鏈接串列,以自該本地儲存裝置讀取該筆資料,並透過該網路子系統來將該筆資料傳送至該NVMe-TCP裝置。 The bridge circuit as described in claim 6, wherein the data access circuit further starts to read the second link according to the storage address of the first node in the second link string in the second storage element serial to read the data from the local storage device and transmit the data to the NVMe-TCP device through the network subsystem. 如申請專利範圍第4項所述之橋接電路,其中該網路子系統自該NVMe-TCP裝置接收一筆資料;以及該資料存取電路依據該第二鏈接串列中第一節點於該第二儲存元件中的儲存位址來開始讀取該第二鏈接串列,以將該筆資料寫入至該本地儲存裝置。 The bridge circuit of claim 4, wherein the network subsystem receives a piece of data from the NVMe-TCP device; and the data access circuit stores the data in the second storage according to the first node in the second link string The storage address in the device starts to read the second link string to write the data to the local storage device. 如申請專利範圍第8項所述之橋接電路,其中該資料存取電路另依據該第二鏈接串列中第一節點於該第二儲存元件中的儲存位址來開始讀取該第二鏈接串列,以自該本地儲存裝置讀取該筆資料,並依據該第一鏈接串列中第一節點於該第一儲存元件中的儲存位址來開始讀取該第一鏈接串列,以將該筆資料寫入至該系統儲存裝置。 The bridge circuit as described in claim 8, wherein the data access circuit further starts to read the second link according to the storage address of the first node in the second link string in the second storage element a series, to read the data from the local storage device, and start reading the first link series according to the storage address of the first node in the first link series in the first storage element, so as to Write the data to the system storage device. 如申請專利範圍第1項所述之橋接電路,其中該橋接電路設置於一PCIe介面卡。 The bridge circuit as described in claim 1, wherein the bridge circuit is disposed on a PCIe interface card. 一種電腦系統,包含有:一電腦主機;以及一橋接電路,包含有:一NVMe裝置控制器,用以透過一PCIe匯流排來與該電腦主機進行溝通;一網路子系統,用以透過一網路來與一NVMe-TCP裝置進行溝通;以及一資料轉送電路,耦接於該NVMe裝置控制器與該網路子系統之間,用以處理有關該NVMe-TCP裝置的資料轉送;其中該NVMe裝置控制器、該網路子系統以及該資料轉送電路均設置於同一晶片,以及該橋接電路會讓該NVMe-TCP裝置被該電腦主機視為一PCIe-NVMe裝置來進行存取。 A computer system includes: a computer host; and a bridge circuit, including: an NVMe device controller for communicating with the computer host through a PCIe bus; a network subsystem for connecting through a network communication with an NVMe-TCP device; and a data transfer circuit, coupled between the NVMe device controller and the network subsystem, for processing data transfer related to the NVMe-TCP device; wherein the NVMe device The controller, the network subsystem and the data transfer circuit are all disposed on the same chip, and the bridge circuit allows the NVMe-TCP device to be accessed by the computer host as a PCIe-NVMe device. 一種電腦系統,包含有:一電腦主機;以及一橋接電路,包含有:一NVMe裝置控制器,用以透過一PCIe匯流排來與該電腦主機進行溝通;一網路子系統,用以透過一網路來與一NVMe-TCP裝置進行溝通;以及一資料轉送電路,耦接於該NVMe裝置控制器與該網路子系統之間,用以處理有關該NVMe-TCP裝置的資料轉送;其中該NVMe裝置控制器、該網路子系統以及該資料轉送電路均設置於同一晶片,以及該電腦主機載入並執行PCIe-NVMe驅動程式來控制該電腦主機與該NVMe裝置控制器之間的溝通,且無須具備NVMe-TCP驅動程式。 A computer system includes: a computer host; and a bridge circuit, including: an NVMe device controller for communicating with the computer host through a PCIe bus; a network subsystem for connecting through a network communication with an NVMe-TCP device; and a data transfer circuit, coupled between the NVMe device controller and the network subsystem, for processing data transfer related to the NVMe-TCP device; wherein the NVMe device The controller, the network subsystem and the data transfer circuit are all set on the same chip, and the computer host loads and executes the PCIe-NVMe driver to control the communication between the computer host and the NVMe device controller, and does not need to have NVMe-TCP driver.
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