CN115882792A - Low-frequency low-noise operational amplifier device - Google Patents

Abstract

The invention discloses a low-frequency low-noise operational amplifier device, which comprises a silicon wafer, wherein an oxide layer is arranged on the surface of the silicon wafer, a P-type well region with certain junction depth is arranged in the silicon wafer, the oxide layer covers the P-type well region, and an N-channel region is arranged in the P-type well region, and the low-frequency low-noise operational amplifier device is characterized in that: the N-type grid region and the P-type well region are internally provided with a P-type grid region, the N-type grid region is internally provided with a group of source regions and drain regions, the P-type grid region is integrally in a grid shape, each source region or drain region is separated in a grid divided by the P-type grid region, the group of source regions and drain regions are respectively in ohmic connection through first metal lead posts and expose an oxide layer, a source electrode and a drain electrode are respectively formed through corresponding connection of metal conduction bands, and the P-type grid region is in ohmic connection through second metal lead posts and exposes the oxide layer and is connected through the metal conduction bands to form a grid electrode. The invention can effectively reduce the grid leakage current and reduce the input noise voltage; meanwhile, ohmic contact resistance between the source and drain terminals and the metal can be reduced, and thermal noise voltage can be reduced.

Description

Low-frequency low-noise operational amplifier device

Technical Field

The invention relates to the technical field of semiconductor integrated circuits, in particular to a low-frequency low-noise operational amplifier of a junction field effect transistor.

Background

Under the conditions of remote distance, passive receiving and the like, acoustic signals received by the sonar system are very weak, and electric signals converted by the sensor are also very weak. Thus, a low noise amplifier is required to amplify it in advance, i.e., a low noise preamplifier. Since the frequency spectrum of the acoustic wave signal is 20Hz to 20KHz, a preamplifier with lower low-frequency noise is required.

The sonar sensor is high-impedance, and the input impedance of the preamplifier is high from the perspective of impedance matching; from the noise contribution point of view, the current noise contribution is dominant at this time, so the input noise current and bias current of the preamplifier are required to be very low, and the temperature in the ocean is not considered to be very high, so the amplifier of the JFET input is an ideal choice, and the current noise is nearly 3 orders of magnitude lower than that of the OP series of NPN input.

One practical way to improve the basic performance of a preamplifier is to mix together two standard operational amplifiers, or a standard operational amplifier and discrete transistors, and such a combination is called a composite amplifier. Well-designed composite amplifiers typically have more outstanding performance than standard operational amplifiers. This is because the composite amplifier is optimized for a certain parameter performance, which is difficult to do in standard amplifiers due to process limitations.

Currently, JFETs are used as input stages in order to achieve lower input bias currents, noise currents and noise voltages. The offset voltage of JFET transistors is typically large, from a few millivolts to tens of millivolts, and therefore requires offset trimming circuitry. And the leakage current needs to be finely adjusted in order to minimize JFET current drift.

At present, a JFET device structure is adopted in the industry as an input, the structure usually adopts a strip-shaped grid structure or a ring-shaped grid structure, the grid leakage current is almost larger than 500pA, the output voltage noise reaches more than 8nV/sqrtHz @10Hz, or the output voltage noise reaches 2nV/sqrtHz @1KHz. Low frequency, low noise and extremely low gate leakage current cannot be achieved.

The input buffer amplifier is formed by utilizing the high input impedance and low noise current characteristics of the NJFET device structure, and a common low noise voltage amplifier can be selected as the second stage. The bias current of the current source is required to be used for the same current source, so that noise has coherence, and common-mode noise is eliminated when differential signals are output.

The relation between VDS and Idss of the N-channel JFET is controlled by VGS, and the channel resistance is increased by the pressurization of VGS, so that Idss is reduced.

Disclosure of Invention

In order to solve the above technical problems, the present invention provides a low frequency and low noise operational amplifier device.

The invention adopts the following technical scheme:

the utility model provides a low frequency low noise operational amplifier device, includes that the surface is equipped with the silicon chip of oxide layer, is equipped with the P type well region of certain junction depth in the silicon chip, and the oxide layer covers P type well region, is equipped with N channel region, its characterized in that in P type well region: the N-type grid region and the P-type well region are internally provided with a P-type grid region, the N-type grid region is internally provided with a group of source regions and drain regions, the P-type grid region is integrally in a grid shape, each source region or drain region is separated in a grid divided by the P-type grid region, the group of source regions and drain regions are respectively in ohmic connection through first metal lead posts and expose an oxide layer, a source electrode and a drain electrode are respectively formed through corresponding connection of metal conduction bands, and the P-type grid region is in ohmic connection through second metal lead posts and exposes the oxide layer and is connected through the metal conduction bands to form a grid electrode.

Furthermore, each source region and each drain region have the same structure and comprise an N + source drain region and an N + contact region, the N + source drain region extends into the P-type well region from the N-channel region, the N + source drain region in the N-channel region is outwards expanded through impurity ion implantation to form the N + contact region, and the impurity ion concentration of the N + contact region is greater than that of the N + source drain region.

Further, the source region and the drain region are symmetrically arranged in the grid of the P-type grid region.

Furthermore, an N + grounding region is arranged in the silicon wafers on two sides of the P-type trap region.

Further, the oxide layer is a silicon dioxide layer.

Compared with the prior art, the invention has the following beneficial effects:

according to the scheme, the P-type grid region structure in a grid line shape is adopted, the area of the P-type grid region is increased, the transconductance of the JFET is improved, meanwhile, each source region and each drain region form a structure which is connected in series and then connected in parallel, the grid leakage current can be effectively reduced, and the input noise voltage is reduced; through setting up the structure that introduces the N + contact region at N + source drain region, can reduce source end, drain terminal and intermetallic ohmic contact resistance, can effectual reduction thermal noise voltage, reduce low noise operational amplifier's in the past voltage noise by 8nV/sqrtHz @10Hz to 2nV/sqrtHz @10Hz. And simultaneously, parameters such as saturation current consistency of the device, grid Ig leakage current and the like are ensured to meet requirements.

Drawings

FIG. 1 is a schematic cross-sectional diagram of an embodiment of a low frequency low noise operational amplifier device according to the present invention;

FIG. 2 is a schematic of the top view structure of FIG. 1;

FIG. 3 isbase:Sub>A schematic cross-sectional view of the structure of FIG. 1A-A;

fig. 4 is a graph of gate leakage data for the present example at 5V operating voltage.

Description of reference numerals: 1. a silicon wafer; 2. an oxide layer; 3. a P-type well region; 4. an N-channel region; 5a, a source region; 5b, a drain region; 51. an N + source drain region; 52. an N + contact region; 6. a P-type gate region; 7. an N + ground region; 8. a first metal lead post; 9. a second metal lead post; 10. and (4) a metal conduction band.

Detailed Description

In order to make the present invention more clear, a low frequency and low noise operational amplifier device of the present invention is further described below with reference to the accompanying drawings, and the specific embodiments described herein are only for explaining the present invention and are not used to limit the present invention.

As shown in fig. 1 to 3, a low-frequency and low-noise operational amplifier device includes a silicon wafer 1, and the silicon wafer 1 is a silicon wafer with an epitaxial substrate. An oxide layer 2 is arranged on the upper surface of the silicon wafer 1, and the oxide layer 2 is preferably a silicon dioxide layer. P-type well regions 3,P are formed in the silicon wafer 1 through P-ion implantation, the well regions 3 have certain junction depths, and the oxide layer 2 completely covers the P-type well regions 3. An N-channel region 4 is arranged in the P-type well region 3, and the oxide layer 2 completely covers the N-channel region 4. A set of source regions 5a and a set of drain regions 5b are provided in the N-channel region 4. P-type gate regions 6 with certain junction depth are arranged in the N-channel region 4 and the P-type well regions 3 on two sides of the N-channel region 4, the P-type gate regions 6 are grid-shaped integrally, and each source region 5a or drain region 5b is separated in a single grid divided by the P-type gate regions 6. The source region 5a and the drain region 5b are ohmic-connected and expose the oxide layer 2 through first metal wiring pillars 8, respectively. The source regions 5a and the drain regions 5b are distributed in a matrix shape when viewed from the surface direction of the silicon wafer, and are symmetrically arranged with the diagonal lines of the grids of the P-type gate regions 6. The group of the source regions 5a and the drain regions 5b are arranged in groups in the diagonal direction of the grid of the P-type gate region 6, each group of the source regions 5a is connected in series through a metal conduction band 10, then each group of the source regions 5a is connected in parallel, and finally a source electrode s is formed, similarly, the drain regions 5b are connected in series through the groups, then each group of the drain regions 5b is connected in parallel, and finally a drain electrode d is formed. The P-type gate region 6 located in the N-channel region 4 is in ohmic connection with the second metal lead pillar 9 and exposes the oxide layer 2 to form a top gate, and the P-type gate region 6 located in the silicon wafer 1 is in ohmic connection with the second metal lead pillar 9 and exposes the oxide layer 2 to form a back gate. The second metal lead column 9 is in a grid shape with the same shape as the P-type gate region 6, the top gate and the back gate are interconnected, and the top gate and the back gate are led out through the metal conduction band 10 to form a gate g.

The source region 5a and the drain region 5b have the same structure, and both of them include an N + source drain region 51 and an N + contact region 52, the N + source drain region 51 extends into the silicon wafer 1 from the N channel region 4, the N + source drain region 51 in the N channel region 4 is implanted with impurity ions and expanded to form the N + contact region 52, and the impurity ion concentration of the N + contact region 52 is greater than that of the N + source drain region 51.

In addition, an N + grounding region 7,N + grounding region 7 is further arranged in the silicon chip 1 on both sides of the P-type well region 3 and is led out through a lead (not shown), and the structure can prevent electrostatic influence.

The preparation process of the structure comprises the following steps:

1) Growing an oxide layer 2 on the surface of the silicon wafer 1;

2) Utilizing the conventional photoetching technology, and carrying out ion implantation and drive-in well thermal diffusion on a P-type well region 3 in a substrate;

3) Preparing an N + source drain region, namely forming a plurality of N + source drain regions 51 in the P-type well region 3 by using a photoetching technology and an ion implantation and thermal diffusion mode;

4) Preparing an N channel region, namely forming an N channel region 4 in the P-type well region 3 by using a photoetching technology and an ion injection and thermal diffusion mode;

5) Preparing a P-type gate region, namely forming a grid-shaped P-type gate region 6 in the N-channel region 4 and the P-type well region 3 in an ion implantation and thermal diffusion mode by utilizing a photoetching technology;

6) Preparing an N + contact region, namely forming the N + contact region in an N-channel region by using a photoetching technology and an ion implantation and thermal diffusion mode, wherein the implantation area of the N + contact region correspondingly covers the area of an N + drain source region;

7) Preparing metal, namely forming a source drain electrode and a grid electrode by using metal sputtering, photoetching and etching processes;

8) Preparing a passivation layer, forming a medium protective film layer on the surface of the oxide layer 2 by using a CVD (chemical vapor deposition) process, and exposing the end of the lead to form a PAD (PAD application PAD).

According to the scheme, the P-type grid region structure in a grid line shape is adopted, the area of the P-type grid region is increased, the transconductance of the JFET is improved, and meanwhile, each source and drain respectively form a mutual parallel connection structure, so that the grid leakage current can be effectively reduced, and the input noise voltage is reduced. As shown in fig. 4, a graph of data for gate leakage current at 5V operating voltage was used. As can be seen from the graph, the gate leakage current at this operating voltage is small.

Since the free electrons that make up the conduction current in the conductor are constantly in thermal motion, there is a voltage across any resistor (conductor) even if it is not connected to a power supply. When the resistor with the resistance value of R is not connected into the circuit, the mean square value of the thermal noise voltage generated in the bandwidth of B is as follows:

（Vn）2＝4KT*R*B

k is Boltzmann constant, B is frequency bandwidth

Power spectral density: (Vn) 2/R/B =4KT

Voltage spectral density: (Vn)/(B) 0.5= (4 KTR) 0.5

The thermal noise voltage is a non-periodically changing time function, the frequency range of the thermal noise voltage is wide, and the band is required to be limited to be 10Hz when the thermal noise voltage is applied to a low-frequency and low-noise operational amplifier. Because the relation between the thermal noise and the resistance is large, when the source end introduces the structure of the N + contact area, the ohmic contact resistance between the source end, the drain end and the metal can be reduced, and the thermal noise voltage can be effectively reduced.

The above examples of the present invention are merely examples for clearly illustrating the present invention and are not intended to limit the embodiments of the present invention. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And such obvious changes and modifications which fall within the spirit of the invention are deemed to be covered by the present invention.

Claims (5)

1. The utility model provides a low frequency low noise operational amplifier device, is equipped with silicon chip (1) of oxide layer (2) including the surface, is equipped with certain junction depth's P type trap area (3) in silicon chip (1), and oxide layer (2) cover P type trap area (3), are equipped with N channel region (4), its characterized in that in P type trap area (3): the N-type trap is characterized in that a P-type gate region (6) is arranged in the N-channel region (4) and the P-type trap region (3), a group of source regions (5 a) and drain regions (5 b) are arranged in the N-channel region (4), the P-type gate region (6) is integrally in a grid line shape, each source region (5 a) or drain region (5 b) is separated in a grid divided by the P-type gate region (6), the group of source regions (5 a) and drain regions (5 b) are respectively in ohmic connection through first metal lead posts (8) and expose oxide layers (2), source electrodes and drain electrodes are respectively formed through corresponding connection of metal conduction bands (10), and the P-type gate region (6) is in ohmic connection through second metal lead posts (9) and exposes the oxide layers (2) and is connected through the metal conduction bands (10) to form a grid electrode.

2. A low frequency, low noise operational amplifier device according to claim 1, wherein: each source region (5 a) and each drain region (5 b) are identical in structure and comprise an N + source drain region (51) and an N + contact region (52), the N + source drain regions (51) extend into the P-type well region (3) from the N channel region (4), the N + source drain regions (51) in the N channel region (4) are implanted with impurity ions and expanded to form the N + contact regions (52), and the impurity ion concentration of the N + contact regions (52) is greater than that of the N + source drain regions (51).

3. A low frequency, low noise operational amplifier device according to claim 2, wherein: the source region (5 a) and the drain region (5 b) are symmetrically arranged in the grid of the P-type gate region (6).

4. A low frequency, low noise operational amplifier device according to claim 3, wherein: and an N + grounding region (7) is also arranged in the silicon wafer (1) at the two sides of the P-type well region (3).

5. A low frequency, low noise operational amplifier device, according to claim 1 or 4, wherein: the oxidation layer (2) is a silicon dioxide layer.

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