CN115881779B - Transistor structure, semiconductor structure and preparation method thereof - Google Patents
Transistor structure, semiconductor structure and preparation method thereof Download PDFInfo
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- CN115881779B CN115881779B CN202310078603.2A CN202310078603A CN115881779B CN 115881779 B CN115881779 B CN 115881779B CN 202310078603 A CN202310078603 A CN 202310078603A CN 115881779 B CN115881779 B CN 115881779B
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Abstract
The application relates to a transistor structure, a semiconductor structure and a preparation method thereof. The transistor structure comprises a body region and a drift region; and a source region located within the body region; the drain region is positioned in the drift region; the grid structure is positioned on the body region and the drift region; two ends of the grid structure extend to the source region and the drift region respectively; and a field plate including a first portion located on the drift region and a second portion located on the gate structure; wherein the first portion of the field plate comprises a comb structure. The transistor structure, the semiconductor structure and the preparation method thereof can improve the voltage resistance while forming the current transmission channel with lower on-resistance, and realize good compromise of higher breakdown voltage and lower on-resistance.
Description
Technical Field
The present disclosure relates to the field of semiconductor manufacturing technologies, and in particular, to a transistor structure, a semiconductor structure, and a method for manufacturing the same.
Background
Currently, laterally diffused metal-oxide-semiconductor (LDMOS) transistors are important in integrated circuit design and manufacture, and LDMOS devices are often used in high-voltage power integrated circuits to meet the requirements of high-voltage resistance, power control, and the like, so the goal pursued by LDMOS devices is to obtain higher breakdown voltage and lower on-resistance.
However, in LDMOS device design, the breakdown voltage (Breakdown Voltage, BV) and the on-resistance (Ron, sp) are both strongly limited by the contradictory relationship between drift region length and doping concentration (also referred to as "silicon limit"): and when the Ron, sp & gtBV 2.5 is applied to high voltage, the on-resistance of the LDMOS device is increased sharply, so that the application of the LDMOS device in a high-voltage power integrated circuit is limited. In addition, in the design of the LDMOS device, the problems that the electric field on the surface of the drift region is unevenly distributed or breakdown points are formed on the surface of the drift region and the like are easily caused by too short or too long of the whole field plate, the reliability of the device is reduced, and the space required by the device is larger are easily caused.
Therefore, how to improve the breakdown voltage and on-resistance of the LDMOS device to achieve a good compromise between a higher breakdown voltage and a lower on-resistance is a problem that needs to be solved currently.
Disclosure of Invention
Based on this, it is necessary to provide a transistor structure, a semiconductor structure and a method for manufacturing the same, which address the shortcomings in the prior art.
According to some embodiments, a transistor structure is provided, including a body region and a drift region; and
a source region located within the body region;
the drain region is positioned in the drift region;
the grid structure is positioned on the body region and the drift region; two ends of the grid structure extend to the source region and the drift region respectively; and
a field plate including a first portion on the drift region and a second portion on the gate structure; wherein the first portion of the field plate comprises a comb structure.
In some embodiments, an orthographic projection of the second portion of the field plate onto the body region and the drift region is located within an orthographic projection of the gate structure onto the body region and the drift region.
In some embodiments, there is a gap between a boundary of the second portion of the field plate away from the first portion and a boundary of the gate structure away from the first portion; the interval is greater than a first threshold and less than a second threshold.
In some embodiments, the first portion and the second portion of the field plate are of unitary construction, and the thicknesses of the first portion and the second portion are the same.
In some embodiments, the thickness of the first portion of the field plate is the same as the thickness of the gate structure.
In some embodiments, the transistor structure further comprises:
a shallow trench isolation structure located within the drift region and between the drain region and the gate structure;
the first portion of the field plate is located on the shallow trench isolation structure.
The present application also provides, according to some embodiments, a semiconductor structure comprising:
a substrate; the substrate includes a first device region; and
a transistor structure as provided in any one of the preceding embodiments; wherein the substrate of the first device region is used as the body region and the drift region in the transistor structure.
In some embodiments, the substrate further comprises a second device region;
the second device region is arranged at intervals from the first device region, and a flash memory unit is formed in the second device region; the flash memory cell includes a first gate and a second gate stacked in a direction away from the substrate;
the grid structure and the first grid are arranged in the same layer, and the field plate and the second grid are arranged in the same layer.
According to some embodiments, the present application provides a method for manufacturing a transistor structure, including:
providing a donor region and a drift region;
forming a source region in the body region;
forming a drain region in the drift region;
forming a gate structure on the body region and the drift region; two ends of the grid structure extend to the source region and the drift region respectively;
forming a field plate partially covering the drift region and the gate structure; the part of the field plate located on the drift region is a first part, and the part of the field plate located on the grid structure is a second part; wherein the first portion of the field plate comprises a comb structure.
According to some embodiments, the present application provides a method for manufacturing a semiconductor structure, including:
providing a substrate; the substrate includes a first device region;
forming a transistor structure; the transistor structure is prepared by adopting the preparation method of the transistor structure provided by the embodiment; wherein the substrate of the first device region is used as the body region and the drift region in the transistor structure.
The transistor structure, the semiconductor structure and the preparation method thereof provided by the embodiment of the application have at least the following beneficial effects:
according to the transistor structure and the preparation method thereof, the multi-sub-accumulation layer can be introduced into the surface of the drift region by the first part of the field plate, which is positioned on the drift region, and the resistivity of the multi-sub-accumulation layer is far smaller than that of other regions of the drift region, so that the on-resistance can be reduced by introducing the multi-sub-accumulation layer, and a current transmission channel with lower on-resistance is formed. The first part of the field plate on the drift region further comprises a comb tooth structure, and the gate structure and the field plate can be prevented from being too short as a whole through the comb tooth structure, so that the electric field distribution on the surface of the drift region is effectively improved, and the voltage resistance of the transistor structure is improved. The transistor structure provided by the embodiment of the application can improve the voltage resistance while forming the current transmission channel with lower on-resistance, and realize good compromise of higher breakdown voltage and lower on-resistance.
The semiconductor structure and the preparation method thereof provided in the embodiments of the present application include the transistor structure provided in any one of the foregoing embodiments, so that the technical effects of the transistor structure provided in the foregoing embodiments can be achieved, and the semiconductor structure and the preparation method thereof can also be achieved, which are not repeated herein.
Drawings
In order to more clearly illustrate the technical solutions of embodiments or conventional techniques of the present application, the drawings required for the descriptions of the embodiments or conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a schematic perspective view of a transistor structure according to some embodiments of the present application;
fig. 2 is a schematic top view of a transistor structure according to some embodiments of the present disclosure;
FIG. 3 is a schematic cross-sectional view of a semiconductor structure according to some embodiments of the present application;
fig. 4 is a flow chart illustrating a method for manufacturing a transistor structure according to some embodiments of the present disclosure;
fig. 5 is a schematic perspective view of a structure obtained in step S104 in the method for manufacturing a transistor structure according to some embodiments of the present application;
fig. 6 is a schematic perspective view of a structure obtained in step S105 in the method for manufacturing a transistor structure according to some embodiments of the present application;
fig. 7 is a flow chart illustrating a method for fabricating a semiconductor structure according to some embodiments of the present disclosure;
fig. 8 is a schematic cross-sectional structure diagram of a gate structure and a first gate structure formed in a method for manufacturing a semiconductor structure according to some embodiments of the present application;
fig. 9 is a schematic cross-sectional structure of a structure obtained in step S2 in a method for manufacturing a semiconductor structure according to some embodiments of the present application.
Reference numerals illustrate:
1. a transistor structure; 111. a body region; 112. a drift region; 121. a source region; 122. a drain region; 123. a body contact region; 13. a gate structure; 14. a field plate; 141. a first portion; 142. a second portion; 15. shallow trench isolation structures; 2. a substrate; 3. a flash memory unit; 31. a first gate; 32. a second gate; m, comb tooth structure; d. spacing; A. a first device region; B. and a second device region.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "on," or "on" another element or layer, it can be directly on, or on the other element or layer, or intervening elements or layers may be present. It will be understood that, although the terms first, second, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, device regions and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, device region or section from another element, component, region, layer, device region or section. Thus, a first element, component, region, layer, device region or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application; for example, the first device region may be referred to as a second device region, and similarly, the second device region may be referred to as a first device region; the first device region and the second device region are different device regions.
Spatial relationship terms such as "located on," "on," or "on," and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "on," "on," or "upper" would then be oriented "under" the other elements or features. Thus, the exemplary terms "located on," "on," and "on" can include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present application, such that variations of the illustrated shapes due to, for example, manufacturing techniques and/or tolerances are to be expected. Embodiments of the present application should not be limited to the particular shapes of regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing techniques. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present application.
In view of the shortcomings in the prior art, the application provides a transistor structure, a semiconductor structure and a preparation method thereof, which can improve the voltage resistance of a transistor and realize good compromise between higher breakdown voltage and lower on resistance while forming a current transmission channel with lower on resistance. The details of which will be elucidated in the following examples.
According to some embodiments, a transistor structure 1 is provided. In the present embodiment, the transistor structure 1 may include, but is not limited to, an LDMOS.
Referring to fig. 1, in some embodiments, the transistor structure 1 may include a body region 111, a drift region 112, a source region 121, a drain region 122, a gate structure 13, and a field plate 14.
Wherein source region 121 is located within body region 111; drain region 122 is located within drift region 112. The gate structure 13 is located on the body region 111 and the drift region 112, and two ends of the gate structure 13 extend onto the source region 121 and the drift region 112, respectively.
The field plate 14 includes a first portion 141 located on the drift region 112 and a second portion 142 located on the gate structure 13. Wherein the first portion 141 of the field plate 14 comprises a comb structure m.
In the transistor structure 1 provided in the foregoing embodiment, when the transistor structure is turned on in the forward direction, the first portion 141 of the field plate 14 located on the drift region 112 may introduce a multi-sub-accumulation layer on the surface of the drift region 112, where the resistivity of the multi-sub-accumulation layer is far smaller than that of other regions of the drift region 112, so that the on-resistance can be reduced by introducing the multi-sub-accumulation layer, thereby forming a current transmission channel with a lower on-resistance.
In the transistor structure 1 provided in the foregoing embodiment, the first portion 141 of the field plate 14 on the drift region 112 further includes the comb-tooth structure m, and by setting the comb-tooth structure m, the gate structure 13 and the field plate 14 can be prevented from being too short, so that the electric field distribution on the surface of the drift region 112 is effectively improved, and the voltage-withstanding performance of the transistor structure 1 is improved.
The transistor structure 1 provided in the above embodiment can improve the voltage resistance while forming the current transmission channel with lower on-resistance, and achieve a good compromise between higher breakdown voltage and lower on-resistance.
Note that, in the embodiment of the present application, the two ends of the gate structure 13 extend onto the source region 121 and the drift region 112 respectively, which means that: both ends of the gate structure 13 in the channel direction (the direction in which the source region 121 and the drain region 122 are connected) extend onto the source region 121 and the drift region 112, respectively.
It should be further noted that, in the embodiment of the present application, the width of each comb tooth in the comb tooth structure m and the spacing between adjacent comb teeth are not specifically limited, and the width of each comb tooth in the comb tooth structure m and the spacing between adjacent comb teeth can be adaptively set according to actual requirements.
In addition, the comb tooth structure m in the embodiment of the present application refers to: the structure is the same as or similar to the comb tooth structure; for example, structures similar to comb structures may include convex finger-shaped spacing structures.
The shape of the field plate 14 is not particularly limited in this application. Referring to fig. 2, in some embodiments, the front projection of the second portion 142 of the field plate 14 onto the body region 111 and the drift region 112 may be located within the front projection of the gate structure 13 onto the body region 111 and the drift region 112.
The length of the field plate 14 in the channel direction is not particularly limited, and the length of the field plate 14 in the channel direction can be adaptively set according to actual requirements. With continued reference to fig. 2, in some embodiments, a space d is provided between a boundary of the second portion 142 of the field plate 14 away from the first portion 141 and a boundary of the gate structure 13 away from the first portion 141. The interval d may be greater than the first threshold and less than the second threshold.
In general, the electric field peaks of the drift region 112, which are the most likely breakdown points, tend to occur at both ends of the field plate 14 and near the source 121 or drain 122 regions. In the transistor structure 1 provided in the above embodiment, the boundary of the second portion 142 of the field plate 14 away from the first portion 141 and the boundary of the gate structure 13 away from the first portion 141 have a space d therebetween, so that the gate structure 13 and the field plate 14 can together form a "convex" stacked structure. Compared with the conventional transistor structure in which the gate structure 13 and the field plate 14 together form a square stacked structure, the transistor structure 1 provided in the above embodiment can further avoid the gate structure 13 and the field plate 14 from being too short or too long, so as to improve the electric field distribution on the surface of the drift region 112 under the condition that the length of the drift region 112 is unchanged, avoid the occurrence of breakdown points on the surface of the drift region 112, further improve the voltage-withstanding performance of the transistor structure 1, and further improve the reliability of the device of the transistor structure 1.
In the embodiment of the present application, the values of the first threshold value and the second threshold value are not particularly limited, as long as the value of the second threshold value is larger than the value of the first threshold value. The numbers of the first threshold and the second threshold can be adaptively set according to actual requirements.
With continued reference to fig. 1-2, in some embodiments, the first portion 141 and the second portion 142 of the field plate 14 may be of unitary construction.
The thickness of the field plate 14 is not particularly limited in this application. In some embodiments, the thickness of the first portion 141 may be the same as the thickness of the second portion 142. In other embodiments, the thickness of the first portion 141 of the field plate 14 may be the same as the thickness of the gate structure 13.
With continued reference to fig. 1, in some embodiments, the transistor structure 1 may further include a body contact region 123.
It is understood that source region 121 and body contact region 123 may both be formed within body region 111 by an implantation process. In some embodiments, body region 111 is a P-type body region, then source region 121 is an n+ source region and body contact region 123 is a p+ body contact region; correspondingly, the drift region 112 is an N-type drift region.
With continued reference to fig. 1-2, in some embodiments, the transistor structure 1 may further include a shallow trench isolation structure 15.
Shallow trench isolation structure 15 is located within drift region 112 and between drain region 122 and gate structure 13. The first portion 141 of the field plate 14 is located on the shallow trench isolation structure 15.
The present application also provides, in accordance with some embodiments, a semiconductor structure.
Referring to fig. 3, in some embodiments, the semiconductor structure may include a substrate 2 and a transistor structure 1 as provided in any of the foregoing embodiments.
Wherein the substrate 2 may comprise a first device region a. On the basis of this, the substrate 2 of the first device region a can be used as the body region 111 and the drift region 112 in the transistor structure 1.
The semiconductor structure provided in the foregoing embodiments includes the transistor structure 1 provided in any one of the foregoing embodiments, so that the technical effects that can be achieved by the transistor structure 1 provided in the foregoing embodiments can be achieved, and the description of the semiconductor structure is omitted here.
With continued reference to fig. 3, in some embodiments, the substrate 2 may further include a second device region B, which may be spaced apart from the first device region a.
With continued reference to fig. 3, in some embodiments, a flash memory cell 3 may be formed within the second device region B.
The flash memory cell 3 may include a first gate 31 and a second gate 32 stacked in a direction away from the substrate 2. The gate structure 13 in the transistor structure 1 may be arranged in the same layer as the first gate 31 and the field plate 14 in the transistor structure 1 may be arranged in the same layer as the second gate 32.
It should be noted that, in the embodiment of the present application, the gate structure 13 in the transistor structure 1 may be disposed in the same layer as the first gate 31, which means: the gate structure 13 and the first gate 31 in the transistor structure 1 may be made of the same material and prepared by the same patterning process; the field plate 14 in the transistor structure 1 may be arranged in the same layer as the second gate 32, which means that: the field plate 14 and the second gate electrode 32 in the transistor structure 1 may be made of the same material and manufactured by the same patterning process.
In the semiconductor structure provided in the above embodiment, the gate structure 13 in the transistor structure 1 is arranged in the same layer as the first gate 31, and the field plate 14 in the transistor structure 1 is arranged in the same layer as the second gate 32, so that it is not necessary to add an additional photomask to form the gate structure 13 or the field plate 14 in the process of preparing the semiconductor structure, and therefore, the production cost can be reduced. Since the gate structure 13 can be formed simultaneously during the formation of the first gate electrode 31 and the field plate 14 can be formed simultaneously during the formation of the second gate electrode 32, the process steps required for preparing the semiconductor structure can be simplified, thereby improving the production efficiency.
The present application also provides, according to some embodiments, a method of fabricating a transistor structure. The method for manufacturing a transistor structure may be used to manufacture the transistor structure 1 provided in some of the foregoing embodiments.
Referring to fig. 4, in one embodiment, the method for manufacturing the transistor structure may include the following steps:
s101: a body region and a drift region are provided.
S102: a source region is formed in the body region.
S103: and forming a drain region in the drift region.
S104: forming a grid structure on the body region and the drift region; two ends of the grid structure extend to the source region and the drift region respectively.
S105: forming a field plate partially covering the drift region and the gate structure; the part of the field plate, which is positioned on the drift region, is a first part, and the part of the field plate, which is positioned on the grid structure, is a second part; wherein the first portion of the field plate comprises a comb structure.
According to the preparation method of the transistor structure, the field plate partially covering the drift region and the gate structure is formed, so that when the field plate is conducted in the forward direction, the first part of the field plate, which is positioned on the drift region, can introduce the multi-sub-accumulation layer on the surface of the drift region, and the resistivity of the multi-sub-accumulation layer is far smaller than that of other regions of the drift region, and therefore the on-resistance can be reduced by introducing the multi-sub-accumulation layer, and a current transmission channel with lower on-resistance is formed.
According to the preparation method of the transistor structure, the first part of the field plate, which is located on the drift region, is further provided with the comb-tooth structure, and the gate structure and the field plate can be prevented from being too short as a whole by forming the comb-tooth structure, so that the electric field distribution on the surface of the drift region is effectively improved, and the voltage resistance of the transistor structure is improved.
The preparation method of the transistor structure provided by the embodiment can improve the voltage resistance while forming the current transmission channel with lower on-resistance, and realize good compromise between higher breakdown voltage and lower on-resistance.
Some embodiments of the present application are understood below in conjunction with fig. 5-6.
Referring to fig. 5, in step S101, a body region 111 and a drift region 112 are provided.
With continued reference to fig. 5, in step S102, a source region 121 is formed within the body region 111.
With continued reference to fig. 5, in step S103, a drain region 122 is formed within the drift region 112.
With continued reference to fig. 5, in step S104, a gate structure 13 is formed on the body region 111 and the drift region 112, and two ends of the gate structure 13 extend onto the source region 121 and the drift region 112, respectively.
Referring to fig. 6, in step S105, a field plate 14 is formed to partially cover the drift region 112 and the gate structure 13. The portion of the field plate 14 located on the drift region 112 is a first portion 141 and the portion of the field plate 14 located on the gate structure 13 is a second portion 142. Wherein the first portion 141 of the field plate 14 comprises a comb structure m.
The present application also provides, according to some embodiments, a method of fabricating a semiconductor structure. The method for manufacturing the transistor structure can be used for manufacturing the semiconductor structure provided by the embodiments.
Referring to fig. 7, in some embodiments, the method for manufacturing the semiconductor structure may include the following steps:
s1: a substrate is provided, the substrate including a first device region.
S2: forming a transistor structure; the substrate of the first device region is used as a body region and a drift region in the transistor structure.
It should be noted that, in step S2, the transistor structure may be prepared by using the preparation method of the transistor structure provided in the foregoing embodiment.
The method for manufacturing a semiconductor structure provided in the foregoing embodiment includes the step of manufacturing a transistor structure by using the method for manufacturing a transistor structure, so that the technical effects achieved by the method for manufacturing a transistor structure can be achieved, and the method for manufacturing a semiconductor structure is not repeated here.
Some embodiments of the present application are understood below in conjunction with fig. 8-9.
Referring to fig. 8, in step S1, a substrate 2 is provided. The substrate 2 may comprise a first device region a.
Referring to fig. 9, in step S2, a transistor structure 1 is formed. The transistor structure 1 may be manufactured by a manufacturing method of the transistor structure 1 provided in the foregoing embodiment, and the substrate 2 of the first device region a is used as the body region 111 and the drift region 112 in the transistor structure 1.
With continued reference to fig. 8, in some embodiments, the substrate 2 may further include a second device region B. The second device region B may be spaced apart from the first device region a.
With continued reference to fig. 9, in some embodiments, a flash memory cell 3 may be formed within the second device region B, and the flash memory cell 3 may include a first gate 31 and a second gate 32 stacked in a direction away from the substrate 2.
As shown in fig. 8, in some embodiments, the following steps may be used to form the gate structure 13 on the body region 111 and the drift region 112, for example:
forming a first gate material layer; the first gate material layer is patterned to form the gate structure 13 and the first gate 31.
In the method for manufacturing a semiconductor structure provided in the above embodiment, the gate structure 13 and the first gate 31 in the transistor structure 1 are arranged in the same layer, so that an additional photomask is not required to be added to form the gate structure 13 in the process of manufacturing the semiconductor structure, thereby reducing the production cost. Since the gate structure 13 can be formed simultaneously during the formation of the first gate electrode 31, the process steps of the method for manufacturing the semiconductor structure can be simplified, thereby improving the production efficiency.
As shown in fig. 9, in some embodiments, the following steps may be used to form the field plate 14 that partially covers the drift region 112 and the gate structure 13, for example:
a second layer of gate material is formed and patterned to form field plate 14 and second gate 32.
In the method for manufacturing a semiconductor structure provided in the above embodiment, the field plate 14 and the second gate electrode 32 in the transistor structure 1 are arranged in the same layer, so that an additional photomask is not required to be added to form the field plate 14 in the process of manufacturing the semiconductor structure, thereby reducing the production cost. Since the field plates 14 can be simultaneously formed during the formation of the second gate electrode 32, the process steps of the method for manufacturing the semiconductor structure can be simplified, thereby improving the production efficiency.
It should be understood that, although the steps in the flowcharts of fig. 4 and 7 are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in fig. 4 and 7 may include a plurality of steps or stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily sequential, but may be performed in rotation or alternately with at least a portion of the steps or stages in other steps or other steps.
It should be noted that, the preparation methods provided in the embodiments of the present application may be used to prepare corresponding structures, so that technical features between the method embodiments and the structural embodiments may be replaced and supplemented with each other on the premise of not generating conflict, so that those skilled in the art can learn about the technical content of the present application.
The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (10)
1. A transistor structure is characterized by comprising a body region and a drift region; and
a source region located within the body region;
the drain region is positioned in the drift region;
the grid structure is positioned on the body region and the drift region; two ends of the grid structure extend to the source region and the drift region respectively; and
a field plate including a first portion on the drift region and a second portion on the gate structure; the first part and the second part of the field plate are of an integral structure, wherein the first part of the field plate comprises a comb tooth structure, and orthographic projection of the second part of the field plate on the body region and the drift region is positioned in orthographic projection of the grid structure on the body region and the drift region; a space is reserved between the boundary of the second part of the field plate away from the first part and the boundary of the grid structure away from the first part; the interval is greater than a first threshold and less than a second threshold; the top surface of the second part of the field plate is higher than the top surface of the comb-tooth structure, and the bottom surface of the second part of the field plate is higher than the bottom surface of the comb-tooth structure;
the transistor structure further includes:
a shallow trench isolation structure located within the drift region and between the drain region and the gate structure;
the first portion of the field plate is located on the shallow trench isolation structure.
2. The transistor structure according to claim 1, wherein,
the thickness of the first and second portions of the field plate is the same.
3. The transistor structure of claim 1, wherein a thickness of the first portion of the field plate is the same as a thickness of the gate structure.
4. The transistor structure of claim 1, further comprising:
a body contact region located within the body region; the body contact region is adjacent to the source region and is positioned on one side of the source region away from the drift region;
the body region is a P-type body region, the source region is an N+ source region, the body contact region is a P+ body contact region, and the drift region is an N-type drift region.
5. A semiconductor structure, comprising:
a substrate; the substrate includes a first device region; and
the transistor structure of any of claims 1 to 4; wherein the substrate of the first device region is used as the body region and the drift region in the transistor structure.
6. The semiconductor structure of claim 5, wherein the substrate further comprises a second device region;
the second device region is arranged at intervals from the first device region, and a flash memory unit is formed in the second device region; the flash memory cell includes a first gate and a second gate stacked in a direction away from the substrate;
the grid structure and the first grid are arranged in the same layer, and the field plate and the second grid are arranged in the same layer.
7. A method of manufacturing a transistor structure, characterized by being used for manufacturing a transistor structure according to any of claims 1 to 4; the preparation method of the transistor structure comprises the following steps:
providing a donor region and a drift region; a shallow trench isolation structure is arranged in the drift region;
forming a source region in the body region;
forming a drain region in the drift region;
forming a gate structure on the body region and the drift region; two ends of the grid structure extend to the source region and the drift region respectively, and orthographic projections of the grid structure on the body region and the drift region are positioned between the source region and the shallow trench isolation structure;
forming a field plate partially covering the drift region and the gate structure; the part of the field plate located on the drift region is a first part, and the part of the field plate located on the grid structure is a second part; the first part and the second part of the field plate are of an integrated structure, wherein the first part of the field plate comprises a comb tooth structure and is positioned on the shallow trench isolation structure; the orthographic projection of the second portion of the field plate on the body region and the drift region is located within the orthographic projection of the gate structure on the body region and the drift region; a space is reserved between the boundary of the second part of the field plate away from the first part and the boundary of the grid structure away from the first part; the interval is greater than a first threshold and less than a second threshold; the top surface of the second portion of the field plate is higher than the top surface of the comb-tooth structure, and the bottom surface of the second portion of the field plate is higher than the bottom surface of the comb-tooth structure.
8. A method of fabricating a semiconductor structure, comprising:
providing a substrate; the substrate includes a first device region;
forming a transistor structure; the transistor structure is prepared by adopting the preparation method of the transistor structure as claimed in claim 7; wherein the substrate of the first device region is used as the body region and the drift region in the transistor structure.
9. The method of fabricating a semiconductor structure of claim 8, wherein the substrate further comprises a second device region; the second device region is arranged at intervals from the first device region, and a flash memory unit is formed in the second device region; the flash memory cell includes a first gate and a second gate stacked in a direction away from the substrate;
forming a gate structure on the body region and the drift region, including:
forming a first gate material layer;
the first gate material layer is patterned to form the gate structure and the first gate.
10. The method of claim 9, wherein forming a field plate partially covering the drift region and the gate structure, comprises:
forming a second gate material layer;
the second gate material layer is patterned to form the field plate and the second gate.
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