CN115881725A - Integrated device structure and preparation method thereof - Google Patents

Abstract

The present disclosure provides an integrated device structure, comprising: a silicon substrate having opposing first and second sides; a fin transistor located on a first side of the silicon substrate; a fin transistor located on a second side of the silicon substrate; the bonding pad is positioned on the first side of the silicon substrate and electrically connected with the fin type transistor on the first side of the silicon substrate; the silicon substrate is provided with through connecting holes, connecting structures are arranged in the connecting holes, and the fin type transistor on the first side of the silicon substrate is electrically connected with the fin type transistor on the second side of the silicon substrate through the connecting structures. The disclosure also provides a method for manufacturing the integrated device structure.

Description

Integrated device structure and preparation method thereof

Technical Field

The present disclosure relates to the field of integrated circuit technologies, and in particular, to an integrated device structure and a method for fabricating the same.

Background

In integrated circuits such as chips (ICs), devices are typically fabricated on only one side of a substrate (e.g., a silicon substrate), and transistors (e.g., field effect transistors, FETs) are one of the devices commonly used therein.

In order to increase the integration density, there have been attempts to reduce the size of the transistor, but the size of the existing transistor has reached 3nm or less, and the space for further reduction is limited.

Disclosure of Invention

The present disclosure provides an integrated device structure and a method of fabricating the same.

In a first aspect, an embodiment of the present disclosure provides an integrated device structure, which includes:

a silicon substrate having opposing first and second sides;

a fin transistor located on a first side of the silicon substrate;

a fin transistor located on a second side of the silicon substrate;

the bonding pad is positioned on the first side of the silicon substrate and electrically connected with the fin type transistor on the first side of the silicon substrate;

the fin-type transistor on the first side of the silicon substrate is electrically connected with the fin-type transistor on the second side of the silicon substrate through the connecting structure.

In some embodiments, the silicon substrate includes a first sub-silicon substrate, a second sub-silicon substrate, and an insulating isolation layer connecting the first sub-silicon substrate and the second sub-silicon substrate, which are stacked.

In some embodiments, the first side of the silicon substrate is provided with at least one insulating layer which is farther away from the silicon substrate than the fin-type transistors, one side of each insulating layer, which is far away from the silicon substrate, is provided with a connecting wire, and the fin-type transistors on the first side of the silicon substrate are electrically connected with the bonding pads through the connecting wires on the same side;

the second side of the silicon substrate is provided with at least one insulating layer which is farther away from the silicon substrate than the fin-type transistor, one side of each insulating layer, which is far away from the silicon substrate, is provided with a connecting wire, and the fin-type transistor on the second side of the silicon substrate is electrically connected with the connecting wire on the first side of the silicon substrate through the connecting wire and the connecting structure on the same side.

In some embodiments, a fin transistor includes a gate, an active region of a fin;

the active region comprises a first contact region, a second contact region and a channel region; one side of the channel region, which is far away from the silicon substrate, and two opposite sides of the channel region along a first direction parallel to the surface of the silicon substrate are provided with grids; the first contact area and the second contact area are respectively positioned on two opposite sides of the channel area along the second direction; the second direction is parallel to the surface of the silicon substrate and intersects the first direction.

In some embodiments, the fin transistor has corresponding connection bumps;

the connection protrusion and the silicon substrate form an integral structure, and the active region and the connection protrusion form an integral structure.

In some embodiments, the channel region includes a plurality of sub-channel regions spaced apart in a direction away from the silicon substrate, with a gate disposed in a space between adjacent sub-channel regions;

the first contact area comprises a plurality of first sub-contact areas in one-to-one correspondence with the sub-channel areas, and the second contact area comprises a plurality of second sub-contact areas in one-to-one correspondence with the sub-channel areas;

two opposite sides of each sub-channel region along the second direction are respectively connected with the first sub-contact region and the second sub-contact region.

In a second aspect, an embodiment of the present disclosure provides a method for manufacturing an integrated device structure, where the integrated device structure is any one of the integrated device structures in the embodiments of the present disclosure; the preparation method comprises the following steps:

providing a silicon substrate;

a fin-type transistor and a bonding pad are formed on a first side of a silicon substrate, a fin-connected transistor is formed on a second side of the silicon substrate, a connecting hole is formed in the silicon substrate, and a connecting structure is formed in the connecting hole.

In some embodiments, the silicon substrate has an isolation layer; providing a silicon substrate includes:

forming a first sub-isolation layer on one side of the first sub-silicon substrate, and forming a second sub-isolation layer on one side of the second sub-silicon substrate;

and connecting the first sub-isolation layer and the second sub-isolation layer to form an isolation layer, thereby obtaining the silicon substrate.

In some embodiments, the fin transistor includes a gate, an active region of a fin; the active region comprises a first contact region, a second contact region and a channel region; one side of the channel region, which is far away from the silicon substrate, and two opposite sides of the channel region along a first direction parallel to the surface of the silicon substrate are provided with grids; the first contact area and the second contact area are respectively positioned on two opposite sides of the channel area along the second direction; the second direction is parallel to the surface of the silicon substrate and intersects with the first direction;

forming a fin transistor and a pad on a first side of the silicon substrate, forming a fin-connected transistor on a second side of the silicon substrate, forming a connection hole in the silicon substrate, and forming a connection structure in the connection hole includes:

forming a fin type transistor substrate on the first side of the silicon substrate; the fin transistor substrate comprises the active region;

forming a first planarization layer on a first side of the silicon substrate, and disposing a first support substrate on the first planarization layer;

turning over the silicon substrate, and forming a fin type transistor matrix on the second side of the silicon substrate;

forming a grid electrode of the fin-type transistor on the second side of the silicon substrate to obtain the fin-type transistor;

forming a second planarization layer on a second side of the silicon substrate, a second support substrate being disposed on the second planarization layer;

turning over the silicon substrate and removing the first support substrate;

and forming a grid electrode of the fin-type transistor on the first side of the silicon substrate to obtain the fin-type transistor.

In some embodiments, the integrated device structure has an insulating layer and a connection line; after the forming the gate of the fin transistor on the first side of the silicon substrate, the method further comprises:

forming the insulating layer, the connecting wire and the bonding pad on the first side of the silicon substrate, and then arranging a third supporting substrate;

turning over the silicon substrate and removing the second supporting substrate;

forming the insulating layer and the connecting wire on the second side of the silicon substrate, forming a connecting hole in the silicon substrate, and forming a connecting structure in the connecting hole;

and removing the third supporting substrate.

According to the related technology, compared with the device arranged on one side of the silicon substrate, the number of devices can be greatly increased and the integration density can be improved under the condition that the size of a single device is not changed; or, under the condition of the same integration density, the size of the device used in the embodiment of the present disclosure can be significantly increased, thereby reducing the difficulty and cost of the preparation process, reducing crosstalk and parasitic effect between devices, and improving the product performance.

Drawings

The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the detailed description serve to explain the disclosure and not limit the disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing in detail embodiments with reference to the attached drawings in which:

fig. 1 is a schematic cross-sectional structural diagram of an integrated device structure along a first direction according to an embodiment of the present disclosure;

FIG. 2 is a schematic cross-sectional structural view of the integrated device structure of FIG. 1 along a second direction;

fig. 3 is a schematic cross-sectional structure view of another integrated device structure provided in the embodiment of the present disclosure along a first direction;

FIG. 4 is a schematic cross-sectional structural view of the integrated device structure of FIG. 3 along a second direction;

fig. 5 is a flowchart of a method for fabricating an integrated device structure according to an embodiment of the present disclosure;

fig. 6 is a flow chart of another method for fabricating an integrated device structure provided by an embodiment of the present disclosure;

FIG. 7 is a schematic cross-sectional structural view illustrating a process of forming a silicon substrate in another integrated device structure fabrication method according to an embodiment of the present disclosure;

fig. 8 is a schematic cross-sectional structure diagram of another method for manufacturing an integrated device structure according to an embodiment of the present disclosure after a fin transistor substrate on a first side is formed;

fig. 9 is a schematic cross-sectional structural diagram after a first supporting substrate is disposed in another integrated device structure fabrication method according to an embodiment of the disclosure;

fig. 10 is a schematic cross-sectional structural view of another method for manufacturing an integrated device structure according to an embodiment of the present disclosure after forming a fin transistor on a second side;

fig. 11 is a schematic cross-sectional structural view after a second supporting substrate is disposed in another integrated device structure fabrication method provided by an embodiment of the present disclosure;

fig. 12 is a schematic cross-sectional structural view after a fin transistor on a first side is formed in another integrated device structure manufacturing method according to an embodiment of the present disclosure;

fig. 13 is a schematic cross-sectional structural view after a third supporting substrate is disposed in another integrated device structure fabrication method provided by an embodiment of the present disclosure;

fig. 14 is a schematic cross-sectional structural view of another integrated device structure provided in the embodiments of the present disclosure after removing the second supporting substrate;

fig. 15 is a schematic cross-sectional structural diagram illustrating a second-side connection line formed in another method for manufacturing an integrated device structure according to an embodiment of the present disclosure;

FIG. 16 is a schematic cross-sectional structural view of an integrated device structure fabricated by another integrated device structure fabrication method provided by an embodiment of the present disclosure;

wherein the reference numbers are: 1. a silicon substrate; 11. a first sub-silicon substrate; 12. a first sub-silicon substrate; 13. an isolation layer; 19. a silicon substrate; 191. a first sub-silicon substrate; 192. a first sub-silicon substrate; 1931. a first sub-isolation layer; 1932. a second sub-isolation layer; 21. a connecting projection; 22. a filling layer; 3. a fin transistor; 31. a channel region; 311. a sub-channel region; 32. a gate electrode; 321. a gate insulating layer; 331. a first contact area; 3311. a first sub-contact region; 332. a second contact area; 3321. a second sub-contact region; 71. a first planarizing layer; 72. a second planarizing layer; 81. a first support substrate; 82. a second support substrate; 83. a third support substrate; 89. a tie layer; 4. a connecting structure; 91. a connecting wire; 92. a pad; 99. an insulating layer.

Detailed Description

In order to make those skilled in the art better understand the technical solution of the present disclosure, the following describes the integrated device structure and the manufacturing method thereof provided by the present disclosure in detail with reference to the attached drawings.

The present disclosure will be described more fully hereinafter with reference to the accompanying drawings, but the illustrated embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth in the disclosure. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

The present disclosure may be described with reference to plan and/or cross-sectional views by way of idealized schematic illustrations of the present disclosure. Accordingly, the example illustrations may be modified in accordance with manufacturing techniques and/or tolerances.

Embodiments of the present disclosure and features of embodiments may be combined with each other without conflict.

The terminology used in the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used in this disclosure, the term "and/or" includes any and all combinations of one or more of the associated listed items. As used in this disclosure, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises," "comprising," "includes," "including," "comprises," "including," "comprising," "including," "involving," and/or "including," when used in this disclosure, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used in this disclosure have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

The present disclosure is not limited to the embodiments shown in the drawings, but includes modifications of configurations formed based on a manufacturing process. Thus, the regions illustrated in the figures have schematic properties, and the shapes of the regions shown in the figures illustrate specific shapes of regions of elements, but are not intended to be limiting.

In a first aspect, referring to fig. 1 to 4, an embodiment of the present disclosure provides an integrated device structure, which includes:

a silicon substrate 1, the silicon substrate 1 having opposite first and second sides;

a fin transistor 3 located on a first side of the silicon substrate 1;

a fin transistor 3 located on a second side of the silicon substrate 1;

a bonding pad 92 positioned on the first side of the silicon substrate 1, wherein the bonding pad 92 is electrically connected with the fin type transistor on the first side of the silicon substrate 1;

the silicon substrate 1 is provided with a through connection hole, a connection structure 4 is arranged in the connection hole, and the fin-type transistor 3 on the first side of the silicon substrate 1 is electrically connected with the fin-type transistor 3 on the second side through the connection structure 4.

The integrated device structure of the disclosed embodiments may be in the form of an integrated circuit such as a chip (IC).

The silicon substrate 1 is a sheet-like or plate-like structure mainly made of silicon-based semiconductor material (e.g., polysilicon or amorphous silicon), two main surfaces of the silicon substrate 1 correspond to two opposite sides (a first side and a second side), and the main surfaces of the silicon substrate 1 are used for disposing other devices in the integrated device structure, that is, the silicon substrate 1 is a base for carrying other devices.

In the embodiment of the present disclosure, a fin Transistor 3, such as a Field Effect Transistor (FET), is disposed on each of the first and second sides of the silicon substrate 1.

The Fin transistor 3 is a kind of transistor having an active region in a shape of a "Fin".

Referring to fig. 1 and 3, the active region of the fin-type transistor 3 is entirely in a "vertical" sheet (fin) shape and includes a channel region (channel) 31 functioning as a switch, so that "two sides (two opposite sides along the first direction)" and "above (a side away from the connection protrusion 21)" of the channel region 31 are provided with a gate 32, that is, the gate 32 can surround the channel region 31 from multiple directions, so that the sensing area under the same size is larger, and the size of the transistor can be further reduced to improve the integration density.

It will be appreciated that the above gate electrode 32 and the channel region 31 must be separated by a gate insulating layer 321 to achieve mutual insulation.

It should be understood that the integrated device structure of the embodiment of the present disclosure may be provided with other devices, such as a capacitor, an inductor, a Thin Film Transistor (TFT), etc., besides the fin Transistor 3, and will not be described in detail herein.

On the first side of the silicon substrate 1, a PAD 92 (PAD) is further provided, which is used for connecting with an external device (such as a PIN, etc.), so as to implement signal transmission between the integrated device structure and the outside. In particular, referring to fig. 3, the bond pad 92 may be disposed on the outermost layer of the integrated device structure.

The bonding pad 92 is electrically connected to other devices (including the fin transistor 3) on the first side of the silicon substrate 1, i.e., the other devices on the first side can be connected to the outside.

Meanwhile, a through connecting hole is also formed in the silicon substrate 1; the connection holes are provided with electrically conductive connection structures 4.

Thus, the connection structure 4 may electrically connect other devices (including the fin transistor 3) on the second side of the silicon substrate 1 to the first side, so that the devices on the two sides of the silicon substrate 1 form an integral circuit and are connected to the outside through the bonding pads 92 on the first side.

The specific manner in which the fin transistor 3 is electrically connected is various. For example, the first electrode (one of the source and the drain), the second electrode (the other of the source and the drain), the gate electrode 32, and the like of the fin transistor 3 are electrically connected to other devices, and can be regarded as electrical connection of the fin transistor 3; for another example, the different fin transistors 3 may be electrically connected directly or indirectly through a connection line 91 or the like.

It should be understood that the connection hole (connection structure 4) should communicate with the layer (e.g., through a portion of the insulating layer 99) where the structure is connected, in addition to penetrating through the silicon substrate 1. In the embodiment of the disclosure, the two sides of the silicon substrate 1 are both provided with the fin-type transistors 3, the fin-type transistors 3 on the two sides are connected into an integral circuit through the connection structure 4 in the silicon substrate 1, and the circuit only leads out signals from one side of the silicon substrate 1 (only the first side is provided with the bonding pad 92), so that compared with the related technology that devices are only arranged on one side of the silicon substrate, the embodiment of the disclosure can greatly increase the number of devices and improve the integration density under the condition that the size of a single device is not changed; or, under the condition of the same integration density, the size of the device used in the embodiment of the present disclosure can be significantly increased, thereby reducing the difficulty and cost of the preparation process, reducing crosstalk and parasitic effect between devices, and improving the product performance.

In some embodiments, the silicon substrate 1 includes a first sub silicon substrate 11, a second sub silicon substrate 12, and an insulating isolation layer 13 connecting the first sub silicon substrate 11 and the second sub silicon substrate 12, which are stacked.

In the embodiment of the present disclosure, the fin transistors 3 are disposed on both sides of the silicon substrate 1, so that the two sides of the silicon substrate 1 are insulated from each other to avoid undesired electrical connection between the fin transistors 3 on both sides.

Specifically, referring to fig. 3 and 4, the silicon substrate 1 may include two sub-silicon substrates (a first sub-silicon substrate 11 and a second sub-silicon substrate 12) made of silicon-based semiconductor materials, and the two sub-silicon substrates are connected by an insulating isolation layer 13, so that each sub-silicon substrate corresponds to one side of the overall silicon substrate 1, and two sides of the overall silicon substrate 1 are insulated from each other.

The isolation layer 13 is made of an insulating material, which may be a silicon carbide material or the like.

The fin transistor 3 comprises a grid 32 and a fin active region; the active region includes a first contact region 331, a second contact region 332, a channel region 31; one side of the channel region 31, which is far away from the silicon 1 substrate, and two opposite sides of the channel region 31 along a first direction parallel to the surface of the silicon substrate 1 are provided with gates 32; the first contact region 331 and the second contact region 332 are respectively located at two opposite sides of the channel region 31 along the second direction; the second direction is parallel to the surface of the silicon substrate 1 and intersects (e.g., is perpendicular to) the first direction.

Referring to fig. 2, the fin-type active region may include a channel region 31 functioning as a switch, and a gate 32 is disposed on both sides of the channel region 31 along a first direction and on a side away from the silicon substrate 1; the two sides of the channel region 31 along the first direction are respectively a first contact region 331 and a second contact region 332, and the first contact region 331 and the second contact region 332 are respectively used for contacting with a first electrode (one of a source and a drain) and a second electrode (the other of the source and the drain) of the fin transistor 3.

Wherein the active region is entirely composed of a semiconductor material (such as a polysilicon material), and different positions therein are doped differently to form different regions; the first electrode, the second electrode, the gate electrode 32, and the like of the fin transistor 3 may be made of a conductive material such as a metal, or may be made of a conductive semiconductor material.

The active region may also include other structures. For example, between the channel region 31 and the contact regions (the first contact region 331 and the second contact region 332), lightly doped regions (LDD) with a low doping concentration may be further disposed to avoid hot carrier degradation.

In some embodiments, the fin transistor 3 has corresponding connection bumps 21; the connection bump 21 forms an integral structure with the silicon substrate 1, and the active regions (first contact region 331, second contact region 332, channel region 31) form an integral structure with the connection bump 21.

Referring to fig. 1 and 2, as a manner of the embodiment of the present disclosure, the silicon substrate 1 may be connected to an integrated bump structure (connection bump 21), and the connection bump 21 is integrated with the active region, that is, a silicon substrate 1, a connection bump 21, and an active region may be formed simultaneously by processing a silicon-based semiconductor material layer (e.g., silicon substrate 19) and removing a portion of the silicon-based semiconductor material layer.

For example, referring to fig. 1 to 4, the connection bumps 21 are located on the surface of the silicon substrate 1, and the active regions of the finfets 3 may be located on the connection bumps 21 (i.e., the connection bumps 21 are located away from the side of the silicon substrate 1), and the filling layer 22 is further located on the surface of the silicon substrate 1 where there are no connection bumps 21, so that the filling layer 22 "fills" the locations where there are no connection bumps 21 to the upper surfaces of the connection bumps 21. Thus, the surface of each side of the silicon substrate 1 is mostly covered with the filling layer 22, the connection bumps 21 are "buried" in the filling layer 22, and the active regions of the finfets 3 are located above the connection bumps 21.

In some embodiments, the channel region 31 includes a plurality of sub-channel regions 311 spaced apart in a direction away from the silicon substrate 1, and a gate electrode 32 is disposed in a space between adjacent sub-channel regions 311;

the first contact region 331 includes a plurality of first sub-contact regions 3311 corresponding to the sub-channel regions 311 one to one, and the second contact region 332 includes a plurality of second sub-contact regions 3321 corresponding to the sub-channel regions 311 one to one;

two opposite sides of each sub-channel region 311 in the second direction are connected with the first and second sub-contact regions 3311 and 3321, respectively.

As another mode of the embodiment of the present disclosure, referring to fig. 3 and 4, the channel region 31 may also include a plurality of spaced portions (sub-channel regions 311), so that the gate electrode 32 also enters the space between the sub-channel regions 311, and may also enter the space between the entire channel region 31 and the connection protrusion 21, so that the gate electrode 32 surrounds each sub-channel region 311 from "four directions", which may further increase the sensing area. Of course, there should be a gate insulating layer 321 between the gate electrode 32 and each adjacent sub-channel region 311 at this time.

Accordingly, referring to fig. 4, in order to prevent the first contact region 331 and the second contact region 332 from contacting the gate 32, each of the first contact region 331 and the second contact region 332 is also divided into a plurality of sub-contact regions (a first sub-contact region 3311 and a second sub-contact region 3321), such that two sides of each sub-channel region 311 along the second direction are respectively contacted with the first sub-contact region 3311 and the second sub-contact region 3321.

It should be understood that the material between the plurality of first sub-contact regions 3311, and between the plurality of second sub-contact regions 3321, with reference to fig. 4, should be insulating.

In some embodiments, the first and second sub-contact regions 3311, 332 are both nanowires, or the first and second sub-contact regions 3311, 332 are both nanosheets.

As a way of the embodiments of the present disclosure, the first sub-contact region 3311 and the second contact region 332 may be in the form of nano-wires (nano-wires) having a small width. Alternatively, as another mode of the disclosed embodiment, the first sub-contact zone 3311 and the second contact zone 332 may also be in the form of nano-sheets (nano-sheets) having a certain width.

Here, "width" refers to the dimension of a stripe structure having a certain length in the direction parallel to the surface of the silicon substrate 1 and perpendicular to the length direction thereof.

In some embodiments, the first side of the silicon substrate 1 is provided with at least one insulating layer 99 which is farther away from the silicon substrate 1 than the fin-type transistor 3, one side of each insulating layer 99, which is far away from the silicon substrate 1, is provided with a connecting wire 91, and the fin-type transistor 3 on the first side of the silicon substrate 1 is electrically connected with the bonding pad through the connecting wire 91 on the same side;

the second side of the silicon substrate 1 is provided with at least one insulating layer 99 which is farther away from the silicon substrate 1 than the fin-type transistor 3, one side of each insulating layer 99, which is far away from the silicon substrate 1, is provided with a connecting wire 91, and the fin-type transistor 3 on the second side of the silicon substrate 1 is electrically connected with the connecting wire 91 on the first side of the silicon substrate 1 through the connecting wire 91 and the connecting structure on the same side.

Referring to fig. 3, as a manner of the embodiment of the present disclosure, one or more insulating layers 99 (e.g., layers of materials such as silicon nitride) are further disposed above the fin transistors 3 on each side of the silicon substrate 1, and each insulating layer 99 is provided with a connection line 91 for electrically connecting different devices.

Thus, the finfets 3 may be electrically connected to the connection lines 91 through the vias in the same-side insulating layers 99, i.e., the connection lines 91 may electrically connect the finfets 3 on the same side to each other. At the same time, the fin transistor 3 on the first side of the silicon substrate 1 is also connected to the pad 92 by a connection wire 91, for example, the pad 92 may be located on the outermost insulating layer 99 on the first side. The connecting lines 91 on the two sides of the silicon substrate 1 are connected to each other through the connecting structure 4, so as to electrically connect the finfets 3 on the two sides, and electrically connect the finfets 3 on the second side to the pads 92.

In a second aspect, referring to fig. 1 to 16, embodiments of the present disclosure provide a method for manufacturing an integrated device structure, which is used for manufacturing any one of the integrated device structures of the embodiments of the present disclosure.

Referring to fig. 5, a method for manufacturing an integrated device structure according to an embodiment of the present disclosure includes:

s201, providing a silicon substrate 19.

S202, forming a fin transistor 3 and a pad 92 on a first side of the silicon substrate 19, forming the fin transistor 3 on a second side of the silicon substrate 19, forming a connection hole in the silicon substrate 19, and forming a connection structure 4 in the connection hole.

When the integrated device structure of the embodiment of the present disclosure is prepared, a silicon substrate 19 made of a silicon-based semiconductor material is provided, then corresponding fin transistors 3 are formed on two sides (a first side and a second side) of the silicon substrate 19 (pads 92 are also formed on the first side), and a connection hole and a connection structure 4 are formed in the silicon substrate 19, so that the silicon substrate 19 is converted into a silicon substrate 1, and the integrated device structure is obtained.

It should be understood that if the above structures of the connection bump 21, the filling layer 22, the insulating layer 99, the connection line 91, etc. are also included in the integrated device structure, the corresponding structures are also formed on the corresponding sides of the silicon substrate 19.

In the embodiment of the present disclosure, the entire layer structure on the silicon substrate 19 (silicon substrate 1) may be formed by a deposition process, and the structure constituting a certain pattern may be formed by a patterning process.

The Deposition process may be a sputtering process, an evaporation process, a Chemical Vapor Deposition (CVD) process, an Atomic Layer Deposition (ALD) process, etc., and is used to form a complete Layer of a certain material on the substrate.

The "patterning process" may include various forms such as a photolithography process, an inkjet printing process, an imprinting process, a partial modification process, etc., among others.

For example, the photolithography process may include the steps of depositing a material layer, coating a photoresist, exposing, developing (removing a portion of the photoresist), etching (removing the material layer without the photoresist, forming the desired structure from the remaining material layer), and stripping the photoresist.

For another example, an inkjet printing process or an imprinting process is a process of directly forming a certain material at a designated position, thereby directly obtaining a desired structure.

For another example, the local modification process is to perform modification treatment on a local part of the material layer, so as to change the property of the material layer at a corresponding position, so that the material layer with changed property forms a desired structure. Illustratively, the semiconductor material layer may be partially doped (made conductive) by plasma implantation to convert the semiconductor material layer at the corresponding position into a conductive structure such as the gate electrode 32, or partially oxidized by plasma implantation to convert the semiconductor material layer into an insulating structure such as the gate insulating layer 321.

For example, for the fin transistor 3 shown in fig. 1, the manufacturing process may include:

(1) A mask is formed on the silicon substrate 19 at locations corresponding to the active regions.

If the width of the active region is small and it is difficult to directly form a mask, an auxiliary layer (such as a polysilicon material) may be formed at a position between the active regions, and then a silicon oxide layer is deposited on the auxiliary layer, and the active region corresponds to the "side" of the auxiliary layer, and then the auxiliary layer and the silicon oxide layer directly above the auxiliary layer are removed, and the "side" silicon oxide layer is used as a mask.

(2) The silicon substrate 19 is etched to remove part of the semiconductor material at the non-mask protected position, and a protruding structure is formed at the silicon substrate 19 protected by the mask.

(3) And depositing to form a silicon oxide layer filled to a half position of the protrusion structure, so that the upper half part of the protrusion structure is exposed and the lower half part of the protrusion structure is buried by the silicon oxide layer, the upper half part of the protrusion structure corresponds to the active region, and the lower half part of the protrusion structure corresponds to the connection protrusion 21.

(4) A mask (e.g., silicon nitride) is formed to wrap the upper half of the bump structure, then the remaining silicon oxide layer is removed, whereby the lower half of the bump structure is exposed, ion implantation doping is performed to form the connecting bumps 21 on the lower half of the bump structure, and then the mask is removed.

(5) A filling layer 22 (e.g., silicon oxide) is formed to fill the upper edge of the connection bump 21, so that the upper half of the bump structure is exposed, and the upper half of the bump structure is doped by ion implantation to form the material required for the channel region 31.

(6) A buffer layer (e.g., silicon oxide) and a conductive layer (e.g., metal) are sequentially formed to cover the upper half of the bump structure, and the buffer layer and the conductive layer are removed at positions corresponding to the first contact region 331 and the second sub-contact region 332, so that the region of the upper half of the bump structure still covered by the buffer layer and the conductive layer becomes the channel region 31, the remaining buffer layer becomes the gate insulating layer 321, and the remaining conductive layer becomes the gate electrode 32.

(7) The exposed regions (regions other than the channel region 31) of the upper half of the protruding structure are epitaxially grown to generate an ohmic contact layer for contact with the electrode, so that the upper half of the protruding structure corresponds to regions on both sides of the channel region 31 to form the first contact region 331 and the second sub-contact region 332, respectively.

(8) And continuously forming the first electrode and the second electrode to obtain the fin type transistor 3.

Specifically, referring to fig. 3, when there are stacked structures of the active fin 311, the gate insulating layer 321, the gate electrode 32, and the like at the channel region 31 of the fin transistor 3, layers of different materials may be sequentially formed at the channel region 31 through a patterning process; alternatively, different modification treatments may be performed on different positions of the semiconductor material layer in the channel region 31; for example, a "frame structure" having spaced apart voids may be formed of a certain material, and then another material may be formed in the voids of the frame structure.

The processes for forming the various structures are various and will not be described in detail herein.

In some embodiments, referring to fig. 6, the silicon substrate 1 includes an isolation layer 13; providing the silicon substrate 19 (S201) includes:

s2011, a first sub-isolation layer 1931 is formed on the first sub-silicon substrate 191 side, and a second sub-isolation layer 1932 is formed on the second sub-silicon substrate 192 side.

S2012, the first sub-isolation layer 1931 is connected to the second sub-isolation layer 1932 to form an isolation layer 13, so as to obtain the silicon substrate 19.

Referring to fig. 7, as a manner of the embodiment of the present disclosure, when the silicon substrate 1 includes the above isolation layer 13, two sub-silicon substrates (the first sub-silicon substrate 191 and the second sub-silicon substrate 192) of silicon-based semiconductor material may be provided, sub-isolation layers (the first sub-isolation layer 1931 and the second sub-isolation layer 1932, for example, silicon carbide layers) may be formed on one sides of the two sub-silicon substrates, respectively, and then the sides of the two sub-isolation layers opposite to the sub-silicon substrates may be connected (e.g., bonded) to each other, thereby obtaining a silicon substrate 19 with the isolation layer 13 in between.

In some embodiments, the fin transistor 3 includes a gate 32, an active region of a fin; the active region includes a first contact region 331, a second contact region 332, a channel region 31; one side of the channel region 31, which is far away from the silicon 1 substrate, and two opposite sides of the channel region 31 along a first direction parallel to the surface of the silicon substrate 1 are provided with gates 32; the first contact region 331 and the second contact region 332 are respectively located on two opposite sides of the channel region 31 along the second direction; the second direction is parallel to the surface of the silicon substrate 1 and intersects (e.g., is perpendicular to) the first direction.

Referring to fig. 6, forming the fin transistor 3, the pad 92, on the first side of the silicon substrate 19, forming the fin transistor 3 on the second side of the silicon substrate 19, forming a connection hole in the silicon substrate 19, and forming the connection structure 4 in the connection hole (S202) includes:

s20201, a fin transistor substrate is formed on the first side of the silicon substrate 19.

The fin type transistor substrate comprises an active region.

S20202, a first planarizing layer 71 is formed on the first side of the silicon substrate 19, and a first supporting substrate 81 is provided on the first planarizing layer 71.

S20203, the silicon substrate 19 is turned over, and a fin-connected transistor base is formed on the second side of the silicon substrate 19.

S20204, forming a gate 32 of the fin transistor 3 on the second side of the silicon substrate 19, thereby obtaining the fin transistor 3.

S20205, a second planarizing layer 72 is formed on a second side of the silicon substrate 19, and a second supporting substrate 82 is provided on the second planarizing layer 72.

S20206, the silicon substrate 19 is turned over, and the first support substrate 81 is removed.

S20207, forming a gate 32 of the fin transistor 3 on the first side of the silicon substrate 19, thereby obtaining the fin transistor 3.

When the silicon substrate 19 is processed, it is usually necessary to support one side of the silicon substrate 19. Thus, as an aspect of the embodiment of the present disclosure, referring to fig. 8 to 12, a fin transistor substrate, i.e., a base structure of an active region of the fin transistor 3, may be formed on the first side of the silicon substrate 19, but at this time, the gate 32 and the like are not formed, and thus, a complete fin transistor is not obtained. Of course, the connection bump 21, the filling layer 22, and the like may be formed at this time, and the first electrode, the second electrode, and the like of the fin transistor 3 may also be formed.

Thereafter, a planarization layer (PLN, specifically, the first planarization layer 71) is formed, which is a layer covering various other structures on the side where the planarization layer is located and "filling in" the step difference of the corresponding structure, so that the surface of the planarization layer on the side away from the silicon substrate 19 is flat, which is beneficial for the subsequent processes.

For example, the planarization layer may be an oxide layer of sufficient thickness deposited, and the surface of the oxide layer is subjected to a Chemical Mechanical (CMP) planarization process.

The planarization layer may also serve as other structures in the integrated device structure, such as the insulating layer 99.

Thereafter, the first support substrate 81 is disposed (e.g., bonded by the adhesive layer 89) on the first planarizing layer 71; therefore, when other structures are formed on the second side of the silicon substrate 19 later, the first support substrate 81 can be used as a support to avoid damaging other structures which are formed on the first side of the silicon substrate 19.

For example, the silicon substrate 19 may be turned over so that a bulk of the finfets is formed on the second side of the silicon substrate 19, supported by the first support substrate 81; and then, continuing to form other structures such as a gate 32 of the fin transistor 3, and obtaining the fin transistor 3 on the second side of the silicon substrate 19.

Thereafter, a second planarizing layer 72 (e.g., deposited) and a second support substrate 82 (e.g., bonded by a bonding layer 89) can be provided on a second side of the silicon substrate 19; and the silicon substrate 19 is turned over again, so that the structure of the silicon substrate 19 is exposed by removing the first supporting substrate 81 with the second supporting substrate 82 as a support, and the gate 32 and the like of the fin transistor 3 are continuously formed, and the fin transistor 3 is also obtained on the first side of the silicon substrate 19.

In some embodiments, referring to fig. 6, after forming the gate 32 of the fin transistor 3 on the first side of the silicon substrate 19 with the connection line 91 and the insulating layer 99 (S2027), further comprising:

s20208, an insulating layer 99, a connection line 91, and a pad 92 are formed on the first side of the silicon substrate 19, and then the third supporting substrate 83 is provided.

S20209, the silicon substrate 19 is turned over, and the second supporting substrate 82 is removed.

S20210, forming an insulating layer 99 and a connection line 91 on the second side of the silicon substrate 19, and forming a connection hole in the silicon substrate 19 and a connection structure 4 in the connection hole.

S20211, the third supporting substrate 83 is removed.

As a mode of the embodiment of the present disclosure, referring to fig. 13 to 16, after the fin transistor 3 is formed on the first side of the silicon substrate 19, the connection line 91, the insulating layer 99, the pad 92, and other structures are formed on the first side to electrically connect different devices on the first side; then, forming a third supporting substrate 83 on the first side of the silicon substrate 19 (for example, bonding through a bonding layer 89), turning over the silicon substrate 19 to support the third supporting substrate 83, removing the second supporting substrate 82 (of course, removing the corresponding bonding layer 89), and continuing to form a connecting line 91, an insulating layer 99, and the like on the second side of the silicon substrate 19 to electrically connect different devices on the second side; thereafter, connection holes are formed through the silicon substrate 19 (and of course through the desired insulating layer 99), in which connection structures 92 are formed (e.g. electroplated) to enable electrical connection of the two-sided devices, and finally the third support substrate 83 is removed (while of course also the respective adhesive layer 89).

Example 1:

referring to fig. 7 to 16, a method for manufacturing an integrated device structure according to an embodiment of the present disclosure may specifically include the following steps:

a101, a substrate (silicon substrate 19) providing a silicon-based semiconductor.

Referring to fig. 7, two single crystal or polycrystalline silicon wafers (a first sub-silicon substrate 191 and a second sub-silicon substrate 192) are used, silicon carbide layers (a first sub-isolation layer 1931 and a second sub-isolation layer 1932) are formed on one side of each of the two silicon wafers, and then the exposed surfaces of the two silicon carbide layers are bonded to form one silicon carbide layer (an isolation layer 13), so that a substrate with two insulated sides is obtained.

Alternatively, doping (e.g., ion implantation) may be performed on both sides of a silicon wafer, so that doped semiconductors (e.g., P-type semiconductors) are formed on both sides of the silicon wafer, and the middle portion of the silicon wafer is made of non-conductive intrinsic silicon, thereby obtaining a substrate with two insulated sides.

It will be appreciated that it is also possible to use the silicon wafer product directly as a substrate.

A102, referring to fig. 8, a connection bump 21, a filling layer 22, and a fin transistor base are formed on the front surface (first side) of the substrate.

The fin transistor substrate includes an active region source (such as the channel region 31, the first contact region 331, the second contact region 332, and the like, but does not include a gate, a gate insulating layer, and the like) of the fin transistor substrate.

Wherein, if the connection holes and the connection structures 4 are to be formed, the substrate may be thinned from the front side to reduce the thickness thereof before the connection projections 21 are formed.

A103, referring to fig. 9, a layer of oxide (e.g., silicon oxide) is deposited on the front surface of the substrate, CMP planarization is performed to obtain the first planarization layer 71 (insulating layer 99), and then the first supporting substrate 81 is disposed on the front surface of the substrate, for example, the first supporting substrate 81 is bonded to the first planarization layer 71 through the bonding layer 89.

A104, referring to fig. 10, the substrate is turned over, so that the connection protrusion 21, the filling layer 22, and the fin-type transistor base body are formed on the back surface (second side) of the substrate with the first support substrate 81 as a support; and then, other structures of the fin transistor, such as the gate electrode 32, the gate insulating layer 321 and the like, are formed continuously, so that the fin transistor 3 is obtained on the back surface of the substrate.

Wherein, if the connection hole and the connection structure 4 are to be formed, the substrate may be thinned from the back side to reduce the thickness thereof before the connection projection 21 is formed.

A105, referring to fig. 11, a layer of oxide (e.g., silicon oxide) is deposited on the back surface of the substrate, CMP planarization is performed to obtain the second planarization layer 72 (insulating layer 99), and then the second supporting substrate 82 is disposed on the back surface of the substrate, such as by bonding the second supporting substrate 82 to the second planarization layer 72 through the bonding layer 89.

And a106, referring to fig. 12, turning over the substrate, so as to use the second supporting substrate 82 as a support, removing the first supporting substrate 81 (certainly, simultaneously removing the corresponding adhesive layer 89), removing the first planarization layer 71 on the front surface of the substrate, and continuing to form other structures of the fin transistor, such as the gate electrode 32, the gate insulating layer 321, and the like, on the front surface of the substrate, so as to obtain the fin transistor 3 on the front surface of the substrate.

A107, referring to fig. 13, one or more layers of metal wirings (such as the connection lines 91, the insulating layer 99, the pads 92, etc.) are formed on the front surface of the substrate, the interconnection of the devices on the front surface is completed, and a third supporting substrate 83 is disposed on the front surface of the substrate, for example, the third supporting substrate 83 is bonded to the metal wirings on the outermost surface through an adhesive layer 89.

A108, referring to fig. 14, the substrate is turned over, so that the third supporting substrate 83 is used as a support, the second supporting substrate 82 is removed (and the corresponding adhesive layer 89 is removed, of course), one or more layers of metal wirings (such as the connecting wires 91 and the insulating layer 99, etc.) are formed on the back side of the substrate, the interconnection of the devices on the back side is completed, connecting holes penetrating through the substrate and the corresponding insulating layer 99 are formed, and the conductive connecting structures 4 are formed in the connecting holes, so as to obtain the structure of fig. 15.

In addition to penetrating through the substrate, the connection hole should also penetrate through other insulating layers 99 between the connection lines 91 that need to be connected on both sides.

Wherein the connection hole and the connection structure 4 should be formed before the connection line 91 connected to the first side, that is, after the connection structure 4 is formed, the connection line 91 connected to the first side is formed, and the connection line 91 covers the connection structure 4, so that after the connection structure 4 is formed, a step of forming one or more insulating layers 99 and the connection line 91 on the second side may be further included, and of course, these subsequently formed connection lines are used for interconnection between devices on the second side, and are not directly connected to the first side.

A109, the third support substrate 83 is removed (and of course the corresponding adhesive layer 89 is also removed), resulting in the integrated device structure of fig. 16.

The present disclosure has disclosed example embodiments and, although specific terms are employed, they are used and should be interpreted in a generic and descriptive sense only and not for purposes of limitation. In some instances, features, characteristics and/or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics and/or elements described in connection with other embodiments, unless expressly stated otherwise, as would be apparent to one skilled in the art. It will, therefore, be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the disclosure as set forth in the appended claims.

Claims (10)

1. An integrated device structure, comprising:

a silicon substrate having opposing first and second sides;

a fin transistor located on a first side of the silicon substrate;

a fin transistor located on a second side of the silicon substrate;

the bonding pad is positioned on the first side of the silicon substrate and electrically connected with the fin type transistor on the first side of the silicon substrate;

the silicon substrate is provided with through connecting holes, connecting structures are arranged in the connecting holes, and the fin type transistor on the first side of the silicon substrate is electrically connected with the fin type transistor on the second side of the silicon substrate through the connecting structures.

2. The integrated device structure of claim 1,

the silicon substrate comprises a first sub silicon substrate, a second sub silicon substrate and an insulating isolation layer, wherein the first sub silicon substrate and the second sub silicon substrate are stacked, and the insulating isolation layer is used for connecting the first sub silicon substrate and the second sub silicon substrate.

3. The integrated device structure of claim 1,

the first side of the silicon substrate is provided with at least one insulating layer which is farther away from the silicon substrate than the fin-type transistors, one side of each insulating layer, which is far away from the silicon substrate, is provided with a connecting wire, and the fin-type transistors on the first side of the silicon substrate are electrically connected with the bonding pads through the connecting wires on the same side;

the second side of the silicon substrate is provided with at least one insulating layer which is farther away from the silicon substrate than the fin-type transistor, one side of each insulating layer, which is far away from the silicon substrate, is provided with a connecting wire, and the fin-type transistor on the second side of the silicon substrate is electrically connected with the connecting wire on the first side of the silicon substrate through the connecting wires on the same side and the connecting structure.

4. The integrated device structure of claim 1,

the fin type transistor comprises a grid electrode and a fin type active region;

the active region comprises a first contact region, a second contact region and a channel region; one side of the channel region, which is far away from the silicon substrate, and two opposite sides of the channel region along a first direction parallel to the surface of the silicon substrate are provided with grids; the first contact area and the second contact area are respectively positioned on two opposite sides of the channel area along the second direction; the second direction is parallel to a surface of the silicon substrate and intersects the first direction.

5. The integrated device structure of claim 4,

the fin type transistor is provided with a corresponding connecting bulge;

the connection protrusion and the silicon substrate form an integrated structure, and the active region and the connection protrusion form an integrated structure.

6. The integrated device structure of claim 4,

the channel region comprises a plurality of sub-channel regions arranged at intervals along a direction deviating from the silicon substrate, and a grid electrode is arranged in an interval between every two adjacent sub-channel regions;

the first contact area comprises a plurality of first sub-contact areas corresponding to the sub-channel areas one by one, and the second contact area comprises a plurality of second sub-contact areas corresponding to the sub-channel areas one by one;

two opposite sides of each sub-channel region along the second direction are respectively connected with the first sub-contact region and the second sub-contact region.

7. A method of manufacturing an integrated device structure, the integrated device structure being as claimed in any one of claims 1 to 6; the preparation method comprises the following steps:

providing a silicon substrate;

forming a fin type transistor and a bonding pad on a first side of the silicon substrate, forming a fin type transistor on a second side of the silicon substrate, forming a connecting hole in the silicon substrate, and forming a connecting structure in the connecting hole.

8. The manufacturing method according to claim 7, wherein the integrated device structure is the integrated device structure according to claim 2; the providing a silicon substrate includes:

forming a first sub-isolation layer on one side of the first sub-silicon substrate, and forming a second sub-isolation layer on one side of the second sub-silicon substrate;

and connecting the first sub-isolation layer and the second sub-isolation layer to form an isolation layer, thereby obtaining the silicon substrate.

9. The method of manufacturing of claim 7, wherein the fin transistor comprises a gate, an active region of a fin; the active region comprises a first contact region, a second contact region and a channel region; one side of the channel region, which is far away from the silicon substrate, and two opposite sides of the channel region along a first direction parallel to the surface of the silicon substrate are provided with grids; the first contact area and the second contact area are respectively positioned on two opposite sides of the channel area along the second direction; the second direction is parallel to the surface of the silicon substrate and intersects with the first direction;

forming a fin transistor and a pad on a first side of the silicon substrate, forming a fin-connected transistor on a second side of the silicon substrate, forming a connection hole in the silicon substrate, and forming a connection structure in the connection hole includes:

forming a fin type transistor substrate on the first side of the silicon substrate; the fin transistor substrate comprises the active region;

forming a first planarization layer on a first side of the silicon substrate, and disposing a first support substrate on the first planarization layer;

turning over the silicon substrate, and forming a fin type transistor matrix on the second side of the silicon substrate;

forming a grid electrode of the fin-type transistor on the second side of the silicon substrate to obtain the fin-type transistor;

forming a second planarization layer on a second side of the silicon substrate, a second support substrate being disposed on the second planarization layer;

turning over the silicon substrate and removing the first support substrate;

and forming a grid electrode of the fin-type transistor on the first side of the silicon substrate to obtain the fin-type transistor.

10. The manufacturing method according to claim 9, wherein the integrated device structure is the integrated device structure according to claim 3; after the forming the gate of the fin transistor on the first side of the silicon substrate, the method further comprises:

forming the insulating layer, the connecting wire and the bonding pad on the first side of the silicon substrate, and then arranging a third supporting substrate;

turning over the silicon substrate and removing the second supporting substrate;

forming the insulating layer and the connecting wire on the second side of the silicon substrate, forming a connecting hole in the silicon substrate, and forming a connecting structure in the connecting hole;

and removing the third supporting substrate.

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