CN115188711A - Contact hole manufacturing method and semiconductor device manufacturing method - Google Patents
Contact hole manufacturing method and semiconductor device manufacturing method Download PDFInfo
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- CN115188711A CN115188711A CN202210836621.8A CN202210836621A CN115188711A CN 115188711 A CN115188711 A CN 115188711A CN 202210836621 A CN202210836621 A CN 202210836621A CN 115188711 A CN115188711 A CN 115188711A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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Abstract
The invention provides a contact hole manufacturing method and a semiconductor device manufacturing method, wherein an insulating medium layer with a certain thickness is covered on the top surface of a first conductive structure, and a sacrificial layer is filled in the space between the first conductive structures, so that after an opening is formed on an etching interlayer medium layer and is used as an upper opening of a contact hole, the lower opening of the contact hole is formed by removing the sacrificial layer in alignment, the requirement on the alignment precision of the contact hole is reduced, and the process difficulty of contact hole manufacturing is further reduced.
Description
Technical Field
The invention relates to the technical field of semiconductor device manufacturing, in particular to a contact hole manufacturing method and a semiconductor device manufacturing method.
Background
In the fabrication of semiconductor integrated circuits, various electronic devices required by the circuits are usually fabricated on a small-area silicon wafer, and appropriate interconnection lines are also fabricated to electrically connect the electronic devices to achieve desired functions, which requires a large number of contact holes to be fabricated on the silicon wafer, and the performance of the contact holes has an important influence on the overall performance of the circuits.
With the development of very large scale integrated circuits, the number of electronic devices in the circuit is increasing, and the size of the devices (cell pitch) is shrinking. In the meantime, the size of the device is continuously reduced, on one hand, higher requirements are put forward on the Critical Dimension (CD) of the contact hole and on the bias precision, and on the other hand, due to the improvement of the density of the device, the distance between the contact hole and other conductive structures is reduced, and when the lithography bias is too large, the device is likely to be short-circuited. In addition, the aspect ratio of the contact hole is increased, which is not favorable for filling the contact hole.
Disclosure of Invention
The invention aims to provide a contact hole manufacturing method and a semiconductor device manufacturing method, which can reduce the difficulty of the contact hole manufacturing process and realize the self-alignment of the contact hole.
In order to achieve the above object, the present invention provides a method for manufacturing a contact hole, comprising:
providing a substrate, wherein at least two first conductive structures which are spaced from each other are formed on the substrate, an insulating medium layer covers the top surfaces of the first conductive structures, and second conductive structures are formed in the substrate at the spacing between the adjacent first conductive structures;
forming a side wall on the inner side wall of the interval, wherein the side wall covers the first conductive structure and the side wall of the insulating medium layer;
filling a sacrificial layer in the gap, and forming an interlayer dielectric layer to cover the sacrificial layer, the insulating dielectric layer and the side wall;
etching the interlayer dielectric layer at the interval, and stopping etching on the top surface of the sacrificial layer to form an opening exposing the top surface of the sacrificial layer;
removing the sacrificial layer in the bottom region of the opening to form a contact hole exposing a top surface of the second conductive structure at the space.
Optionally, the first conductive structure comprises a gate; the second conductive structure includes an ion-doped region formed in the substrate at the space, and the contact hole exposes a portion of a top surface of the ion-doped region.
Optionally, the ion doped region includes a body region formed in the substrate at the space and a source region formed in a surface layer of the body region, and the contact hole exposes a part of a top surface of the source region and a top surface of the body region between adjacent source regions.
Optionally, the step of forming the first conductive structure and the second conductive structure includes:
a gate dielectric layer, a gate electrode layer and an insulating dielectric layer are sequentially covered on the substrate;
etching the insulating dielectric layer and the gate electrode layer to form a gate electrode with the top surface covered with the insulating dielectric layer;
carrying out body region ion implantation on the substrate at the interval to form a body region;
and forming a source region in the surface layer of the body region by corresponding photoetching and source region ion implantation.
Optionally, at least one of the first conductive structure and the second conductive structure is a polysilicon resistor, a plate of a capacitor, a conductive plug, or a metal interconnection line in a multilayer metal interconnection structure.
Optionally, the top surface of the sacrificial layer is higher than the top surface of the first conductive structure and lower than the top surface of the insulating medium layer; and when the interlayer dielectric layer at the interval is etched and stops on the top surface of the sacrificial layer, removing part of the insulating dielectric layer and the side wall to enable the line width of the opening to be larger than the line width of the top surface of the sacrificial layer, and enabling the side wall of the insulating dielectric layer to form a step which does not expose the top surface of the first conductive structure in the opening.
Optionally, the sacrificial layer in the bottom region of the opening is removed by a wet etching process, and the contact hole has a structure with a wide top and a narrow bottom.
Optionally, after removing the sacrificial layer in the bottom region of the opening to form a contact hole, the method further includes: and etching part of the thickness substrate below the bottom of the contact hole so that the bottom of the contact hole is deep into the corresponding thickness of the ion doping area.
Based on the same inventive concept, the present invention also provides a semiconductor device manufacturing method, which includes:
by adopting the contact hole manufacturing method, the corresponding contact hole is formed;
and filling a conductive material into the contact hole.
Optionally, the semiconductor device to be manufactured is an IGBT or an MOS transistor, the first conductive structure includes a gate, the second conductive structure includes a source region, and the step of filling the contact hole with a conductive material includes: depositing a metal layer, wherein the metal fills the contact hole and deposits corresponding thickness above the insulating medium layer; and photoetching and etching the metal layer to form a source electrode metal wire for electrically leading out the source region outwards.
Compared with the prior art, the technical scheme of the invention at least has the following beneficial effects:
1. the method is compatible with the prior art, the contact holes can be formed in a self-aligned mode, and the requirement on the alignment precision of the contact holes is low;
2. the distance between the contact hole and the first conductive structure can be controlled through the side wall and the insulating medium layer according to requirements;
3. through the sacrificial layer and the insulating medium layer on the top surface of the first conductive structure, the first conductive structure is protected during hole opening, the shape of an inverted trapezoidal contact hole with a wide upper part and a narrow lower part is favorably formed, the depth-to-width ratio of the contact hole is reduced, and material filling in the contact hole is favorably realized.
Drawings
FIG. 1 is a schematic cross-sectional view of a device manufactured by a conventional contact hole process.
FIG. 2 is a schematic flow chart illustrating a method for fabricating a contact hole according to an embodiment of the invention.
FIG. 3 is a schematic cross-sectional view of a contact hole manufacturing method and a semiconductor device manufacturing method according to an embodiment of the present invention.
FIG. 4 is a schematic cross-sectional view of a contact hole manufacturing method and a semiconductor device manufacturing method according to another embodiment of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present invention. It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout. It will be understood that when a layer is referred to as being formed on another layer, it can be formed directly on the other layer or intervening layers may also be present. Where the terms "upper", "lower", "top", "bottom", "inner", "middle", "longitudinal", "lateral", and the like indicate orientations or positional relationships based on those shown in the drawings, it is merely for convenience in describing the present invention and simplifying the description, and it is not intended to indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present invention, where "longitudinal" may be understood as a direction perpendicular to the surface of a substrate, and "lateral" may be understood as a direction parallel to the surface of a substrate. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items. The terms "identical", "equal" and "consistent" include identical and identical meanings, and may also include meanings that are approximately the same or approximately equal under the allowed process tolerances. The terms "first," "second," and the like in the description are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other sequences than described or illustrated herein. Similarly, if the method described herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method. In order to make the description of the drawings clearer, the present specification does not mark every drawing with a reference numeral that is the same for every drawing, although the same elements may be easily recognized in all drawings.
As described in the background, the conventional contact hole manufacturing process has drawbacks.
Taking the manufacturing of planar devices such as IGBTs and MOS transistors as an example, in the prior art, referring to fig. 1, after completing the etching of the polysilicon gate (i.e., the first conductive structure) 101, the manufacturing of the gate sidewall 102, and the ion implantation of the source region (i.e., the second conductive structure) 103, the manufacturing of a source contact hole (contact via) 105 is usually completed through deposition, photolithography, and etching of the interlayer dielectric layer 104, and further, the contact hole 105 is filled with a metal 106 to form a conductive plug or a metal wire (or called an interconnection line) for electrically leading out the source region 103 to the outside.
With the continuous reduction of the size of the device and the continuous increase of the density of the device, on one hand, higher requirements are put on the photoetching Critical Dimension (CD) and the offset precision of the contact hole, on the other hand, because the density of the device is improved, the distance between the contact hole and the polysilicon gate is reduced, the photoetching offset can generate larger influence on the threshold voltage of the device, so that the devices such as an IGBT (insulated gate bipolar transistor) and an MOS (metal oxide semiconductor) transistor are more prone to generating current concentration in the using process to cause burning-out, the actual use of the devices is seriously influenced, and when the photoetching offset is overlarge, the grid and the source/drain of the MOS transistor or the grid and the emitter of the IGBT can even be directly caused to be short-circuited.
Of course, similar problems as described above also exist in the fabrication of contact holes in multilevel metal interconnect structures or other semiconductor devices.
Based on the above, the invention provides a contact hole manufacturing method and a semiconductor device manufacturing method, wherein an insulating medium layer with a certain thickness is covered on the top surface of a first conductive structure, so that when the contact hole is formed by etching the interlayer medium layer, a step can be formed, the size of the upper opening of the contact hole is increased, the lower opening of the self-aligned contact hole is formed by utilizing a sacrificial layer, the self-alignment of the contact hole can be realized, and the requirements on the CD and the alignment precision of the contact hole are reduced.
The technical solution proposed by the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is provided for the purpose of facilitating and clearly illustrating embodiments of the present invention.
Referring to fig. 2, an embodiment of the invention provides a method for forming a contact hole, including:
s1, providing a substrate, wherein at least two first conductive structures which are spaced from each other are formed on the surface of the substrate, an insulating medium layer covers the top surfaces of the first conductive structures, and second conductive structures are formed in the substrate at the spacing between the adjacent first conductive structures;
s2, forming a side wall on the inner side wall of the interval, wherein the side wall covers the first conductive structure and the side wall of the insulating medium layer;
s3, filling a sacrificial layer in the interval, and forming an interlayer dielectric layer to cover the sacrificial layer, the insulating dielectric layer and the side wall;
s4, etching the interlayer dielectric layer at the interval, and stopping etching on the top surface of the sacrificial layer to form an opening exposing the top surface of the sacrificial layer;
and S5, removing the sacrificial layer in the bottom area of the opening to form a contact hole exposing the top surface of the second conductive structure at the interval.
Referring to fig. 3, in this embodiment, the substrate 200 provided in step S1 is any suitable semiconductor substrate for manufacturing devices such as an IGBT or an MOS transistor, which may be a bare silicon wafer, or a silicon wafer processed by a certain process, for example, a fin or a Shallow Trench Isolation (STI) has been formed in the substrate 200.
As an example, the implementation process of step S1 specifically includes:
first, referring to (a) in fig. 3, a gate dielectric layer 201, a gate electrode layer, and an insulating dielectric layer 203 are sequentially covered on the substrate 200, wherein a material of the gate dielectric layer 201 may include silicon oxide or a high-k (e.g., a dielectric constant k is greater than 7) dielectric, which may be formed by a thermal oxidation process, a chemical vapor deposition process, or an atomic layer vapor deposition process, and the like, a material of the gate electrode layer may include polysilicon and/or metal, which may be formed by a chemical vapor deposition process, and the like, and a material of the insulating dielectric layer 203 may include silicon nitride and/or silicon oxide, and the like. The deposition thickness of the insulating dielectric layer 203 needs to be selected reasonably, so that the height of the subsequent sacrificial layer is increased, and meanwhile, a step required by the etching of the interlayer dielectric layer is formed on the side wall of the insulating dielectric layer after the opening is formed, and the step is prevented from exposing the top surface of the gate.
Next, with continuing reference to fig. 3 (a), the insulating dielectric layer 203 and the gate layer are etched, and the etching is stopped at the gate dielectric layer 201 to form a plurality of gates 202 spaced apart from each other and covered with the insulating dielectric layer 203 on top surfaces, where the gates 202 are formed with at least two first conductive structures spaced apart from each other on the surface of the substrate 200.
Then, referring to fig. 3 (B), a body region ion implantation is performed into the substrate 200 at the space 204 between the adjacent gates 202, and an annealing process is performed to form a body region 200p. The implanted ions may be at least one p-type ion such as boron, indium, gallium, etc. Body region 200p may extend laterally under a portion of the bottom of gate 202 to overlap gate 202.
Then, source regions 200s corresponding to the gates 202 one-to-one are formed in the surface layer of the body region 200p by photolithography and source region ion implantation and annealing. In the present embodiment, two mutually separated source regions 200s corresponding to the gates 202 on both sides are formed in the space 204, and each source region 200s extends below a part of the bottom of the corresponding gate 202 to overlap the corresponding gate 202 in the vertical direction. Source region 200s serves as a second conductive structure formed in substrate 200 at spaces 204 between adjacent gates 202, and body region 200p and source region 200s together constitute an ion-doped region formed in substrate 200 at spaces 204.
Referring to fig. 3 (C), in step S2, sidewall materials such as silicon oxide are deposited and etched to form a sidewall (spacer) 205 covering the inner sidewall of the spacer 204, where the sidewall 205 may be a single-layer film structure or a composite structure formed by stacking multiple layers of films, and the thickness of the sidewall 205 is adjusted according to the actual requirement of the bottom line width of the contact hole to be formed and the distance between the formed contact hole and the gate 202.
In step S3, referring to fig. 3 (D), a sacrificial layer 206 may be formed by vapor deposition or spin coating to cover the top surface of the insulating dielectric layer 203 and fill the spacers 204, so as to bury the insulating dielectric layer 203, the spacers 204 and the sidewalls 205. The material of the sacrificial layer 206 may be selected from any suitable material different from that of the insulating dielectric layer 203 and the sidewall spacers 205, for example, when the material of the insulating dielectric layer 203 and the material of the sidewall spacers 205 are both silicon oxide, the sacrificial layer 206 may be silicon nitride. Then, with continued reference to (D) of fig. 3, the sacrificial layer 206 is etched back until the top surface of the sacrificial layer 206 is lower than the top surface of the insulating dielectric layer 203 and higher than the top surface of the gate 202, thereby removing the sacrificial layer 206 on the top surface of the insulating dielectric layer 203, so that the remaining sacrificial layer 206 is only located in the space 204. Next, referring to (E) in fig. 3, an interlayer dielectric layer 207 is deposited, and optionally, the top surface of the deposited interlayer dielectric layer 207 may be further subjected to chemical mechanical polishing until the top surface of the interlayer dielectric layer 207 is flat, and the top portions of the insulating dielectric layer 203, the sidewall 205 and the sacrificial layer 206 are still buried in the polished interlayer dielectric layer 207.
Referring to fig. 3 (F), in step S4, the interlayer dielectric layer 207 is etched and etched by using a conventional contact hole process until the top surface of the sacrificial layer 206 is exposed, thereby forming an opening 208a. In this step, a portion of the edge of the insulating dielectric layer 203 at the space 204 and a top portion of the sidewall spacer 205 may be etched away together, so that a line width of the formed opening 208a may be greater than a line width of the space 204 (i.e., greater than a top line width of the sacrificial layer 206), so that the opening 208a may expose a portion of the surface of the insulating dielectric layer 203 and the top surface of the sidewall spacer 205, and the sidewall of the insulating dielectric layer 203 forms a step 207a in the opening 208a, which does not expose the top surface of the gate 202.
Optionally, the opening 208a has an inverted trapezoid structure with a wide top and a narrow bottom to facilitate the subsequent processes.
Referring to (G) of fig. 3, in step S5, the sacrificial layer 206 in the bottom region of the opening 208a may be removed by a wet etching process to form a contact hole 208, and the contact hole 208 is formed in a structure with a wide top and a narrow bottom.
Optionally, in step S5, the gate dielectric layer 201 under the bottom of the contact hole is further etched and opened along the contact hole 208, and etching is continued to remove a part of the thickness of the substrate 200 (i.e., a part of the thickness of the source region 200S and the thickness of the body region 200p between the source regions 200S), so that the bottom of the contact hole 208 extends into the body region 200p and the source region 200S with corresponding thicknesses, that is, the contact hole 208 exposes a part of the top surface of the source region 200S and simultaneously exposes the top surface of the body region 200p between the source regions 200S. And the spacing between the contact hole 208 and the gate 202 is controlled by the thickness of the sidewall spacer and the insulating dielectric layer.
In this embodiment, first, with the aid of pre-filling and subsequent removal of the sacrificial layer 206, on one hand, the process of forming a contact hole with a large aspect ratio by etching the interlayer dielectric layer is divided into etching the opening 208a in the interlayer dielectric layer 207 and removing the sacrificial layer 206, and the aspect ratio of the two processes is reduced, which is beneficial to improving the morphology of the finally formed contact hole; on the other hand, by removing the sacrificial layer 206 and under the limiting action of the side wall 205, the contact hole 208 can be formed in a self-aligned manner, so that the alignment precision requirement of the contact hole 208 is greatly reduced; in addition, on the basis that the line width of the sacrificial layer 206 meets the requirement of the line width at the bottom of the contact hole 208, the line width of the opening 208a in the interlayer dielectric layer 207 can be allowed to be larger, so that the contact hole 208 is in an inverted trapezoid shape with a wide upper part and a narrow lower part, the aspect ratio of the contact hole 208 can be further reduced to the greatest extent, and the subsequent material filling in the contact hole 208 is facilitated.
Referring to fig. 2 and fig. 3, the present embodiment further provides a method for manufacturing a semiconductor device, which includes:
firstly, by adopting the contact hole manufacturing method (namely, the steps S1 to S5), the corresponding contact hole 208 is formed, and the specific process can refer to the above description and is not repeated herein;
then, referring to (H) of fig. 3 with emphasis, the contact hole 208 is filled with a conductive material 209. For example, a metal silicide is formed on the bottom surface of the contact hole 208 to reduce the contact resistance, then a thin metal barrier material, a thin adhesion layer or a seed layer material is sequentially deposited, a thick metal layer material is deposited until the metal layer material can fill the contact hole 208 and can cover the top surface of the interlayer dielectric layer 207 by a required thickness, and further chemical mechanical polishing is performed, so as to form a conductive material 209 with a flat top surface, when the top surface of the conductive material 209 is chemically and mechanically polished to be flush with the top surface of the interlayer dielectric layer 207, the conductive material 209 serves as a conductive plug filled in the contact hole 208, and when the top surface of the conductive material 209 still has a certain cover thickness on the top surface of the interlayer dielectric layer 207 after chemical mechanical polishing, the conductive material 209 may be further subjected to photolithography and etching to form a required metal line, and the metal line is electrically connected with the source region 200s through the portion filled in the contact hole 208.
Optionally, the semiconductor device to be manufactured is an IGBT or MOS transistor, the first conductive structure includes a gate, the second conductive structure includes a source region, and the step of filling the contact hole with a conductive material includes: depositing a metal layer, wherein the metal fills the contact hole and deposits a corresponding thickness above the grid; and photoetching and etching the metal layer to form a source electrode metal wire for electrically leading out the source region outwards.
In addition, the manufacturing method of the semiconductor device of the embodiment adopts the contact hole manufacturing process of the invention, so that the problem of photoetching misalignment caused by increased device density, reduced device size and reduced distance between the contact hole and the grid in the prior art can be avoided, the problem of enlarged fluctuation range of threshold voltage caused by contact hole offset can be avoided, the problem of burning or short circuit caused by more easily concentrated current in the using process of the device can be further avoided, and the reliability of the device is enhanced.
In the above embodiments, the combination of the first conductive structure as the gate and the second conductive structure as the source region and the body region is taken as an example for explanation, but the technical solution of the present invention is not limited thereto, and it can be used in any suitable process requiring contact hole manufacturing.
For example, referring to fig. 4, in another embodiment of the present invention, the substrate 200 is a substrate that has been subjected to a back-end interconnection process, the first conductive structure formed on the surface thereof is an intermediate metal interconnection line in a multi-layer metal interconnection structure, the second conductive structure 200s is a lower metal interconnection line or a conductive plug in the multi-layer metal interconnection structure, and at this time, the contact hole 208 filled with the conductive material 209 is used to electrically connect the second conductive structure 200s and an upper metal interconnection line above the first conductive structure.
For another example, in other embodiments of the present invention, the first conductive structure is a polysilicon resistor or a capacitor plate, and the second conductive structure is a gate or a source or drain region of a transistor.
In addition, the technical scheme of the invention is not limited to the application of manufacturing the IGBT or MOS transistor device, but can also be applied to any other suitable device which needs to manufacture a contact hole, for example, the contact hole self-alignment of the CIS device can be realized by applying the manufacturing of the CIS device, so that the problem that the device structure is damaged in the contact hole self-alignment etching process due to the reduction of the pixel unit size in the CIS device is solved, and the performance reliability of the device is improved. For another example, the method can be applied to the manufacture of a memory, and the self-alignment of the contact hole of the memory unit is realized, so that the problem that the device structure is damaged in the self-alignment etching process of the contact hole due to the reduction of the size of the memory unit is solved, and the performance reliability of the device is improved.
In summary, according to the contact hole manufacturing method and the semiconductor device manufacturing method provided by the invention, the insulating medium layer with a certain thickness covers the top surface of the first conductive structure, and the sacrificial layer is filled in the space between the first conductive structures, so that after the interlayer medium layer is etched to form the opening as the upper opening of the contact hole, the lower opening of the contact hole is formed by removing the sacrificial layer in alignment, the requirement on the alignment precision of the contact hole is reduced, and the process difficulty of manufacturing the contact hole is further reduced.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art according to the above disclosure are within the scope of the present invention.
Claims (10)
1. A method for manufacturing a contact hole, comprising:
providing a substrate, wherein at least two first conductive structures which are spaced from each other are formed on the substrate, an insulating medium layer covers the top surfaces of the first conductive structures, and second conductive structures are formed in the substrate at the spacing between the adjacent first conductive structures;
forming a side wall on the inner side wall of the interval, wherein the side wall covers the first conductive structure and the side wall of the insulating medium layer;
filling a sacrificial layer in the gap, and forming an interlayer dielectric layer to cover the sacrificial layer, the insulating dielectric layer and the side wall;
etching the interlayer dielectric layer at the interval, and stopping etching on the top surface of the sacrificial layer to form an opening exposing the top surface of the sacrificial layer;
and removing the sacrificial layer in the opening bottom area to form a contact hole exposing the top surface of the second conductive structure at the interval.
2. The contact hole manufacturing method of claim 1, wherein the first conductive structure includes a gate electrode; the second conductive structure includes an ion-doped region formed in the substrate at the space, and the contact hole exposes a portion of a top surface of the ion-doped region.
3. The contact hole manufacturing method of claim 2, wherein the ion-doped region includes a body region formed in the substrate at the space and a source region formed in a surface layer of the body region, and the contact hole exposes a portion of a top surface of the source region and a top surface of the body region between adjacent source regions.
4. The contact hole manufacturing method of claim 3, wherein the step of forming the first conductive structure and the second conductive structure comprises:
sequentially covering a gate dielectric layer, a gate electrode layer and an insulating dielectric layer on the substrate;
etching the insulating dielectric layer and the gate electrode layer to form a gate electrode with the top surface covered with the insulating dielectric layer;
carrying out body region ion implantation on the substrate at the interval to form a body region;
and forming a source region in the surface layer of the body region by corresponding photoetching and source region ion implantation.
5. The contact hole fabrication method of claim 1, wherein at least one of the first conductive structure and the second conductive structure is a polysilicon resistor, a plate of a capacitor, a conductive plug, or a metal interconnect line in a multi-layer metal interconnect structure.
6. The contact hole manufacturing method of any one of claims 1 to 5, wherein a top surface of the sacrificial layer is higher than a top surface of the first conductive structure and lower than a top surface of the insulating dielectric layer; and when the interlayer dielectric layer at the interval is etched and stops on the top surface of the sacrificial layer, part of the insulating dielectric layer and the side wall are also removed, so that the line width of the opening is larger than the line width of the top surface of the sacrificial layer, and the side wall of the insulating dielectric layer forms a step which does not expose the top surface of the first conductive structure in the opening.
7. The method for manufacturing a contact hole according to claim 6, wherein the sacrificial layer in the bottom region of the opening is removed by a wet etching process, and the contact hole has a structure which is wide at the top and narrow at the bottom.
8. The method of claim 2, wherein after removing the sacrificial layer in the bottom region of the opening to form a contact hole, further comprising: and etching part of the thickness substrate below the bottom of the contact hole so that the bottom of the contact hole extends into the corresponding thickness of the ion doping area.
9. A method of manufacturing a semiconductor device, comprising:
forming a corresponding contact hole by using the contact hole manufacturing method according to any one of claims 1 to 8;
and filling a conductive material into the contact hole.
10. The manufacturing method of a semiconductor device according to claim 9, wherein the semiconductor device to be manufactured is an IGBT or MOS transistor, the first conductive structure includes a gate, the second conductive structure includes a source region, and the step of filling the contact hole with a conductive material includes: depositing a metal layer, wherein the metal fills the contact hole and deposits corresponding thickness above the insulating medium layer; and photoetching and etching the metal layer to form a source electrode metal wire for electrically leading out the source region outwards.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210836621.8A CN115188711A (en) | 2022-07-15 | 2022-07-15 | Contact hole manufacturing method and semiconductor device manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116454022A (en) * | 2023-06-16 | 2023-07-18 | 合肥新晶集成电路有限公司 | Semiconductor device and method for manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116454022A (en) * | 2023-06-16 | 2023-07-18 | 合肥新晶集成电路有限公司 | Semiconductor device and method for manufacturing the same |
| CN116454022B (en) * | 2023-06-16 | 2023-08-25 | 合肥新晶集成电路有限公司 | Semiconductor device and method for manufacturing the same |
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