CN115881186A - Three-dimensional memory, preparation method and data operation method - Google Patents

Abstract

The invention discloses a three-dimensional memory, a preparation method and a data operation method, wherein the three-dimensional memory is formed by periodically arranging a multilayer structure in the vertical direction, the multilayer structure comprises a first lead layer, a first capacitor layer, a first gate layer, a second lead layer, a second capacitor layer and a second gate layer, the first lead layer is formed by a plurality of mutually parallel leads, the first gate layer is formed by an array formed by uniformly distributing a plurality of gate tubes, the first capacitor layer is formed by an array formed by uniformly distributing a plurality of capacitors, and the lower electrode of each capacitor in the first capacitor layer is connected with the upper electrode of one gate tube in the first gate layer.

Description

Three-dimensional memory, preparation method and data operation method

Technical Field

The invention belongs to the technical field of memories, and particularly relates to a three-dimensional memory, a preparation method and a data operation method.

Background

In the von neumann computer architecture, DRAM (dynamic random access memory) plays a role as a link between external memory and CPU, playing a very important role in the stability of the computer system. The DRAM adopts a 1T1C structure, namely, the DRAM is formed by connecting 1 transistor and 1 storage unit in series, as the transistor is used as a three-port device, a peripheral control circuit needs to cause larger area consumption, and the three-port device is not suitable for realizing three-dimensional stacking, so that the DRAM is difficult to realize high-density storage through three-dimensional integration, which is also the most critical factor for limiting the performance of the DRAM at present.

In order to solve the problem of low storage density of the DRAM, a plurality of novel memories which can replace the DRAM have been explored in the academic circles and the industrial circles in the field of the memory at present, wherein the 1S1C memory unit which is provided by the chinese patent CN202111280349.1 and is formed by connecting an OTS gate tube and a capacitor in series is comparable to the DRAM in terms of reading, writing, erasing speed and power consumption, and is a novel storage technology which is very hopeful to replace the DRAM, but no research is provided at present on whether the three-dimensional integrated structure and the three-dimensional integrated function of the DRAM can be used for realizing the reading, writing and erasing functions of data;

the traditional crossbar structure is generally applied to a resistive random access memory, the requirement of a memory unit on the polarity of an operation pulse is not high, the pulse can be applied from a top electrode of the memory device and can also be applied from a bottom electrode of the memory device, for a 1S1C memory unit, data is stored by depending on the polarity of charges stored on a capacitor, the written data is related to the threshold voltage and the holding voltage of a gating device each time, and the threshold voltage and the holding voltage of the gating tube have deviation in the positive and negative directions, so the 1S1C memory is very sensitive to the polarity of the applied pulse, and when the read-write operation is carried out, the pulse application mode must be accurately controlled.

Disclosure of Invention

In view of the defects of the prior art, the present invention provides a three-dimensional memory, which aims to solve the problem of low storage density of a 1S1C memory plane structure.

The three-dimensional memory provided by the invention is formed by periodically arranging a multilayer structure in the vertical direction, wherein the multilayer structure comprises a first lead layer, a first capacitor layer, a first gate layer, a second lead layer, a second capacitor layer and a second gate layer; the first wire layer consists of a plurality of wires which are parallel to each other; the first gate tube layer comprises a plurality of gate tubes, and the lower electrode of each gate tube in the first gate tube layer is connected with one conducting wire in the first conducting wire layer; the first capacitor layer comprises a plurality of capacitors, and the lower electrode of each capacitor in the first capacitor layer is connected with the upper electrode of one gate tube in the first gate tube layer; the second lead layer comprises a plurality of leads which are parallel to each other, and the upper electrode of each capacitor in the first capacitor layer is connected with one lead in the second lead layer; the second gate tube layer comprises a plurality of gate tubes, and the lower electrode of each gate tube in the second gate tube layer is connected with one conducting wire in the second conducting wire layer; the second capacitor layer comprises a plurality of capacitors, a lower electrode of each capacitor in the second capacitor layer is connected with an upper electrode of one gate tube in the second gate tube layer, and an upper electrode of each capacitor in the second capacitor layer is connected with one wire in the first wire layer of the multilayer structure arranged in the next period.

The first gating tube layer and the second gating tube layer are both composed of an array formed by uniformly distributing a plurality of gating tubes; the first capacitor layer and the second capacitor layer are both composed of arrays formed by uniformly distributing a plurality of capacitors.

Furthermore, the second wire layer is composed of a plurality of wires which are parallel to each other and form a certain angle with the wires of the first wire layer in the horizontal direction.

The angle is preferably greater than 0 and equal to or less than 90 degrees.

Furthermore, the capacitance in the first capacitance layer is the same as the capacitance in the second capacitance layer, and the gate tube in the first gate tube layer is the same as the gate tube in the second gate tube layer.

Wherein, the gate tubes in the first gate tube layer and the second gate tube layer have bidirectional conduction characteristics, and a forward threshold voltage Vth + and a forward holding voltage Vhold + exist in the forward direction, and a reverse threshold voltage Vth-and a reverse holding voltage Vhold-exist in the reverse direction.

The invention also provides a data operation method based on the three-dimensional memory, which comprises a data reading operation method and a data writing operation method, wherein the data reading operation method comprises the following steps:

(1) Judging that a storage unit to be operated is positioned in the second layer of the three-dimensional memory; specifically, the address instruction may be decoded to obtain a physical address location of the memory unit according to the address instruction transmitted by the memory control module, where the physical address location includes the memory unit in the layer number of the three-dimensional memory.

(2) When data reading operation is needed, if the layer is the nth layer, applying forward reading voltage Vread + on a word line electrode connected with the top electrode of the memory cell, and applying reverse reading voltage Vread-on a bit line electrode connected with the bottom electrode of the memory cell; if the layer is the (n + 1) th layer, applying a forward reading voltage Vread + on a bit line electrode connected with the top electrode of the memory cell, and applying a reverse reading voltage Vread-on a word line electrode connected with the bottom electrode of the memory cell;

when data writing operation is needed, if the layer is the nth layer, applying a forward writing voltage Vwrite + on a word line electrode connected with the top electrode of the memory cell, and applying a reverse writing voltage Vwrite-on a bit line electrode connected with the bottom electrode of the memory cell; if the layer is the (n + 1) th layer, applying a forward writing voltage Vwrite + to a bit line electrode connected with the top electrode of the memory cell, and applying a reverse writing voltage Vwrite-to a word line electrode connected with the bottom electrode of the memory cell;

the nth layer unit and the (n + 1) th layer unit share a word line, the (n + 1) th layer unit and the (n + 2) th layer unit share a bit line, and n is a positive integer greater than or equal to 1 and generally less than or equal to 1000.

Furthermore, a voltage difference Vwrite is formed between two ends of the memory cell by applying a forward writing voltage Vwrite + and a reverse writing voltage Vwrite-to the two ends of the memory cell respectively, when the voltage difference between the two ends of a gate tube in the selected memory cell is larger than a threshold voltage Vth of the gate tube, the gate tube is opened, a capacitor is charged, so that a capacitor voltage Vc in the memory cell reaches a specific value, two different capacitor voltages Vc are obtained by designing two different Vwrite, one Vc is marked as a state 0, and the other Vc is marked as a state 1, so that a data storage function is realized.

The operating method of data reading comprises the steps that a voltage difference Vread is formed between two ends of a selected memory cell by applying specific voltages (Vread + and Vread-) on a lead in a first lead layer connected with the selected memory cell and a lead in a second lead layer connected with the selected memory cell, so that a gate tube in the memory cell in a state 0 can be opened, the gate tube in the memory cell in a state 1 cannot be opened, and the data state of the memory cell is judged by sensing the change of current in the leads; during data reading and writing, the voltage applied to the conductive line does not cause the gate tube in the unselected memory cell to open.

Further preferably, the data read operation and the data write operation can implement either a bitwise operation or an entire row operation, and the entire row operation includes: applying a word line voltage V1 to a wire shared by the memory cells in the row (the application of the word line voltage V1 does not open a gate tube in the memory cells), and applying a bit line voltage V2 to another wire connected with the corresponding memory cell according to the operation to be performed by each memory cell, wherein the bit line voltage V2 and the word line voltage V1 jointly act to open the gate tube in the memory cell, thereby completing the read-write operation.

The invention also provides a preparation method based on the three-dimensional memory, which comprises the following steps:

(1) Forming a first electrode layer consisting of a plurality of parallel strip electrodes on a substrate of a memory cell;

(2) Forming a first insulating layer on the first electrode layer;

(3) Selectively etching to remove the first insulating layer and leaving a plurality of hole arrays penetrating through the first insulating layer, wherein the holes are positioned right above the first electrode layer strip-shaped electrodes; specifically, the hole array can be square, rectangular or parallelogram;

(4) Sequentially forming a first gate tube layer, a second electrode layer and a first dielectric layer in the hole;

(5) Forming a third electrode layer consisting of a plurality of strip electrodes which are not connected with each other and are parallel, wherein the third electrode layer is vertical to the strip electrodes of the first electrode layer in the horizontal direction, and the holes are positioned at the intersection of the first electrode layer and the third electrode layer;

(6) Sequentially repeating the steps (2) to (5), wherein the position of the hole formed in each layer is deviated from the position of the hole formed in the previous layer by 2d in the horizontal direction until the number of the target three-dimensional memory layers is obtained; wherein d is the characteristic size of the hole;

(7) And etching an interface of each layer of electrode and obtaining the three-dimensional memory.

Through the technical scheme, compared with the prior art, the invention has the following beneficial effects:

(1) The memory is simple in structure, when a multilayer 1S1C memory needs to be prepared, only the previous steps need to be simply repeated, the 1S1C memory units can be stacked in the vertical direction, and the storage density of the 1S1C memory can be greatly improved; and the structural integrity of the memory cells in the crossbar structure, and enables all memory cells to have better state uniformity.

(2) The memory structure can realize independent addressing of each memory unit, realize bitwise operation and whole-line operation, and enrich the application scenes of the memory.

(3) An operation method for the crossbar structure of the 1S1C memory is proposed, because the gate tubes in the 1S1C memory have polarity difference in forward and reverse directions, which results in different responses when the same voltage is applied to the 1S1C memory in forward and reverse directions. In the conventional crossbar structure, after the memory cell is selected, V/2 is applied only to the word line and-V/2 is applied to the bit line, and it is not necessary to care whether the top electrode or the bottom electrode of the memory cell is connected to the word line. In the invention, the voltage applied on the word line and the bit line is adjusted by judging the layer number of the storage unit, so that the polarity difference of a gating device is overcome, and the data consistency of the storage unit is better.

(4) The provided 1S1C memory preparation method staggers the positions of the holes in the same area in the vertical direction, avoids the influence of surface unevenness on the shape of the holes in the upper layer caused by the preparation and filling of the holes in the lower layer, and ensures the stability of the performance of the 1S1C memory along with the increase of the number of stacked layers.

Drawings

FIG. 1 is a schematic structural diagram of a three-dimensional memory according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a three-dimensional memory according to an embodiment of the present invention, wherein a write 0 pulse is applied;

FIG. 3 is a schematic diagram of a three-dimensional memory provided by an embodiment of the present invention applying write 1 pulses;

FIG. 4 is a schematic diagram of a three-dimensional memory applying a read pulse according to an embodiment of the present invention;

FIG. 5 is a flowchart illustrating a method for manufacturing a three-dimensional memory according to an embodiment of the present invention;

fig. 6 is a top view of a partial area of a 1S1C memory in a three-dimensional memory according to an embodiment of the invention.

The same reference numbers will be used throughout the drawings to refer to the same or like elements or structures, wherein: 1 is the bit line, 2 is the word line, 3 is the gate line, 4 is the capacitor, 21 is the word line voltage, 22 is the capacitor voltage, 23 is the bit line voltage, and 42 is the current flowing through the memory cell.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

Fig. 1 illustrates a structure of a three-dimensional memory provided by an embodiment of the present invention, and for convenience of description, only the portions related to the embodiment of the present invention are illustrated, and the following detailed description is provided in conjunction with the accompanying drawings:

the memory uses gate tube 3 and capacitor 4 to connect in series to form the most basic memory cell, one end of each memory cell is connected with word line 2, another end is connected with bit line 1, the memory cell is set at the cross of word line 2 and bit line 1, to form cross bar structure, two memory cells adjacent in vertical direction share the same word line or bit line; if the three-dimensional memory is structurally divided according to a word line layer, a bit line layer and a storage unit layer, the storage unit layer is arranged above the word line layer in the vertical direction of the three-dimensional memory, the bit line layer is arranged above the storage unit layer, the next storage unit layer is arranged above the bit line layer, the next word line layer is arranged above the storage unit layer, and the storage unit layers are used as a structural period and are stacked periodically in the vertical direction, so that three-dimensional data storage can be realized.

In the three-dimensional memory, all the memory cells are made of the same material and the same structure under the same process condition, so that the memory cells have better consistency.

In the three-dimensional memory, a gate tube has a bidirectional conduction characteristic, a threshold voltage Vth and a holding voltage Vhold exist in the forward direction and the reverse direction, when the voltage of the two ends of the gate tube exceeds the threshold voltage Vth, the gate tube is switched from a high-impedance state to a low-impedance state, and when the voltage of the two ends of the gate tube in the low-impedance state is lower than the holding voltage Vhold, the gate tube is switched from the low-impedance state to the high-impedance state.

The storage unit formed by connecting the gate tube and the capacitor in series has the characteristic that when voltage Vin is applied to two ends of the storage unit, the voltage at two ends of the gate tube is larger than threshold voltage Vth, the gate tube is opened, the capacitor is charged, and the voltage Vc on the capacitor is related to the voltage Vin applied to the two ends of the storage unit, so that two different capacitor voltages Vc are obtained by designing two different Vin, one Vc is marked as a storage state 0, and the other Vc is marked as a storage state 1, so that the function of data storage can be realized.

When the memory cell in the three-dimensional memory is operated, voltages need to be applied to a word line and a bit line connected with the memory cell respectively, and a voltage difference between the word line voltage and the bit line voltage can be loaded on the memory cell, so that the memory cell can be operated.

When data writing operation is carried out on the memory cells in the three-dimensional memory, the voltage difference between the word line voltage and the bit line voltage can enable the gate tube of the selected memory cell to be opened, the capacitor is charged to the corresponding capacitor voltage Vc, and for the unselected memory cells, the gate tube is in a closed state, and the capacitor voltage Vc is not influenced.

When data reading operation is carried out on a storage unit in the three-dimensional memory, a voltage difference between a word line voltage and a bit line voltage is loaded to two ends of the storage unit, a gate tube in the storage unit in a state 0 can be opened, a gate tube in the storage unit in a state 1 cannot be opened, and the data state of the storage unit is judged by sensing the change of current in a lead.

The three-dimensional memory can realize not only bit operation but also whole-row operation, and when the whole-row operation is needed, a specific voltage is applied to a word line shared by the memory cells in the row, and then the specific voltage is applied to the other conducting wire connected with the corresponding memory cell according to the operation to be carried out by each memory cell.

The conduction of the gate tube in the 1S1C memory of the invention in the forward direction and the reverse direction has a difference, which is particularly represented by the difference of about 0.2V between the threshold voltage Vth and the holding voltage Vhold of the gate tube in the forward direction and the reverse direction. In the crossbar structure adopted by the invention, the memory cells are arranged at the cross points of word lines and bit lines, the adjacent memory cells share the word lines or the bit lines, the lower electrodes of the memory cells in the first layer are connected with the word lines, the upper electrodes of the memory cells in the first layer are connected with the bit lines, the lower electrodes of the memory cells in the second layer are connected with the bit lines, and the upper electrodes of the memory cells in the second layer are connected with the word lines. However, in the 1S1C memory, the polarity is quite sensitive, for example, when writing 1 operation is performed, if a voltage of V/2 is applied to the fixed word line and a voltage of-V/2 is applied to the bit line, the voltages on the write capacitors of the cells in which the upper electrodes of the memory cells are connected to the word line and the upper electrodes of the memory cells are connected to the bit line will be different due to different opening directions of the gate transistors, which affects the state uniformity of the whole memory cell and is easy to generate data storage errors. The same phenomenon exists for the read operation, and if the read voltage values applied by the word line and the bit line are fixed, the difference of the forward and reverse data reading can also be caused because the turn-on voltages of the gate tubes in the forward and reverse directions are different, and the difference can reduce the read margin in the design of the read circuit and easily cause read errors.

Therefore, the word lines and the bit lines are controlled to apply different voltages according to the number of the memory cells (namely, the odd number layer or the even number layer).

And (3) reading: if the layer is the nth layer, applying Vread + to a word line electrode connected with the top electrode of the memory cell, and applying Vread-to a bit line electrode connected with the bottom electrode of the memory cell; if the layer is the (n + 1) th layer, applying Vread + to a bit line electrode connected with the top electrode of the memory cell, and applying Vread-to a word line electrode connected with the bottom electrode of the memory cell;

and (3) writing: if the layer is the nth layer, applying Vwrite + on a word line electrode connected with the top electrode of the memory cell, and applying Vwrite-on a bit line electrode connected with the bottom electrode of the memory cell; if the layer is the (n + 1) th layer, applying Vwrite + on a bit line electrode connected with the top electrode of the memory cell, and applying Vwrite-on a word line electrode connected with the bottom electrode of the memory cell;

wherein the nth layer unit and the (n + 1) th layer unit share a word line, and the (n + 1) th layer unit and the (n + 2) th layer unit share a bit line;

respectively applying Vwrite + and Vwrite-to two ends of a storage unit to form a voltage difference Vwrite at two ends of the storage unit, enabling the voltage difference at two ends of a gate tube in the selected storage unit to be larger than a threshold voltage Vth of the gate tube, opening the gate tube, charging a capacitor, enabling a capacitor voltage Vc in the storage unit to reach a specific value, designing two different Vwrite to obtain two different capacitor voltages Vc, marking one Vc as a state 0, and marking the other Vc as a state 1 to realize a data storage function;

the operating method of data reading includes applying specific voltage (here, vread + and Vread-) to the wires in the first wire layer connected to the selected memory cell and the wires in the second wire layer connected to the selected memory cell to form voltage difference Vread across the selected memory cell, so that the gate tube in the memory cell in state 0 can be opened, the gate tube in the memory cell in state 1 can not be opened, and the data state of the memory cell can be judged by sensing the current change in the wires;

during data reading and writing, the voltage applied to the conductive lines does not cause the gate tubes in the unselected memory cells to open.

The following is further detailed in conjunction with preferred examples:

example 1:

in the three-dimensional memory provided by the embodiment of the invention, the threshold voltage Vth of the selected gating tube is 4V, and the holding voltage Vhold is 3V.

As shown in FIG. 2, when the data 0 to be written is set, the word line voltage 21 is 2.2V, the bit line voltage 23 is-2.2V, and the initial state capacitor voltage 22 is 0V, so that a voltage difference of 4.4V is formed across the gate tube, which is greater than the threshold voltage of 4V, the gate tube is opened, the capacitor is charged, when the capacitor voltage 22 reaches 1.4V, the voltage across the gate tube starts to be less than the holding voltage of 3V, the gate tube is closed, and the capacitor voltage 22 is maintained at 1.4V.

As shown in FIG. 3, when the data 1 to be written is required, the word line voltage 21 is set to-2.2V, the bit line voltage 23 is set to 2.2V, and since the initial state capacitor voltage 22 is 0V, a voltage difference of 4.4V is formed across the gate tube, which is greater than the threshold voltage of 4V, the gate tube is opened, the capacitor is charged, when the capacitor voltage 22 reaches-1.4V, the voltage across the gate tube starts to be less than the holding voltage of 3V, the gate tube is closed, and the capacitor voltage 22 is maintained at-1.4V.

Therefore, the state 0 can be represented by the capacitor voltage of 1.4V, and the state 1 can be represented by the capacitor voltage of-1.4V, so that the function of data storage is realized. When data writing operation is carried out, the voltage applied to the word line and the bit line is 2.2V or-2.2V, and the voltage of the capacitor in the memory cell is 1.4V or-1.4V, so that for the half-selected cell and the unselected cell, the voltage at the two ends of the gate tube is less than 4V and less than the threshold voltage, the gate tube is not opened, and the stored data information is not influenced.

As shown in FIG. 4, during a data read operation, the word line voltage 21 is 1.5V and the bit line voltage 23 is-1.5V, which results in a 3V voltage differential across the memory cell. If the read unit is in the state 0, namely the capacitor voltage is 1.4V, the voltage at the two ends of the gate tube is 1.6V and is less than the threshold voltage, the gate tube cannot be opened, and the read current cannot be generated; if the read cell is in state 1, i.e. the capacitor voltage is-1.4V, and the voltage at both ends of the gate tube is 4.4V, which is greater than the threshold voltage, the gate tube will open to generate a read current 42 with a larger amplitude, so that the data storage state of the selected memory cell can be determined by sensing whether a large current is generated in the word line and the bit line.

In the data reading operation, the voltage applied to the word line and the bit line is 1.5V or-1.5V, and the voltage of the capacitor in the memory cell is 1.4V or-1.4V, so that for the half-selected cell and the unselected cell, the voltage at the two ends of the gate tube is less than 4V and less than the threshold voltage, the gate tube is not opened, and the stored data information is not influenced.

Data read and data write may also implement full row operations. When data reading operation is carried out, the voltage of a word line shared by the cells in the row is set to be 1.5V, then the voltage of a bit line connected with each cell is set to be-1.5V, and the storage state of the storage cell can be sensed by reading the current on each bit line; when data writing operation is carried out, firstly, the voltage of a word line shared by the row of units is set to be 2.2V, then the voltage of a bit line connected with a storage unit needing to be subjected to writing 0 operation is set to be-2.2V, then the writing 0 operation can be completed, then the voltage of the word line shared by the row of units is set to be-2.2V, and then the voltage of the bit line connected with the storage unit needing to be subjected to writing 1 operation is set to be 2.2V, and then the writing 1 operation can be completed. By the method, the row-by-row operation of the memory cells can be realized.

Example 2:

the preparation method of the three-dimensional memory provided by the embodiment of the invention comprises the following steps:

(1) Growing a plurality of strip-shaped electrodes W which are parallel to each other on a silicon substrate by utilizing magnetron sputtering, wherein the thickness of the strip-shaped electrodes W is 100nm;

(2) Growing a layer of SiO2 serving as an insulating layer by PECVD, wherein the thickness of the insulating layer is 100nm;

(3) Etching a plurality of small holes in SiO2 by using dry etching selectivity, wherein the small holes Kong Guoke are formed in the electrode tungsten, the small holes are arranged in a square shape, and each small hole is positioned right above the strip-shaped electrode;

(4) Sequentially growing 20nm GeTe9 and 100nm W in the small hole by magnetron sputtering;

(5) Growing 20nm SiO2 in the small hole by utilizing PECVD;

(6) Growing a plurality of parallel strip-shaped electrodes W by magnetron sputtering, wherein the thickness of the strip-shaped electrodes W is 100nm, and the strip-shaped electrodes W are vertical to the strip-shaped electrodes W grown in the step (1);

(7) Repeating (2) - (6), and the position of the hole formed by each layer is shifted by 2d (d is the characteristic size of the hole) in the horizontal direction than the hole formed by the previous layer;

(8) And etching the pad of each layer of electrode in sequence by using dry etching.

As shown in fig. 6, which is a schematic top view of a partial area of a 1S1C memory according to the present invention, where the area is a top view of a cross area between a word line electrode and a bit line electrode, and the memory cells are all provided with the cross area between the word line electrode and the bit line electrode, and three circular holes at different positions can be seen in the figure, which indicates that the holes of each layer are at different positions in the horizontal direction, because the 1S1C memory proposed in the present invention is implemented by etching holes in an insulating layer and filling functional layer materials in the holes, after the holes of each layer are filled with the materials, the formed surface has depressions or protrusions, and therefore, when the second layer 1S1C memory is still etched at the position in the horizontal direction, the shape of the obtained holes is affected by the shape of the holes in the front layer, which results in the performance of the 1S1C memory cells with a higher number of layers, and the errors in the shape are accumulated, and the number of the layers is higher, which results in the shape of the holes is worse, so that the position of the holes of each layer is shifted from the feature size of the holes in the front layer by 2 holes, the feature size of the holes in the front layer, which also results in the performance of the surface of the 1S1C cells in the latter layer. The above are preferred embodiments of the present invention, and all changes made according to the technical scheme of the present invention that produce functional effects do not exceed the scope of the technical scheme of the present invention belong to the protection scope of the present invention.

It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (10)

1. The three-dimensional memory is characterized by being formed by periodically arranging a multilayer structure in the vertical direction, wherein the multilayer structure comprises a first lead layer, a first capacitor layer, a first gate tube layer, a second lead layer, a second capacitor layer and a second gate tube layer;

the first lead layer consists of a plurality of leads which are parallel to each other;

the first gate tube layer comprises a plurality of gate tubes, and the lower electrode of each gate tube in the first gate tube layer is connected with one conducting wire in the first conducting wire layer;

the first capacitor layer comprises a plurality of capacitors, and the lower electrode of each capacitor in the first capacitor layer is connected with the upper electrode of one gate tube in the first gate tube layer;

the second lead layer comprises a plurality of leads which are parallel to each other, and the upper electrode of each capacitor in the first capacitor layer is connected with one lead in the second lead layer;

the second gate tube layer comprises a plurality of gate tubes, and the lower electrode of each gate tube in the second gate tube layer is connected with one conducting wire in the second conducting wire layer;

the second capacitor layer comprises a plurality of capacitors, a lower electrode of each capacitor in the second capacitor layer is connected with an upper electrode of one gate tube in the second gate tube layer, and an upper electrode of each capacitor in the second capacitor layer is connected with one wire in the first wire layer of the multilayer structure arranged in the next period.

2. The three-dimensional memory of claim 1, wherein the first gate layer and the second gate layer are each comprised of an array of a plurality of gate tubes evenly distributed;

the first capacitor layer and the second capacitor layer are both composed of an array formed by uniformly distributing a plurality of capacitors.

3. The three-dimensional memory according to claim 1 or 2, wherein the second conductive line layer is composed of a plurality of conductive lines parallel to each other and at an angle to the conductive lines of the first conductive line layer in the horizontal direction.

4. The three-dimensional memory according to claim 3, wherein the angle is greater than 0 and equal to or less than 90 degrees.

5. The three-dimensional memory of claim 1, wherein a capacitance in the first capacitance layer is the same as a capacitance in the second capacitance layer, and wherein a gate pipe in the first gate layer is the same as a gate pipe in the second gate layer.

6. The three-dimensional memory of any one of claims 1-5, wherein the gate tubes in the first gate tube layer and the second gate tube layer have a bidirectional conduction characteristic and have a forward threshold voltage Vth +, a forward holding voltage Vhold +, and a reverse threshold voltage Vth-, a reverse holding voltage Vhold-in-exist in a forward direction.

7. A data operation method based on the three-dimensional memory of any one of claims 1 to 6, wherein the data operation method comprises an operation method of data reading and an operation method of data writing:

(1) Judging that a storage unit to be operated is positioned in the second layer of the three-dimensional memory;

(2) When data reading operation is needed, if the layer is the nth layer, applying forward reading voltage Vread + on a word line electrode connected with the top electrode of the memory cell, and applying reverse reading voltage Vread-on a bit line electrode connected with the bottom electrode of the memory cell; if the layer is the (n + 1) th layer, applying a forward reading voltage Vread + on a bit line electrode connected with the top electrode of the memory cell, and applying a reverse reading voltage Vread-on a word line electrode connected with the bottom electrode of the memory cell;

when data writing operation is needed, if the layer is the nth layer, applying a forward writing voltage Vwrite + on a word line electrode connected with the top electrode of the memory cell, and applying a reverse writing voltage Vwrite-on a bit line electrode connected with the bottom electrode of the memory cell; if the layer is the (n + 1) th layer, applying a forward writing voltage Vwrite + to a bit line electrode connected with the top electrode of the memory cell, and applying a reverse writing voltage Vwrite-to a word line electrode connected with the bottom electrode of the memory cell;

the nth layer unit and the (n + 1) th layer unit share a word line, the (n + 1) th layer unit and the (n + 2) th layer unit share a bit line, and n is a positive integer greater than or equal to 1 and generally less than or equal to 1000.

8. The data operating method as claimed in claim 7, wherein a voltage difference Vwrite is formed between two ends of the memory cell by applying a forward write voltage Vwrite + and a reverse write voltage Vwrite-respectively, the gate tube is opened when the voltage difference between two ends of the gate tube in the selected memory cell is greater than a threshold voltage Vth of the gate tube, the capacitor is charged, so that a capacitor voltage Vc in the memory cell reaches a specific value, two different Vwrite are designed to obtain two different capacitor voltages Vc, one capacitor voltage Vc is marked as a state 0, and the other capacitor voltage Vc is marked as a state 1, thereby realizing the function of data storage; when the capacitor is charged, the voltage at two ends of the gate tube is reduced, when the voltage at two ends of the gate tube is reduced to be less than Vhold, the charging is stopped, and at the moment, the corresponding capacitor voltage is the specific value.

9. The data manipulation method of claim 7 wherein the data read operation and the data write operation are performed either as a bitwise operation or as a full row operation; wherein the whole row of operations comprises: a word line voltage V1 is applied to a conductor common to the memory cells of the row and a bit line voltage V2 is applied to the other conductor connected to the respective memory cell, depending on the operation to be performed by each memory cell.

10. A method for preparing a three-dimensional memory based on any one of claims 1 to 6, comprising the following steps:

(1) Forming a first electrode layer consisting of a plurality of parallel strip electrodes on a substrate of a memory cell;

(2) Forming a first insulating layer on the first electrode layer;

(3) Selectively etching to remove the first insulating layer and leaving a plurality of hole arrays penetrating through the first insulating layer, wherein the holes are positioned right above the first electrode layer strip-shaped electrodes;

(4) Sequentially forming a first gate tube layer, a second electrode layer and a first dielectric layer in the hole;

(5) Forming a third electrode layer consisting of a plurality of strip electrodes which are not connected with each other and are parallel, wherein the third electrode layer is vertical to the strip electrodes of the first electrode layer in the horizontal direction, and the holes are positioned at the intersection of the first electrode layer and the third electrode layer;

(6) Sequentially repeating the steps (2) to (5), wherein the position of the hole formed in each layer is deviated from the position of the hole formed in the previous layer by 2d in the horizontal direction until the number of the target three-dimensional memory layers is obtained; wherein d is the characteristic size of the hole;

(7) And etching an interface of each layer of electrode and obtaining the three-dimensional memory.

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