CN115879403A - On-site programmable logic gate array circuit and data processing method - Google Patents

Abstract

The embodiment of the invention discloses a field programmable gate array circuit, a data processing method and a circuit design method. Wherein, the field programmable gate array circuit includes: a communication interface; the system comprises at least one functional module, a plurality of switching matrix modules and a plurality of switching modules, wherein the switching matrix modules comprise a plurality of switching matrixes, the functional operator modules are connected with the switching matrixes, and one or more switching matrixes are connected between any two functional operator modules; the communication interface is directly or indirectly connected to at least a part of the switching matrix. The invention can avoid carrying out complete flow design on the FPGA again, and improves the flexibility of the FPGA.

Description

On-site programmable logic gate array circuit and data processing method

Technical Field

The invention relates to the technical field of electronic circuits, in particular to a field programmable gate array circuit, a data processing method and a circuit design method.

Background

An FPGA (Field Programmable Gate Array) is a kind of digital logic circuit, the most basic units of a digital logic system are an and Gate, an or Gate, a not Gate, etc., the Gate circuit is composed of elements such as a diode, a triode, a resistor, etc., and then the and Gate, the or Gate, and the not Gate constitute various flip-flops to realize state memory. FPGAs are digital Integrated Circuits (ICs) made up of configurable or programmable logic blocks connected by configurable interconnection resources. Design engineers may program such devices to perform a variety of tasks.

At present, the logic operation function realized by a functional module in the FPGA is single, and the flexibility is poor. When the logical operation function of the functional module needs to be reconfigured by the FPGA, the steps of front-end algorithm planning, coding, simulation, comprehensive layout and wiring, design convergence and the like need to be performed on the FPGA again, which is time-consuming, labor-consuming and low in efficiency.

Disclosure of Invention

Aiming at the defects of the prior art, the invention provides a field programmable gate array circuit, a data processing method and a circuit design method, aiming at solving the technical problem of poor flexibility of an FPGA in the prior art.

To solve the above problem, in a first aspect, an embodiment of the present invention provides a field programmable gate array circuit, which includes:

a communication interface;

at least one functional module comprising a plurality of functional operator modules and a switching matrix module, the switching matrix module comprising a plurality of switching matrices; one or more switching matrixes are connected between any two functional operator modules; the communication interface is directly or indirectly connected to at least a part of the switching matrix.

Further, in the field programmable gate array circuit, the plurality of functional operator modules include a first functional operator module, a second functional operator module, and a third functional operator module, where the first functional operator module and the second functional operator module each include a plurality of operator modules, two adjacent switching matrices are connected to each other, each operator module in the first functional operator module is connected to one switching matrix, each operator module in the second functional operator module is connected to two adjacent switching matrices, and the third functional operator module is connected to each switching matrix.

Further, in the field programmable gate array circuit, the switching matrix module includes a first switching matrix, a second switching matrix, a third switching matrix and a fourth switching matrix; the first functional operator module comprises a first operator module, a second operator module, a third operator module and a fourth operator module, and the second functional operator module comprises a fifth operator module, a sixth operator module, a seventh operator module and an eighth operator module;

wherein the first switching matrix is connected to the second switching matrix, the third switching matrix, the first operator module, the fifth operator module, the sixth operator module, and the third functional operator module, respectively;

the second switching matrix is respectively connected with the second operator module, the fifth operator module, the seventh operator module and the third functional operator module;

the third switching matrix is respectively connected with the third operator module, the sixth operator module, the eighth operator module and the third functional operator module;

the fourth switching matrix is connected to the second switching matrix, the third switching matrix, the fourth operator module, the seventh operator module, the eighth operator module, and the third functional operator module, respectively.

Furthermore, in the field programmable gate array circuit, the switch matrix module further includes a fifth switch matrix, a sixth switch matrix, a seventh switch matrix, and an eighth switch matrix, the fifth operator module includes a first operator and a second operator, the sixth operator module includes a third operator and a fourth operator, the seventh operator module includes a fifth operator and a sixth operator, and the eighth operator module includes a seventh operator and an eighth operator;

wherein the first operator is connected to the first switching matrix and the fifth switching matrix respectively;

the second operator is respectively connected with the second switching matrix and the fifth switching matrix;

the third operator is respectively connected with the first switching matrix and the sixth switching matrix;

the fourth operator is respectively connected with the fourth switching matrix and the sixth switching matrix;

the fifth operator is respectively connected with the second switching matrix and the seventh switching matrix;

the sixth operator is respectively connected with the fourth switching matrix and the seventh switching matrix;

the seventh operator is respectively connected with the third switching matrix and the eighth switching matrix;

the seventh operator is respectively connected with the fourth switching matrix and the eighth switching matrix;

the third functional operator module is respectively connected with the first switching matrix, the second switching matrix, the third switching matrix, the fourth switching matrix, the fifth switching matrix, the sixth switching matrix, the seventh switching matrix and the eighth switching matrix;

the fifth switching matrix is respectively connected with the first switching matrix and the second switching matrix;

the sixth switching matrix is respectively connected with the first switching matrix and the third switching matrix;

the seventh switching matrix is respectively connected with the second switching matrix and the fourth switching matrix;

and the eighth switching matrix is respectively connected with the third switching matrix and the fourth switching matrix.

Further, in the field programmable gate array circuit, the plurality of functional operator modules includes at least one of: multiplier, trigger, filter, convolution kernel, accumulator, adder, subtracter and delay unit.

Further, in the field programmable gate array circuit, the switching matrix module receives at least one path of input signals input from outside through the communication interface; and the switching matrix module outputs at least one path of output signal to the outside through the communication interface.

Further, in the field programmable gate array circuit, the functional module is configured to execute a target logical operation on a target signal input to the functional module, where the target logical operation includes N sub-logical operations, N functional operator modules in the functional module respectively execute the N sub-logical operations, and the switching matrix module is configured to configure a communication link of a connection end of the N functional operator modules to execute the target logical operation on the target signal.

In a second aspect, an embodiment of the present invention further provides a data processing method, which is applied to the field programmable gate array circuit in the first aspect;

the data processing method comprises the following steps:

the communication interface receives an externally input signal to be processed;

the functional module acquires a target signal and executes the target logic operation to obtain a first processing result of the target signal; the target signal is the signal to be processed or a signal obtained based on the signal to be processed;

the communication interface outputs the first processing result or a second processing result obtained based on the first processing result.

In a third aspect, an embodiment of the present invention further provides a circuit design method, including:

designing the circuit on the target circuit board into the field programmable gate array circuit of the first aspect;

determining a first target logic operation which is required to be executed by the functional module and aims at a first target signal; the first target logical operation comprises N sub-logical operations, and N functional operator modules in the plurality of functional operator modules are capable of executing the N sub-logical operations respectively;

configuring the communication links of the connection ends of the N functional operator modules to be a processing procedure capable of executing the first target logic operation on the first target signal by configuring the switch matrix module.

Further, in the circuit design method, the designing the circuit on the target circuit board to be the field programmable gate array circuit of the first aspect includes:

acquiring operator demand information, wherein the operator demand information is used for expressing the quantity requirements of various functional operator modules;

and designing a circuit on the circuit board into the field programmable gate array circuit according to the operator requirement information.

According to the field programmable gate array circuit provided by the embodiment of the invention, the communication interface and at least one functional module are arranged in the FPGA, the functional modules are simultaneously provided with a plurality of functional operator modules and a switching matrix module, one or more switching matrixes in the switching matrix module are connected between any two functional operator modules to realize flexible configuration of the functional modules, and the communication interface is directly or indirectly connected with at least one part of the switching matrix.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a block diagram of a field programmable gate array circuit according to an embodiment of the present invention;

FIG. 2 is a schematic block diagram of functional modules provided by an embodiment of the present invention;

FIG. 3 is another schematic block diagram of functional modules provided in an embodiment of the present invention;

fig. 4 is a link diagram of the functional module performing logic operation according to the embodiment of the present invention;

FIG. 5 is another chain diagram illustrating logic operations performed by the functional modules according to an embodiment of the present invention;

FIG. 6 is another link diagram illustrating the logic operations performed by the functional modules according to the embodiment of the present invention;

FIG. 7 is a schematic block diagram of a data processing method provided by an embodiment of the present invention;

FIG. 8 is a schematic block diagram of a circuit design method provided by an embodiment of the present invention;

fig. 9 is another schematic block diagram of a circuit design method according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

Referring to fig. 1, fig. 1 is a block diagram of a field programmable gate array circuit according to an embodiment of the present invention.

As shown in fig. 1, a field programmable gate array circuit includes:

a communication interface 10;

at least one functional module 20, said functional module 20 comprising a plurality of functional operator modules and a switching matrix module, said switching matrix module comprising a plurality of switching matrices; one or more switching matrixes are connected between any two functional operator modules; the communication interface 10 is directly or indirectly connected to at least part of the switching matrix.

Specifically, the function module 20 is configured to execute a target logical operation on a target signal input to the function module 20, where the target logical operation includes N sub-logical operations, N function operator modules in the function module 20 execute the N sub-logical operations respectively, and the switching matrix module is configured to configure a communication link of a connection end of the N function operator modules to execute the target logical operation on the target signal.

Wherein the functional operator module comprises at least one of: multiplier, trigger, filter, convolution kernel, accumulator, adder, subtracter and delay unit. In the functional module 20 there are three types of functional operator modules, one of which is connected to only one of the switching matrices in the switching matrix module, another to two adjacent switching matrices in the switching matrix module, and yet another to all switching matrices in the switching matrix module.

The method and the device can not only directly realize the general algorithm in the FPGA through the functional module 20, but also realize a complex high-performance complete algorithm. When the function module 20 is required to perform target logic operation on an input target signal, the function module 20 is only required to be connected with a required function operator module through a switching matrix in the switching matrix module, so that the function operator module can receive a corresponding signal and execute corresponding logic operation, and further the function module 20 realizes the logic operation on the target signal, so that steps of front-end algorithm planning, encoding, simulation, comprehensive layout and wiring, design convergence and the like do not need to be performed on the FPGA again, and the flexibility of the FPGA is greatly improved.

In some embodiments, as shown in fig. 2, the functional operator modules include a first functional operator module, a second functional operator module, and a third functional operator module, the first functional operator module, the second functional operator module each including a plurality of operator modules, the switch matrix module including a plurality of switch matrices; each operator module in the first functional operator module is connected with one switching matrix, each operator module in the second functional operator module is connected with two adjacent switching matrices, and the third functional operator is connected with each switching matrix.

Specifically, the first functional operator module and each operator module in the second functional operator and the third functional operator module are connected through one or more switching matrices, and the operator modules and the third functional operator modules are not directly connected.

The first functional operator module and the second functional operator module comprise a plurality of operator modules, the third functional operator module can comprise one operator module or a plurality of operator modules, the operator modules are operators with logical operation functions, and each operator module comprises at least one of the following modules: multiplier, trigger, filter, convolution kernel, accumulator, adder, subtracter and delay unit.

In this embodiment, the first functional operator module and the second functional operator module may be formed by any one or more operators of a multiplier, a trigger, a filter, a convolution kernel, an accumulator, an adder, a subtractor, and a delay unit, and the third functional operator module may be any one operator of a multiplier, a trigger, a filter, a convolution kernel, an accumulator, an adder, a subtractor, and a delay unit.

It should be noted that the first functional operator module, the second functional operator module and the third functional operator module in the present application are obtained by performing statistics on operators required by different algorithms and combining the operators according to operator use probabilities, where the statistics are obtained based on the control, operation and model requirements of all vehicle-mounted devices.

In addition, in this embodiment, the FPGA includes at least one of the functional modules 20, and the functional modules 20 are all connected to the switch matrix module. The number of functional modules 20 in the FPGA can be determined according to the size of the FPGA and the complexity of the algorithm it needs to implement.

According to the FPGA-based intelligent control system, the first function operator module, the second function operator module, the third function operator module and the plurality of switching matrixes are arranged in the function module 20 in the FPGA, the first function operator module and the second function operator module respectively comprise the plurality of operator modules, each operator module in the first function operator module is connected with one switching matrix, each operator module in the second function operator module is connected with two adjacent switching matrixes, the third function operator is connected with each switching matrix, a general algorithm can be realized in the FPGA, a complex high-performance complete algorithm can be realized, the relative position between the switching matrix and each operator module is fixed, the unification of time sequence and logic in the function module 20 is ensured, in addition, the situation that the FPGA is subjected to complete flow design again is avoided, and the flexibility of the FPGA is improved.

In some embodiments, the functional operator module and the switch matrix module are configured by a configuration module. Specifically, the connection between each of the first functional operator module and the second functional operator module and each of the switching matrices in the switching matrix module may be configured by a configuration module, so that a specific function can be implemented in the functional module 20.

Meanwhile, the input end of the switching matrix can be connected with the input end or the output end of each operator module, the output end of the switching matrix can also be connected with the input end or the output end of each operator module, and the specific connection mode can be connected and configured by adopting a configuration module according to practical application.

It can be understood that the input and output ends of each operator module are connected to the corresponding switch matrix, and the switch matrix is configured by the configuration module, so that signals can be input to the operator module, and output signals can be received from the operator module, and also signals can be input to the operator module, and output signals can be received from the operator module.

In some embodiments, as shown in fig. 2, the switch matrix module includes a first switch matrix, a second switch matrix, a third switch matrix, and a fourth switch matrix; the first functional operator module comprises a first operator module, a second operator module, a third operator module and a fourth operator module, and the second functional operator module comprises a fifth operator module, a sixth operator module, a seventh operator module and an eighth operator module; wherein the first switching matrix is connected to the second switching matrix, the third switching matrix, the first operator module, the fifth operator module, the sixth operator module, and the third functional operator module, respectively; the second switching matrix is respectively connected with the second operator module, the fifth operator module, the seventh operator module and the third functional operator module; the third switching matrix is respectively connected with the third operator module, the sixth operator module, the eighth operator module and the third functional operator module; the fourth switching matrix is connected to the second switching matrix, the third switching matrix, the fourth operator module, the seventh operator module, the eighth operator module, and the third functional operator module, respectively.

Specifically, the first operator module, the second operator module, the third operator module, and the fourth operator module may be any one of a multiplier, a trigger, a filter, a convolution kernel, an accumulator, an adder, a subtractor, and a delay unit, and the fifth operator module, the sixth operator module, the seventh operator module, and the eighth operator module may be any one of a multiplier, a trigger, a filter, a convolution kernel, an accumulator, an adder, a subtractor, and a delay unit, or multiple operators.

In some embodiments, as shown in fig. 3, the switch matrix module further comprises a fifth switch matrix, a sixth switch matrix, a seventh switch matrix, and an eighth switch matrix, the fifth operator module comprises a first operator and a second operator, the sixth operator module comprises a third operator and a fourth operator, the seventh operator module comprises a fifth operator and a sixth operator, and the eighth operator module comprises a seventh operator and an eighth operator; wherein the first operator is connected to the first switching matrix and the fifth switching matrix respectively; the second operator is respectively connected with the second switching matrix and the fifth switching matrix; the third operator is respectively connected with the first switching matrix and the sixth switching matrix; the fourth operator is respectively connected with the fourth switching matrix and the sixth switching matrix; the fifth operator is respectively connected with the second switching matrix and the seventh switching matrix; the sixth operator is respectively connected with the fourth switching matrix and the seventh switching matrix; the seventh operator is respectively connected with the third switching matrix and the eighth switching matrix; the seventh operator is respectively connected with the fourth switching matrix and the eighth switching matrix; the third functional operator module is connected to the first switching matrix, the second switching matrix, the third switching matrix, the fourth switching matrix, the fifth switching matrix, the sixth switching matrix, the seventh switching matrix, and the eighth switching matrix, respectively; the fifth switching matrix is respectively connected with the first switching matrix and the second switching matrix; the sixth switching matrix is respectively connected with the first switching matrix and the third switching matrix; the seventh switching matrix is respectively connected with the second switching matrix and the fourth switching matrix; and the eighth switching matrix is respectively connected with the third switching matrix and the fourth switching matrix.

Specifically, the first operator module, the second operator module, the third operator module, and the fourth operator module may be any one of a multiplier, a trigger, a filter, a convolution kernel, an accumulator, an adder, a subtractor, and a delay unit, and the first operator, the second operator, the third operator, the fourth operator, the fifth operator, the sixth operator, the seventh operator, and the eighth operator may be any one or more of a multiplier, a trigger, a filter, a convolution kernel, an accumulator, an adder, a subtractor, and a delay unit.

In some embodiments, the switch matrix module receives at least one input signal input from the outside through the communication interface 10; the switching matrix module outputs at least one output signal to the outside through the communication interface 10. One or more input signals may be input to the switching matrix module from the outside of the FPGA, and after performing logic operation in the functional module 20, one or more output signals may be output through the switching matrix.

Specifically, when the switching matrix module receives an input signal input from the outside through the communication interface 10 and outputs an output signal to the outside, as shown in fig. 4, the input signal Iin may be input to the first operator module through the first switching matrix for processing, after the input signal Iin is processed by the first operator module, the input signal Iin may be input to the second functional operator module through the first switching matrix for processing, after the input signal Iin is processed by the second functional operator module, the input signal Iin may be input to the seventh operator module through the fourth switching matrix for processing, and after the processing in the seventh operator module is completed, the generated signal Iout may be input to the external chip through the fourth switching matrix.

When the switching matrix module receives one path of input signals input by the external chip through the communication interface 10 and outputs a plurality of paths of output signals to the external chip, as shown in fig. 5, the input signals Iin may be input to the sixth operator module through the first switching matrix for processing, the sixth operator module may process the input signals Iin to generate two paths of signals, one path of signals may be input to the fifth operator module through the first switching matrix for processing, the fifth operator module may input to the second operator module through the second switching matrix for processing after processing is completed, the second operator module may input the generated signals Iout1 to the external chip through the second switching matrix and the fourth switching matrix in sequence after processing is completed, the other path of signals may be input to the eighth operator module through the third switching matrix and the fourth switching matrix in sequence, and the eighth operator module may input the generated signals Iout2 to the external chip through the fourth switching matrix after processing is completed.

When the switching matrix module receives a plurality of input signals input by an external chip through the communication interface 10 and outputs a plurality of output signals to the external chip, as shown in fig. 6, an input signal Iin1 may be input into a first operator module through a first switching matrix, the first operator module may input the input signal Iin1 into a fifth operator module through the first switching matrix after processing, the fifth operator module may input into a second functional operator module through the first switching matrix after processing, after second functional processing is completed, two signals may be generated, one signal may be input into a third operator module through the second switching matrix, the first switching matrix and the third switching matrix respectively, after processing by the third operator module is completed, the generated signal Iout2 may be input into the external chip through the third switching matrix and the fourth switching matrix respectively, the other signal may be input into the second operator module through the second switching matrix for processing, and after processing by the second operator module, the generated signal Iout3 may be input into the external chip through the second switching matrix and the fourth switching matrix respectively; the input signal Iin1 may also be input to a fifth operator module through the first switching matrix, the fifth operator module may input the input signal Iin1 into the fifth operator module again through the first switching matrix after processing, the fifth operator module may input the input signal Iin into the second functional operator module through the first switching matrix after processing, the second functional operator module may input the input signal Iin into the seventh operator module through the fourth switching matrix after processing, meanwhile, the input signal Iin2 may be input into the fourth operator module through the first switching matrix, the third switching matrix, and the fourth switching matrix respectively for processing, the fourth operator module processes the input signal Iin2 and also inputs the same into the seventh operator module through the fourth switching matrix, the seventh operator module processes a signal generated by the input signal Iin1 and a signal generated by the input signal Iin2, and may input a generated signal Iout4 into an external chip through the fourth matrix; similarly, the input signal Iin1 may be input to the sixth operator module through the first switching matrix and processed in the sixth operator module, and after the processing in the sixth operator module is completed, the generated signal Iout1 may be input to the external chip through the third switching matrix and the fourth switching matrix, respectively.

In some embodiments, an embodiment of the present invention further provides a data processing method, where the field programmable gate array circuit includes: a communication interface 10; at least one functional module 20, said functional module 20 comprising a plurality of functional operator modules and a switching matrix module, said switching matrix module comprising a plurality of switching matrices; one or more switching matrixes are connected between any two functional operator modules; the communication interface 10 is directly or indirectly connected to at least part of the switching matrix.

As shown in fig. 7, the data processing method includes:

s110, receiving an externally input signal to be processed according to the communication interface 10;

s120, the functional module 20 obtains a target signal and executes the target logic operation to obtain a first processing result of the target signal; the target signal is the signal to be processed or a signal obtained based on the signal to be processed;

s130, the communication interface 10 outputs the first processing result or a second processing result obtained based on the first processing result.

Specifically, before the FPGA circuit provided in the present application is used to process data, the function operator module needs to be selected according to a specific application scenario and a specific function implemented by the application scenario, and meanwhile, the function operator and the switching matrix module are connected and configured according to the configuration module, so that when the communication interface 10 receives a signal to be processed input by an external chip, the function module 20 in the FPGA circuit can perform corresponding logical operation, thereby obtaining a processing result of the signal to be processed, and can be output to the outside of the FPGA through the switching matrix and the communication interface 10 in sequence.

In some embodiments, as shown in fig. 8, the present application further provides a circuit design method, comprising:

s210, designing a circuit on a target circuit board into the field programmable gate array circuit;

s220, determining a first target logic operation to be performed by the functional module 20 according to a first target signal; the first target logical operation comprises N sub-logical operations, N functional operator modules of the plurality of functional operator modules being capable of performing the N sub-logical operations, respectively;

s230, configuring the switching matrix module, and configuring the communication links of the connection ends of the N functional operator modules as a processing procedure capable of executing the first target logic operation on the first target signal.

Specifically, the first target signal is a signal that the function module 20 needs to perform the target logical operation, the number and the type of the function operator modules can be determined by the first target signal, and meanwhile, the required function operator modules are connected by the switching matrix in the switching matrix module, so that the signal that each function operator module needs to process can enter the corresponding function operator module through the switching matrix to perform the corresponding logical operation, thereby implementing that the function module 20 performs the first target logical operation on the first target signal.

In some embodiments, when the function module 20 needs to perform the second target logical operation on the second target signal, after M sub-logical operations required for the second target logical operation are determined, M functional operator modules required for the M sub-logical operations are determined in the function module 20 to be capable of performing each sub-logical operation in the second target logical operation, and then the communication links of the connection ends of the functional operator modules are configured to be capable of performing the second target logical operation on the second target signal through the switching matrix in the switching matrix module, so that the functional operator modules perform the second target logical operation on the second target signal.

It can be understood that, no matter the functional module 20 performs the first target logical operation on the first target signal or performs the second target logical operation on the second target signal, it only needs to design the circuit on the target circuit board as the field programmable gate array circuit provided in the present application in advance, then determine the sub-logical operation required by the corresponding target logical operation, and determine the functional operator module for processing each sub-logical operation in the functional module 20, and configure the communication link of the connection end of each functional operator module to be capable of performing the corresponding target logical operation on each target signal through the switching matrix in the switching matrix module.

It should be noted that the first target signal and the second target signal are only some specific embodiments illustrated in the present application, and in the present application, the functional module 20 may further perform a third target logic operation on a third target signal, or perform a fourth target logic operation on a fourth target signal, and the like, and the functional module 20 may select a target logic operation corresponding to each target signal according to an actual application, and the present embodiment is not limited specifically.

In some embodiments, as shown in fig. 9, step S210 includes steps S211 and S212.

S211, acquiring operator demand information, wherein the operator demand information is used for expressing the quantity requirements of various functional operator modules;

s212, according to the operator requirement information, designing a circuit on the circuit board into the field programmable gate array circuit.

Specifically, the operator demand information can be determined according to an application scenario in which the FPGA circuit is located, and is obtained by combining the use probabilities of the operators in the application scenario used by the FPGA circuit. For example, in a vehicle-mounted application scene, the use probability of each operator in vehicle-mounted application can be counted through the control, operation and model requirements of all vehicle-mounted devices to determine the requirement information of the operator, so that the number requirement of various functional operator modules in the FPGA circuit is determined to complete the design of the FPGA circuit.

The FPGA circuit designed by the method is designed based on the application scene where the FPGA circuit is located, the FPGA circuit can realize a general algorithm in the corresponding application scene, the FPGA circuit does not need to be repeatedly designed in the same application scene for a complete flow, and the flexibility of the FPGA can be greatly improved.

While the invention has been described with reference to specific embodiments, the invention is not limited thereto, and various equivalent modifications and substitutions can be easily made by those skilled in the art within the technical scope of the invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (10)

1. A field programmable gate array circuit, comprising:

a communication interface;

at least one functional module comprising a plurality of functional operator modules and a switching matrix module, the switching matrix module comprising a plurality of switching matrices; one or more switching matrixes are connected between any two functional operator modules; the communication interface is directly or indirectly connected to at least a part of the switching matrix.

2. The field programmable gate array circuit according to claim 1, wherein the plurality of functional operator modules comprises a first functional operator module, a second functional operator module, and a third functional operator module, wherein the first functional operator module and the second functional operator module each comprise a plurality of operator modules, wherein two adjacent switching matrices are connected, wherein each operator module of the first functional operator module is connected to one switching matrix, wherein each operator module of the second functional operator module is connected to two adjacent switching matrices, and wherein the third functional operator module is connected to each switching matrix.

3. The field programmable gate array circuit of claim 1, wherein the switch matrix module comprises a first switch matrix, a second switch matrix, a third switch matrix, and a fourth switch matrix; the first functional operator module comprises a first operator module, a second operator module, a third operator module and a fourth operator module, and the second functional operator module comprises a fifth operator module, a sixth operator module, a seventh operator module and an eighth operator module;

wherein the first switching matrix is connected to the second switching matrix, the third switching matrix, the first operator module, the fifth operator module, the sixth operator module, and the third functional operator module, respectively;

the second switching matrix is respectively connected with the second operator module, the fifth operator module, the seventh operator module and the third functional operator module;

the third switching matrix is respectively connected with the third operator module, the sixth operator module, the eighth operator module and the third functional operator module;

the fourth switching matrix is connected to the second switching matrix, the third switching matrix, the fourth operator module, the seventh operator module, the eighth operator module, and the third functional operator module, respectively.

4. The field programmable gate array circuit according to claim 3, wherein the switching matrix module further comprises a fifth switching matrix, a sixth switching matrix, a seventh switching matrix, and an eighth switching matrix, the fifth operator module comprising the first operator and the second operator, the sixth operator module comprising the third operator and the fourth operator, the seventh operator module comprising the fifth operator and the sixth operator, the eighth operator module comprising the seventh operator and the eighth operator;

wherein the first operator is connected to the first switching matrix and the fifth switching matrix respectively;

the second operator is respectively connected with the second switching matrix and the fifth switching matrix;

the third operator is respectively connected with the first switching matrix and the sixth switching matrix;

the fourth operator is respectively connected with the fourth switching matrix and the sixth switching matrix;

the fifth operator is respectively connected with the second switching matrix and the seventh switching matrix;

the sixth operator is respectively connected with the fourth switching matrix and the seventh switching matrix;

the seventh operator is respectively connected with the third switching matrix and the eighth switching matrix;

the seventh operator is respectively connected with the fourth switching matrix and the eighth switching matrix;

the third functional operator module is respectively connected with the first switching matrix, the second switching matrix, the third switching matrix, the fourth switching matrix, the fifth switching matrix, the sixth switching matrix, the seventh switching matrix and the eighth switching matrix;

the fifth switching matrix is respectively connected with the first switching matrix and the second switching matrix;

the sixth switching matrix is respectively connected with the first switching matrix and the third switching matrix;

the seventh switching matrix is respectively connected with the second switching matrix and the fourth switching matrix;

and the eighth switching matrix is respectively connected with the third switching matrix and the fourth switching matrix.

5. The field programmable gate array circuit according to claim 1, wherein the functional operator module comprises at least one of: multiplier, trigger, filter, convolution kernel, accumulator, adder, subtracter and delay unit.

6. The FPGA circuit of claim 1, wherein the switch matrix module receives at least one input signal inputted from outside through the communication interface; and the switching matrix module outputs at least one path of output signal to the outside through the communication interface.

7. The fpga circuit of any one of claims 1 to 6, wherein said functional module is configured to perform a target logical operation on a target signal input to said functional module, said target logical operation comprises N sub logical operations, N functional operator modules in said functional module respectively perform said N sub logical operations, and said switching matrix module is configured to configure the communication links of the connection ends of said N functional operator modules to perform said target logical operation on said target signal.

8. A data processing method applied to the field programmable gate array circuit of claim 7;

the data processing method comprises the following steps:

the communication interface receives an externally input signal to be processed;

the functional module acquires a target signal and executes the target logic operation to obtain a first processing result of the target signal; the target signal is the signal to be processed or a signal obtained based on the signal to be processed;

the communication interface outputs the first processing result or a second processing result obtained based on the first processing result.

9. A method of designing a circuit, comprising:

designing the circuitry on the target circuit board as the field programmable gate array circuitry of any one of claims 1 to 6;

determining a first target logic operation aiming at a first target signal, which is required to be executed by the functional module; the first target logical operation comprises N sub-logical operations, and N functional operator modules in the plurality of functional operator modules are capable of executing the N sub-logical operations respectively;

configuring, by configuring the switch matrix module, the communication links of the connection ends of the N functional operator modules as a processing procedure capable of executing the first target logical operation on the first target signal.

10. The circuit design method according to claim 9, wherein the designing the circuit on the target circuit board as the field programmable gate array circuit according to any one of claims 1 to 6 comprises:

acquiring operator demand information, wherein the operator demand information is used for expressing the quantity requirements of various functional operator modules;

according to the operator requirement information, designing a circuit on the circuit board into the field programmable gate array circuit of any one of claims 1 to 6.

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