CN115877619A - Array substrate, array substrate motherboard and display device - Google Patents

Abstract

An array substrate, comprising: the circuit board comprises a substrate base plate, at least one first routing wire and at least one second routing wire. The substrate base plate includes: a display area and a first peripheral area located at one side of the display area. The first peripheral region includes at least: a first wiring area and a first binding area; the first wiring area is located on one side, close to the edge of the array substrate, of the first binding area. The at least one first routing wire and the at least one second routing wire are located in the first routing area. The orthographic projection of the first routing wire on the substrate base plate is overlapped with the orthographic projection of the second routing wire on the substrate base plate. Each first trace includes: at least two sub-traces. Two sub-wires in each first wire are electrically connected through at least one first connecting electrode. The first connecting electrode is made of transparent conductive material.

Description

Array substrate, array substrate motherboard and display device

Technical Field

The present disclosure relates to but not limited to the field of display technologies, and in particular, to an array substrate, an array substrate motherboard and a display device.

Background

The liquid crystal display device has the advantages of low power consumption, no radiation and the like. A liquid crystal display device generally includes a liquid crystal panel including an array substrate, a color filter substrate, and a liquid crystal layer interposed therebetween.

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

The embodiment of the disclosure provides an array substrate, an array substrate motherboard and a display device.

In one aspect, an embodiment of the present disclosure provides an array substrate, including: the circuit board comprises a substrate base plate, at least one first wire and at least one second wire. The substrate base plate includes: a display area and a first peripheral area located at one side of the display area. The first peripheral region includes at least: the device comprises a first wiring area and a first binding area; the first wiring area is located on one side, close to the edge of the array substrate, of the first binding area. The at least one first routing wire and the at least one second routing wire are located in the first routing area. The orthographic projection of the first routing wires on the substrate base plate is overlapped with the orthographic projection of the second routing wires on the substrate base plate. Each first trace includes: at least two sub-traces. Two sub-wires in each first wire are electrically connected through at least one first connecting electrode. The first connecting electrode is made of transparent conductive material.

In some exemplary embodiments, an orthographic projection of the first connecting electrode on the substrate base does not overlap with an orthographic projection of the second routing wire on the substrate base.

In some exemplary embodiments, the second trace is made of a metal material, and an orthographic projection of the first connection electrode on the substrate is located on a side, away from the first binding region, of the orthographic projection of the second trace on the substrate.

In some exemplary embodiments, the second trace is made of a transparent conductive material.

In some exemplary embodiments, the first trace includes: the first sub-wiring and the second sub-wiring are electrically connected through two first connecting electrodes. The first sub-trace is provided with a first main body, and a first protrusion and a second protrusion which protrude from the first main body towards one side of the second sub-trace. The second sub-trace is provided with a second main body, and a third projecting part and a fourth projecting part which project from the second main body towards one side of the first sub-trace. The first protrusion and the third protrusion are electrically connected through one first connection electrode, and the second protrusion and the fourth protrusion are electrically connected through the other first connection electrode. The two first connecting electrodes do not overlap in an orthographic projection of the substrate base plate.

In some exemplary embodiments, the first trace includes: the first sub-wiring and the second sub-wiring are electrically connected through one first connecting electrode, and the second sub-wiring and the third sub-wiring are electrically connected through the other first connecting electrode.

In some exemplary embodiments, the plurality of first connection electrodes connected to different first traces are aligned in the second direction.

In some exemplary embodiments, the first bonding area is provided with at least one third trace, and the at least one first trace and the at least one third trace are electrically connected through at least one second connection electrode; the second connecting electrode is made of transparent conductive materials.

In some exemplary embodiments, the second connection electrode is located at a side of the first connection electrode away from the substrate base plate.

In some exemplary embodiments, the first bonding area further provides at least one first bonding pin, and the at least one third trace is electrically connected to the driver chip through the at least one first bonding pin.

In some exemplary embodiments, the first peripheral region further comprises: and the second wiring extends to the third binding region and is electrically connected with at least one third binding pin.

In some exemplary embodiments, the array substrate includes, in a direction perpendicular to the array substrate: the first conductive layer, the first insulating layer, the semiconductor layer, the first transparent conductive layer, the second insulating layer and the second transparent conductive layer are sequentially arranged on the substrate base plate. The sub-routing is positioned on the second conductive layer; the first connecting electrode is located on the first transparent conductive layer.

In some exemplary embodiments, the second trace is located on the first conductive layer or the second transparent conductive layer.

In some exemplary embodiments, the second insulating layer is provided with an isolation groove, an orthographic projection of the isolation groove on the substrate base plate overlaps with an orthographic projection of the first connecting electrode on the substrate base plate, and an orthographic projection of the isolation groove on the substrate base plate does not overlap with orthographic projections of the first routing wire and the second routing wire on the substrate base plate.

In another aspect, an embodiment of the present disclosure provides a display device including the array substrate as described above.

In another aspect, an embodiment of the present disclosure provides an array substrate motherboard, including: a plurality of array regions and a plurality of test electrode regions corresponding to the plurality of array regions one to one. Each array region includes: a display area and a first peripheral area located at one side of the display area. The first peripheral area at least comprises a first wiring area and a first binding area, and the first wiring area is positioned on one side of the first binding area, which is close to the test electrode area. At least one test electrode is located at the test electrode zone. The at least one first routing wire and the at least one second routing wire are located in the first routing area. The at least one second routing wire is electrically connected with the at least one test electrode of the test electrode area, and the at least one second routing wire extends from the first routing area to the first binding area. The orthographic projection of the first routing wire on the substrate base plate is overlapped with the orthographic projection of the second routing wire on the substrate base plate. Each second trace includes: at least two sub-traces. Two sub-wirings in each second wiring are electrically connected through at least one first connecting electrode. The first connecting electrode is made of transparent conductive material.

In some exemplary embodiments, the test electrode region is provided with a plurality of regularly arranged test electrodes, the first wire routing region is provided with a plurality of first wires, and the plurality of first wires are electrically connected with the plurality of test electrodes in a one-to-one correspondence manner.

Other aspects will be apparent upon reading and understanding the attached figures and detailed description.

Drawings

The accompanying drawings are included to provide a further understanding of the disclosed embodiments and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the example serve to explain the principles of the disclosure and not to limit the disclosure. The shapes and sizes of one or more of the elements in the drawings are not to be considered as true scale, but rather are merely intended to illustrate the present disclosure.

Fig. 1 is a schematic view of an array substrate according to at least one embodiment of the present disclosure;

fig. 2 is a schematic partial cross-sectional view of a display area of an array substrate according to at least one embodiment of the present disclosure;

FIG. 3 is a partial schematic view of the region S1 in FIG. 1;

FIG. 4 is a schematic partial cross-sectional view taken along line P-P' of FIG. 3;

FIG. 5 is a partially enlarged view of the first bonding area shown in FIG. 3;

FIG. 6 is a schematic partial cross-sectional view taken along line Q-Q' of FIG. 5;

fig. 7 is a partial schematic view of a motherboard of an array substrate according to at least one embodiment of the present disclosure;

FIG. 8 is another partial schematic view of the region S1 in FIG. 1;

FIG. 9 is an enlarged view of the region S2 in FIG. 8;

FIG. 10 is another partial schematic view of the region S1 in FIG. 1;

FIG. 11 is a schematic partial cross-sectional view taken along the line R-R' in FIG. 10;

FIG. 12 is another partial schematic view of the region S1 in FIG. 1;

FIG. 13 is a schematic view of a partial cross section taken along the direction V-V' in FIG. 12;

FIG. 14 is another partial schematic view of the region S1 in FIG. 1;

FIG. 15 is a schematic partial cross-sectional view taken along the line U-U' in FIG. 14;

fig. 16 is a schematic view of a display device according to at least one embodiment of the present disclosure.

Detailed Description

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Embodiments may be embodied in many different forms. One of ordinary skill in the art will readily recognize the fact that the manner and content can be modified into other forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited to the contents described in the following embodiments. The embodiments and features of the embodiments in the present disclosure may be arbitrarily combined with each other without conflict.

In the drawings, the size of one or more constituent elements, the thickness of layers, or regions may be exaggerated for clarity. Accordingly, one aspect of the disclosure is not necessarily limited to the dimensions, and the shapes and sizes of one or more components in the drawings are not to reflect a true scale. Further, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes, numerical values, and the like shown in the drawings.

The ordinal numbers such as "first", "second", "third", and the like in the present specification are provided for avoiding confusion among the constituent elements, and are not limited in number. "plurality" in this disclosure means two or more.

In this specification, for convenience, words such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicating orientations or positional relationships are used to explain positional relationships of constituent elements with reference to the drawings, only for convenience of description and simplification of description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the described directions of the constituent elements. Therefore, the words described in the specification are not limited to the words described in the specification, and may be replaced as appropriate.

In this specification, the terms "mounted," "connected," and "connected" are to be construed broadly unless otherwise explicitly specified or limited. For example, it may be a fixed connection, or a removable connection, or an integral connection; may be a mechanical connection, or a connection; either directly or indirectly through intervening components, or both may be interconnected. The meaning of the above terms in the present disclosure can be understood by those of ordinary skill in the art as appropriate.

In this specification, "electrically connected" includes a case where constituent elements are connected together by an element having some kind of electrical action. The "element having some kind of electrical function" is not particularly limited as long as it can transmit an electrical signal between connected components. Examples of the "element having a certain electric function" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having a plurality of functions, and the like.

In this specification, a transistor refers to an element including at least three terminals, i.e., a gate, a drain, and a source. The transistor has a channel region between a drain (a drain electrode terminal, a drain region, or a drain electrode) and a source (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain, the channel region, and the source. In this specification, a channel region refers to a region through which current mainly flows.

In this specification, the first pole may be a drain and the second pole may be a source, or the first pole may be a source and the second pole may be a drain. In the case where transistors of opposite polarities are used, or in the case where the direction of current flow during circuit operation changes, the functions of the "source" and the "drain" may be interchanged. Therefore, in this specification, "source" and "drain" may be interchanged with each other.

In the present specification, "parallel" means a state in which an angle formed by two straight lines is-10 ° or more and 10 ° or less, and therefore, includes a state in which the angle is-5 ° or more and 5 ° or less. The term "perpendicular" means a state in which an angle formed by two straight lines is 80 ° or more and 100 ° or less, and therefore includes a state in which an angle is 85 ° or more and 95 ° or less.

"about" and "approximately" in this disclosure refer to the situation where the limits are not strictly defined, allowing process and measurement error. In the present disclosure, "substantially the same" means that the numerical values are within 10% of each other.

Along with more and more attention on improving the self physical quality through the motion of people, the intelligent wearable product is more and more popular among people. Products are dressed to intelligence (for example, intelligent wrist-watch, bracelet etc.) not only possess traditional time prompt facility, have still integrateed functions such as alarm clock, the detection of shooing, rhythm of the heart, motion data statistics, motion state detection. Along with people's liking to intelligence wearing product, people not only require intelligence to dress the product and possess the function integration characteristics, still pay close attention to its outward appearance shape more and more. For example, smart watches are increasingly adopting a true circle design from a rounded design. However, the lower border of a smart wearable product of a true circle design is extremely narrowed, e.g., the width of the lower border is below about 2.5 millimeters (mm). Along with the narrowing of the lower frame, the test electrode of the display panel cannot be placed inside the display panel and can only be placed outside the display panel, so that the test wiring needs to cross over the cutting line of the display panel, the test wiring is exposed at the position of the cutting line, the test wiring exposed by the cutting line cannot be coated with glue, when the reliability high-temperature high-humidity test (for example, the temperature is 60 ℃ and the humidity is 90%), a fracture of the test wiring at the position of the cutting line is extremely easy to corrode, and water vapor enters the inside of the display panel along the test wiring, so that the internal wiring of the display panel is corroded.

An embodiment of the present disclosure provides an array substrate, including: the circuit board comprises a substrate base plate, at least one first routing wire and at least one second routing wire. The substrate base plate comprises a display area and a first peripheral area positioned on one side of the display area. The first peripheral region includes at least: the device comprises a first wiring area and a first binding area. The first wiring area is located on one side, close to the edge of the array substrate, of the first binding area. The at least one first routing wire and the at least one second routing wire are located in the first routing area. The orthographic projection of the first routing wire on the substrate base plate is overlapped with the orthographic projection of the second routing wire on the substrate base plate. Each first trace includes: at least two sub-traces. Two sub-wires in each first wire are electrically connected through at least one first connecting electrode. The first connecting electrode is made of transparent conductive material.

In some examples, the first trace is configured as a test trace that transmits a test signal and the second trace is configured as a ground connection line that transmits a ground signal. However, this embodiment is not limited to this.

The array substrate that this embodiment provided, the first connection electrode that adopts transparent conducting material carries out the wire jumper design to first walking the line, forms steam isolation channel, can avoid steam to get into array substrate inside from array substrate edge along first walking the line to improve the line corrosion conditions that exists in the high humidity test of reliance.

In some exemplary embodiments, an orthogonal projection of the first connecting electrode on the substrate base does not overlap an orthogonal projection of the second routing wire on the substrate base. The second wiring can be prevented from being burnt by the first connecting electrode due to overlarge wiring current of the second wiring when orthographic projections of the first connecting electrode and the second wiring are overlapped.

In some exemplary embodiments, the second wire is made of a metal material, and an orthographic projection of the first connecting electrode on the substrate base is located on a side, away from the first binding region, of the orthographic projection of the second wire on the substrate base. For example, the second trace may be located on a side of the first trace close to the substrate base plate. In this example, since the second wire is made of a metal material, the first connection electrode is disposed on one side of the second wire close to the edge of the array substrate to form a water vapor isolation channel, so that the second wire can be prevented from being corroded, and the corrosion of the wire in the reliability high-temperature high-humidity test can be improved.

In some exemplary embodiments, the second trace is made of a transparent conductive material. In some examples, the material of the second trace may be Indium Tin Oxide (ITO), and since the activity of ITO is low, corrosion does not easily occur in the reliability high temperature and high humidity test, and the corrosion of the trace existing in the reliability high temperature and high humidity test may be improved. For example, the second routing lines may be located at a side of the first connection electrodes and the first routing lines away from the substrate base plate. In this example, the orthographic projection of the first connecting electrode on the substrate base plate can be located on a side of the orthographic projection of the second wire on the substrate base plate, which is far away from the first bonding area, or a side close to the first bonding area. However, this embodiment is not limited to this.

In some exemplary embodiments, the first trace may include: the first sub-wiring and the second sub-wiring are electrically connected through two first connecting electrodes. The first sub-trace is provided with a first main body, a first protrusion part and a second protrusion part, wherein the first protrusion part and the second protrusion part protrude from the first main body towards one side of the second sub-trace. The second sub-trace is provided with a second main body, and a third protrusion and a fourth protrusion which protrude from the second main body towards one side of the first sub-trace. The first and third projecting portions are electrically connected by one first connection electrode, and the second and fourth projecting portions are electrically connected by the other first connection electrode. The two first connecting electrodes do not overlap in an orthographic projection of the substrate base plate. In this example, two parallel transmission channels are established between the first wires by the two first connection electrodes, which can reduce the risk of wire burnout.

In some exemplary embodiments, the first trace may include: the first sub-wiring and the second sub-wiring are electrically connected through one first connecting electrode, and the second sub-wiring and the third sub-wiring are electrically connected through the other first connecting electrode. In this example, two water vapor isolation channels may be formed in the second trace through the two first connection electrodes, so that water vapor may be further prevented from entering the array substrate along the first trace.

In some exemplary embodiments, the plurality of first connection electrodes connected to different first traces are aligned in the second direction. In this example, the plurality of first connection electrodes are continuously arranged along one direction, so that a water vapor blocking channel can be formed, and corrosion of the traces can be avoided.

In some exemplary embodiments, the first bonding area is provided with at least one third trace, and the at least one first trace and the at least one third trace are electrically connected through at least one second connection electrode. The second connecting electrode is made of transparent conductive material. In some examples, the second connection electrode may be located at a side of the first routing line and the third routing line away from the substrate. In this example, the second connection electrode is used to establish the jumper channels of the first trace and the third trace, so that water vapor can be further isolated, and the internal trace of the array substrate is prevented from being corroded.

In some exemplary embodiments, the first bonding area is further provided with at least one first bonding pin, and the at least one third trace is electrically connected to the driver chip through the at least one first bonding pin. In some examples, when the array substrate is not bound with the driver chip, the first trace may transmit a test signal to the third trace to implement a test on the array substrate. And after the array substrate is subjected to first routing cutting and is bound with the driving chip, transmitting a signal to the third routing through the driving chip.

In some exemplary embodiments, the first peripheral region further comprises: and the second binding area is positioned on one side of the first binding area, which is far away from the display area. The second binding area is provided with a plurality of third binding pins, and the second routing extends to the third binding area and is electrically connected with at least one third binding pin. For example, the third bonding pin electrically connected to the second trace is a ground pin.

In some exemplary embodiments, the array substrate includes, in a direction perpendicular to the array substrate: the semiconductor device comprises a first conducting layer, a first insulating layer, a semiconductor layer, a first transparent conducting layer, a second insulating layer and a second transparent conducting layer which are sequentially arranged on a substrate. The sub-wiring is positioned on the second conductive layer; the first connecting electrode is positioned on the first transparent conducting layer. In some examples, the second trace may be located on the first conductive layer or the second transparent conductive layer. However, this embodiment is not limited to this.

In some exemplary embodiments, the second insulating layer is provided with an isolation groove. The orthographic projection of the isolation groove on the substrate base plate is overlapped with the orthographic projection of the first connecting electrode on the substrate base plate, and the orthographic projection of the isolation groove on the substrate base plate is not overlapped with the orthographic projection of the first wiring and the second wiring on the substrate base plate. In this example, by forming the isolation trench in the second insulating layer, moisture can be better isolated from entering the inside of the array substrate.

The scheme of the present embodiment is illustrated by some examples below.

In some exemplary embodiments, the array substrate of the present embodiment may be an LCD array substrate. The liquid crystal layer is filled between the array substrate and the color film substrate after the array substrate and the color film substrate are oppositely arranged, so that an LCD display panel can be manufactured, the twisting of liquid crystal molecules is driven by an electric field, and light rays selectively pass through the liquid crystal layer to present images with different gray scales. An electric field for driving the liquid crystal molecules to twist is formed between the pixel electrode and the common electrode. In some examples, the pixel electrode and the common electrode may be both disposed on the array substrate, for example, the pixel electrode and the common electrode may be disposed in the same layer or in different layers. However, this embodiment is not limited to this.

Fig. 1 is a schematic view of an array substrate according to at least one embodiment of the present disclosure. In some exemplary embodiments, as shown in fig. 1, the array substrate includes: the display device includes a display area AA, a first peripheral area B1 located on a side of the display area AA, and a second peripheral area B2 located on a side of the display area AA away from the first peripheral area B1. For example, the first peripheral area B1 is located at one side of the display area AA along the second direction Y. The first peripheral area B1 is in communication with the second peripheral area B2 and surrounds the display area AA. In some examples, the display area AA may be circular or elliptical. The first and second peripheral areas B1 and B2 may form a circular ring or an elliptical ring surrounding the display area AA. However, this embodiment is not limited to this. For example, the display area AA may be rectangular or other shape.

In some exemplary embodiments, the display area AA is provided with a plurality of gate lines and a plurality of data lines, which may cross to define a plurality of sub-pixel areas, each of which is provided with a pixel electrode, a common electrode, and a pixel circuit connected to the pixel electrode. The pixel circuit may include at least one thin film transistor. For example, a drain electrode of the thin film transistor may be electrically connected to the pixel electrode, a source electrode may be electrically connected to the data line, and a gate electrode may be electrically connected to the gate line. The on-off of the thin film transistor is controlled by scanning signals transmitted by the grid lines, and pixel voltages transmitted by the data lines are output to the pixel electrodes through the driving circuit. The common electrode is connected to a common voltage line. An electric field for driving the liquid crystal molecules to deflect is formed between the pixel electrode and the common electrode, so that the display of a specific gray scale is realized.

Fig. 2 is a partial cross-sectional view of a display area according to at least one embodiment of the present disclosure. In some exemplary embodiments, as shown in fig. 2, in a direction perpendicular to the array substrate, the display area AA may include: the display device comprises a substrate base plate 10, a first conducting layer, a first insulating layer 11, a semiconductor layer, a first transparent conducting layer, a second insulating layer 12 and a second transparent conducting layer, wherein the first conducting layer, the first insulating layer 11, the semiconductor layer, the first transparent conducting layer, the second insulating layer 12 and the second transparent conducting layer are sequentially arranged on the substrate base plate 10. In some examples, the first conductive layer includes at least: a gate electrode 141 of a thin film transistor of the pixel circuit. The semiconductor layer includes at least: an active layer 142 of thin film transistors of the pixel circuit. The second conductive layer includes at least: a source electrode 143 and a drain electrode 144 of a thin film transistor of the pixel circuit. The first transparent conductive layer includes at least the pixel electrode 16, and the second transparent conductive layer includes at least the common electrode 18. The pixel electrode 16 is in direct contact with the drain electrode 144 of the thin film transistor of the pixel circuit. The common electrode 18 may have a plurality of slits.

In some exemplary embodiments, the substrate base plate 10 may be a transparent base, for example, a quartz base, a glass base, or an organic resin base. The first insulating layer 11 and the second insulating layer 12 may employ any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The first insulating layer 11 is also referred to as a Gate Insulator (GI) layer; the second insulating layer 12 is also referred to as passivation layer. The first conductive layer and the second conductive layer may employ a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single-layer structure, or a multi-layer composite structure, such as Ti/Al/Ti, or the like. The first transparent conductive layer and the second transparent conductive layer may be made of a transparent conductive material, for example, indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO). The semiconductor layer may be made of one or more materials such as amorphous indium gallium zinc Oxide (a-IGZO), zinc oxynitride (ZnON), indium Zinc Tin Oxide (IZTO), amorphous silicon (a-Si), polysilicon (p-Si), hexathiophene, and polythiophene, which means that the present disclosure is applicable to transistors manufactured based on Oxide (Oxide) technology, silicon technology, and organic technology.

In some exemplary embodiments, as shown in fig. 1, the first peripheral area B1 of the array substrate may be substantially symmetrical with respect to a center line O of the array substrate in the first direction X. The first direction X intersects the second direction Y, for example, the first direction X is perpendicular to the second direction Y. The first peripheral area B1 on the left side of the center line O will be described as an example.

Fig. 3 is a partial schematic view of the region S1 in fig. 1. In some exemplary embodiments, as shown in fig. 3, the first peripheral region B1 includes: a first routing area, a first bonding area B11 and a second bonding area B12. The second binding region B12 is located at a side of the first binding region B11 away from the display area AA. The first routing area is located on one side of the first bonding area B11 close to the edge E of the array substrate. The first bonding region B11 may be provided with a driver chip, and the second bonding region B12 may be connected to a Flexible Printed Circuit (FPC). In some examples, the driving chip may be configured to provide a data signal and to provide a control signal of the gate driving circuit. The FPC may be configured to provide driving signals, power signals, and the like required for a module test to a display panel subsequently assembled with the array substrate. However, this embodiment is not limited to this.

In some exemplary embodiments, as shown in fig. 3, the first routing area is provided with a plurality of first traces 21 (e.g., twelve first traces). The plurality of first routing lines 21 may be configured to provide test data signals, test switch signals, and test signals (e.g., test clock signals, test start signals, and test power signals, etc.) provided to the gate driving circuit. The plurality of first traces 21 extend from the edge E of the array substrate to the first bonding area B11 along the first direction X, and are electrically connected to the plurality of third traces 25 in the first bonding area B11 through the second connection electrode 26. For example, the first traces 21 and the third traces 25 can be electrically connected in a one-to-one correspondence. The third traces 25 extend from the first bonding area B11 to one side of the display area AA. For example, the third traces 25 may extend to the second peripheral region and be electrically connected to the gate driving circuit disposed in the second peripheral region. The plurality of third traces 25 may be configured to provide a clock signal, an initial signal, a power signal, and the like to the gate driving circuit. However, this embodiment is not limited to this.

In some exemplary embodiments, as shown in fig. 3, the first routing area is further provided with a second routing 23. The second trace 23 extends along the second direction Y at the first trace region. The extending direction of the second wire 23 intersects with the extending direction of the plurality of first wires 21. The orthographic projection of the second routing lines 23 on the substrate is overlapped with the orthographic projection of the first routing lines 21 on the substrate. In some examples, the plurality of first traces 21 are disposed at the same layer, and the second trace 23 is located at a side of the plurality of first traces 21 close to the substrate.

In some exemplary embodiments, as shown in fig. 3, a third connection electrode 24 is disposed on a side of the first routing area away from the bonding area B12 in the second direction Y. The third connection electrode 24 is positioned at a side of the first routing area adjacent to the display area. The third connection electrode 24 may include: and the first sub-connection electrode is electrically connected with the second sub-connection electrode. An orthographic projection of the first sub-connection electrode on the substrate base and an orthographic projection of the second sub-connection electrode on the substrate base may overlap, e.g., coincide. In some examples, the first sub-connection electrode may be located at the first conductive layer, and the second sub-connection electrode may be located at the second transparent conductive layer. The second insulating layer is provided with a first through hole K1, the first insulating layer and the second insulating layer in the first through hole K1 are removed, and the second sub-connecting electrode is electrically connected with the first sub-connecting electrode through the first through hole K1. In this example, one end of the second wire 23 is connected to the first connection electrode, and the other end passes through the plurality of first wires 21, extends to the second bonding region B12, and is electrically connected to one third bonding pin (e.g., a ground pin) of the second bonding region B12. In some examples, the second trace 23 and the first sub-connection electrode may be a unitary structure. However, the present embodiment is not limited to this.

In some exemplary embodiments, when the array substrate and the color filter substrate are set in a box-to-box manner, a conductive adhesive (e.g., a conductive silver adhesive) may be coated on the third connection electrode 24 of the array substrate so as to be electrically connected to the color filter substrate. The third connection electrode 24 and the second trace 23 may form a static electricity leading-out path, thereby performing a static electricity eliminating function.

Fig. 4 is a partial cross-sectional view taken along the direction P-P' in fig. 3. In some exemplary embodiments, one first trace 21 is taken as an example for illustration. As shown in fig. 3 and 4, one first trace 21 may include: a first sub-trace 211 and a second sub-trace 212. The first sub-trace 211 and the second sub-trace 212 can extend substantially along the first direction X. During the preparation process of the array substrate, the first sub-trace 211 is cut at the edge E of the array substrate. In the first routing area, the first sub-routing 211 and the second sub-routing 212 of the first routing 21 are electrically connected through the first connection electrode 22.

In some exemplary embodiments, as shown in fig. 4, the first sub-trace 211 and the second sub-trace 212 of one first trace 21 may be located at the second conductive layer, and the first connection electrode 22 may be located at the first transparent conductive layer. The second trace 23 may be located on the first conductive layer. In this example, the first connection electrode 22 is made of a transparent conductive material (e.g., ITO), and the first sub-line 211 and the second sub-line 212 are made of a metal material, so that the first connection electrode has low activity and is not easy to corrode in a high temperature and high humidity reliability test, and thus a moisture isolation channel can be established through the first connection electrode to prevent moisture from entering the inside of the array substrate through the first sub-line 211 to corrode the second sub-line 212. In this example, the first connection electrode is located on the first transparent conductive layer, and can be directly contacted with the second conductive layer so as to be electrically connected with the first trace without a punching process; moreover, short circuit with the second sub-connection electrode positioned on the second transparent conducting layer in the gluing process can be avoided.

In some exemplary embodiments, as shown in fig. 3 and 4, an orthogonal projection of the first connection electrode 22 on the base substrate does not overlap an orthogonal projection of the second routing line 23 on the base substrate. The orthographic projection of the first connecting electrode 22 on the substrate base plate is positioned on one side of the second wire 23 far away from the first binding area B11. In this example, the moisture isolation channel established by the first connection electrode 22 can prevent the second trace 23 from corroding. Moreover, the orthographic projections of the first connecting electrodes 22 and the second wires 23 on the substrate are not overlapped, so that the first connecting electrodes 22 can be prevented from being burnt when the current of the second wires 23 is too large.

In some exemplary embodiments, as shown in fig. 3, each of the first wirings 21 is connected to one of the first connection electrodes 22. The plurality of first connection electrodes 22 connected by the plurality of first wires 21 are sequentially arranged along the second direction Y, and the plurality of first connection electrodes 22 are aligned in the second direction Y. The arrangement direction of the plurality of first connection electrodes 22 is substantially parallel to the second direction Y. However, this embodiment is not limited to this.

In some exemplary embodiments, as shown in fig. 3, the length of the first connection electrode 22 in the first direction X may be greater than or equal to 20 micrometers and less than or equal to 200 micrometers. For example, the length of the first connection electrode 22 may be about 40um to 80um, e.g., 40um or 50um. However, this embodiment is not limited to this. In this example, since the first connection electrode is made of a transparent conductive material and the resistance of the transparent conductive material is relatively large, the situation that the first trace is burnt due to an excessively large resistance can be avoided by limiting the length of the first connection electrode 22, thereby being beneficial to improving the detection accuracy of the array substrate. In some examples, the lengths of the plurality of first connection electrodes 22 along the first direction X may be substantially the same, or partially the same, or different from each other. However, the present embodiment is not limited to this.

In some exemplary embodiments, as shown in fig. 3, the orthographic projection of the first connection electrode 22 on the substrate base plate may be rectangular. However, this embodiment is not limited to this. For example, the orthographic projection of the first connecting electrode on the substrate base plate may be waved or other shape.

Fig. 5 is a partially enlarged schematic view of the first bonding area shown in fig. 3. Fig. 6 is a partial cross-sectional view taken along the line Q-Q' in fig. 5.

In some exemplary embodiments, as shown in fig. 3 and 5, the first binding region B11 is provided with a plurality of first binding pins 31, and a plurality of second binding pins 33. The plurality of first bonding pins 31 are sequentially arranged along the first direction X, and the plurality of second bonding pins 33 are sequentially arranged along the first direction X. For example, the plurality of first bonding pins 31 are arranged in a row, and the plurality of second bonding pins 33 are arranged in a row. The plurality of second bonding pins 33 are located at a side of the first bonding pins 31 away from the display area. In some examples, the plurality of first bonding pins 31 are located on the second conductive layer, and the third trace 25 is electrically connected to at least one first bonding pin 31. For example, one third trace 25 may be electrically connected with two first bonding pins 31. The third wire 25 may be electrically connected with the driving chip through the first bonding pin 31. The plurality of second bonding pins 32 may have a double-layered structure, and the at least one second bonding pin 32 may include a first sub-pin located in the first conductive layer and a second sub-pin located in the second transparent conductive layer. The second bonding pin 32 may be electrically connected with the driving chip. The driver chip may provide gate driving signals (e.g., including clock signals, power signals, start signals, etc.) through the first and second bonding pins 31 and 32.

In some exemplary embodiments, as shown in fig. 3 and 5, the second sub-trace 212 of the first trace 21 extends to the first bonding area B11 and is electrically connected to the third trace 25 through the second connection electrode 26. The plurality of first traces 21 and the plurality of third traces 25 may be electrically connected in a one-to-one correspondence. For example, the first routing lines 21 extend along the first direction X, and the third routing lines 25 may extend along the second direction Y toward one side of the display area AA.

In some exemplary embodiments, as shown in fig. 6, the first trace 21 may be located on the second conductive layer, and the third trace 25 may be located on the first conductive layer. The second connection electrode 26 may be positioned at the second transparent conductive layer. One end of the second connection electrode 26 is electrically connected to the first trace 21 through a via hole formed in the second insulating layer 12, and the other end is electrically connected to the third trace 25 through a via hole formed in the second insulating layer 12 and the first insulating layer 11. In this example, the first routing wire and the third routing wire are subjected to jumper wire design through the second connecting electrode located on the second transparent conductive layer, so that water vapor invasion can be further prevented.

In some exemplary embodiments, as shown in fig. 3, the second bonding region B12 is provided with a plurality of third bonding pins 33. The plurality of third binding pins 33 are sequentially arranged along the first direction X, for example, the plurality of third binding pins 33 are arranged in a row. The second trace 23 may extend to the second bonding region B12 and be electrically connected to one of the third bonding pins 33 (e.g., a ground pin) to achieve grounding. The at least one third bonding pin 33 may have a double-layer structure, for example, the at least one third bonding pin may include a third sub-pin located in the first conductive layer and a fourth sub-pin located in the second transparent conductive layer, the third sub-pin is electrically connected to the fourth sub-pin, and an orthogonal projection of the third sub-pin on the substrate base overlaps an orthogonal projection of the fourth sub-pin on the substrate base. The third binding pin 33 may be electrically connected with the FPC.

Fig. 7 is a partial schematic view of a motherboard of an array substrate according to at least one embodiment of the present disclosure. In some exemplary embodiments, in the preparation process of the array substrate, an array substrate mother board is formed, and then a plurality of array substrates are obtained by cutting the array substrate mother board. In some examples, an array substrate motherboard includes: a plurality of array regions and a plurality of test electrode regions C1 corresponding to the plurality of array regions one to one. The array region may include: the display device comprises a display area and a first peripheral area positioned on one side of the display area, wherein the first peripheral area at least comprises a first wiring area and a first binding area, and the first wiring area is positioned on one side, close to a test electrode area C1, of a first binding area B11. After the array substrate mother board is prepared, the circuit of the array region is tested by using the test electrode region, and after the test is finished, the test electrode region C1 can be cut off according to a cutting line CT, so that the array substrate is obtained. In some examples, the array substrate may be electrically and optically tested using the test electrode regions, for example, to detect whether a pure color picture has poor display. However, the present embodiment is not limited to this.

In some exemplary embodiments, as shown in fig. 7, the test electrode region C1 is provided with a plurality of test electrodes 30. The plurality of test electrodes 30 may be regularly arranged. However, the present embodiment is not limited to this.

In some exemplary embodiments, as shown in fig. 7, a plurality of test electrodes 30 are connected to a plurality of first traces 21 in a one-to-one correspondence. The plurality of first routing lines 21 may extend from the first routing line region of the array region to the test electrode region C1 to be electrically connected with the test electrodes 30. In some examples, the test electrode 30 may be a double-layer structure. For example, the test electrode 30 may include a first sub-test electrode located at the second conductive layer and a second sub-test electrode located at the second transparent conductive layer. The first sub-test electrode and the second sub-test electrode can be electrically connected through a second via hole K2 formed in the second insulating layer. The orthographic projections of the first sub-test electrode and the second sub-test electrode on the substrate base plate can have an overlap, such as a coincidence. However, the present embodiment is not limited to this.

For the related description of the array region of the array substrate motherboard of the present embodiment, reference may be made to the description of the array substrate, and thus, the description thereof is omitted here.

Fig. 8 is another partial schematic view of the region S1 in fig. 1. Fig. 9 is an enlarged schematic view of the region S2 in fig. 8. Fig. 8 omits to illustrate the first binding region.

In some exemplary embodiments, as shown in fig. 8, the first routing area of the first peripheral area is provided with a second routing 23 and a plurality of first routing 21 (e.g., ten first routing). The at least one first trace 21 may include: a first sub-trace 211 and a second sub-trace 212. The first sub-trace 211 may be electrically connected with the second sub-trace 212 through two first connection electrodes. The orthographic projection of the first connecting electrode on the substrate base plate is not overlapped with the orthographic projection of the second wire 23 on the substrate base plate, and the first connecting electrode is positioned on one side of the second wire 23 far away from the first binding area B11, namely one side of the second wire 23 close to the edge E of the array base plate.

In some exemplary embodiments, as shown in fig. 9, the first sub-trace 211 includes a first main body 211c, a first protrusion 211a and a second protrusion 211b protruding from the first main body 211c toward the second sub-trace 212. First protrusion 211a and second protrusion 211b are not connected, i.e., there is a recess between first protrusion 211a and second protrusion 211b. The second sub-trace 212 includes a second main body 212c, a third protrusion 212a and a fourth protrusion 212b protruding from the second main body 212c toward the first sub-trace 211. Third projection 212a and fourth projection 212b are not connected, i.e., there is a recess between third projection 212a and fourth projection 212b. The first connection electrode 22a connects the first and third protrusions 211a and 212a, and the first connection electrode 22b connects the second and fourth protrusions 211b and 212b. In some examples, there is an overlap of an orthogonal projection of the first connection electrode 22a on the substrate base with an orthogonal projection of the first and third protrusions 211a and 212a on the substrate base, and an orthogonal projection of the first connection electrode 22b on the substrate base with an orthogonal projection of the second and fourth protrusions 211b and 212b on the substrate base. However, this embodiment is not limited to this. In this example, two parallel transmission channels are established in one first wire by using two first connection electrodes, so that the risk of burning the first connection electrodes can be reduced.

In some exemplary embodiments, as shown in fig. 8, some of the first traces (for example, seven first traces) may be arranged in a dual transmission channel design, and the remaining first traces (for example, three first traces) are arranged in a single transmission channel design. For example, a dual transmission channel design may be provided for the first trace transmitting a large current signal (e.g., a clock signal, a high voltage signal, etc.) to reduce the risk of burning the first connection electrode. However, this embodiment is not limited to this.

In some exemplary embodiments, as shown in fig. 8, the first routing line 21 may be located at the second conductive layer, the first connection electrode may be located at the first transparent conductive layer, and the second routing line 23 may be located at the first conductive layer. For the rest of the structure of the array substrate of this embodiment, reference may be made to the description of the foregoing embodiments, and therefore, the description thereof is omitted here.

Fig. 10 is another partial schematic view of the region S1 in fig. 1. Fig. 11 is a partial cross-sectional view taken along the direction R-R' in fig. 10. The first bonding region is omitted from fig. 10.

In some exemplary embodiments, as shown in fig. 10 and 11, the second trace 23 may be located on the second transparent conductive layer. The orthographic projection of the first connecting electrode 22a on the substrate base plate is positioned on one side of the second routing 23 close to the first binding area. In this example, the second wire 23 is located on the second transparent conductive layer, so that the situation that the first wire is burnt out due to excessive current when the second wire 23 transmits static electricity can be prevented. Moreover, because the second transparent conducting layer is made of transparent conducting materials, the activity of the transparent conducting materials is small, corrosion is not easy to occur in high-temperature and high-humidity reliability testing, and even if the first connecting electrode is arranged on one side, close to the first binding area, of the second wiring 23, water vapor can be prevented from entering the internal wiring. In other exemplary embodiments, an orthographic projection of the first connecting electrode on the substrate base may be located on a side of an orthographic projection of the second trace 23 on the substrate base, which is close to the first bonding area.

For the rest of the structure of the array substrate of this embodiment, reference may be made to the description of the foregoing embodiments, and therefore, the description thereof is omitted here.

Fig. 12 is another partial schematic view of the region S1 in fig. 1. Fig. 13 is a partial cross-sectional view taken along V-V' in fig. 12. The first bonding region is omitted from fig. 12.

In some exemplary embodiments, as shown in fig. 12 and 13, the first trace 21 may include: a first sub-trace 211, a second sub-trace 212 and a third sub-trace 213. The first sub-trace 211 and the second sub-trace 212 are electrically connected to each other through the first connection electrode 22a, and the second sub-trace 212 and the third sub-trace 213 are electrically connected to each other through the first connection electrode 22 b. The orthographic projection of the first connecting electrodes 22a and 22b on the substrate base does not overlap with the orthographic projection of the second wiring 23 on the substrate base, and is positioned on one side of the second wiring 23 close to the edge E of the array base. In this example, the second trace 23 may be located on the first conductive layer. The first routing line 21 may be located at the second conductive layer, and the first connection electrodes 22a and 22b may be located at the first transparent conductive layer.

In some exemplary embodiments, as shown in fig. 12, the plurality of first connection electrodes 22a are sequentially arranged in the second direction Y, and may not be misaligned in the first direction X, thereby forming the first moisture blocking channel. The plurality of first connection electrodes 22b are sequentially arranged in the second direction Y, and may not be misaligned in the first direction X, thereby forming a second moisture blocking passage. The second sub-trace 212 between the first moisture barrier channel and the second moisture barrier channel can act as a corrosion zone to better isolate moisture from entering the inner trace.

In other examples, the second trace 23 may be located on the second transparent conductive layer, and the first moisture blocking channel and the second moisture blocking channel may be located on two opposite sides of the second trace 23 in the first direction X, or may be located on one side of the second trace 23 close to the first bonding area. However, this embodiment is not limited to this.

For the rest of the structure of the array substrate of this embodiment, reference may be made to the description of the foregoing embodiments, and therefore, the description thereof is omitted.

Fig. 14 is another partial schematic view of the region S1 in fig. 1. Fig. 15 is a partial cross-sectional view taken along the direction U-U' in fig. 14. The first bonding region is omitted from fig. 14.

In some exemplary embodiments, as shown in fig. 14 and 15, the second insulating layer 12 is provided with an isolation groove OP. An orthogonal projection of the isolation groove OP on the base substrate overlaps an orthogonal projection of the first connection electrode 22 on the base substrate. The isolation groove OP may expose at least a portion of the first connection electrode 22. The orthographic projection of the isolation groove OP on the substrate base plate is not overlapped with the orthographic projection of the second routing line 23 and the first routing line 21 on the substrate base plate. In some examples, the isolation groove OP may be formed around an edge of the array substrate. In this example, by forming the isolation groove OP at the position of the first connection electrode 22, an isolation strip may be formed using the isolation groove OP, and the first sub-trace 211 is limited to one side of the isolation strip, thereby better isolating the ingress of moisture.

In some examples, the width of the isolation groove OP may be less than the length of the first connection electrode 22 in the first direction X, which is not covered by the second conductive layer.

For the rest of the structure of the array substrate of this embodiment, reference may be made to the description of the foregoing embodiments, and therefore, the description thereof is omitted here.

The present embodiment further provides an array substrate motherboard, including: the testing device comprises a plurality of array regions and a plurality of testing electrode regions which are in one-to-one correspondence with the array regions. Each array region includes: a display area and a first peripheral area located at one side of the display area. The first peripheral area at least comprises a first wiring area and a first binding area, and the first wiring area is positioned on one side of the first binding area, which is close to the test electrode area. At least one test electrode is located at the test electrode zone. The at least one first routing wire and the at least one second routing wire are located in the first routing area. The at least one first wire is electrically connected with the at least one test electrode of the test electrode area, and the at least one first wire extends from the first wire area to the first binding area. The orthographic projection of the first routing wire on the substrate base plate is overlapped with the orthographic projection of the second routing wire on the substrate base plate. Each first trace includes: at least two sub-traces. Two sub-wires in each first wire are electrically connected through at least one first connecting electrode. The first connecting electrode is made of transparent conductive material.

In some exemplary embodiments, the test electrode area is provided with a plurality of regularly arranged test electrodes, the first routing area is provided with a plurality of first routing lines, and the plurality of first routing lines are electrically connected with the plurality of test electrodes in a one-to-one correspondence manner.

For the related description of the array substrate motherboard of this embodiment, reference may be made to the description of the foregoing embodiments, and therefore, the description thereof is omitted.

An embodiment of the present disclosure also provides a display device, including the array substrate as described above.

Fig. 16 is a schematic structural diagram of a display device according to at least one embodiment of the present disclosure. In some exemplary embodiments, as shown in fig. 16, the display device may include: the liquid crystal display panel comprises an array substrate 61, a color filter substrate 62 and a liquid crystal layer 63 filled between the array substrate 61 and the color filter substrate 62, wherein the array substrate and the color filter substrate 62 are arranged oppositely. In some examples, the display device of the present embodiment may be a Fringe Field Switching (FFS) type or an Advanced-Super Dimension Switching (AD-SDS) type LCD display panel in which the pixel electrode and the common electrode are both disposed on the array substrate and are disposed in different layers. The structure of the array substrate 61 can refer to the structure of the array substrate of the above embodiments, and therefore, the description thereof is omitted. The color film substrate 62 may include a substrate, a color film layer disposed on the substrate, and an alignment layer disposed on a side of the color film layer away from the substrate. The color film layer can comprise a plurality of color film units with different colors and a black matrix positioned between the color film units. However, this embodiment is not limited to this.

In some examples, the display device may be any product or component having a display function, such as an LCD display panel, an OLED display panel, a mini-LED display panel, a micro-LED display panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, a vehicle-mounted display, a watch, a bracelet, and the like. However, this embodiment is not limited to this.

The drawings in this disclosure relate only to the structures to which this disclosure relates and other structures may be referred to in the general design. Without conflict, features of embodiments of the present disclosure, i.e., embodiments, may be combined with each other to arrive at new embodiments.

It will be understood by those skilled in the art that various modifications and equivalent arrangements may be made in the present disclosure without departing from the spirit and scope of the present disclosure, and the scope of the appended claims should be accorded the full scope of the disclosure.

Claims (17)

1. An array substrate, comprising:

a base substrate comprising: a display area and a first peripheral area located at one side of the display area; the first peripheral region includes at least: the device comprises a first wiring area and a first binding area; the first wiring area is positioned on one side, close to the edge of the array substrate, of the first binding area;

at least one first routing wire and at least one second routing wire are positioned in the first routing area; the orthographic projection of the first routing wire on the substrate base plate is overlapped with the orthographic projection of the second routing wire on the substrate base plate;

each of the first traces includes: at least two sub-traces; the two sub-wires in each first wire are electrically connected through at least one first connecting electrode; the first connecting electrode is made of transparent conductive materials.

2. The array substrate of claim 1, wherein an orthographic projection of the first connecting electrode on the substrate does not overlap with an orthographic projection of the second trace on the substrate.

3. The array substrate of claim 2, wherein the second trace is made of a metal material, and an orthographic projection of the first connecting electrode on the substrate is located on a side of the orthographic projection of the second trace on the substrate, which is far away from the first bonding area.

4. The array substrate of claim 2, wherein the second trace is made of a transparent conductive material.

5. The array substrate of claim 1, wherein the first trace comprises: the first sub-wiring and the second sub-wiring are electrically connected through two first connecting electrodes;

the first sub-trace is provided with a first main body, a first protrusion part and a second protrusion part, wherein the first protrusion part and the second protrusion part protrude from the first main body towards one side of the second sub-trace;

the second sub-trace is provided with a second main body, and a third convex part and a fourth convex part which are convex from the second main body to one side of the first sub-trace;

the first protrusion and the third protrusion are electrically connected by one first connection electrode, and the second protrusion and the fourth protrusion are electrically connected by the other first connection electrode;

the two first connecting electrodes do not overlap in an orthographic projection of the substrate base plate.

6. The array substrate of claim 1, wherein the first trace comprises: the first sub-wiring and the second sub-wiring are electrically connected through one first connecting electrode, and the second sub-wiring and the third sub-wiring are electrically connected through the other first connecting electrode.

7. The array substrate of claim 1, wherein a plurality of the first connecting electrodes connected to different ones of the first traces are aligned in a second direction.

8. The array substrate according to claim 1, wherein the first bonding area is provided with at least one third trace, and the at least one first trace and the at least one third trace are electrically connected through at least one second connection electrode; the second connecting electrode is made of transparent conductive materials.

9. The array substrate of claim 8, wherein the second connection electrode is located on a side of the first connection electrode away from the substrate base plate.

10. The array substrate of claim 8, wherein the first bonding area further comprises at least one first bonding pin, and the at least one third trace is electrically connected to the driving chip through the at least one first bonding pin.

11. The array substrate of claim 1, wherein the first peripheral region further comprises: and the second wiring extends to the third binding region and is electrically connected with at least one third binding pin.

12. The array substrate according to any one of claims 1 to 11, wherein in a direction perpendicular to the array substrate, the array substrate comprises: the first conducting layer, the first insulating layer, the semiconductor layer, the first transparent conducting layer, the second insulating layer and the second transparent conducting layer are sequentially arranged on the substrate;

the sub-routing is positioned on the second conductive layer; the first connecting electrode is positioned on the first transparent conducting layer.

13. The array substrate of claim 12, wherein the second trace is located on the first conductive layer or the second transparent conductive layer.

14. The array substrate of claim 12, wherein the second insulating layer is provided with an isolation groove, an orthographic projection of the isolation groove on the substrate base overlaps with an orthographic projection of the first connecting electrode on the substrate base, and an orthographic projection of the isolation groove on the substrate base does not overlap with an orthographic projection of the first trace and the second trace on the substrate base.

15. A display device comprising the array substrate according to any one of claims 1 to 14.

16. An array substrate motherboard, comprising:

the array structure comprises a plurality of array regions and a plurality of test electrode regions which are in one-to-one correspondence with the array regions;

each array region includes: the testing electrode area comprises a display area and a first peripheral area positioned on one side of the display area, wherein the first peripheral area at least comprises a first wiring area and a first binding area, and the first wiring area is positioned on one side, close to the testing electrode area, of the first binding area;

at least one test electrode located at the test electrode region;

the at least one first routing wire and the at least one second routing wire are positioned in the first routing area; the at least one first routing wire is electrically connected with at least one test electrode of the test electrode area, and the at least one first routing wire extends from the first routing area to the first binding area; the orthographic projection of the first routing wires on the substrate is overlapped with the orthographic projection of the second routing wires on the substrate;

each of the first traces includes: at least two sub-wires; the two sub-wires in each first wire are electrically connected through at least one first connecting electrode; the first connecting electrode is made of transparent conductive materials.

17. The array substrate motherboard of claim 16, wherein the test electrode area is provided with a plurality of regularly arranged test electrodes, the first wire area is provided with a plurality of first wires, and the plurality of first wires are electrically connected with the plurality of test electrodes in a one-to-one correspondence.

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