CN114335029A

CN114335029A - Array substrate, display panel and display device

Info

Publication number: CN114335029A
Application number: CN202210016332.3A
Authority: CN
Inventors: 崔容豪; 玄丽燕; 胡迎宾; 倪柳松; 赵策
Original assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Priority date: 2022-01-07
Filing date: 2022-01-07
Publication date: 2022-04-12

Abstract

The disclosure relates to the technical field of display, and discloses an array substrate, a display panel and a display device; the array substrate comprises a first driving thin film transistor, a second driving thin film transistor and a connecting wire; the first driving thin film transistor comprises a first active layer, wherein the first active layer comprises a first channel region, a first conductive region and a second conductive region, and the first conductive region and the second conductive region are positioned at two ends of the first channel region; the second driving thin film transistor comprises a second active layer, wherein the second active layer comprises a second channel region, a third conductive region and a fourth conductive region which are positioned at two ends of the second channel region; the connecting wire extends from the third conductive region to the first conductive region, and opposite ends thereof are connected to the third conductive region and the first conductive region, respectively. The array substrate reduces the area of a wiring area and improves the aperture opening ratio.

Description

Array substrate, display panel and display device

Technical Field

The disclosure relates to the technical field of display, in particular to an array substrate, a display panel and a display device.

Background

In order to increase the brightness of the display panel, it is necessary to ensure the aperture ratio of the display panel; in order to ensure the aperture ratio, the opaque area of the thin film transistor needs to be reduced; however, it is difficult to reduce the opaque region of the display panel to increase the aperture ratio.

It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The present disclosure is directed to overcome the disadvantage of low aperture ratio in the prior art, and provides an array substrate, a display panel and a display device with high aperture ratio.

According to an aspect of the present disclosure, there is provided an array substrate including:

a first driving thin film transistor including a first active layer, the first active layer including: a first channel region, and first and second conductibility regions located at both ends of the first channel region;

a second driving thin film transistor provided at one side of the first driving thin film transistor, the second driving thin film transistor including a second active layer, the second active layer including: a second channel region, and third and fourth conductive regions located at both ends of the second channel region;

and a connecting wire extending from the third conductive region to the first conductive region, and having opposite ends connected to the third conductive region and the first conductive region.

In one exemplary embodiment of the present disclosure, the connection wire is an extension of the third conductive region to the first driving thin film transistor side.

In an exemplary embodiment of the present disclosure, the array substrate further includes:

the power line is arranged on one side, away from the second driving thin film transistor, of the first driving thin film transistor and extends along a first direction, and the first conductive area is connected with the power line;

the first driving thin film transistor further includes: a first gate, a first source and a first drain, the first conductive region overlapping and connected to the first drain, the first drain connected to the power supply line, the second conductive region overlapping and connected to the first source, the first channel region overlapping and connected to the first gate;

the second driving thin film transistor further includes: a second gate and a second source, the fourth conductive region overlapping and connected to the second source, and the second channel region overlapping the second gate.

In an exemplary embodiment of the present disclosure, the connection wire and the first gate are disposed in the same material in the same layer.

the two data lines are arranged between the first driving thin film transistor and the second driving thin film transistor in parallel and extend along a first direction;

first and second switching thin film transistors including a third gate electrode, a third active layer, a third source electrode, and a third drain electrode, the third active layer including: a third channel region, and a fifth conductive region and a sixth conductive region located at both ends of the third channel region, the fifth conductive region overlapping and connected to the third source electrode, and the sixth conductive region overlapping and connected to the third drain electrode; the third source electrode of the first switch thin film transistor is overlapped and connected with the first grid electrode, the third source electrode of the second switch thin film transistor is overlapped and connected with the second grid electrode, and the two third drain electrodes are correspondingly connected with the two data lines;

and a gate line connected to the third gate electrode, the gate line extending in a second direction, the second direction intersecting the first direction.

In an exemplary embodiment of the present disclosure, the gate line includes:

a plurality of first portions provided in a double-line structure and extending in a second direction;

and a plurality of second portions arranged in a single-line structure and extending in a second direction, the second portions being connected between two adjacent first portions, and the third gate being a part of the second portions.

In an exemplary embodiment of the present disclosure, the first switching thin film transistor is disposed at the first direction side of the first driving thin film transistor, the second switching thin film transistor is disposed at the first direction side of the second driving thin film transistor, and the first switching thin film transistor and the second switching thin film transistor are located between the data line and the power line.

In an exemplary embodiment of the present disclosure, the first gate includes:

a first gate body portion disposed opposite to the first channel region;

the first grid electrode extension part is connected with the first grid electrode body part and is positioned on one side of the first grid electrode body part close to the data line;

the second gate includes:

a second gate body portion disposed opposite to the second channel region;

and the second grid electrode extension part is connected with the second grid electrode body part and is positioned on one side of the second grid electrode body part close to the data line.

In an exemplary embodiment of the present disclosure, an extending direction of the third active layer crosses an extending direction of the gate line, the third source electrode of the first switching thin film transistor overlaps and is connected to an end portion of the first gate extending portion near the data line, and the third source electrode of the second switching thin film transistor overlaps and is connected to an end portion of the second gate extending portion near the data line.

a first detection thin film transistor and a second detection thin film transistor, the first detection thin film transistor and the second detection thin film transistor including a fourth gate electrode, a fourth active layer, a fourth source electrode, and a fourth drain electrode, the fourth active layer including: a fourth channel region, and a seventh conductive region and an eighth conductive region located at two ends of the fourth channel region, wherein the seventh conductive region overlaps and is connected to the fourth source electrode, the eighth conductive region overlaps and is connected to the fourth drain electrode, the first detection thin film transistor is located at one side of the first driving thin film transistor, which is far away from the first switching thin film transistor, and the second detection thin film transistor is located at one side of the second driving thin film transistor, which is far away from the second switching thin film transistor;

the reference voltage line is arranged on one side of the second driving thin film transistor, which is far away from the first driving thin film transistor, and extends along the first direction;

the sensing control signal line is arranged on one side of the first driving thin film transistor, which is far away from the first switch thin film transistor, and extends along the second direction;

the reference connecting wire is arranged on one side of the sensing control signal wire, which is far away from the first driving thin film transistor, and is connected with the reference voltage wire;

wherein the fourth source of the first detecting thin film transistor is connected to the first source, the fourth source of the second detecting thin film transistor is connected to the second source, the fourth drain is connected to the reference voltage line through the reference connection wire, and the fourth gate is connected to the sensing control signal line.

In an exemplary embodiment of the present disclosure, the sensing control signal line includes:

a plurality of third portions provided in a double line structure and extending in the second direction;

and the fourth parts are arranged in a single-wire structure and extend along the second direction, the fourth parts are connected between two adjacent third parts, and the fourth grid is part of the fourth parts.

a first light shielding layer, wherein the first driving thin film transistor is overlapped with the first light shielding layer, and the first light shielding layer and the first grid electrode form a capacitor;

and the second light shielding layer is overlapped with the second driving thin film transistor, and the second light shielding layer and the second grid electrode form a capacitor.

In an exemplary embodiment of the present disclosure, the first light shielding layer, the second light shielding layer, and the reference connection wire are disposed in the same layer as a material; the first active layer, the second active layer, the third active layer and the fourth active layer are arranged in the same material in the same layer; the grid line, the sensing control signal line, the first grid electrode, the second grid electrode, the third grid electrode and the fourth grid electrode are arranged on the same layer of the same material; the first source electrode, the first drain electrode, the second source electrode, the third drain electrode, the fourth source electrode, the fourth drain electrode, the data line, the power line, and the reference voltage line are disposed in the same layer of material.

According to another aspect of the present disclosure, there is provided a display panel including: the array substrate as set forth in any one of the above.

According to still another aspect of the present disclosure, there is provided a display device including: the display panel is described above.

According to the array substrate, the connecting wires extend from the third conductive area to the first conductive area, and two opposite ends of the connecting wires are correspondingly connected with the third conductive area and the first conductive area; the third conductive region is directly connected with the first conductive region through a connecting wire, and wiring is not needed to be arranged on the side faces of the first driving thin film transistor and the second driving thin film transistor to connect the third conductive region with the first conductive region, so that the area of the wiring region of the array substrate is reduced, the aperture ratio of the array substrate is improved, and the display brightness is improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.

Fig. 1 is a schematic structural view of an array substrate in the related art.

Fig. 2 is a schematic structural diagram of a crossing of a second drain and a gate line in fig. 1.

Fig. 3 is a circuit configuration diagram of a driving circuit of one sub-pixel.

Fig. 4 is a schematic structural diagram of an exemplary embodiment of an array substrate according to the present disclosure.

Fig. 5 is a schematic structural diagram of the reference connection wire and the light-shielding layer in fig. 4.

Fig. 6 is a schematic structural diagram after an active layer is formed on the basis of fig. 5.

Fig. 7 is a schematic structural view after a gate electrode, a gate line, and the like are formed on the basis of fig. 6.

Fig. 8 is a schematic structural diagram of another exemplary embodiment of an array substrate according to the present disclosure.

Description of reference numerals:

1. a reference connection lead; 101. a connecting wire;

21. a first light-shielding layer; 22. a second light-shielding layer; 23. a third light-shielding layer; 24. a fourth light-shielding layer;

31. a first active layer; 311. a first channel region; 312. a first region of electrical conductivity; 313. a second region of electrical conductivity;

32. a second active layer; 321. a second channel region; 322. a third conductive region; 323. a fourth conductive region;

33. a third active layer; 331. a third channel region; 332. a fifth conductive region; 333. a sixth conductive region;

34. a fourth active layer; 341. a fourth channel region; 342. a seventh conductive region; 343. an eighth conductive region;

35. a fifth active layer; 351. a fifth channel region; 352. a ninth conductive region; 353. a tenth conductived region;

36. a sixth active layer; 361. a sixth channel region; 362. an eleventh conductive region; 363. a twelfth conductimetric region;

37. connecting a lead;

41. a first gate electrode; 411. a first gate body portion; 412. a first gate extension;

42. a second gate electrode; 421. a second gate body portion; 422. a second gate extension;

43. a third gate electrode; 44. a fourth gate electrode;

45. a fifth gate electrode; 451. a fifth gate body portion; 452. a fifth gate extension;

46. a sixth gate; 461. a sixth gate body portion; 462. a sixth gate extension;

47. a gate line; 471. a first portion; 472. a second portion;

48. a sensing control signal line; 481. a third portion; 482. a fourth part;

51. a first source electrode; 52. a first drain electrode; 53. a second source electrode; 54. a third source electrode; 55. a third drain electrode; 56. a fourth source electrode; 57. a fourth drain electrode; 58. a fifth source electrode; 59. a sixth source electrode; 60. a sixth drain electrode; 61. a power line; 62. a data line; 63. a reference voltage line; 64. a second drain electrode;

71. a first driving thin film transistor; 72. a second driving thin film transistor; 73. a third driving thin film transistor; 74. a fourth driving thin film transistor;

81. a first switching thin film transistor; 82. a second switching thin film transistor; 83. a third switching thin film transistor; 84. a fourth switching thin film transistor;

91. a first detection thin film transistor; 92. a second detection thin film transistor; 93. a third detection thin film transistor; 94. and a fourth detection thin film transistor.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted. Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the device of the icon were turned upside down, the element described as "upper" would become the element "lower". When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.

The terms "a," "an," "the," "said," and "at least one" are used to indicate the presence of one or more elements/components/parts/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.; the terms "first," "second," and "third," etc. are used merely as labels, and are not limiting on the number of their objects.

In the related art, a White Organic light emitting semiconductor (White Organic light emitting semiconductor) Display panel includes four sub-pixels to form a pixel unit, and thus, it is difficult to reduce an opaque region of the WOLED Display panel to increase an aperture ratio.

Referring to fig. 1, in the related art, the first conductive region 312 of the first driving thin film transistor 71 is directly connected to the power supply line 61, where direct connection means direct connection through a via hole on an insulating layer; the third conductive region 322 of the second driving thin film transistor 72 is connected to the connection line 101 through the second drain electrode 64, and is connected to the power line 61 through the connection line 101, and the second drain electrode 64 overlaps the gate line 47 and the data line 62 also overlaps the connection line 101. The connecting wires 101 increase the area of the wiring area of the array substrate, thereby reducing the aperture opening ratio of the array substrate and further reducing the display brightness; referring to fig. 2, an insulating layer is disposed between the second drain 64 and the gate line 47, and the gate line 47 has a relatively large thickness, so that the second drain 64 has a relatively small width at a portion where the second drain 64 overlaps the gate line 47, which is likely to cause short circuit of the second drain 64, and the insulating layer is relatively thin, which may cause short circuit between the second drain 64 and the gate line 47, thereby causing poor product quality.

It should be noted that the term "overlap" or "overlapping" as used herein means that there is an overlap or an overlap in the orthogonal projection on the substrate base plate.

The present disclosure example embodiments provide an array substrate, which, as shown in fig. 4, may include a first driving thin film transistor 71, a second driving thin film transistor 72, a connection wire, and a power (Vdd) line 61; the first driving thin film transistor 71 may include a first active layer 31, and the first active layer 31 may include a first channel region 311, and first and second conductive regions 312 and 313 at both ends of the first channel region 311; the second driving thin film transistor 72 is disposed at one side of the first driving thin film transistor 71, the second driving thin film transistor 72 may include a second active layer 32, the second active layer 32 may include a second channel region 321, and a third conductive region 322 and a fourth conductive region 323 located at both ends of the second channel region 321; a power supply (Vdd) line 61 is provided on a side of the first driving thin film transistor 71 away from the second driving thin film transistor 72 and extends in the first direction Y, and the first conductive region 312 is connected to the power supply line 61; the connecting wire 37 extends from the third conductive region 322 to the first conductive region 312, and opposite ends thereof are connected to the third conductive region 322 and the first conductive region 312, respectively.

In the array substrate of the present disclosure, the first driving thin film transistor 71 and the second driving thin film transistor 72 share one power line 61; in addition, the third conductive region 322 and the first conductive region 312 are directly connected through the connecting wire 37, and wiring on the side surfaces of the first driving thin film transistor 71 and the second driving thin film transistor 72 is not needed to connect the third conductive region 322 and the first conductive region 312, so that the area of the wiring region of the array substrate is reduced, the aperture ratio of the array substrate is improved, and the display brightness is improved.

The WOLED display panel includes four sub-pixels constituting a pixel unit, and as shown in fig. 3, the driving circuit of one sub-pixel may include three thin film transistors (a first driving thin film transistor 71, a first switching thin film transistor 81, and a first detecting thin film transistor 91) and a capacitor C, and the driving circuits of the four sub-pixels are a first driving circuit, a second driving circuit, a third driving circuit, and a fourth driving circuit, that is, the first driving circuit, the second driving circuit, the third driving circuit, and the fourth driving circuit constitute the driving circuit of the pixel unit. The first driving circuit, the second driving circuit, the third driving circuit and the fourth driving circuit are all disposed on the array substrate, and a pixel unit is taken as an example for description below.

Referring to fig. 4, the array substrate may further include a power line 61, a data line 62, a reference voltage line 63, a gate line 47, and a sensing control signal line 48.

The first driving circuit, the second driving circuit, the third driving circuit and the fourth driving circuit are sequentially arranged along the second direction X, wherein the first driving circuit and the second driving circuit are a first group, and the third driving circuit and the fourth driving circuit are a second group.

The Vdd (power) line 61, the data line 62, and the reference voltage line 63 all extend in a first direction Y, and the gate line 47 and the sensing control signal line 48 all extend in a second direction X, which intersects with the first direction Y, for example, the first direction Y and the second direction X may be perpendicular.

The power supply lines 61 are provided in two in one pixel unit, the two power supply lines 61 are provided on opposite sides of the second direction X of the driving circuits, the first driving circuit and the second driving circuit share one power supply line 61, and the third driving circuit and the fourth driving circuit share one power supply line 61.

The data lines 62 are arranged in four, two of the data lines 62 are arranged side by side between the first driving circuit and the second driving circuit, and the other two data lines 62 are arranged side by side between the third driving circuit and the fourth driving circuit.

The reference voltage line 63 is provided in one, and the reference voltage line 63 is provided between the second driving circuit and the third driving circuit.

The gate line 47 and the sensing control signal line 48 are disposed at opposite sides of the first direction Y of the driving circuit.

In the present example embodiment, the array substrate may include a substrate, and the first, second, third, and fourth driving circuits are disposed at one side of the substrate. The material of the substrate base plate may include an inorganic material, for example, the inorganic material may be glass, quartz, metal, or the like. The material of the base substrate may also include an organic material, and for example, the organic material may be a resin-based material such as polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate. The base substrate may be formed from a plurality of material layers, for example the base substrate may comprise a plurality of base layers, the material of which may be any of those described above. Of course, the base substrate may be provided as a single layer, and may be any one of the above materials.

In the present exemplary embodiment, as shown in fig. 4 and 5, a light-shielding layer is provided on one side of the base substrate, the light-shielding layer includes a first light-shielding layer 21, a second light-shielding layer 22, a third light-shielding layer 23, and a fourth light-shielding layer 24, and the light-shielding layer may be made of metal. The four light shielding layers are arranged along the second direction X. The light-shielding layer may also serve as one electrode of the capacitor C. The orthographic projections of the four driving thin film transistors on the substrate are correspondingly positioned in the orthographic projections of the four shading layers on the substrate. Light rays emitted into the active layer from the substrate can generate photon-generated carriers in the active layer, so that the characteristics of the driving thin film transistor are influenced, and the display image quality of the display device is influenced finally; the light rays emitted from the substrate can be shielded by the light shielding layer, so that the characteristics of the driving thin film transistor are prevented from being influenced, and the display image quality of the display device is prevented from being influenced.

The reference connecting wire 1 is further arranged on one side of the substrate, namely the reference connecting wire 1 and the shading layer are arranged on the same layer and made of the same material, namely the reference connecting wire 1 and the shading layer are formed through the same patterning process. The reference connection wire 1 extends along the second direction X, and the reference connection wire 1 is disposed on a side of the sensing control signal line 48 away from the first driving thin film transistor 71.

In the present exemplary embodiment, a buffer layer is disposed on a side of the light-shielding layer away from the substrate, the buffer layer plays a role of blocking moisture and impurity ions in the substrate (especially organic material) and also plays a role of increasing hydrogen ions for an active layer to be formed subsequently, and the buffer layer is made of an insulating material and can insulate and isolate the light-shielding layer from the active layer.

An active layer is disposed on a side of the buffer layer away from the substrate, and as shown in fig. 4 and 6, the active layer may include a connection wire 37, a first active layer 31, a second active layer 32, a third active layer 33, a fourth active layer 34, a fifth active layer 35, and a sixth active layer 36. That is, the connection wire 37, the first active layer 31, the second active layer 32, the third active layer 33, the fourth active layer 34, the fifth active layer 35 and the sixth active layer 36 are disposed in the same material, that is, the connection wire 37, the first active layer 31, the second active layer 32, the third active layer 33, the fourth active layer 34, the fifth active layer 35 and the sixth active layer 36 are formed through the same patterning process.

The third active layer 33 is provided with four, and the fourth active layer 34 is also provided with four. The first active layer 31, the second active layer 32, the fifth active layer 35, and the sixth active layer 36 are sequentially arranged in the first direction Y. Among them, the first active layer 31, one third active layer 33, and one fourth active layer 34 belong to a driving circuit of one sub-pixel, for example, a driving circuit of a white sub-pixel; the second active layer 32, one third active layer 33 and one fourth active layer 34 belong to a driving circuit of another sub-pixel, for example, a driving circuit of a red sub-pixel; the fifth active layer 35, one third active layer 33 and one fourth active layer 34 belong to a driving circuit of yet another sub-pixel, for example, a driving circuit of a green sub-pixel; the sixth active layer 36, one third active layer 33 and one fourth active layer 34 belong to a driving circuit of yet another sub-pixel, for example, a driving circuit of a blue sub-pixel.

The first active layer 31 may include a first channel region 311, and a first conductive region 312 and a second conductive region 313 at both ends of the first channel region 311. The first and second

conductive regions

312 and 313 are located at both ends of the first channel region 311 in the first direction Y. Specifically, the first active layer 31 may include a first rectangular region extending along the second direction X and a second rectangular region extending along the first direction Y, the second rectangular region being connected to a side of the first rectangular region adjacent to the gate line 47. The middle portion of the second rectangular region is a first channel region 311, the portion of the second rectangular region distant from the first rectangular region is a first conductive region 312, and the portion of the second rectangular region close to the first rectangular region and the first rectangular region constitute a second conductive region 313. The area of the second conductive region 313 is larger than the area of the first conductive region 312.

The second active layer 32 may include a second channel region 321, and a third conductive region 322 and a fourth conductive region 323 located at both ends of the second channel region 321. The third conductive region 322 and the fourth conductive region 323 are located at both ends of the second channel region 321 in the first direction Y. Specifically, the second active layer 32 may include a third rectangular region extending along the second direction X and a fourth rectangular region extending along the first direction Y. The fourth rectangular region is connected to a side of the third rectangular region adjacent to the gate line 47. The middle of the fourth rectangular area is a second channel area 321.

A portion of the fourth rectangular region distant from the third rectangular region is a third conductive region 322, and a portion of the fourth rectangular region close to the third rectangular region and the third rectangular region constitute a fourth conductive region 323. The area of the fourth conductive region 323 is larger than the area of the third conductive region 322.

The connecting wire 37 may be provided in an elongated shape, and the elongated shape is a linear shape, and the connecting wire 37 extends along the second direction X, extends from the third conductive region 322 to the first conductive region 312, and connects the third conductive region 322 with the first conductive region 312. The third conductive region 322, the connection wire 37, and the first conductive region 312 are connected together when they are formed, and the connection wire 37 is an extension of the third conductive region 322 toward the first driving thin film transistor 71, or the connection wire 37 is an extension of the first conductive region 312 toward the second driving thin film transistor 72. Of course, in other example embodiments of the present disclosure, the connection wire 37 is also provided in a curved shape as long as the body direction is extended from the third conductive region 322 to the first conductive region 312; furthermore, due to the arrangement of the position of the third conductive region 322 and the position of the first conductive region 312, the connecting wire 37 may also be arranged obliquely, i.e. the extending direction of the connecting wire 37 may form a set angle with the second direction X.

The fifth active layer 35 may include a fifth channel region 351, and ninth and tenth

conductive regions

352 and 353 located at both ends of the fifth channel region 351. The ninth and tenth

conductive regions

352 and 353 are located at both ends of the fifth channel region 351 in the first direction Y. Specifically, the fifth active layer 35 may include a fifth rectangular region extending along the second direction X and a sixth rectangular region extending along the first direction Y. The sixth rectangular region is connected to a side of the fifth rectangular region adjacent to the gate line 47. The middle of the sixth rectangular region is a fifth channel region 351.

A portion of the sixth rectangular region distant from the fifth rectangular region is a ninth conductive region 352, and a portion of the sixth rectangular region close to the fifth rectangular region and the fifth rectangular region constitute a tenth conductive region 353. The tenth conductive region 353 has an area larger than that of the ninth conductive region 352.

The sixth active layer 36 may include a sixth channel region 361, and an eleventh conductive region 362 and a twelfth conductive region 363 which are located at both ends of the sixth channel region 361. The eleventh conductive region 362 and the twelfth conductive region 363 are located at both ends of the sixth channel region 361 in the first direction Y. Specifically, the sixth active layer 36 may include a seventh rectangular region extending along the second direction X and an eighth rectangular region extending along the first direction Y, the eighth rectangular region being connected to a side of the seventh rectangular region close to the gate line 47. The eighth rectangular region has a sixth channel region 361 in the middle, an eleventh conductive region 362 in a portion of the eighth rectangular region distant from the seventh rectangular region, and a twelfth conductive region 363 in a portion of the eighth rectangular region close to the seventh rectangular region and the seventh rectangular region.

The area of the twelfth conductive region 363 is larger than the area of the eleventh conductive region 362.

The connecting wire 37 may be provided in a long strip shape, and the long strip shape is a linear shape, and the connecting wire 37 extends in the second direction X, extends from the ninth conductive region 352 to the eleventh conductive region 362, and connects the ninth conductive region 352 and the eleventh conductive region 362. The ninth conductive region 352, the connecting wire 37, and the eleventh conductive region 362 are connected together when they are formed, and the connecting wire 37 is an extension of the ninth conductive region 352 toward the sixth driving thin film transistor 76, or the connecting wire 37 is an extension of the eleventh conductive region 362 toward the fifth driving thin film transistor 75. Of course, in other example embodiments of the present disclosure, the connection wire 37 is also provided in a curved shape as long as the body direction is extended from the ninth region of conductivation 352 to the eleventh region of conductivation 362; furthermore, due to the arrangement of the position of the ninth conductive region 352 and the position of the eleventh conductive region 362, the connecting wire 37 may also be arranged obliquely, i.e. the extending direction of the connecting wire 37 may form a set angle with the second direction X.

The first active layer 31, the second active layer 32, the fifth active layer 35, and the sixth active layer 36 may also be provided in other structures, for example, the first active layer may include a circular or elliptical main body portion, and stripe-shaped protruding portions are provided on the circular or elliptical main body portion, a part of the protruding portions may be a channel region, another part of the protruding portions may be a conductive region, and the main body portion may be a conductive region.

The third active layer 33 may include a third channel region 331, and fifth and sixth

conductive regions

332 and 333 located at both ends of the third channel region 331. The third active layer 33 is provided in a rectangular shape, the third active layer 33 extends in the first direction Y, and the fifth conductive region 332 and the sixth conductive region 333 are located at opposite ends of the third channel region 331 in the first direction Y. The third active layer 33 is disposed on a side of the first active layer 31 away from the reference connection wire 1, and the four third active layers 33 are sequentially arranged along the second direction X. In other example embodiments of the present disclosure, the third active layer 33 may be disposed at a side of the first active layer 31 close to the data line.

The fourth active layer 34 may include a fourth channel region 341, and seventh and eighth

conductive regions

342 and 343 at both ends of the fourth channel region 341. The fourth active layer 34 is provided in a rectangular shape, the fourth active layer 34 also extends in the first direction Y, and the seventh and eighth

conductive regions

342 and 343 are located at opposite ends of the fourth channel region 341 in the first direction Y. The four fourth active layers 34 are all disposed between the first active layer 31 and the reference connection wire 1, and the four fourth active layers 34 are sequentially arranged along the second direction X. In other example embodiments of the present disclosure, the fourth active layer 34 may be disposed on a side of the first active layer 31 close to the data line.

And a gate insulating layer is arranged on one side of the active layer far away from the substrate base plate. The gate insulating layer is used to insulate and isolate the active layer from the subsequently formed gate electrode, the gate line 47 and the sensing control signal line 48, and may cover the entire array substrate or only the portion where the gate electrode, the gate line 47 and the sensing control signal line 48 are disposed.

A gate electrode, a gate line 47 and a sensing control signal line 48 are disposed on a side of the gate insulating layer away from the substrate. Referring to fig. 4 and 7, the gate electrode may include a first gate electrode 41, a second gate electrode 42, a third gate electrode 43, a fourth gate electrode 44, a fifth gate electrode 45, and a sixth gate electrode 46. The gate line 47, the sensing control signal line 48, the first gate electrode 41, the second gate electrode 42, the third gate electrode 43, the fourth gate electrode 44, the fifth gate electrode 45, and the sixth gate electrode 46 are disposed in the same material at the same layer, that is, they are formed through the same patterning process.

The third gate electrode 43 and the fourth gate electrode 44 are each provided in number of four; wherein the first gate 41, the third gate 43 and the fourth gate 44 belong to a driving circuit of a sub-pixel, for example, a driving circuit of a white sub-pixel; the second gate 42, one third gate 43 and one fourth gate 44 belong to a drive circuit of another sub-pixel, for example, a drive circuit of a red sub-pixel; the fifth gate electrode 45, one third gate electrode 43 and one fourth gate electrode 44 belong to a drive circuit of a further sub-pixel, for example, a drive circuit of a green sub-pixel; the sixth gate 46, one third gate 43 and one fourth gate 44 belong to a driving circuit of a further sub-pixel, for example a driving circuit of a blue sub-pixel.

The first gate electrode 41 may extend in the second direction X. The first gate electrode 41 may include a first gate body portion 411 and a first gate extension portion 412, the first gate body portion 411 being disposed opposite to the first channel region 311; the first gate extension portion 412 is connected to the first gate body portion 411 and is located on one side of the first gate body portion 411 close to the data line 62; the first gate body portion 411 and the first gate extension portion 412 are connected in the second direction X. An end portion of the first gate extension 412 near the data line 62 overlaps the third source electrode 54, and the width of the end portion is greater than that of the remaining portion. The first gate 41 may also serve as another electrode of the capacitor C.

The second gate electrode 42 may extend in the second direction X. The second gate 42 may include a second gate body portion 421 and a second gate extension 422, the second gate body portion 421 being disposed opposite to the second channel region 321; the second gate extension 422 is connected to the second gate body portion 421 and is located on a side of the second gate body portion 421 close to the data line 62, and the second gate body portion 421 and the second gate extension 422 are connected in the second direction X. The width of the portion of the second gate electrode 42 overlapping the third source electrode 54 is greater than the width of the remaining portion. The second gate 42 may also serve as the other electrode of the capacitor C.

The fifth gate electrode 45 may extend in the second direction X. The fifth gate electrode 45 may include a fifth gate body portion 451 and a fifth gate extension portion 452, the fifth gate body portion 451 being disposed opposite to the fifth channel region 351; the fifth gate extension portion 452 is connected to the fifth gate body portion 451 and is located on the fifth side of the fifth gate body portion 451 close to the data line 62; the fifth gate body portion 451 and the fifth gate extension portion 452 are connected in the second direction X. The width of the portion of the fifth gate electrode 45 overlapping the third source electrode 54 is greater than the width of the remaining portion. The fifth gate electrode 45 may also serve as the other electrode of the capacitor C.

The sixth gate 46 may extend in the second direction X. The sixth gate 46 may include a sixth gate body portion 461 and a sixth gate extension 462, the sixth gate body portion 461 being disposed opposite to the sixth channel region 361; the sixth gate extension 462 is connected to the sixth gate body portion 461 and located on the sixth side of the sixth gate body portion 461 close to the data line 62; the sixth gate body portion 461 and the sixth gate extension 462 are connected in the second direction X. The width of the portion of the sixth gate 46 overlapping the third source 54 is greater than the width of the remaining portion. The sixth gate 46 may also serve as the other electrode of the capacitor C.

The first gate electrode 41, the second gate electrode 42, the fifth gate electrode 45, and the sixth gate electrode 46 are disposed such that four third active layers 33 can be disposed adjacent to the data line 62, and four third drain electrodes 55 connected between the four data lines 62 and the four third active layers 33 can be disposed to be shorter, thereby improving electrical performance and reducing various risks.

The gate line 47 and the sensing control signal line 48 each extend in the second direction X. The gate line 47 is provided on a side of the first driving thin film transistor 71 remote from the first detecting thin film transistor 91. The sensing control signal line 48 is provided on a side of the first driving thin film transistor 71 away from the first switching thin film transistor 81.

The gate line 47 may include a plurality of first portions 471 and a plurality of second portions 472; the first part 471 is arranged in a double-line structure, that is, the first part 471 may include two wires, main portions of the two wires are arranged substantially in parallel, and two conductive ends are correspondingly connected into a whole; with such an arrangement, under the condition that one wire is broken, the other wire can still conduct electricity, so that the conductivity of the gate line 47 is ensured. The second portion 472 is provided in a single line structure, i.e., the second portion 472 may include one conductive line. The second portion 472 is connected between two adjacent first portions 471, that is, the second portion 472 is connected to both ends of two adjacent first portions 471.

The first portion 471 extends along the second direction X, and the second portion 472 also extends along the second direction X, so that the gate line 47 extends along the second direction X as a whole.

The third gate electrode 43 is disposed opposite to the third channel region 331, the third gate electrode 43 may be a portion of the gate line 47, and the third gate electrode 43 may be a portion of the second portion 472; so that both ends of the third gate electrode 43 are connected to the gate line 47.

The sensing control signal line 48 may include a plurality of third portions 481 and a plurality of fourth portions 482; the third portion 481 is configured as a double-line structure, that is, the third portion 481 may include two wires, main portions of the two wires are substantially parallel to each other, and two ends of the two wires are correspondingly connected to each other; so configured, in the event of an open circuit in one wire, the other wire can still conduct electricity, thereby ensuring the conductivity of the sensing control signal line 48. The fourth portion 482 is provided in a single wire configuration, i.e., the fourth portion 482 may include one wire. The fourth portion 482 is connected between the adjacent two third portions 481, that is, the fourth portion 482 is connected to both end portions of the adjacent two third portions 481.

The third portion 481 extends in the second direction X, and the fourth portion 482 also extends in the second direction X, so that the sensing control signal line 48 extends in the second direction X as a whole.

The fourth gate 44 is disposed opposite to the fourth channel region 341, the fourth gate 44 may be a portion of the sensing control signal line 48, and the fourth gate 44 may be a portion of the fourth portion 482, such that both ends of the fourth gate 44 are connected to the sensing control signal line 48.

In addition, in some other example embodiments of the present disclosure, the connection wire 37 may be disposed in the same material layer as the first gate electrode 41, that is, the connection wire 37 may be formed by the same patterning process as the first gate electrode 41. The structure of the connecting wire 37 is the same as that described above, but is provided in a different conductive layer. One connecting wire 37 may be connected to the first and third

conductive regions

312 and 322 through a via hole in the gate insulating layer, and the other connecting wire 37 may be connected to the ninth and eleventh

conductive regions

352 and 362 through a via hole in the gate insulating layer.

An insulating layer is provided on the sides of the gate electrode, the gate line 47 and the sensing control signal line 48 away from the substrate, the insulating layer covers the entire array substrate, and a plurality of via holes are provided on the insulating layer, so that the source and drain electrodes of each thin film transistor can be connected to the conductive region of the active layer and the reference connection wire 1.

Referring to fig. 4, dotted circles indicate via holes, and a power line 61, a data line 62, a reference voltage (V-Ref) line 63, and source and drain electrodes of the respective thin film transistors are provided on a side of the insulating layer away from the substrate base. The power line 61, the data line 62, the reference voltage (V-Ref) line 63, and the source and drain electrodes (the first source electrode 51, the first drain electrode 52, the second source electrode 53, the third source electrode 54, the third drain electrode 55, the fourth source electrode 56, the fourth drain electrode 57, the fifth source electrode 58, the sixth source electrode 59, and the sixth drain electrode 60) of each thin film transistor are disposed in the same material layer, that is, they are formed through the same patterning process.

The power supply line 61, the data line 62, and the reference voltage line 63 all extend in the first direction Y.

Specifically, in the above description of the active layer, it has been described that one connecting wire 37 extends from the third conductive region 322 toward the first conductive region 312 side in the second direction X until the third conductive region 322 is connected to the first conductive region 312. The other connecting wire 37 extends from the ninth conductive region 352 to the eleventh conductive region 362 side in the second direction X until the ninth conductive region 352 and the eleventh conductive region 362 are connected.

The first drain electrode 52 extends along the second direction X, one end of the first drain electrode 52 is directly connected to the power line 61, and the first drain electrode 52 and the power line 61 are connected together when being manufactured and formed; the other end of the first drain 52 is connected to the first conductive region 312 through a via hole in the insulating layer. It is achieved that the first drive circuit and the second drive circuit share one power supply line 61.

The sixth drain 60 extends along the second direction X, one end of the sixth drain 60 is directly connected to the other power line 61, and the sixth drain 60 and the other power line 61 are connected together when being manufactured and formed; the other end of the sixth drain electrode 60 is connected to the eleventh conductive region 362 through a via hole in the insulating layer. It is realized that the third drive circuit and the fourth drive circuit share one power supply line 61.

The third source 54 of the first switching thin film transistor 81 extends substantially along the first direction Y, one end of the third source 54 overlaps and is connected to the first gate 41 through a via hole in the insulating layer, and the other end of the third source 54 overlaps and is connected to the fifth conductive region 332 of the first switching thin film transistor 81 through a via hole in the insulating layer.

The third source 54 of the second switching thin film transistor 82 extends substantially along the first direction Y, one end of the third source 54 overlaps and is connected to the second gate 42 through a via hole in the insulating layer, and the other end of the third source 54 overlaps and is connected to the fifth conductive region 332 of the second switching thin film transistor 82 through a via hole in the insulating layer.

The third source 54 of the third switching thin film transistor 83 extends substantially along the first direction Y, one end of the third source 54 overlaps and is connected to the fifth gate 45 through a via hole in the insulating layer, and the other end of the third source 54 overlaps and is connected to the fifth conductive region 332 of the third switching thin film transistor 83 through a via hole in the insulating layer.

The third source electrode 54 of the fourth switching thin film transistor 84 extends substantially along the first direction Y, one end of the third source electrode 54 overlaps and is connected to the sixth gate electrode 46 through a via hole in the insulating layer, and the other end of the third source electrode 54 overlaps and is connected to the fifth conductive region 332 of the fourth switching thin film transistor 84 through a via hole in the insulating layer.

The third drain electrode 55 of the first switching thin film transistor 81 extends substantially along the second direction X, one end of the third drain electrode 55 overlaps and is connected to the sixth conductive region 333 of the first switching thin film transistor 81 through a via hole in an insulating layer, the other end of the third drain electrode 55 is directly connected to the data line 62 adjacent to the first switching thin film transistor 81, and the third drain electrode 55 and the data line 62 are connected together when they are formed.

The third drain electrode 55 of the second switching thin film transistor 82 extends substantially along the second direction X, one end of the third drain electrode 55 overlaps and is connected to the sixth conductive region 333 of the second switching thin film transistor 82 through a via hole in an insulating layer, the other end of the third drain electrode 55 is directly connected to the data line 62 adjacent to the second switching thin film transistor 82, and the third drain electrode 55 and the data line 62 are connected together when they are formed.

The third drain electrode 55 of the third switching thin film transistor 83 extends substantially along the second direction X, one end of the third drain electrode 55 overlaps and is connected to the sixth conductive region 333 of the third switching thin film transistor 83 via a via hole in an insulating layer, the other end of the third drain electrode 55 is directly connected to the data line 62 adjacent to the third switching thin film transistor 83, and the third drain electrode 55 and the data line 62 are connected together when they are formed.

The third drain electrode 55 of the fourth switching thin film transistor 84 extends substantially along the second direction X, one end of the third drain electrode 55 overlaps and is connected to the sixth conductive region 333 of the fourth switching thin film transistor 84 through a via hole in an insulating layer, the other end of the third drain electrode 55 is directly connected to the data line 62 adjacent to the fourth switching thin film transistor 84, and the third drain electrode 55 and the data line 62 are connected together when being manufactured and formed.

The reference voltage line 63 is provided in one, and the reference voltage line 63 is provided between the second driving circuit and the third driving circuit. The reference voltage line 63 is connected to the reference connection wire 1 through a via hole in the insulating layer.

The fourth drain electrode 57 of the first detecting thin film transistor 91 extends substantially in the second direction X, one end of the fourth drain electrode 57 overlaps and is connected to the eighth conductive region 343 of the first detecting thin film transistor 91 through a via hole in the insulating layer, and the other end of the fourth drain electrode 57 is connected to the reference connection wire 1 through a via hole in the insulating layer, so that the fourth drain electrode 57 of the first detecting thin film transistor 91 is connected to the reference voltage line 63 through the reference connection wire 1.

The fourth drain electrode 57 of the second detecting thin film transistor 92 extends substantially in the second direction X, one end of the fourth drain electrode 57 overlaps and is connected to the eighth conductive region 343 of the second detecting thin film transistor 92 through a via hole in an insulating layer, and the other end of the fourth drain electrode 57 is connected to the reference connection wiring 1 through a via hole in an insulating layer, so that the fourth drain electrode 57 of the second detecting thin film transistor 92 is connected to the reference voltage line 63 through the reference connection wiring 1.

The fourth drain electrode 57 of the third detecting thin film transistor 93 extends substantially in the second direction X, one end of the fourth drain electrode 57 overlaps and is connected to the eighth conductive region 343 of the third detecting thin film transistor 93 through a via hole in an insulating layer, and the other end of the fourth drain electrode 57 is connected to the reference connection wire 1 through a via hole in an insulating layer, so that the fourth drain electrode 57 of the third detecting thin film transistor 93 is connected to the reference voltage line 63 through the reference connection wire 1.

It should be noted that the fourth drain 57 of the second detection thin film transistor 92 may be directly connected to the reference voltage line 63, and the fourth drain 57 of the third detection thin film transistor 93 may also be directly connected to the reference voltage line 63.

The fourth drain electrode 57 of the fourth detecting thin film transistor 94 extends substantially in the second direction X, one end of the fourth drain electrode 57 overlaps and is connected to the eighth conductive region 343 of the fourth detecting thin film transistor 94 through a via hole in an insulating layer, and the other end of the fourth drain electrode 57 is connected to the reference connection wire 1 through a via hole in an insulating layer, so that the fourth drain electrode 57 of the fourth detecting thin film transistor 94 is connected to the reference voltage line 63 through the reference connection wire 1.

The fourth source electrode 56 of the first detecting thin film transistor 91 extends substantially in the second direction X, one end of the fourth source electrode 56 overlaps and is connected to the seventh conductive region 342 of the first detecting thin film transistor 91 through a via hole in the insulating layer, and the other end of the fourth source electrode 56 is connected to the first source electrode 51 of the first driving thin film transistor 71. The first source electrode 51 of the first driving thin film transistor 71 extends substantially in the first direction Y, and one end of the first source electrode 51 overlaps and is connected to the second conductive region 313 of the first driving thin film transistor 71 through a via hole in the insulating layer. The other end of the fourth source 56 is directly connected to the other end of the first source 51, and the fourth source 56 and the first source 51 are connected together when they are formed. Further, since the fourth source 56 and the first source 51 of the first detection thin film transistor 91 are connected to the first light shielding layer 21 through a via hole in the insulating layer and the first light shielding layer 21 serves as one electrode of the capacitor C, both the fourth source 56 and the first source 51 of the first detection thin film transistor 91 are connected to one electrode of the capacitor C.

The fourth source electrode 56 of the second detection thin film transistor 92 extends substantially along the second direction X, one end of the fourth source electrode 56 overlaps and is connected to the seventh conductive region 342 of the second detection thin film transistor 92 through a via hole in the insulating layer, and the other end of the fourth source electrode 56 is connected to the second source electrode 53 of the second driving thin film transistor 72. The second source electrode 53 of the second driving thin film transistor 72 extends substantially in the first direction Y, and one end of the second source electrode 53 overlaps and is connected to the fourth conductive region 323 of the second driving thin film transistor 72 through a via hole in the insulating layer. The other end of the fourth source 56 is directly connected to the other end of the second source 53, and the fourth source 56 and the second source 53 are connected together when they are formed. The fourth source 56 and the second source 53 of the second detection thin film transistor 92 are connected to the second light-shielding layer 22 through via holes in the insulating layer, and the second light-shielding layer 22 serves as one electrode of the capacitor C, so that both the fourth source 56 and the second source 53 of the second detection thin film transistor 92 are connected to one electrode of the capacitor C.

The fourth source electrode 56 of the third detection thin film transistor 93 extends substantially along the second direction X, one end of the fourth source electrode 56 overlaps and is connected to the seventh conductive region 342 of the third detection thin film transistor 93 through a via hole in the insulating layer, and the other end of the fourth source electrode 56 is connected to the fifth source electrode 58 of the third driving thin film transistor 73. The fifth source electrode 58 of the third driving thin film transistor 73 extends substantially in the first direction Y, and one end of the fifth source electrode 58 overlaps and is connected to the tenth conduction region 353 of the third driving thin film transistor 73 through a via hole in the insulating layer. The other end of the fourth source 56 is directly connected to the other end of the fifth source 58. the fourth source 56 and the fifth source 58 are formed and connected together. The fourth source 56 and the fifth source 58 of the third detection thin film transistor 93 are connected to the third light-shielding layer 23 through via holes in the insulating layer, and the third light-shielding layer 23 serves as one electrode of the capacitor C, so that both the fourth source 56 and the fifth source 58 of the third detection thin film transistor 93 are connected to one electrode of the capacitor C.

The fourth source electrode 56 of the fourth detecting thin film transistor 94 extends substantially along the second direction X, one end of the fourth source electrode 56 overlaps and is connected to the ninth conductive region 352 of the fourth detecting thin film transistor 94 through a via hole in the insulating layer, and the other end of the fourth source electrode 56 is connected to the sixth source electrode 59 of the fourth driving thin film transistor 74. The sixth source electrode 59 of the fourth driving thin film transistor 74 extends substantially along the first direction Y, and one end of the sixth source electrode 59 overlaps and is connected to the twelfth conductive region 363 of the fourth driving thin film transistor 74 through a via hole on the insulating layer. The other end of the fourth source 56 is directly connected to the other end of the sixth source 59, and the fourth source 56 and the sixth source 59 are connected together when they are formed. The fourth source 56 and the sixth source 59 of the fourth detection thin film transistor 94 are connected to the fourth light shielding layer 24 through via holes in the insulating layer, and the fourth light shielding layer 24 serves as one electrode of the capacitor C, so that both the fourth source 56 and the sixth source 59 of the fourth detection thin film transistor 94 are connected to one electrode of the capacitor C.

In the array substrate disclosed by the disclosure, the first conductive region 312 and the third conductive region 322 are directly connected into a whole when the active layer is formed, and the second drain 64 and the connecting wire 101 are avoided, so that the area of the wiring region of the array substrate is reduced, the aperture opening ratio of the array substrate is improved, and the display brightness is improved; in addition, the second drain 64 and the gate line 47 are not overlapped, so that the open circuit of the second drain 64 is avoided, the short circuit of the second drain 64 and the gate line 47 is also avoided, and the product yield is improved; in addition, although the connecting wire 37 overlaps the data line 62, a thick insulating layer is provided between the connecting wire 37 and the data line 62, and the thickness of the connecting wire 37 is thin, so that there is no risk of the data line 62 being disconnected or the connecting wire 37 and the data line 62 being short-circuited; the power supply line 61 receives a dc voltage, and the connection lead 37 is used, which does not affect the driving of the thin film transistor.

In addition, in other example embodiments of the present disclosure, the driving circuit of one sub-pixel may include two thin film transistors and one capacitor C, and in this case, the reference connection wire 1, the reference voltage line 63, and the sensing control signal line 48 may not be provided. Also, the driving circuit of one sub-pixel may further include more thin film transistors and one capacitor C.

In addition, in still other example embodiments of the present disclosure, one pixel unit may also include three sub-pixels, for example, a red sub-pixel, a green sub-pixel, and a blue sub-pixel. The power line 61 may be shared by the driving circuits of the two sub-pixels, that is, the array substrate may include a first driving thin film transistor 71, a second driving thin film transistor 72, and a third driving thin film transistor 73, the connecting wire 37 extends from the third conductive region 322 of the second driving thin film transistor 72 to the first conductive region 312 of the first driving thin film transistor 71, and opposite ends of the connecting wire 37 are connected to the third conductive region 322 and the first conductive region 312, respectively, and the first conductive region 312 is connected to the power line 61. The detailed description of the specific structure is already provided above, and therefore, the detailed description is omitted here.

Based on the same inventive concept, example embodiments of the present disclosure provide a display panel, which may include the array substrate of any one of the above. The specific structure of the array substrate has been described in detail above, and therefore, the detailed description thereof is omitted.

The display panel can also comprise a first electrode, a pixel dielectric layer, a light-emitting layer, a second electrode and an encapsulation layer group. The first electrode is arranged on one side, far away from the substrate base plate, of the protective layer and is connected with the source electrode or the drain electrode through a third through hole in the protective layer; the first electrode may be an anode, and the material of the first electrode may be a transparent conductive material, for example, ITO (indium tin oxide), IZO (indium zinc oxide), or the like. The pixel medium layer is arranged on one side, far away from the substrate base plate, of the first electrode, a fourth through hole is formed in the pixel medium layer and communicated to the first electrode, and part of the first electrode is exposed through the fourth through hole. The light emitting layer is arranged in the fourth through hole and is connected with the first electrode. The second electrode is disposed on a side of the light emitting layer away from the base substrate, and the second electrode may be a cathode.

The packaging layer group is arranged on one side, far away from the substrate base plate, of the second electrode. The encapsulation layer group may include an organic layer and an inorganic layer, and the number of layers and the stacking manner of the organic layer and the inorganic layer may be set as required, which is not described herein any more.

Based on the same inventive concept, the disclosed example embodiments provide a display device, which may include the display panel described above. The detailed structure of the display panel has already been described above, and therefore, the detailed description thereof is omitted here.

The specific type of the display device is not particularly limited, and any display device commonly used in the art may be used, specifically, for example, a mobile device such as a mobile phone, a wearable device such as a watch, a VR device, and the like.

It should be noted that the display device includes other necessary components and components besides the display panel, taking a display as an example, specifically, such as a housing, a circuit board, and the like, and those skilled in the art can perform corresponding supplement according to the specific use requirement of the display device, and details are not described herein.

Compared with the prior art, the beneficial effects of the display panel and the display device provided by the exemplary embodiment of the present invention are the same as the beneficial effects of the array substrate provided by the exemplary embodiment described above, and are not repeated herein.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. An array substrate, comprising:

and a connecting wire extending from the third conductive region to the first conductive region, and opposite ends of the connecting wire are connected to the third conductive region and the first conductive region, respectively.

2. The array substrate according to claim 1, wherein the connection wire is an extension of the third conductive region extending toward the first driving thin film transistor.

3. The array substrate of claim 1, further comprising:

4. The array substrate of claim 3, wherein the connecting wires and the first gates are disposed in the same layer of material.

5. The array substrate of claim 3, further comprising:

6. The array substrate of claim 5, wherein the gate line comprises:

7. The array substrate of claim 5, wherein the first switching thin film transistor is disposed on the first direction side of the first driving thin film transistor, the second switching thin film transistor is disposed on the first direction side of the second driving thin film transistor, and the first switching thin film transistor and the second switching thin film transistor are disposed between the data line and the power line.

8. The array substrate of claim 5, wherein the first gate comprises:

a first gate body portion disposed opposite to the first channel region;

the second gate includes:

a second gate body portion disposed opposite to the second channel region;

9. The array substrate of claim 8, wherein an extending direction of the third active layer intersects an extending direction of the gate line, the third source electrode of the first switching thin film transistor overlaps and is connected to an end portion of the first gate extending portion near the data line, and the third source electrode of the second switching thin film transistor overlaps and is connected to an end portion of the second gate extending portion near the data line.

10. The array substrate of claim 5, further comprising:

11. The array substrate of claim 10, wherein the sensing control signal line comprises:

12. The array substrate of claim 10, further comprising:

13. The array substrate as claimed in claim 12, wherein the first light shielding layer, the second light shielding layer and the reference connection wires are disposed in the same layer and material; the first active layer, the second active layer, the third active layer and the fourth active layer are arranged in the same material in the same layer; the grid line, the sensing control signal line, the first grid electrode, the second grid electrode, the third grid electrode and the fourth grid electrode are arranged on the same layer of the same material; the first source electrode, the first drain electrode, the second source electrode, the third drain electrode, the fourth source electrode, the fourth drain electrode, the data line, the power line, and the reference voltage line are disposed in the same layer of material.

14. A display panel, comprising: an array substrate according to any one of claims 1 to 13.

15. A display device, comprising: the display panel of claim 14.