CN115877155A

CN115877155A - Method and structure for testing electrical performance of device

Info

Publication number: CN115877155A
Application number: CN202110949979.7A
Authority: CN
Inventors: 宋王琴
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2021-08-18
Filing date: 2021-08-18
Publication date: 2023-03-31

Abstract

The embodiment of the application relates to the field of semiconductors, and provides a method and a structure for testing electrical properties of a device, wherein the method comprises the following steps: providing at least two transistors, a first conductive plug and a second conductive plug, wherein the first conductive layer is contacted with all the first conductive plugs, the second conductive layer is contacted with all the second conductive plugs, and one transistor is a transistor to be tested; carrying out graphical processing on the first conducting layer and the second conducting layer to form a first electric connection layer and a second electric connection layer, wherein the first electric connection layer is only contacted with all first conducting plugs corresponding to the transistor to be tested, and the second electric connection layer is only contacted with all second conducting plugs corresponding to the transistor to be tested; providing variable test signals to the first electric connection layer, the second electric connection layer and the grid electrode of the transistor to be tested, and acquiring output signals of the first electric connection layer and the second electric connection layer; and detecting the electrical property of the transistor to be detected based on the output signal. The embodiment of the application is beneficial to improving the accuracy of the electrical performance of the measured device.

Description

Method and structure for testing electrical performance of device

Technical Field

The embodiment of the application relates to the field of semiconductors, in particular to a method and a structure for testing electrical properties of a device.

Background

In the manufacture of electronic products, particularly integrated circuits, it is often necessary to test the electrical properties of the devices. In the product failure analysis or competitive product analysis, the saturation current of a device in an integrated circuit chip is an important parameter, the current driving capability of the device is represented, and the test method capable of accurately measuring the saturation current of the device in the integrated circuit chip is designed, so that a person designing the product can know the current driving capability of the important device in a mainstream product in the market, and reference is provided for the design of a new product.

However, when testing the electrical performance of the device in the integrated circuit chip, the resistance of the probe for testing the device, the contact resistance between the probe and the device under test, and the resistance generated by the connection between the internal structures of the device under test all interfere with the test structure, which affects the electrical performance of the device under test, for example, reduces the accuracy of the saturation current of the device in the integrated circuit chip.

Therefore, there is a need to provide a new method for testing electrical properties of a device to improve the accuracy of the measured electrical properties of the device.

Disclosure of Invention

The embodiment of the application provides a method and a structure for testing the electrical performance of a device, which are at least beneficial to improving the accuracy of the measured electrical performance of the device.

According to some embodiments of the present application, a method for testing electrical performance of a device provided by an aspect of the embodiments of the present application includes: providing a device, wherein the device is provided with at least two transistors which are spaced from each other, the transistor is provided with a source electrode, a drain electrode and a grid electrode, the transistor is also provided with at least two first conductive plugs which are contacted with the source electrode and at least two second conductive plugs which are contacted with the drain electrode, the device is also provided with a first conductive layer and a second conductive layer, the first conductive layer is electrically connected with all the first conductive plug contacts corresponding to at least two transistors, the second conductive layer is electrically connected with all the second conductive plug contacts corresponding to at least two transistors, and one transistor is taken as a transistor to be tested; performing graphical processing on the first conducting layer to form a first electric connection layer, wherein the first electric connection layer is only in contact and electric connection with all the first conducting plugs corresponding to the transistors to be tested; carrying out graphical processing on the second conducting layer to form a second electric connection layer, wherein the second electric connection layer is only in contact and electric connection with all the second conducting plugs corresponding to the transistors to be tested; providing variable test signals to the first electric connection layer, the second electric connection layer and the grid electrode of the transistor to be tested, and acquiring output signals of the first electric connection layer and the second electric connection layer; and detecting the electrical property of the transistor to be detected based on the output signal.

According to some embodiments of the present application, in another aspect, there is provided a test structure for implementing the test method described above, including: the transistor is provided with a source electrode, a drain electrode and a grid electrode, and is also provided with at least two first conductive plugs which are contacted with the source electrode and at least two second conductive plugs which are contacted with the drain electrode, wherein one transistor is used as a transistor to be tested; the first electric connection layer is only in contact electric connection with all the first conductive plugs corresponding to the transistors to be tested; and the second electric connection layer is only in contact electric connection with all the second conductive plugs corresponding to the transistors to be tested.

The technical scheme provided by the embodiment of the application has at least the following advantages:

when the device actually works, the control of the source electrodes of the transistors is realized through the first conducting layer, and the control of the drain electrodes of the transistors is realized through the second conducting layer. In the test circuit, in order to measure the electrical performance of a single transistor, one transistor of at least two transistors is set as a transistor to be tested, the first conducting layer and the second conducting layer are subjected to graphical processing, and a first electric connection layer corresponding to the first conducting layer and a second electric connection layer corresponding to the second conducting layer are formed. The first electric connection layer is only in contact electric connection with all the first conductive plugs corresponding to the transistors to be tested, and the second electric connection layer is only in contact electric connection with all the second conductive plugs corresponding to the transistors to be tested, so that interference of the transistors adjacent to the transistors to be tested on the test results of the transistors to be tested is avoided, and the electrical performance of the single transistor to be tested is tested.

In addition, the first electric connection layer is in contact electric connection with all the first conductive plugs corresponding to the transistor to be tested, so that the parallel connection state of the plurality of first conductive plugs during the actual work of the transistor to be tested can be simulated truly, and the difference between the resistance at the source electrode in the test circuit and the resistance at the source electrode in the actual work circuit can be reduced; the second electric connection layer is in contact electric connection with all the second conductive plugs corresponding to the transistor to be tested, so that the parallel connection state of the second conductive plugs during actual working of the transistor to be tested can be simulated truly, and the difference between the resistance at the drain electrode in the test circuit and the resistance at the drain electrode in the actual working circuit can be reduced. Moreover, the first electric connection layer provides a test voltage for the source electrode through each first conductive plug of the transistor to be tested, and the second electric connection layer provides a test voltage for the drain electrode through each second conductive plug of the transistor to be tested, so that the test voltage on the source electrode is distributed uniformly, the test voltage on the drain electrode is also distributed uniformly, and the area of the source electrode and the drain electrode in a working state is increased. Therefore, the first electric connection layer and the second electric connection layer are formed, so that the accuracy of the electrical performance of the transistor to be tested measured through the test circuit is improved, and the accuracy of the saturation current value of the transistor to be tested is improved.

Drawings

One or more embodiments are illustrated by corresponding figures in the drawings, which are not to be construed as limiting the embodiments, unless expressly stated otherwise, and the drawings are not to scale.

Fig. 1 is a schematic partial top view of the interior of a device provided in an embodiment of the present application;

FIG. 2 is a schematic diagram of a method for testing electrical properties of a device according to an embodiment of the present disclosure;

FIG. 3 is a schematic view of a partial cross-sectional view taken along the direction AA1 in FIG. 2;

FIG. 4 is a schematic diagram of a testing method corresponding to FIG. 2;

FIG. 5 is another schematic diagram of a method for testing electrical properties of a device according to an embodiment of the present disclosure;

fig. 6 is a schematic diagram of a testing method corresponding to fig. 5.

Detailed Description

It is known from the background art that the accuracy of the test results generated by the test methods for measuring the electrical properties of devices is to be improved.

It has been found through analysis that the current voltammetry of devices on an integrated circuit chip is tested on a conductive layer, which is usually electrically connected to a plurality of conductive structures (e.g., field effect transistors) in the device, and thus the measured result is not the current voltammetry of a single conductive structure when the test is performed on the conductive layer.

In some embodiments, the device has at least two spaced transistors having a source, a drain, and a gate, at least two first conductive plugs in contact with the source, and at least two second conductive plugs in contact with the drain, and a first conductive layer in electrical connection with all of the first conductive plug contacts corresponding to the at least two transistors and a second conductive layer in electrical connection with all of the second conductive plug contacts corresponding to the at least two transistors. When measuring the electrical performance of a single transistor, a probe for testing is disposed on a conductive plug in contact with the transistor to avoid the transistors adjacent to the adjacent transistor from interfering with the test results of the transistor.

When the device works actually, the first conductive plugs are arranged on the source electrodes of the transistors, the first conductive plugs are electrically connected with each other through the first conductive layers, the second conductive plugs are arranged on the drain electrodes of the transistors, and the second conductive plugs are electrically connected with each other through the second conductive layers, so that the source electrodes of the transistors are controlled through the first conductive layers, and the drain electrodes of the transistors are controlled through the second conductive layers.

However, on one hand, when the transistor to be tested actually works, at least two first conductive plugs connected with the source contact of the transistor to be tested are in contact and electrical connection with the same first conductive layer, and at least two second conductive plugs connected with the drain contact of the transistor to be tested are in contact and electrical connection with the same second conductive layer, so that in an actual working circuit, the first conductive plugs and the second conductive plugs are in parallel connection, the equivalent resistance of the at least two first conductive plugs at the source is smaller than that of a single first conductive plug, and the equivalent resistance of the at least two second conductive plugs at the drain is smaller than that of a single second conductive plug. When a transistor to be tested is tested, because the probe for testing the source electrode is only arranged on one of the first conductive plugs, in a test circuit, the resistance at the source electrode is the resistance of a single first conductive plug and is larger than the resistance at the source electrode in an actual working circuit, and the probe is only arranged on one first conductive plug, so that the test voltage applied to the source electrode by the probe through the first conductive plug is not uniformly distributed on the source electrode, namely the voltage of a local area close to the first conductive plug on the source electrode can reach the test voltage, the voltage of other areas of the source electrode cannot reach the test voltage, the area which is equivalent to the area actually in the working state on the source electrode is smaller than the area in the actual working state, and so on, the resistance at the drain electrode in the test circuit is the resistance of a single second conductive plug and is larger than the resistance at the drain electrode in the actual working circuit, and when the probe for testing the drain electrode is only arranged on one of the second conductive plugs, the area in the drain electrode is also smaller than the area in the actual working state.

Whether the resistance at the source electrode in the test circuit is larger than the resistance at the source electrode in the actual working circuit, the resistance at the drain electrode in the test circuit is larger than the resistance at the drain electrode in the actual working circuit, the area of the source electrode in the test circuit, which is really in the working state, is smaller than the area in the actual working state, and the area of the drain electrode in the test circuit, which is really in the working state, is smaller than the area in the actual working state, the saturation current value of the transistor to be tested, which is measured by the test circuit, is smaller than the saturation current value of the transistor to be tested in the actual working state, so that the accuracy of the test result of the transistor to be tested is influenced.

On the other hand, the resistances of the probes arranged on the first conductive plug and the second conductive plug of the transistor to be tested and the contact resistance between the probes and the first conductive plug or the second conductive plug can occupy a part of test voltage, so that the voltage value actually applied to the source electrode or the drain electrode through the probes is smaller than the voltage value which is set for the probes and is applied to the source electrode or the drain electrode, the saturation current value of the transistor to be tested measured through the test circuit is smaller than the saturation current value of the transistor to be tested in actual operation, and the accuracy of the test result of the transistor to be tested is influenced.

The embodiment of the application provides a method for testing electrical properties of a device, which comprises the following steps: the first conducting layer and the second conducting layer are subjected to graphical processing to form a first electric connection layer corresponding to the first conducting layer and a second electric connection layer corresponding to the second conducting layer, the source electrode of the transistor to be tested is prevented from being electrically connected with the source electrodes of other transistors through the first electric connection layer, the drain electrode of the transistor to be tested is prevented from being electrically connected with the drain electrodes of other transistors through the second electric connection layer, and therefore interference of the other transistors on the test result of the transistor to be tested is avoided, and the electrical performance of a single transistor to be tested is tested. In addition, the first electric connection layer and the second electric connection layer are favorable for simulating the state that the plurality of first conductive plugs are connected in parallel and the plurality of second conductive plugs are connected in parallel when the transistor to be tested actually works, so that the difference between the resistance at the source electrode in the test circuit and the resistance at the source electrode in the actual working circuit is reduced, and the difference between the resistance at the drain electrode in the test circuit and the resistance at the drain electrode in the actual working circuit is reduced.

To make the objects, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in the various embodiments of the present application, numerous technical details are set forth in order to provide a better understanding of the present application. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments.

An embodiment of the present application provides a method for testing electrical properties of a device, and a semiconductor structure provided in an embodiment of the present application will be described in detail below with reference to the accompanying drawings. Fig. 1 is a schematic partial top view of a device according to an embodiment of the present disclosure; FIG. 2 is a schematic diagram of a method for testing electrical properties of a device according to an embodiment of the present disclosure; FIG. 3 is a schematic view of a partial cross-sectional view taken along direction AA1 in FIG. 2; FIG. 4 is a schematic diagram of a testing method corresponding to FIG. 2; FIG. 5 is another schematic diagram of a method for testing electrical properties of a device according to an embodiment of the present disclosure; fig. 6 is a schematic diagram of a testing method corresponding to fig. 5.

Referring to fig. 1 to 6, the method for testing the electrical properties of the device includes the following steps:

referring to fig. 1 and fig. 2, a device is provided, in which at least two transistors are spaced from each other, each transistor has a source 110, a drain 120 and a gate 130, each transistor further has at least two first conductive plugs 140 contacting the source 110 and at least two second conductive plugs 150 contacting the drain 120, each device further has a first conductive layer 102 and a second conductive layer 103, and the first conductive layer 102 is electrically connected to all the first conductive plugs 140 corresponding to at least two transistors, and the second conductive layer 103 is electrically connected to all the second conductive plugs 150 corresponding to at least two transistors, wherein one transistor is used as a transistor 101 to be tested.

It should be noted that the device has a substrate 100, and the source 110 and the drain 120 of the transistor are both located in the substrate 100. In the direction of the substrate 100 pointing to the first conductive plug 140, the portion of the thickness of the substrate 100 covered by the dashed line box I in fig. 1 is the source 110, the portion of the thickness of the substrate 100 covered by the dashed line box II is the drain 120, and the gate 130 is located above a portion of the surface of the substrate 100. In fig. 1, for example, two adjacent transistors share the source 110 or the drain 120, and all the transistors share the gate 130, in practical applications, the source, the drain, and the gate between different transistors may not be shared. With continued reference to fig. 1, the device further comprises: the third conductive layer formed by contact electric connection among the gates 130 of all the transistors, a third conductive plug 131 in contact with the third conductive layer, a fourth conductive layer 132 in contact electric connection with the third conductive plug 131, the substrate 104, a fourth conductive plug 114 on the substrate 104, and a fifth conductive layer 124 in contact electric connection with the fourth conductive plug 114.

It should be noted that, in fig. 1, it is exemplified that the same source 110 has 4 first conductive plugs 140, the same drain 120 has 4 second conductive plugs 150, the gate 130 has 1 third conductive plug 131, and the substrate 104 has 8 fourth conductive plugs 114, in practical application, the number of the first conductive plugs on the same source and the number of the second conductive plugs on the same drain are not less than two, and the number of the third conductive plugs and the number of the fourth conductive plugs are not limited.

It should be noted that the transistor 101 to be tested may include a plurality of sub-transistors, that is, a local region of the substrate 100 corresponding to one first conductive plug 140 in the transistor 101 to be tested is a source of one sub-transistor, a source 110 of the transistor 101 to be tested is formed by sources of a plurality of sub-transistors together, and a local region of the substrate 100 corresponding to one second conductive plug 150 in the transistor 101 to be tested is a drain of one sub-transistor, and a drain 120 of the transistor 101 to be tested is formed by drains of a plurality of sub-transistors together, as an example, in fig. 1, one transistor 101 to be tested includes 4 sub-transistors, and in practical applications, the number of sub-transistors in the same transistor 101 to be tested is not limited. The electrical property of the sub-transistor in the transistor 101 to be tested can be represented by the electrical property of the transistor 101 to be tested. Further, the transistor other than the transistor 101 to be tested may also include a plurality of sub-transistors.

It should be noted that, in some embodiments, the top surface of the first conductive plug 140 away from the top surface of the substrate 100, the top surface of the second conductive plug 150 away from the top surface of the substrate 100, and the top surface of the third conductive plug 131 away from the substrate 100 are flush with the top surface of the fourth conductive plug 114 away from the top surface of the substrate 100. Moreover, in a direction in which the substrate 100 points to the first conductive plug 140, the thickness of the first conductive layer 102, the thickness of the second conductive layer 103, the thickness of the fourth conductive layer 132, and the thickness of the fifth conductive layer 124 are equal, that is, the first conductive layer 102, the second conductive layer 103, the fourth conductive layer 132, and the fifth conductive layer 124 are in a structure disposed in the same layer.

With reference to fig. 1 and fig. 2, the first conductive layer 102 is patterned to form a first electrical connection layer 112, and the first electrical connection layer 112 is electrically connected to all the first conductive plugs 140 corresponding to the transistor 101 to be tested only in a contact manner; and patterning the second conductive layer 103 to form a second electrical connection layer 113, wherein the second electrical connection layer 113 is electrically connected with all the second conductive plugs 150 corresponding to the transistor 101 to be tested only in a contacting manner.

Because the first electrical connection layer 112 is only in contact electrical connection with all the first conductive plugs 140 corresponding to the transistor 101 to be tested, and the second electrical connection layer 113 is only in contact electrical connection with all the second conductive plugs 150 corresponding to the transistor 101 to be tested, the first electrical connection layer 112 and the second electrical connection layer 113 are beneficial to simulating a state that the plurality of first conductive plugs 140 are connected in parallel and the plurality of second conductive plugs 150 are connected in parallel when the transistor 101 to be tested actually works, so as to reduce a difference between a resistance at the source 110 in the test circuit and a resistance at the source 110 in the actually working circuit and reduce a difference between a resistance at the drain 120 in the test circuit and a resistance at the drain 120 in the actually working circuit, and the first electrical connection layer 112 and the second electrical connection layer 113 are beneficial to increasing a region where the source 110 and the drain 120 are in a working state, so as to be beneficial to improving accuracy of electrical performance of the transistor 101 to be tested measured by the test circuit, so as to improve accuracy of a saturation current value of the transistor 101 to be tested, so as to improve electrical performance of the measured by the sub-transistor 101 to be tested and accuracy of the saturation current value.

In addition, the fifth conductive layer 124 is in contact with and electrically connected to all the fourth conductive plugs 114, which is beneficial to truly simulating the parallel connection state of the plurality of fourth conductive plugs 114 when the transistor 101 to be tested actually works, and is beneficial to increasing the area of the substrate 104 in the working state, thereby being beneficial to improving the accuracy of the electrical property of the transistor 101 to be tested measured by the test circuit, and improving the accuracy of the saturation current value of the transistor 101 to be tested.

In some embodiments, referring to fig. 2 and fig. 3 in combination, the surface of the source 110 of the transistor 101 to be tested is a first plane, and the orthographic projection of the first electrical connection layer 112 on the first plane covers the orthographic projection of all the first conductive plugs 140 corresponding to the transistor 101 to be tested on the first plane; the surface of the drain 120 of the transistor 101 to be tested is a second plane, and the orthographic projection of the second electrical connection layer 113 on the second plane covers the orthographic projection of all the second conductive plugs 150 corresponding to the transistor 101 to be tested on the second plane. In this way, the first electrical connection layer 112 facilitates to uniformly apply the test voltage or the test current to the source 110 through each first conductive plug 140 corresponding to the transistor 101 to be tested, and the second electrical connection layer 113 facilitates to uniformly apply the test voltage or the test current to the drain 120 through each second conductive plug 150 corresponding to the transistor 101 to be tested, so that the working state of the transistor 101 to be tested in the test circuit is closer to the working state of the transistor 101 to be tested in the actual working circuit, thereby improving the accuracy of the electrical performance of the transistor 101 to be tested measured through the first electrical connection layer 112 and the second electrical connection layer 113, and improving the accuracy of the measured electrical performance and the saturation current value of the sub-transistor in the transistor 101 to be tested.

In addition, the surface of the substrate 104 is a third plane, and an orthogonal projection of the fifth conductive layer 124 on the third plane covers an orthogonal projection of all the fourth conductive plugs 114 on the substrate 104 on the third plane; the plane of the gate 130 away from the substrate 100 is a fourth plane, and the orthographic projection of the third conductive layer on the fourth plane covers the orthographic projection of all the third conductive plugs 131 on the gate 130 on the fourth plane. In this way, the fifth conductive layer 124 is beneficial to uniformly apply a test voltage or a test current to the substrate 104 through each fourth conductive plug 114 corresponding to the substrate 104, and the third conductive layer is beneficial to simulate a state of transmitting an electrical signal to the gate 130 in an actual working circuit, so that a working state of the transistor 101 to be measured in the test circuit is closer to a working state of the transistor 101 to be measured in the actual working circuit, and thus, the accuracy of the measured electrical performance of the transistor 101 to be measured is improved, and the accuracy of the measured electrical performance of the transistor 101 to be measured is improved.

In some embodiments, the step of patterning the first conductive layer 102 may further include: at least one third electrical connection layer 122 is formed, and each third electrical connection layer 122 is electrically connected in contact with only the first conductive plug 140 corresponding to one transistor except the transistor 101 to be tested. The step of patterning the second conductive layer 103 may further include: at least one fourth electrical connection layer 123 is formed, and each fourth electrical connection layer 123 is electrically connected in contact with only the second conductive plug 150 corresponding to one transistor except the transistor 101 to be tested. In fig. 2, as an example, a transistor except the transistor 101 to be tested includes a row of 4 sub-transistors, in practical application, the number of sub-transistors in a transistor except the transistor 101 to be tested is not limited.

Thus, when the transistors except the transistor 101 to be tested need to test the electrical performance, the states of the plurality of first conductive plugs 140 connected in parallel and the plurality of second conductive plugs 150 connected in parallel when a certain transistor except the transistor 101 to be tested actually works can be simulated through the third electrical connection layer 122 and the fourth electrical connection layer 123, so as to reduce the difference between the resistance at the source 110 in the test circuit and the resistance at the source 110 in the actually working circuit and reduce the difference between the resistance at the drain 120 in the test circuit and the resistance at the drain 120 in the actually working circuit, and the first electrical connection layer 112 and the second electrical connection layer 113 are beneficial to increasing the area where the source 110 and the drain 120 are in the working state, thereby being beneficial to improving the accuracy of the electrical performance of the certain transistor except the transistor 101 to be tested measured through the test circuit and being beneficial to improving the universality of the test method provided by the embodiment of the present application.

It should be noted that an orthographic projection of the third electrical connection layer 122 on the first plane may cover an orthographic projection of all the first conductive plugs 140 on the transistors corresponding to the third electrical connection layer 122 on the first plane, and an orthographic projection of the fourth electrical connection layer 123 on the second plane may cover an orthographic projection of all the second conductive plugs 150 on the transistors corresponding to the fourth electrical connection layer 123 on the second plane. In this way, when the transistors except the transistor 101 to be tested need to test the electrical performance, the third electrical connection layer 122 facilitates to uniformly apply the test voltage or the test current to the source 110 through each first conductive plug 140 corresponding to a certain transistor except the transistor 101 to be tested, and the fourth electrical connection layer 123 facilitates to uniformly apply the test voltage or the test current to the drain 120 through each second conductive plug 150 corresponding to a certain transistor except the transistor 101 to be tested, so that the working state of the certain transistor except the transistor 101 to be tested in the test circuit is closer to the working state of the certain transistor in the actual working circuit, thereby improving the accuracy of the electrical performance of the transistor 101 to be tested measured through the third electrical connection layer 122 and the fourth electrical connection layer 123.

It should be noted that, when the first conductive layer 102 and the second conductive layer 103 are configured in the same layer, patterning processes on the first conductive layer 102 and the second conductive layer 103 may be performed simultaneously, which is beneficial to simplifying process steps for preparing the first electrical connection layer 112 and the second electrical connection layer 113, and when the third electrical connection layer 122 and the fourth electrical connection layer 123 need to be formed, the first electrical connection layer 112, the second electrical connection layer 113, the third electrical connection layer 122, and the fourth electrical connection layer 123 may also be formed through the same patterning process, so as to simplify process steps for preparing the third electrical connection layer 122 and the fourth electrical connection layer 123. In other embodiments, the first electrical connection layer and the second electrical connection layer may be prepared in steps, and when the third electrical connection layer and the fourth electrical connection layer need to be formed, the third electrical connection layer and the fourth electrical connection layer may also be prepared in steps.

In some embodiments, the first conductive layer 102 and the second conductive layer 103 are both located within the device, and before the patterning process is performed on the first conductive layer 102 and the second conductive layer 103, the testing method further comprises: the device is planarized until the top surface of the first conductive layer 102 and the top surface of the second conductive layer 103 are exposed. In addition, when the first conductive layer 102, the second conductive layer 103, the fourth conductive layer 132, and the fifth conductive layer 124 are formed in the same layer, the top surface of the fourth conductive layer 132 and the top surface of the fifth conductive layer 124 are also exposed by the planarization process.

The first conductive layer 102 and the second conductive layer 103 may be patterned by using a focused ion beam technique. The focused ion beam technology is a novel micro-nano processing technology integrating the processes of appearance observation, positioning sample preparation, component analysis, film deposition and maskless etching, and the compatibility of the focused ion beam technology and the semiconductor technology can combine the two technologies, so that the precision and the speed of analysis and repair of materials, processes and devices in the microelectronic industry are greatly improved, and therefore, the first conductive layer 102 and the second conductive layer 103 are subjected to graphical processing through the focused ion beam technology, and the size precision of the formed first electric connection layer 112 and the second electric connection layer 113 is improved.

The process parameters of the focused ion beam technology include: the voltage is 20kV to 30kV, and the beam current is 5nA to 20nA. When the process parameters are within the range, the size precision of the formed first electrical connection layer 112 and the second electrical connection layer 113 is ensured to be higher, and meanwhile, the working efficiency of preparing the first electrical connection layer 112 and the second electrical connection layer 113 is improved. In some embodiments, the operation mode of the apparatus for forming a focused ion beam may be adjusted to an ion enhanced etching mode, which is advantageous for improving the alignment accuracy of the focused ion beam in the step of patterning the first conductive layer 102 and the second conductive layer 103, and the shapes of the first electrical connection layer 112 and the second electrical connection layer 113 that are preliminarily formed may be finely adjusted, thereby further improving the dimensional accuracy of the first electrical connection layer 112 and the second electrical connection layer 113 that are formed.

Referring to fig. 2 to 6, after forming the first and second electrical connection layers 112 and 113, the testing method further includes: variable test signals are provided to the first electrical connection layer 112, the second electrical connection layer 113 and the gate of the transistor 101 to be tested, and output signals of the first electrical connection layer 112 and the second electrical connection layer 113 are acquired.

Wherein the steps of providing a variable test signal and acquiring an output signal comprise: providing a first test signal to the first electrical connection layer 112 and obtaining a first output signal of the first electrical connection layer 112, wherein the first test signal is a constant voltage signal; providing a second test signal to the second electrical connection layer 113 and obtaining a second output signal of the second electrical connection layer 113; the gate 130 of the transistor under test 101 is provided with a third test signal, which is a voltage signal.

It should be noted that, in some embodiments, the first test signal may be 0V, that is, the source is in the 0V state by providing the first test signal to the first electrical connection layer 112. In addition, the voltage of the gate 130 when the transistor 101 under test is in the saturation state may be different for different types of transistors 101 under test, and thus, the voltage signal provided to the gate 130 by the third test signal may be different when the different types of transistors 101 under test are tested.

The method for providing the first test signal and the second test signal and obtaining the first output signal and the second output signal may be at least two of the following ways:

in some embodiments, referring to fig. 2 and 4, a first probe d through which a first test signal is provided and a second probe e through which a first output signal is obtained are provided; and providing a third probe c and a fourth probe b, acquiring a second output signal through the third probe c, and providing a second test signal through the fourth probe b, wherein the first output signal and the second test signal are both current signals, and the first test signal and the second output signal are both voltage signals.

The first probe d and the second probe e are in contact with and electrically connected with the first electrical connection layer 112, and the contact positions of the first probe d and the second probe e with the first electrical connection layer 112 are different; the third probe c and the fourth probe b are electrically connected to the second electrical connection layer 113 in contact, and the third probe c and the fourth probe b are in different contact positions with the first electrical connection layer 112.

Further, with continued reference to fig. 4, the testing method further comprises: providing a voltage detection module, wherein the voltage detection module is electrically connected between the first probe d and the third probe c, and the voltage detection module acquires a source drain voltage value based on a first test signal and a second output signal; and providing a current detection module, wherein the current detection module is electrically connected between the second probe e and the fourth probe b, and the current detection module acquires a source drain current value based on the first output signal and the second test signal.

A first closed circuit is formed among the transistor 101 to be tested, the first probe d, the voltage detection module and the third probe c, and the current in the first closed circuit is extremely small and is approximately zero, so that the voltage drop generated in the first closed circuit by the resistances of the first probe d and the third probe c, the contact resistance between the first probe d and the first electrical connection layer 112, and the contact resistance between the third probe c and the second electrical connection layer 113 is approximately zero. Therefore, in the first circuit closed loop, the source-drain voltage value can be accurately obtained through the voltage detection module, so that the accuracy of the measured electrical property of the transistor 101 to be measured is improved.

A second circuit closed loop is formed among the transistor 101 to be tested, the second probe e, the current detection module and the fourth probe b, and the first circuit closed loop and the second circuit closed loop cannot interfere with each other. In the second circuit closed loop, the currents flowing through the second probe e, the fourth probe b and the transistor 101 to be tested are the same, and the resistances of the second probe e and the fourth probe b, the contact resistance between the second probe e and the first electrical connection layer 112, and the contact resistance between the fourth probe b and the second electrical connection layer 113 do not interfere with the source-drain current value obtained by the current detection module.

Therefore, the method for measuring the transistor 101 to be measured through the first probe d, the second probe e, the third probe c and the fourth probe b is beneficial to improving the accuracy of the source-drain voltage value obtained through the voltage detection module, and is further beneficial to improving the accuracy of the measured electrical property of the transistor 101 to be measured.

In other embodiments, referring to fig. 5 and 6, a source probe g is provided, a first test signal is provided through the source probe g, and a first output signal is obtained; and providing a drain probe h, providing a second test signal and acquiring a second output signal through the drain probe h, wherein the first test signal and the second test signal are both voltage signals, and the first output signal and the second output signal are both current signals.

Further, with continued reference to fig. 6, the testing method further comprises: providing a voltage detection module, wherein the voltage detection module is electrically connected between a source probe g and a drain probe h, and the voltage detection device acquires a source and drain voltage value based on a first test signal and a second test signal; and providing a current detection module, wherein the current detection module is electrically connected between the source probe g and the drain probe h, and the current detection device acquires the current value of the source and the drain based on the first output signal and the second output signal.

In the above two embodiments, when the gates 130 of all the transistors are electrically connected to form the third conductive layer, the device further has a third conductive plug 131 in contact with the third conductive layer; the method of providing the third test signal to the gate 130 of the transistor under test 101 may include: a fifth probe a is provided, and a third test signal is provided to the third conductive plug 131 through the fifth probe a.

Wherein the fifth probe a is electrically connected to the third conductive plug 131 in contact therewith. In some embodiments, the surface of the third conductive plug 131 away from the substrate 100 is in contact with and electrically connected to the fourth conductive layer 132, and the fifth probe a indirectly provides the third test signal to the gate 130 by applying the third test signal to the fourth conductive layer 132.

In addition, when the substrate 104 in the device has the fourth conductive plug 114 and the fifth conductive layer 124 in contact and electrical connection with the fourth conductive plug 114, the testing method further includes: and providing a sixth probe f, and enabling the sixth probe f to be in contact and electrical connection with the fifth conductive layer 124, so that the sixth probe f applies a constant voltage signal to the substrate 104 through the fifth conductive layer 124 and the fourth conductive plug 114. In some embodiments, the constant voltage signal applied to the substrate 104 by the sixth probe f is 0V.

In the above various embodiments, after the output signals of the first electrical connection layer 112 and the second electrical connection layer 113 are acquired, the electrical performance of the transistor 101 to be tested is detected based on the output signals.

The electrical property of the transistor 101 to be tested includes a current-voltage characteristic curve.

In some embodiments, the voltage-current characteristic curve of the transistor 101 to be tested may be obtained based on the source-drain voltage value and the source-drain current value. In addition, when the voltage corresponding to the third test signal provided to the gate 130 of the transistor 101 to be tested is equal to the source-drain voltage value, the saturation current of the transistor 101 to be tested can be obtained according to the current-voltage characteristic curve of the transistor 101 to be tested. In other embodiments, based on the source-drain voltage value and the source-drain current value, the equivalent resistance of the transistor 101 to be tested at each stage may also be obtained.

It should be noted that when the voltage value corresponding to the third test signal provided to the gate 130 of the transistor 101 to be tested is equal to the source-drain voltage value, the transistor 101 to be tested is in a saturation state, and the source-drain current value obtained at this time is the saturation current value of the transistor 101 to be tested. In some embodiments, the voltage signal corresponding to the first test signal provided by the first probe d is 0V, the voltage value of the source and drain is changed from 0V to 12V by adjusting the test signal provided by the third probe c, the voltage signal applied to the substrate 104 by the sixth probe f is 0V, the gate voltage of the transistor 101 to be tested in the saturation state is 1.1V, that is, the voltage signal applied to the gate 139 by the fifth probe a is 1.1V, and when the voltage value of the source and drain is equal to the gate voltage 1.1V, the current value of the source and drain corresponding to the voltage value of the source and drain is the saturation current value of the transistor 101 to be tested.

In summary, by forming the first electrical connection layer 112 and the second electrical connection layer 113, it is beneficial to simulate a state where the plurality of first conductive plugs 140 are connected in parallel and the plurality of second conductive plugs 150 are connected in parallel when the transistor 101 to be tested actually works, so as to reduce a difference between a resistance at the source 110 in the test circuit and a resistance at the source 110 in the actually working circuit and reduce a difference between a resistance at the drain 120 in the test circuit and a resistance at the drain 120 in the actually working circuit, and the first electrical connection layer 112 and the second electrical connection layer 113 are beneficial to increase an area where the source 110 and the drain 120 are in a working state, so as to be beneficial to improve accuracy of electrical performance of the transistor 101 to be tested measured by the test circuit and improve accuracy of a saturation current value of the transistor 101 to be tested, thereby helping a person designing a product to know current driving capability of an important device in a mainstream product in the market and providing a reference for design of a new product.

Another embodiment of the present application further provides a test structure for implementing the test method.

Referring to fig. 1, the test structure includes: at least two transistors spaced apart from each other, the transistors having a source 110, a drain 120 and a gate 130, the transistors further having at least two first conductive plugs 140 contacting the source 110 and at least two second conductive plugs 150 contacting the drain 120, one of the transistors being a transistor 101 to be tested; a first electrical connection layer 112, wherein the first electrical connection layer 112 is only electrically connected with all the first conductive plugs 140 corresponding to the transistor 101 to be tested; and the second electrical connection layer 113, wherein the second electrical connection layer 113 is electrically connected with all the second conductive plugs 150 corresponding to the transistor 101 to be tested only in a contacting manner.

The test structure may further include: third electrical connection layers 122, wherein each third electrical connection layer 122 is electrically connected with the first conductive plug 140 corresponding to only one transistor except the transistor 101 to be tested in a contact manner; and fourth electrical connection layers 123, wherein each fourth electrical connection layer 123 is electrically connected in contact with only the second conductive plug 150 corresponding to one transistor except the transistor 101 to be tested.

Furthermore, the test structure has a substrate 100, the test structure further comprising: the third conductive layer formed by contact electric connection among the gates 130 of all the transistors, a third conductive plug 131 in contact with the third conductive layer, a fourth conductive layer 132 in contact electric connection with the third conductive plug 131, the substrate 104, a fourth conductive plug 114 on the substrate 104, and a fifth conductive layer 124 in contact electric connection with the fourth conductive plug 114.

It should be noted that the transistor 101 to be tested may include a plurality of sub-transistors, that is, a local region of the substrate 100 corresponding to one first conductive plug 140 in the transistor 101 to be tested is a source of one sub-transistor, the source 110 of the transistor 101 to be tested is formed by sources of a plurality of sub-transistors together, a local region of the substrate 100 corresponding to one second conductive plug 150 in the transistor 101 to be tested is a drain of one sub-transistor, the drain 120 of the transistor 101 to be tested is formed by drains of a plurality of sub-transistors together, in addition, one transistor except the transistor 101 to be tested may include one column of sub-transistors, in fig. 1, taking an example that one transistor 101 to be tested includes one column of 4 sub-transistors, and one transistor except the transistor 101 to be tested includes one column of 4 sub-transistors, in practical applications, the number of sub-transistors in the same transistor 101 to be tested and the number of sub-transistors in one transistor except the transistor 101 to be tested are not limited.

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the present application, and that various changes in form and details may be made therein without departing from the spirit and scope of the present application in practice. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the application, and it is intended that the scope of the application be limited only by the claims appended hereto.

Claims

1. A method for testing electrical properties of a device, comprising:

providing a device, wherein the device is provided with at least two transistors which are spaced from each other, the transistor is provided with a source electrode, a drain electrode and a grid electrode, the transistor is also provided with at least two first conductive plugs which are contacted with the source electrode and at least two second conductive plugs which are contacted with the drain electrode, the device is also provided with a first conductive layer and a second conductive layer, the first conductive layer is electrically connected with all the first conductive plug contacts corresponding to at least two transistors, the second conductive layer is electrically connected with all the second conductive plug contacts corresponding to at least two transistors, and one transistor is taken as a transistor to be tested;

carrying out graphical processing on the first conducting layer to form a first electric connection layer, wherein the first electric connection layer is only in contact and electric connection with all the first conducting plugs corresponding to the transistor to be tested;

carrying out graphical processing on the second conducting layer to form a second electric connection layer, wherein the second electric connection layer is only in contact and electric connection with all the second conducting plugs corresponding to the transistors to be tested;

providing variable test signals to the first electric connection layer, the second electric connection layer and the grid electrode of the transistor to be tested, and acquiring output signals of the first electric connection layer and the second electric connection layer;

and detecting the electrical property of the transistor to be detected based on the output signal.

2. A method of testing an electrical property of a device as claimed in claim 1, wherein the electrical property comprises a volt-ampere characteristic.

3. The method for testing electrical properties of a device according to claim 1, wherein prior to patterning said first conductive layer and said second conductive layer, said method further comprises: and carrying out planarization treatment on the device until the top surfaces of the first conducting layer and the second conducting layer are exposed.

4. A method for testing electrical properties of a device according to any of claims 1 to 3, wherein the method for providing variable test signals to the first electrical connection layer, the second electrical connection layer and the gate of the transistor under test and obtaining output signals of the first electrical connection layer and the second electrical connection layer comprises:

providing a first test signal to the first electric connection layer and acquiring a first output signal of the first electric connection layer, wherein the first test signal is a constant voltage signal;

providing a second test signal to the second electrical connection layer and obtaining a second output signal of the second electrical connection layer;

and providing a third test signal to the grid electrode of the transistor to be tested, wherein the third test signal is a voltage signal.

5. The method for testing electrical properties of a device according to claim 4, wherein the method of providing said first test signal and said second test signal and obtaining said first output signal and said second output signal comprises:

providing a first probe and a second probe, providing the first test signal through the first probe, and acquiring the first output signal through the second probe;

providing a third probe and a fourth probe, obtaining the second output signal through the third probe, and providing the second test signal through the fourth probe, wherein the first output signal and the second test signal are both current signals, and the first test signal and the second output signal are both voltage signals.

6. The method for testing electrical properties of a device of claim 5, wherein the method of providing said first test signal and said second test signal and obtaining said first output signal and said second output signal further comprises:

providing a voltage detection module, wherein the voltage detection module is electrically connected between the first probe and the third probe, and the voltage detection module acquires a source-drain voltage value based on the first test signal and the second output signal;

and providing a current detection module, wherein the current detection module is electrically connected between the second probe and the fourth probe, and the current detection module acquires a source drain current value based on the first output signal and the second test signal.

7. The method for testing electrical properties of a device according to claim 4, wherein the method of providing said first test signal and said second test signal and obtaining said first output signal and said second output signal comprises:

providing a source probe, providing the first test signal through the source probe and acquiring the first output signal;

and providing a drain probe, providing the second test signal and acquiring the second output signal through the drain probe, wherein the first test signal and the second test signal are both voltage signals, and the first output signal and the second output signal are both current signals.

8. The method for testing electrical properties of a device of claim 7, wherein the method of providing said first test signal and said second test signal and obtaining said first output signal and said second output signal further comprises:

providing a voltage detection module, wherein the voltage detection module is electrically connected between the source probe and the drain probe, and the voltage detection device acquires a source-drain voltage value based on the first test signal and the second test signal;

and providing a current detection module, wherein the current detection module is electrically connected between the source electrode probe and the drain electrode probe, and the current detection device acquires a source drain electrode current value based on the first output signal and the second output signal.

9. The method for testing the electrical performance of the device according to claim 6 or 8, wherein a volt-ampere characteristic curve of the transistor to be tested is obtained based on the source-drain voltage value and the source-drain current value; and when the voltage corresponding to the third test signal provided to the grid electrode of the transistor to be tested is equal to the source-drain voltage value, acquiring the saturation current of the transistor to be tested according to the volt-ampere characteristic curve of the transistor to be tested.

10. The method for testing the electrical performance of the device according to claim 5 or 7, wherein the contact electrical connection between the gates of all the transistors forms a third conductive layer, and the device further comprises a third conductive plug in contact with the third conductive layer;

a method of providing a third test signal to a gate of the transistor under test, comprising:

providing a fifth probe through which the third test signal is provided to the third conductive plug.

11. The method of claim 1, wherein the first conductive layer and the second conductive layer are patterned using a focused ion beam technique.

12. The method for testing electrical properties of a device as claimed in claim 11, wherein the process parameters of the focused ion beam technique comprise: the voltage is 20kV to 30kV, and the beam current is 5nA to 20nA.

13. The method for testing electrical properties of a device according to claim 1, wherein a surface of a source electrode of the transistor to be tested is a first plane, and an orthogonal projection of the first electrical connection layer on the first plane covers an orthogonal projection of all the first conductive plugs corresponding to the transistor to be tested on the first plane; the surface of the drain electrode surface of the transistor to be tested is a second plane, and the orthographic projection of the second electric connection layer on the second plane covers the orthographic projection of all the second conductive plugs corresponding to the transistor to be tested on the second plane.

14. The method for testing electrical properties of a device according to claim 1, wherein the step of patterning the first conductive layer further comprises:

and forming at least one third electric connection layer, wherein each third electric connection layer is only in contact and electric connection with the first conductive plug corresponding to one transistor except the transistor to be tested.

15. The method for testing electrical properties of a device according to claim 1, wherein the step of patterning the second conductive layer further comprises:

and forming at least one fourth electric connection layer, wherein each fourth electric connection layer is only in contact and electric connection with the second electric conduction plug corresponding to one transistor except the transistor to be tested.

16. A test structure for carrying out the test method according to any one of claims 1 to 15, comprising:

the transistor is provided with a source electrode, a drain electrode and a grid electrode, and is also provided with at least two first conductive plugs which are contacted with the source electrode and at least two second conductive plugs which are contacted with the drain electrode, wherein one transistor is used as a transistor to be tested;

the first electric connection layer is only in contact electric connection with all the first conductive plugs corresponding to the transistors to be tested;

and the second electric connection layer is only in contact electric connection with all the second conductive plugs corresponding to the transistors to be tested.

17. The test structure of claim 16, comprising:

each third electric connection layer is only in contact electric connection with the first electric conduction plug corresponding to one transistor except the transistor to be tested;

and each fourth electric connection layer is only in contact electric connection with the second electric conduction plug corresponding to one transistor except the transistor to be tested.