CN115865639A - Device for realizing main and standby redundancy of network ports of multi-processor board card - Google Patents
Device for realizing main and standby redundancy of network ports of multi-processor board card Download PDFInfo
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Abstract
The invention discloses a device for realizing the redundancy of main and standby network ports of a multi-processor board card; belonging to the field of computer network communication. The method is realized based on a hardware circuit, the network port connection state is judged by detecting a network port indicator lamp through an FPGA, and a processor controls network port switching through a relay according to the network port state to realize network redundancy; when the main network port is switched to the standby network port, the main network port is monitored through the single chip microcomputer, and once the main network port is detected to be recovered to be normal, the processor controls the relay to be switched to the main network port, so that the main network port is used preferentially. The system comprises: the system comprises a network exchange chip, two groups of signal relays, a programmable logic device (FPGA), a general processor and a singlechip with a network port. The method realizes the network port redundancy by using hardware circuit switching, does not have the risk of network storm, and has high reliability; the exchange chip register does not need to be read and written, and the design difficulty is small; the preferential use of the main network port can be realized.
Description
Technical Field
The invention belongs to the field of computer network communication, and particularly relates to a device for realizing main and standby redundancy of network ports of a multi-processor board card.
Background
With the improvement of the integration level of the circuit board, a plurality of processors with network ports may be placed on one circuit board, the circuit board is required to have two network ports to the outside, the two network ports are respectively connected to different network switches, and when a network fault occurs to a main network port, the main network port can be quickly switched to a standby network port, so that network redundancy is realized.
The traditional solution is to add a network switch chip on the circuit board, connect the network ports of multiple processors to the network switch chip respectively, and the network switch chip is to go out two network ports. This presents a problem in that if the two portals are connected to the same subnet, a network loop occurs, resulting in a network storm. In order to avoid network loops, software is required to read the port status register of the switching chip at regular time to obtain the link status of the two ports, one port is enabled according to the link status of the port, and the other port is disabled. The method requires that the processor can read the register in the network port switching chip, the small port network switching chip is mostly configured by hardware pins, and the original factory does not open the relevant document of the register, which increases the difficulty of software design. Moreover, the software control method has poor reliability and risks that two network ports are enabled simultaneously.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: how to implement portal redundancy for a circuit board containing multiple processors.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows:
a device for realizing main and standby redundancy of network ports of a multi-processor board card comprises a network switching chip, an FPGA, a general processor, a singlechip, a first group of signal relays and a second group of signal relays;
the network port pins of the network switching chip are respectively connected with the general processor and the plurality of common processors, the external network port pins are connected with the common points of the first group of relays, and the indicator lamp pins of the external network port are connected with one state input pin of the FPGA; the normally closed point of the first group of relays is connected with the normally closed point of the second group of relays, and the normally open point of the first group of relays is connected with the standby network port; the common point of the second group of relays is connected with the main network port, and the normally open point of the second group of relays is connected with the network port of the singlechip; the output pin of the singlechip is connected with the other state input pin of the FPGA; a static storage controller pin of the general processor is connected with an FPGA pin and used for reading and writing a register in the FPGA; the level control output pin of the FPGA is connected with the control input pins of the two groups of relays;
the FPGA is used for monitoring the state of an external network port indicator lamp of the network switching chip and the state of a main network output by the singlechip in real time and reporting the network state to the general processor; the power supply is also used for outputting high and low levels to control the suction state of the two groups of relays according to the network port switching control instruction output by the general processor;
the general processor is used for judging the switching of the main network port and the standby network port according to the state reported by the FPGA, the system is powered on to use the main network port by default, when the state of the external network port indicator lamp of the network switching chip is abnormal, the switching is judged to be switched to the standby network port, when the state of the main network port is normal, the switching is judged to be switched back to the main network port, and a network port switching control instruction is output to the FPGA;
the two groups of relays are used for switching under the control of the FPGA, and when the first group of relays is switched to the standby network port, the second group of relays switches the main network port to the singlechip network port;
the single chip microcomputer is used for monitoring the main network port and transmitting the state of the main network port to the FPGA.
Furthermore, the FPGA comprises a network port state register and a network port switching register, when the external network port indicator lamp of the network switching chip is turned off for more than a set time, the main network port is judged to be disconnected, the network port state is written into the lowest bit0 of the network port state register by the FPGA, the state bit is 0 when the main network port is normal, and the state bit is 1 when the main network port is disconnected.
Further, after power-on, the initial value of the network port switching register is 0x00, the level control output pin of the FPGA outputs low level, the relay is released, and the network switching chip switches the external network port to the main network port; the general processor reads the net port state register at set time intervals, when the lowest bit0 is 0, the current net port is normal, the main net port is still used, when the lowest bit0 is 1, the current net port is abnormal, the general processor writes 0x01 into the net port switching register, the level control output pin of the FPGA outputs high level, the relay is attracted, the external net port is switched to the standby net port, and the main net port is switched to the singlechip net port.
Further, when the standby network port is used, the single chip microcomputer monitors the state of the main network port, informs the FPGA of the state of the main network port through an IO (input/output) level, and the FPGA writes the state of the main network port into the second bit1 of the network port state register.
Further, when the standby network port is used, the general processor reads the network port state register at set time intervals, when bit1 of the network port state register is 0, the main network port is judged to be recovered to be normal, 0x00 is written into the network port switching register, the level control output pin of the FPGA outputs low level, the relay is released, the external network port is switched to the main network port, and meanwhile the main network port is disconnected with the network port of the single chip microcomputer.
Furthermore, the relay is controlled by a triode, when the input level of the base electrode of the triode is low, the triode is closed, and the relay is in a release state; when the input level of the base electrode of the triode is high, the triode is conducted, and the relay is in a pull-in state.
Drawings
FIG. 1 is an overall block diagram of the present invention.
FIG. 2 is a control flow chart of the present invention.
Fig. 3 is a circuit for switching a network port according to the present invention.
Detailed Description
The following describes in further detail embodiments of the method of the present invention with reference to the accompanying drawings.
As shown in fig. 1, processors 1 to 4 are a plurality of processors with network ports on a board, where processor 1 is a general-purpose processor for processing network port switching; the network ports of the several processors are connected to a network switching chip. The main network port and the standby network port are two external network ports, and the priority of the main network port is high.
A device for realizing the main and standby redundancy of the network ports of a multi-processor board card comprises: the system comprises a network switching chip, two groups of signal relays (a relay 1 and a relay 2), a programmable logic device (FPGA), a general processor (a processor 1) and a single chip microcomputer with a network port. The network switching chip adopted by the invention is a five-port 10/100M Ethernet switching chip RTL8305NB by Ri, the signal relay is a macro-sending double-pole double-throw single-steady-state signal relay HFD4/3-SR, the FPGA is EG4X20BG256 of Shanghai' an circuit, the general processor is GD32F407VGT which is a million-easy-to-innovate one, and the singlechip is GD32F107RCT6 which is a million-easy-to-innovate one.
The connection of the device is shown in fig. 1. The network ports of the four processors on the circuit board are respectively connected to the network ports of the network switching chip. The processor 1 is a general-purpose processor GD32F407VGT6, which is connected to the FPGA through its static memory controller interface, and reads and writes registers inside the FPGA. The FPGA meets the time sequence requirement of the processor for reading and writing the external memory through VHDL programming, and the function of the register is realized.
One state input pin of the FPGA is connected to an indicator lamp pin of a network port 5 of the network switching chip, and the state of the network port indicator lamp is monitored in real time. When the network port connection is normal, the network port indicator lamp flashes at the frequency of 32ms on and 32ms off; when the net mouth is disconnected, the indicator light is turned off. When the indicator light is turned off for more than 200ms, the network port is considered to be disconnected. And the other state input pin of the FPGA is connected to one output pin of the singlechip, so that the state of the main network port is monitored in real time. When the main network port is connected normally, the output pin of the single chip outputs low level, and when the main network port is disconnected, the output pin of the single chip outputs high level. And the level control output pin of the FPGA is connected to the control input pins of the two groups of relays to control the switching of the relays.
The FPGA comprises a network port state register and a network port switching register, wherein the network port state register and the network port switching register are two eight-bit registers defined in the FPGA, and the power-on default value is 0x00. The FPGA writes the state of the external network port into the lowest bit0 of the network port state register, wherein the bit0 is 0 when the network is normal, and the bit0 is 1 when the network is disconnected; when the standby network port is used, the singlechip monitors the idle main network port and informs the FPGA of the state of the main network port through an output pin, wherein the low level indicates that the main network port is normal, and the high level indicates that the main network port is disconnected; and the FPGA writes the state of the main port into a second bit1 of the port state register, the main port is set to be 0 when being normal, and the main port is set to be 1 when being disconnected. And the general processor reads the network port state register once every 2 seconds, and writes a numerical value into a network port switching register in the FPGA for switching control according to the value of the network port state register. The lowest bit0 of the network port switching register is defined as a network port switching bit, when bit0=0, the network port switching pin of the FPGA outputs low level, the relay is released, and the relay is switched to a main network port; when bit0=1, the network port switching pin of the FPGA outputs high level, the relay is closed, the relay is switched to the standby network port, and meanwhile, the single chip microcomputer starts to monitor the main network port.
The network port switching control flow is as shown in fig. 2, after power-on, the initial value of the network port switching register is 0x00, the level control output pin of the fpga outputs low level, the relay is released, and the network switch chip switches the external network port to the main network port. The general processor reads the network port state register every 2 seconds, and when the lowest bit0 is 0, the state of the currently used network port is normal, and the main network port is still used; when the lowest bit0 is 1, the state of the currently used network port is abnormal, the general processor writes 0x01 into the network port switching register, the level control output pin of the FPGA outputs high level, the relay is closed, the external network port is switched to the standby network port, and meanwhile the idle main network port is switched to the singlechip network port.
When the standby network port is used, the single chip microcomputer monitors the state of the main network port, informs the FPGA of the state of the main network port through IO, the FPGA writes the state of the main network port into a second bit1 of the network port state register, the main network port is set to 0 when the main network port returns to normal, and the main network port is set to 1 when the main network port is disconnected; the general processor reads the network port state register every 2 seconds, when bit1 of the network port state register is 0, the main network port is recovered to be normal, the general processor writes 0x00 into the network port switching register, the level control output pin of the FPGA outputs low level, the relay is released, the external network port is switched to the main network port, and meanwhile the main network port is disconnected from the network port of the single chip microcomputer.
The network port switching circuit is shown in fig. 3, relays K1 and K2 are a first group of relays, relays K3 and K4 are a second group of relays, and control signals of the four relays come from level control output pins of the same FPGA. The common point of the first group of relays K1 and K2 is connected to an external network port of the network exchange chip, the normally closed point is connected with the normally closed point of the second group of relays, and the normally open point is connected with an external standby network port. The common point of the second group of relays K3 and K4 is connected with an external main network port, the normally closed point is connected with the normally closed point of the first group of relays, and the normally open point is connected to the singlechip network port.
The relay is controlled by the triode, when the input level of the base electrode of the triode is low, the triode is closed, and the relay is in a release state; when the input level of the base electrode of the triode is high, the triode is conducted, and the relay is in a pull-in state. And a base electrode control signal of the triode is connected to a level control output pin of the FPGA. The freewheeling diode next to the relay is shown to release the current from the coil when the relay is turned off.
A signal relay can control the switching of a pair of differential signals; the hundred million net mouth has two pairs of differential signals, and two relays are needed. Furthermore, there are four pairs of differential signals for the gigabit network port, requiring four relays.
In summary, the above is only a preferred application example of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (6)
1. A device for realizing main and standby redundancy of network ports of a multi-processor board card is characterized by comprising a network switching chip, an FPGA, a general processor, a singlechip, a first group of signal relays and a second group of signal relays;
the network port pins of the network switching chip are respectively connected with the general processor and the plurality of common processors, the external network port pins are connected with the common points of the first group of relays, and the indicator lamp pins of the external network port are connected with one state input pin of the FPGA; the normally closed point of the first group of relays is connected with the normally closed point of the second group of relays, and the normally open point of the first group of relays is connected with the standby network port; the common point of the second group of relays is connected with the main network port, and the normally open point of the second group of relays is connected with the network port of the singlechip; the output pin of the singlechip is connected with the other state input pin of the FPGA; a static storage controller pin of the general processor is connected with an FPGA pin and used for reading and writing a register in the FPGA; the level control output pin of the FPGA is connected with the control input pins of the two groups of relays;
the FPGA is used for monitoring the state of an external network port indicator lamp of the network switching chip and the state of a main network output by the singlechip in real time and reporting the network state to the general processor; the universal processor is also used for outputting high and low levels to control the suction state of the two groups of relays according to a network port switching control instruction output by the universal processor;
the general processor is used for judging the switching of the main network port and the standby network port according to the state reported by the FPGA, the system is powered on to use the main network port by default, when the state of the external network port indicator lamp of the network switching chip is abnormal, the switching is judged to be switched to the standby network port, when the state of the main network port is normal, the switching is judged to be switched back to the main network port, and a network port switching control instruction is output to the FPGA;
the two groups of relays are used for switching under the control of the FPGA, and when the first group of relays is switched to the standby network port, the second group of relays switches the main network port to the singlechip network port;
the single chip microcomputer is used for monitoring the main network port and transmitting the state of the main network port to the FPGA.
2. The device for realizing the main and standby redundancy of the network ports of the multiprocessor board card according to claim 1, wherein the FPGA comprises a network port state register and a network port switching register, when the external network port indicator lamp of the network switch chip is turned off for more than a set time, the disconnection of the main network port is determined, the FPGA writes the network port state into the lowest bit0 of the network port state register, the state bit is 0 when the main network port is normal, and the state bit is 1 when the disconnection occurs.
3. The apparatus according to claim 2, wherein the initial value of the network port switching register after power-on is 0x00, the output pin of the fpga outputs a low level, the relay is released, and the network switch chip switches the external network port to the main network port; the general processor reads the network port state register at set time intervals, when the lowest bit0 is 0, the current network port using state is normal, the main network port is still used, when the lowest bit0 is 1, the current network port using state is abnormal, the general processor writes in the network port switching register by 0x01, the level control output pin of the FPGA outputs high level, the relay is attracted, the external network port is switched to the standby network port, and meanwhile, the main network port is switched to the singlechip network port.
4. The device for realizing the main/standby redundancy of the network ports of the multiprocessor board card according to claim 3, wherein when the standby network port is used, the single chip monitors the state of the main network port, informs the FPGA of the state of the main network port through an IO level, and the FPGA writes the state of the main network port into the second bit1 of the network port state register.
5. The apparatus as claimed in claim 4, wherein when the standby port is used, the general purpose processor reads the port status register at set time intervals, when bit1 of the port status register is 0, determines that the main port is recovered to normal, writes 0x00 into the port switching register, outputs a low level from the level control output pin of the fpga, releases the relay, switches the external port to the main port, and simultaneously disconnects the main port from the network port of the single chip microcomputer.
6. The device for realizing the main and standby redundancy of the network ports of the multi-processor board card according to claim 1, wherein the relay is controlled by a triode, when the input level of the base electrode of the triode is low, the triode is closed, and the relay is in a release state; when the input level of the base electrode of the triode is high, the triode is conducted, and the relay is in a pull-in state.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030056105A (en) * | 2001-12-27 | 2003-07-04 | 한국전자통신연구원 | Duplication board system and active/standby decision method and thereof |
| CN212847014U (en) * | 2020-08-18 | 2021-03-30 | 北京华电众信技术股份有限公司 | Control system |
| CN216772405U (en) * | 2021-12-31 | 2022-06-17 | 深圳微步信息股份有限公司 | Double-network-port single-pass switching circuit and terminal equipment |
| CN217216609U (en) * | 2022-05-16 | 2022-08-16 | 大连市共进科技有限公司 | Network port switching device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030056105A (en) * | 2001-12-27 | 2003-07-04 | 한국전자통신연구원 | Duplication board system and active/standby decision method and thereof |
| CN212847014U (en) * | 2020-08-18 | 2021-03-30 | 北京华电众信技术股份有限公司 | Control system |
| CN216772405U (en) * | 2021-12-31 | 2022-06-17 | 深圳微步信息股份有限公司 | Double-network-port single-pass switching circuit and terminal equipment |
| CN217216609U (en) * | 2022-05-16 | 2022-08-16 | 大连市共进科技有限公司 | Network port switching device |
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