CN215897892U

CN215897892U - Video processing circuit and video monitoring equipment

Info

Publication number: CN215897892U
Application number: CN202121551151.8U
Authority: CN
Inventors: 刘志凡; 范章华
Original assignee: Streamax Technology Co Ltd
Current assignee: Streamax Technology Co Ltd
Priority date: 2021-07-08
Filing date: 2021-07-08
Publication date: 2022-02-22
Anticipated expiration: 2031-07-08

Abstract

The application is suitable for the technical field of video monitoring, and provides a video processing circuit and video monitoring equipment, and the circuit includes: at least one port; the network switching unit is connected with at least one port and used for outputting an interrupt signal and the video data to the video data processing unit when detecting that video data are input into any one port; a video data processing unit for determining a second target port of the input video data based on status information of the respective ports when the interrupt signal and the video data are received; setting the value of the interrupt event flag bit as a first preset value; awakening and executing a preset process; when the preset process is executed, the preset process is used for realizing the operation of associating the video data with the target display interface corresponding to the second target port; and after the preset process is executed, setting the value of the interrupt event flag bit as a second preset value, and controlling the preset process to enter a dormant state. Thereby improving the resource utilization and cost-effectiveness ratio of the video data processing unit in the video processing circuit.

Description

Video processing circuit and video monitoring equipment

Technical Field

The application relates to the technical field of video monitoring, in particular to a video processing circuit and video monitoring equipment.

Background

In recent years, the popularization and construction of safe cities and smart communities greatly promote the rapid development of the security monitoring industry. With the rapid development of the security monitoring industry, various video monitoring devices emerge in the market. The video monitoring device generally comprises a video data processing unit and a network switching unit, and in a specific application, the input of multiple paths of video data can be realized by expanding a plurality of ports on the network switching unit. The network switching unit can send the video data input from different ports to the video data processing unit, and the video data processing unit can complete the detection of the ports for inputting the video data, the processing of the video data and other operations.

In the detection of ports, the existing video data processing unit generally detects status information of each port based on a polling mechanism, and determines a port for inputting video data according to the status information of each port. However, since the polling mechanism is designed based on program logic of circular scanning, it occupies more system resources of the video data processing unit, thereby reducing resource utilization of the video data processing unit, resulting in a lower cost-effectiveness ratio of the video data processing unit in terms of input detection of video data.

SUMMERY OF THE UTILITY MODEL

In view of this, embodiments of the present application provide a video processing circuit and a video monitoring apparatus, so as to solve the technical problem that a video data processing unit in an existing video processing circuit has a low resource utilization rate and a low cost-effectiveness ratio in the aspect of input detection of video data.

A first aspect of an embodiment of the present application provides a video processing circuit, including:

at least one port;

the network switching unit is connected with the at least one port and used for generating an interrupt signal when detecting that video data are input into any one port and outputting the interrupt signal and the video data to the video data processing unit;

the video data processing unit is connected with the network switching unit, and is used for acquiring the state information of the at least one port when the interrupt signal and the video data are received, and determining a second target port for inputting the video data based on the state information; setting the value of the interrupt event flag bit as a first preset value after the second target port is determined; awakening a preset process in a dormant state and executing the preset process; after the preset process is executed, setting the value of the interrupt event flag bit as a second preset value, and controlling the preset process to enter the dormant state; the first preset value is used for indicating that a port event of the network switching unit is triggered, and the second preset value is used for indicating that the port event is not triggered; and the preset process is used for realizing the operation of associating the video data with a target display interface corresponding to the second target port when executed.

A second aspect of an embodiment of the present application provides a video monitoring apparatus, including: a display device, a video capture device and a video processing circuit as described above in relation to the first aspect; the video processing circuit is connected with the display device and the video acquisition device; the video acquisition device is used for acquiring video data and sending the video data to the video processing circuit through the at least one port.

The video processing circuit and the video monitoring equipment provided by the embodiment of the application have the following beneficial effects:

according to the video processing circuit provided by the embodiment of the application, when the network switching unit detects that video data is input at any port, an interrupt signal is generated, and the interrupt signal and the input video data are sent to the video data processing unit, the video data processing unit acquires the state information of each port after receiving the interrupt signal from the network switching unit, detects a second target port of the input video data based on the state information of each port, and awakens a preset process in a dormant state to associate the video data with a target display interface corresponding to the second target port; and the video data processing unit can be enabled to enter the dormant state again after the preset process is executed, and the system resources of the video data processing unit can be released after the preset process enters the dormant state, so that compared with the prior art that the port detection is realized by adopting a polling mechanism, the system resources of the video data processing unit are greatly saved, and the resource utilization rate and the cost effectiveness ratio of the video data processing unit are improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.

Fig. 1 is a schematic structural diagram of a video processing circuit according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of a video processing circuit according to another embodiment of the present application;

fig. 3 is a schematic circuit diagram of a video processing circuit according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of a video monitoring device according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

It should be noted that the words "first", "second", and the like are used in the embodiments of the present application to distinguish the same items or similar items having substantially the same functions and actions. For example, the first indicator light and the second indicator light are only used for distinguishing different indicator lights, and the sequence of the indicator lights is not limited. Those skilled in the art will appreciate that the terms "first," "second," etc. do not denote any order or quantity, nor do the terms "first," "second," etc. denote any order or importance.

Additionally, the words "exemplary" or "such as" are used herein to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g.," is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.

In the detection of ports, the conventional video data processing unit generally detects status information of each port based on a polling mechanism, and determines a port to which video data is input according to the status information of each port. However, since the polling mechanism is designed based on program logic of circular scanning, it occupies more system resources of the video data processing unit, thereby reducing resource utilization of the video data processing unit, resulting in a lower cost-effectiveness ratio of the video data processing unit in terms of input detection of video data.

In addition, in order to enable a user to intuitively know the state of each port (for example, whether the port has video data input or not), at least one indicator lamp may be configured for each port, and the state of the corresponding port is indicated by the on-off state of the indicator lamp. In order to realize the control of the indicator light, the network switching unit is generally required to have an indicator light control function, which not only increases the material cost of the network switching unit and causes the cost of the video monitoring device to increase, but also limits the model selection range of the network switching unit (i.e., reduces the model selection range of the network switching unit), and reduces the adaptability of the video monitoring device to the network switching unit.

Based on this, the embodiment of the present application first provides a video processing circuit. Referring to fig. 1, fig. 1 is a schematic structural diagram of a video processing circuit according to an embodiment of the present disclosure. As shown in fig. 1, the video processing circuit 10 may include: at least one port P _1 to P _ n, a network switching unit 11 and a video data processing unit 12. Wherein n is a positive integer, and n can be set according to actual requirements, and is not limited herein. For example, when n is 8, the video processing circuit 10 includes 8 ports P _1 to P _ 8.

Specifically, at least one port P _1 to P _ n is used for receiving video data and transmitting the video data to the network switching unit 11.

In a specific application, the at least one port P _1 to P _ n may be connected to a video capture device to receive video data from the video capture device. In one possible implementation, different ports may be connected to different video capture devices; in another possible implementation, different ports may be connected to the same video capture device. By way of example and not limitation, at least one port P _ 1-P _ n may be an Ethernet interface. The video capture device may be a webcam.

It should be noted that, in this embodiment, when video data is input into any one of the ports, a port event of the network switching unit 11 is triggered. Of course, in other embodiments, when the connection state of any one port and the network switching unit 11 changes from the normal connection state to the disconnection state, or changes from the disconnection state to the normal connection state, a port event of the network switching unit 11 may also be triggered, and the port event of the network switching unit 11 may be defined according to actual requirements, and is not limited herein.

Specifically, the network switching unit 11 is connected to at least one port P _1 to P _ n, and the network switching unit 11 is configured to generate an interrupt signal when detecting that video data is input to any one of the ports, and output the interrupt signal and the video data input from any one of the ports to the video data processing unit 12.

In a specific embodiment, the network switching unit 11 may include a data transmitting terminal D1, a data managing terminal D3, an interrupt signal output terminal INT1, and at least one video data transmitting terminal for respectively connecting at least one port P _1 to P _ n. Based on this, the network switching unit 11, upon detecting that video data is input to any one of the ports, may output an interrupt signal to the video data processing unit 12 through its interrupt signal output terminal INT1, and output video data to the video data processing unit 12 through its data transmission terminal D1.

In one possible implementation, the interrupt signal may be a low level signal. Based on this, when detecting that video data is input to any one of the ports, the network switching unit 11 may output a low level signal to the video data processing unit 12 through the interrupt signal output terminal INT 1; the network switching unit 11 may output a high level signal to the video data processing unit 12 through the interrupt signal output terminal INT1 when detecting that all ports have no video data input. That is, when no video data is input to all the ports P _1 to P _ n, the network switching unit 11 may output a high level signal to the video data processing unit 12 through the interrupt signal output terminal INT 1; when at least one port has video data input, the network switching unit 11 may output a low level signal to the video data processing unit 12 through the interrupt signal output terminal INT 1.

Specifically, the video data processing unit 12 is connected to the network switching unit 11, and the video data processing unit 12 is configured to obtain status information of at least one port P _1 to P _ n when receiving the interrupt signal and the video data from the network switching unit 11, and determine a second target port of the input video data based on the status information of the at least one port P _1 to P _ n; setting the value of the interrupt event flag bit as a first preset value after the second target port is determined; awakening a preset process in a dormant state and executing the preset process; and after the preset process is executed, setting the value of the interrupt event flag bit as a second preset value, and controlling the preset process to enter a dormant state.

In this embodiment, the first preset value is used to indicate that a port event of the network switching unit 11 is triggered, and the second preset value is used to indicate that a port event of the network switching unit 11 is not triggered. Illustratively, a port event may include, but is not limited to, a video data input event. The first preset value and the second preset value may be set according to actual requirements, for example, the first preset value may be 1, and the second preset value may be 0, that is, when the value of the interrupt event flag is 1, it indicates that a port event of the network switching unit 11 is triggered, for example, it indicates that at least one port has video data input; when the value of the interrupt event flag bit is 0, it indicates that the port event of the network switching unit 11 is not triggered, for example, that all ports have no video data input.

The video data processing unit 12 may receive and process the interrupt signal output by the network switching unit 11 using a hardware interrupt mechanism. Based on this, in a specific embodiment, the video data processing unit 12 may include an interrupt signal input terminal INT2 and a data transmission terminal D2, the interrupt signal transmission terminal INT2 of the video data processing unit 12 is connected with the interrupt signal output terminal INT1 of the network switching unit 11, and the data transmission terminal D2 of the video data processing unit 12 is connected with the data transmission terminal D1 of the network switching unit 11. The video data processing unit 12 may receive the interrupt signal from the network switching unit 11 through its interrupt signal input terminal INT2 and the video data from the network switching unit 11 through its data transmission terminal D2.

In another embodiment, the video data processing unit 12 may further include a data management terminal D4, and the data management terminal D4 of the video data processing unit 12 may be connected to the data management terminal D3 of the network switching unit 11. The network switching unit 11 may include at least one status register corresponding to at least one port P _1 to P _ n, and each status register is used to store status information of its corresponding port.

The status information of the port may include, but is not limited to, a data exchange status and a connection status between the port and the network switching unit 11. Wherein, the data exchange state may include: with and without data exchange. For example, when the data exchange state of a certain port is data exchange, the value of the port active state bit in the state register corresponding to the port may be 1; when the data exchange state of a certain port is no data exchange, the value of the port active state bit in the state register corresponding to the port may be 0. The connection state may include: normally connected and disconnected. For example, when a port is normally connected to the network switching unit 11, the value of the port connection status bit in the status register corresponding to the port may be 1; when the connection state of a port and the network switching unit 11 is disconnected, the value of the port connection state bit in the state register corresponding to the port may be 0.

Based on this, the video data processing unit 12 can acquire the status information of at least one of the ports P _1 to P _ n from the network switching unit 11 through the data management terminal D4 of the video data processing unit 12 after receiving the interrupt signal and the video data from the network switching unit 11. Specifically, when the video data processing unit 12 receives the interrupt signal and the video data from the network switching unit 11, it may obtain values of status registers corresponding to the ports P _1 to P _ n from the network switching unit 11, determine a first target port whose connection state with the network switching unit 11 is a normal connection state currently based on values of port connection status bits in the status registers corresponding to the ports P _1 to P _ n, and determine a second target port to which the video data is input based on values of port active status bits in the status registers corresponding to the ports P _1 to P _ n.

For example, assuming that the video data processing unit 12 detects that the values of the port connection status bits in the status registers corresponding to the ports P _1 to P _ n are all 1, the video data processing unit 12 determines that the ports P _1 to P _ n are all normally connected to the network switching unit 11 currently, that is, the ports P _1 to P _ n are all the first target ports at this time. Assuming that the video data processing unit 12 detects that the value of the port active status bit in the status register corresponding to the port P _1 is 1, and the values of the port active status bits in the status registers corresponding to the other ports are all 0, the video data processing unit 12 determines that the port P _1 currently has data exchange with the network switching unit 11, and at this time, the port P _1 is a second target port, that is, the video data received by the video data processing unit 12 is input from the port P _ 1.

In this embodiment, the preset process may be used to implement, when executed by the video data processing unit 12, an operation of associating the video data input from the second target port with a target display interface corresponding to the second target port. Wherein, the display interface refers to a software interface for outputting video data to a user interface.

In a specific application, the video data processing unit 12 may be a system on chip (SoC) having a video encoding function and a video decoding function, and more specifically, the video data processing unit 12 may be a SoC loaded with a Linux operating system.

The network switching unit 11 may comprise a network switch chip.

As can be seen from the above, in terms of hardware structure, the video processing circuit provided in this embodiment has an interrupt signal output end on the network switching unit and an interrupt signal input end on the video data processing unit, so that the network switching unit can generate an interrupt signal when detecting that video data is input into any port connected to the network switching unit, and send the interrupt signal together with the input video data to the video data processing unit; in the aspect of programming, the video data processing unit acquires the state information of each port after receiving an interrupt signal from the network switching unit, detects a second target port of input video data based on the state information of each port, and awakens a preset process in a dormant state to associate the video data with a target display interface corresponding to the second target port; and the video data processing unit can be enabled to enter the dormant state again after the preset process is executed, and the system resources of the video data processing unit can be released after the preset process enters the dormant state, so that compared with the prior art that the port detection is realized by adopting a polling mechanism, the system resources of the video data processing unit are greatly saved, and the resource utilization rate and the cost effectiveness ratio of the video data processing unit are improved.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a video processing circuit according to another embodiment of the present disclosure. As shown in fig. 2, compared with the embodiment corresponding to fig. 1, the video processing circuit 10 in the present embodiment further includes: at least one first indicator lamp L1_ 1-L1 _ n corresponding to the at least one port P _ 1-P _ n, respectively, and a first indicator lamp control unit 13. Wherein, the first indicator light control unit 13 is connected with the video data processing unit 12 and at least one first indicator light L1_ 1-L1 _ n.

Since each port corresponds to one first indicator light, the number of the first indicator lights is equal to the number of the ports. For example, the port P _1 may correspond to the first indicator lamp L1_1, the port P _2 may correspond to the first indicator lamp L1_2, and the port P _ n may correspond to the first indicator lamp L1_ n.

In this embodiment, the first indicator lamps L1_1 to L1_ n are used for indicating the connection status between the corresponding ports and the network switching unit 11. In a specific application, the states of the first indicator lights L1_1 to L1 — n may include an on state and an off state. For example, the present embodiment may indicate that the connection state of the port corresponding to the first indicator lamp and the network switching unit 11 is the normal connection state through the lighting state of the first indicator lamp, and indicate that the connection state of the port corresponding to the first indicator lamp and the network switching unit 11 is the disconnection state through the extinguishing state of the first indicator lamp. Wherein the lighting state may include a normally-on state.

Specifically, the video data processing unit 12 is further configured to determine, according to the state information of the ports P _1 to P _ n, a first target port of which the connection state with the network switching unit 11 is a normal connection state from the ports P _1 to P _ n after the state information of the ports P _1 to P _ n is acquired, and send a first indicator light control instruction to the first indicator light control unit 13. The first indicator light control instruction is used to instruct the first indicator light control unit 13 to light the first indicator light corresponding to the first target port.

The first indicator light control unit 13 is configured to receive a first indicator light control instruction from the video data processing unit 12, and light a first indicator light corresponding to the first target port based on the first indicator light control instruction, so that the indicator light corresponding to the first target port is in a normally-on state. Accordingly, the first indicator lamp corresponding to the port of which the connection state of the network switching unit 11 is the disconnection state is in the off state.

In a particular embodiment, the video data processing unit 12 may include a first indicator light control terminal CTL 1. The first indicator light control unit 13 may include a controlled terminal CTLD1 and at least one indicator light control terminal. The controlled end CTLD1 of the first indicator light control unit 13 is connected to the first indicator light control end CTL1 of the video data processing unit 12, and at least one indicator light control end of the first indicator light control unit 13 is connected to at least one of the first indicator lights L1_1 to L1_ n, respectively. Based on this, the video data processing unit 12 can send the first indicator light control instruction to the first indicator light control unit 13 through the first indicator light control terminal CTL1 thereof after determining the first target port. After receiving the first indicator light control instruction from the video data processing unit 12, the first indicator light control unit 13 may output an indicator light lighting signal through an indicator light control end of the first indicator light, which is used to connect to the first indicator light corresponding to the first target port, to light the first indicator light corresponding to the first target port, so that the first indicator light corresponding to the first target port enters a normally-on state. For example, if the port P _1 is a first target port, since the port P _1 corresponds to the first indicator light L1_1, and the first indicator light L1_1 is connected to the 1 st indicator light control end of the first indicator light control unit 13, after receiving the first indicator light control command, the first indicator light control unit 13 may output an indicator light lighting signal through the 1 st indicator light control end thereof to light the first indicator light L1_1 corresponding to the port P _1, so that the first indicator light L1_1 corresponding to the port P _1 is in a normally-on state, and further indicate to the user that the connection state between the current port P _1 and the network switching unit 11 is a normal connection state.

In a specific application, the first indicator lights L1_1 to L1_ n may be Light Emitting Diodes (LEDs). Of course, the first indicator lights L1_1 to L1 — n may be other types of indicator lights, and the specific type of the first indicator light is not particularly limited herein.

As can be seen from the above, in this embodiment, each port is configured with one first indicator light, the connection state between the corresponding port and the network switching unit is indicated as the normal connection state through the normally-on state of the first indicator light, and the connection state between the corresponding port and the network switching unit is indicated as the disconnection state through the off state of the first indicator light, so that on one hand, a user can intuitively know the connection state between each port and the network switching unit; on the other hand, since the first indicator light control unit is added in the video processing circuit, the on-off state of each first indicator light is controlled by the first indicator light control unit, therefore, the network switching unit does not need to have the control function of the first indicator light, thereby not only reducing the material cost of the network switching unit, but also enables network switching units not having the first indicator light control function to be applied in the video processing circuit, namely, the network switching unit having the first indicator light control function and the network switching unit not having the first indicator light control function can be used in the video processing circuit of the present embodiment, therefore, the limitation of the network switching unit on the model selection range is reduced, the model selection range of the network switching unit is expanded, and the adaptability of the video processing circuit to the network switching unit is improved.

With continued reference to fig. 2, in another embodiment of the present application, the video processing circuit 10 may further include: at least one second indicator lamp L2_1 to L2 — n corresponding to the at least one port P _1 to P _ n, respectively, and a second indicator lamp control unit 14. Wherein the second indicator lamp control unit 14 is connected with the video data processing unit 12 and at least one second indicator lamp L2_ 1-L2 _ n.

Since each port corresponds to one second indicator light, the number of the second indicator lights is equal to the number of the ports. For example, the port P _1 may correspond to the second indicator light L2_1, the port P _2 may correspond to the second indicator light L2_2, and the port P _ n may correspond to the second indicator light L2_ n.

In this embodiment, the second indicator lamps L2_1 to L2_ n are used to indicate the data exchange status of the corresponding ports. In a specific application, the states of the second indicator lights L2_1 to L2 — n may include a blinking state and an extinguishing state. For example, in this embodiment, the blinking state of the second indicator light may indicate that the port corresponding to the second indicator light has data exchange, and the extinguishing state of the second indicator light indicates that the port corresponding to the second indicator light has no data exchange.

Specifically, the video data processing unit 12 is further configured to send a second indicator light control instruction to the second indicator light control unit 14 after the second target port is determined.

The second indicator light control instruction is used for instructing the second indicator light control unit 14 to control the second indicator light corresponding to the second target port to enter a flashing state.

Correspondingly, the second indicator light control unit 14 is configured to receive a second indicator light control instruction from the video data processing unit 12, and control a second indicator light corresponding to the second target port to enter a flashing state based on the second indicator light control instruction.

In a particular embodiment, the video data processing unit 12 may include a second indicator light control terminal CTL 2. The second indicator lamp control unit 14 may include a controlled terminal CTLD2 and at least one indicator lamp control terminal. The controlled end CTLD2 of the second indicator lamp control unit 14 is connected to the second indicator lamp control end CTL2 of the video data processing unit 12, and at least one indicator lamp control end of the second indicator lamp control unit 14 is connected to at least one of the second indicator lamps L2_1 to L2 — n, respectively. Based on this, the video data processing unit 12 can send a second indicator light control instruction to the second indicator light control unit 14 through its second indicator light control terminal CTL2 after determining the second target port. After receiving the second indicator light control instruction from the video data processing unit 12, the second indicator light control unit 14 may output an indicator light flashing signal through an indicator light control end of the second indicator light, which is used to connect to the second indicator light corresponding to the second target port, so as to control the second indicator light corresponding to the second target port to enter a flashing state. For example, if the port P _1 is a second destination port (i.e. the port P _1 has data exchange), since the port P _1 corresponds to the second indicator light L2_1, and the second indicator light L2_1 is connected to the 1 st indicator light control terminal of the second indicator light control unit 14, after receiving the second indicator light control command, the second indicator light control unit 14 can output an indicator light flashing signal through the 1 st indicator light control terminal thereof to control the second indicator light L2_1 corresponding to the port P _1 to enter a flashing state, thereby indicating to the user that the port P _1 has data exchange, for example, video data input.

In a specific application, the second indicator lights L2_1 to L2_ n may be Light Emitting Diodes (LEDs). Of course, the second indicator lights L2_1 to L2 — n may be other types of indicator lights, and the specific type of the second indicator light is not particularly limited herein.

As can be seen from the above, in this embodiment, each port is configured with one second indicator light, the corresponding port is indicated to have data exchange through the flashing state of the second indicator light, and the corresponding port does not have data exchange through the turning-off state of the second indicator light, so that on one hand, the data exchange state of each port can be shown to a user, so that the user can intuitively know which ports have data exchange and which ports do not have data exchange; on the other hand, in this embodiment, since the second indicator light control unit is further added to the video processing circuit, and the second indicator lights are controlled by the second indicator light control unit to enter the flashing state or the extinguishing state, so that the network switching unit does not need to have a control function for the first indicator light and/or the second indicator light, the material cost of the network switching unit can be reduced, and the network switching unit without the control function for the first indicator light and/or the second indicator light can be applied to the video processing circuit, thereby expanding the selection range of the network switching unit and improving the adaptability of the video processing circuit to the network switching unit.

In a specific application, for most of network switching units with low cost positioning and low integration level, a port in the network switching unit for controlling the first indicator light is usually multiplexed with other ports for cost control, and since the network switching unit of this type can only realize control of the second indicator light, the network switching unit can be applied to a video processing circuit which only extends the first indicator light control unit and the first indicator light. For a network switching unit having neither a first indicator light control function nor a second indicator light control function, the network switching unit can be applied to a video processing circuit in which a first indicator light control unit, a first indicator light, a second indicator light control unit, and a second indicator light are simultaneously expanded.

With continued reference to fig. 2, in another embodiment of the present application, the video data processing unit 12 may further be connected to a display device 20. The display device 20 may be configured to display a preset user interface, where the preset user interface may include at least one display area corresponding to at least one of the ports P _1 to P _ n. Each display area is used for displaying the video data input from the port corresponding to the display area.

Based on this, the video data processing unit 12 may also control the display device 20 to display the preset user interface after executing the preset program, and display the video data input from the second target port in the target display area corresponding to the second target port in the preset user interface.

In a particular application, the display device 20 may be a display screen, such as a monitor.

As can be seen from the above, in the video processing circuit provided in this embodiment, since the video data processing unit is connected to the display device, and the video data processing unit can control the display device to display the preset user interface, and display the video data input from the second target port in the target display area corresponding to the second target port in the preset user interface, not only can the user view (for example, preview or playback, etc.) the video data through the display device, but also the user can intuitively know from which port the video data is input.

With continued reference to fig. 2, in yet another embodiment of the present application, the video processing circuit 10 may further include a communication unit 15 connected to the video data processing unit 12. The video data processing unit 12 can establish a communication connection with the target terminal device 30 through the communication unit 15.

Correspondingly, the video data processing unit 12 may also transmit the video data input from the second destination port to the destination terminal device 30 through the communication unit 15.

In one possible implementation, the communication unit 15 may be a wireless communication unit, such as a wireless fidelity (WIFI) module, a fourth generation mobile communication technology (4G) communication module, or a fifth generation mobile communication technology (5G) communication module, and so on. Based on this, the video data processing unit 12 can establish a wireless communication connection with the target terminal device 30 through the communication unit 15 and transmit video data to the target terminal device 30 in a wireless communication manner.

In another possible implementation, the communication unit 15 may be a wired communication unit, such as an ethernet communication unit. Based on this, the video data processing unit 12 can establish a wired communication connection with the target terminal device 30 through the communication unit 15 and transmit video data to the target terminal device 30 in a wired communication manner.

Illustratively, the target terminal device 30 may be built with a video management console. In a specific application, the target terminal device 30 includes but is not limited to: mobile phones, tablet computers, desktop computers, wearable devices, and the like.

As can be seen from the above, the video processing circuit provided in this embodiment may send the video data to the target terminal device in a wireless communication manner or a wired communication manner, so that the video data may be displayed or applied on the target terminal device, and thus, a user may preview real-time video data or play back the video data on the target terminal device, thereby implementing a remote monitoring function.

With continued reference to fig. 2, in yet another embodiment of the present application, the video processing circuit 10 further includes a storage unit 16 connected to the video data processing unit. Correspondingly, the video data processing unit 12 may also transmit the video data input from the second target port to the storage unit 16. The storage unit 16 stores the video data received from the video data processing unit 12, so that a local storage function of the video data can be realized, and thus, a user can preview or play back the video data locally stored by the video data processing unit through a preset user interface when necessary.

Referring to fig. 3, fig. 3 is a schematic circuit diagram of a video processing circuit according to an embodiment of the present disclosure. Compared with the embodiment corresponding to fig. 2, the video data processing unit 12 in this embodiment specifically includes: at least one first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a first capacitor C1 and a video codec chip U1.

Specifically, each data port MII1 corresponding to a Media Independent Interface (MII) data bus of the video codec chip U1 is connected to a first end of a first resistor R1, second ends of all the first resistors R1 form a data transmission end of the video data processing unit 12, a management port data pin MDIO1 of the video codec chip U1 is connected to a first end of a second resistor R2, a second end of the second resistor R2 is connected to a first end of a third resistor R3, a second end of the third resistor R3 is connected to a first power supply, a management port clock pin MDCK1 of the video codec chip U1 is connected to a first end of a fourth resistor R4, a second end of the fourth resistor R4 and a second end of a second resistor R2 form a data management end of the video data processing unit 12, a first end of a fifth resistor R638 is connected to the first power supply, a first end of the fifth resistor R1, a first end of the fifth resistor R5, a first end of the second resistor R632, and a second end of the video codec chip GPIO output pin are connected to a common input/output capacitor U638, a first end of the video codec chip U638 The second terminal of the first capacitor C1 is grounded, the second general input/output pin GPIO _1 of the video codec chip U1 is connected to the first terminal of the sixth resistor R6, the third general input/output pin GPIO _2 of the video codec chip U1 is connected to the first terminal of the seventh resistor R7, the fourth general input/output pin GPIO _3 of the video codec chip U1 is connected to the first terminal of the eighth resistor R8, the fifth general input/output pin GPIO _4 of the video codec chip U1 is connected to the first terminal of the ninth resistor R9, the sixth general input/output pin GPIO _5 of the video codec chip U1 is connected to the first terminal of the tenth resistor R10, the seventh general input/output pin GPIO _6 of the video codec chip U1 is connected to the first terminal of the eleventh resistor R11, the second terminal of the sixth resistor R6, the second terminal of the seventh resistor R7, and the eighth resistor R8 form a first control unit for controlling the video lamp, a second terminal of the ninth resistor R9, a second terminal of the tenth resistor R10, and a second terminal of the eleventh resistor R11 constitute a second indicator lamp control terminal of the video data processing unit 12.

In this embodiment, the first power supply is used to provide a voltage signal with a voltage value of VDD. VDD may be set according to actual requirements, for example, VDD may be 3.3 volts (V).

Referring to fig. 3, in another embodiment of the present application, the network switching unit 11 may specifically include: switch controller U2 and twelfth resistor R12.

Specifically, all data ports MII2 corresponding to the MII data bus of the switch controller U2 constitute a data transmission end of the network switching unit 11, the management Port data pin MDIO2 and the management Port clock pin MDCK2 of the switch controller U2 constitute a data management end of the network switching unit 11, the interrupt pin # INT of the switch controller U2 is connected to the first end of the twelfth resistor R12, the second end of the twelfth resistor R12 is an interrupt signal output end of the network switching unit 11, and at least one video data transmission pin Port _1 to Port _ n of the switch controller U2 are at least one video data transmission end of the network switching unit 11, respectively.

In one possible implementation of this embodiment, the interrupt pin # INT of the switch controller U2 is active low; correspondingly, the first GPIO _0 pin of the video codec chip U1 is enabled for low interrupts.

Referring to fig. 3, in another embodiment of the present application, the first indicator control unit 13 may specifically include: a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a second capacitor C2, a first shift register U3, and at least one first current limiting resistor Rs1_1 to Rs1_ n corresponding to at least one port P _1 to P _ n, respectively.

Specifically, the power pin VCC of the first shift register U3, the first terminal of the second capacitor C2, the first terminal of the thirteenth resistor R13, the first terminal of the fourteenth resistor R14, and the first terminal of the fifteenth resistor R15 are commonly connected to the first power supply, the second terminal of the second capacitor C2 is grounded, the second terminal of the thirteenth resistor R13 is connected to the serial data transmission pin SER1 of the first shift register U3, the second terminal of the fourteenth resistor R14 is connected to the data shift clock pin RCLK1 of the first shift register U3, the second terminal of the fifteenth resistor R15 is connected to the register clock pin SRCLK1 of the first shift register U3, the serial data transmission pin SER1 of the first shift register U3, the data shift clock pin RCLK1, and the register clock pin clk1 form the controlled terminal of the first indicator lamp control unit 13, at least one first indicator pin Q2_ n _ 1-Q _ n _ R69556 of the first shift register U3 is connected to at least one current limiting resistor sr 1-86n _ 8653, the second ends of the at least one first current limiting resistors Rs1_ 1-Rs 1_ n are at least one indicator lamp control end of the first indicator lamp control unit 13, respectively.

Referring to fig. 3, in another embodiment of the present application, the first indicator lamp control unit 13 may further include: and at least one first electrostatic protection device D1_ 1-D1 _ n corresponding to the at least one port P _ 1-P _ n, respectively.

Specifically, cathodes of the at least one first electrostatic protection device D1_1 to D1_ n are respectively connected to at least one first indicator lamp control pin Q1_1 to Q1_ n of the first shift register U3, and anodes of all the first electrostatic protection devices D1_1 to D1_ n are grounded.

With continued reference to fig. 3, in yet another embodiment of the present application, the second indicator light control unit 14 includes: a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a third capacitor C3, a second shift register U4 and at least one second current limiting resistor Rs2_ 1-Rs 2_ n corresponding to at least one port P _ 1-P _ n, respectively;

a power supply pin VCC2 of the second shift register U4, a first end of a third capacitor C3, a first end of a sixteenth resistor R16, a first end of a seventeenth resistor R17 and a first end of an eighteenth resistor R18 are commonly connected to the first power supply, a second end of the third capacitor C3 is grounded, a second end of the sixteenth resistor R16 is connected to the serial data transmission pin SER2 of the second shift register U4, a second end of the seventeenth resistor R17 is connected to the data shift clock pin RCLK2 of the second shift register U4, a second end of the eighteenth resistor R18 is connected to the register clock pin SRCLK2 of the second shift register U4642, a serial data transmission pin SER 695 2 of the second shift register U4, a data shift clock pin RCLK2 and a register clock pin clk2 constitute a controlled end of the second indicator lamp control unit 14, at least one indicator lamp control pin Q2_ n-Q2 _2 of the second shift register U4 is respectively connected to the second current limiting resistor srn 2, the second ends of the at least one second current limiting resistor Rs2_ 1-Rs 2_ n are at least one indicator lamp control end of the second indicator lamp control unit 14, respectively.

With continued reference to fig. 3, in yet another embodiment of the present application, the second indicator light control unit 14 further includes: and at least one second electrostatic protection device D2_ 1-D2 _ n corresponding to the at least one port P _ 1-P _ n, respectively.

Specifically, cathodes of the at least one second electrostatic protection device D2_1 to D2_ n are respectively connected to at least one indicator lamp control pin Q2_1 to Q2_ n of the second shift register U4, and anodes of all the second electrostatic protection devices D2_1 to D2_ n are grounded.

In a specific application, each of the first electrostatic protection devices D1_ 1-D1 _ n and the second electrostatic protection devices D2_ 1-D2 _ n may be an electrostatic discharge (ESD) device, such as a transient voltage diode (TVS).

The following describes the specific operation principle of the video processing circuit provided in the embodiment of the present application in detail with reference to fig. 3:

as shown in fig. 3, when there is no data exchange between all the ports P _1 to P _ n and the network switching unit 11, the interrupt pin # INT of the switch controller U2 has no signal output, and at this time, the first GPIO _0 of the video codec chip U1 is in a logic high state because the first GPIO _0 of the video codec chip U1 is pulled up to VDD by the fifth resistor R5. When the first GPIO _0 pin of the video codec chip U1 is at a logic high level, the video codec chip U1 does not send an indicator light control command to the first shift register U3.

When data interaction exists between a certain port and the network switch unit 11 (for example, there is video data input at the port P _ 1), the interrupt pin # INT of the switch controller U2 outputs a low level signal, and the first GPIO _0 of the video codec chip U1 is in a logic low level state. When the first GPIO _0 of the video codec chip U1 is in a logic low level state, the video codec chip U1 may obtain the state information of each of the ports P _1 to P _ n from the switch controller U2 through the management port data pin MDIO1, and determine, according to the state information of the ports P _1 to P _ n, a first target port whose connection state with the switch controller U2 is a normal connection state at present and/or a second target port to which video data is input. After the video coding and decoding chip U1 determines the second target port and/or the first target port, a first indicator light control command may be output to the first shift register U3 through the second general input/output pin GPIO _1, the third general input/output pin GPIO _2, and the fourth general input/output pin GPIO _3 thereof, where the first indicator light control command is used to instruct the first shift register U3 to light a first indicator light corresponding to the first target port; and/or the video codec chip U1 may further send a second indicator light control command to the second shift register U4 through the fifth general purpose input/output pin GPIO _4, the sixth general purpose input/output pin GPIO _5, and the seventh general purpose input/output pin GPIO _6, where the second indicator light control command is used to instruct the second shift register U4 to control the first indicator light corresponding to the second target port to enter a blinking state.

According to the embodiment of the application, the first capacitor C1 is arranged between the first general input/output pin GPIO _0 of the video coding/decoding chip U1 and the ground, so that the first general input/output pin GPIO _0 of the video coding/decoding chip U1 can be prevented from being interfered by an interference signal. Taking the circuit structure of the first indicator light control unit 13 as an example, by arranging a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a thirteenth resistor R13, a fourteenth resistor R14 and a fifteenth resistor R15 on a communication link between the video codec chip U1 and the first shift register U3, the stability of the first indicator light control command output by the video codec chip U1 can be improved; the first current limiting resistors Rs1_ 1-Rs 1_ n are arranged between the indicator lamp control pins Q1_ 1-Q1 _ n of the first shift register U3 and the first indicator lamp, and can be respectively used for adjusting the brightness of the first indicator lamp connected with each indicator lamp control pin Q1_ 1-Q1 _ n; the first electrostatic protection devices D1_1 to D1_ n are arranged between the indicator lamp control pins Q1_1 to Q1_ n of the first shift register U3 and the ground, and can be respectively used for performing electrostatic protection on the first indicator lamp connected with each indicator lamp control pin Q1_1 to Q1_ n. It should be noted that the circuit structure of the second indicator lamp control unit 14 and the circuit structure of the first indicator lamp control unit 13 are designed based on the same concept, and the beneficial effects corresponding to the circuit structure of the second indicator lamp control unit 14 are not described again here.

Referring to fig. 4, fig. 4 is a schematic structural diagram of a video monitoring apparatus according to an embodiment of the present disclosure. The video monitoring apparatus 40 may include: a display device 41, a video capture device 42, and a video processing circuit 43. The video processing circuit 43 is connected to the display device 41 and the video capture device 42. The video capture device 42 is used to capture video data and send the video data to the video processing circuit 43.

It should be noted that the video processing circuit 43 in this embodiment may be the video processing circuit in the embodiment corresponding to fig. 1 or fig. 2, and for the structure, the beneficial effects, and the like of the video processing circuit, reference may be made to the relevant description in the embodiment corresponding to fig. 1 or fig. 2, and details thereof are not repeated here.

In a specific embodiment, the number of the video capture devices 42 may be at least one, the at least one video capture device 42 may be respectively connected to at least one port of the video processing circuit 43, and each video capture device 42 may transmit video data to the video processing circuit 43 through the port to which it is connected.

In a specific application, the video monitoring device 40 may be, for example, a network high definition video camera, and the embodiment of the present application does not specifically limit the specific type of the video monitoring device.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims

1. A video processing circuit, comprising:

at least one port;

2. The video processing circuit of claim 1, wherein the video processing circuit further comprises:

at least one first indicator light corresponding to the at least one port respectively;

the first indicator light control unit is connected with the video data processing unit and the at least one first indicator light, and is used for receiving a first indicator light control instruction from the video data processing unit and lighting the first indicator light corresponding to the first target port based on the first indicator light control instruction; the first indicator light control instruction is output by the video data processing unit after the first target port is determined according to the state information, and the first target port refers to a port of which the connection state with the network switching unit is a normal connection state.

3. The video processing circuit of claim 2, wherein the video processing circuit further comprises:

at least one second indicator light corresponding to the at least one port, respectively;

the second indicator lamp control unit is connected with the video data processing unit and the at least one second indicator lamp, and is used for receiving a second indicator lamp control instruction from the video data processing unit and controlling the second indicator lamp corresponding to the second target port to enter a flashing state based on the second indicator lamp control instruction; and the second indicator light control instruction is output by the video data processing unit after the second target port is determined.

4. The video processing circuit according to any of claims 1 to 3, wherein the video data processing unit comprises: the video coding and decoding circuit comprises at least one first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a first capacitor and a video coding and decoding chip;

each data port corresponding to the media independent interface data bus of the video coding and decoding chip is connected with a first end of one first resistor, second ends of all the first resistors form a data transmission end of the video data processing unit, a management port data pin of the video coding and decoding chip is connected with a first end of a second resistor, a second end of the second resistor is connected with a first end of a third resistor, a second end of the third resistor is connected with a first power supply, a management port clock pin of the video coding and decoding chip is connected with a first end of a fourth resistor, a second end of the fourth resistor and a second end of the second resistor form a data management end of the video data processing unit, a first end of the fifth resistor is connected with the first power supply, and a second end of the fifth resistor, a first end of the first capacitor and a first general input and output pin of the video coding and decoding chip are connected together as the data management end of the video coding and decoding chip The second end of the first capacitor is grounded, the second general input/output pin of the video codec chip is connected to the first end of the sixth resistor, the third general input/output pin of the video codec chip is connected to the first end of the seventh resistor, the fourth general input/output pin of the video codec chip is connected to the first end of the eighth resistor, the fifth general input/output pin of the video codec chip is connected to the first end of the ninth resistor, the sixth general input/output pin of the video codec chip is connected to the first end of the tenth resistor, the seventh general input/output pin of the video codec chip is connected to the first end of the eleventh resistor, and the second end of the sixth resistor, the second end of the seventh resistor and the second end of the eighth resistor form a first indicator lamp control end of the video data processing unit, and the second end of the ninth resistor, the second end of the tenth resistor and the second end of the eleventh resistor form a second indicator lamp control end of the video data processing unit.

5. The video processing circuit according to any of claims 1 to 3, wherein the network switching unit comprises: a switch controller and a twelfth resistor;

all data ports corresponding to a media independent interface data bus of the switch controller form a data transmission end of the network switching unit, a management port data pin and a management port clock pin of the switch controller form a data management end of the network switching unit, an interrupt pin of the switch controller is connected with a first end of the twelfth resistor, a second end of the twelfth resistor is an interrupt signal output end of the network switching unit, and each video data transmission pin of the switch controller is a video data transmission end of the network switching unit.

6. A video processing circuit according to claim 2 or 3, wherein the first indicator control unit comprises: a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a second capacitor, a first shift register, and at least one first current limiting resistor corresponding to the at least one port respectively;

a power pin of the first shift register, a first end of the second capacitor, a first end of the thirteenth resistor, a first end of the fourteenth resistor, and a first end of the fifteenth resistor are commonly connected to a first power supply, a second end of the second capacitor is grounded, a second end of the thirteenth resistor is connected to a serial data transmission pin of the first shift register, a second end of the fourteenth resistor is connected to a data shift clock pin of the first shift register, a second end of the fifteenth resistor is connected to a register clock pin of the first shift register, the serial data transmission pin, the data shift clock pin, and the register clock pin of the first shift register form a controlled end of the first indicator lamp control unit, and each indicator lamp control pin of the first shift register is connected to a first end of one of the first current-limiting resistors, and the second end of each first current-limiting resistor is an indicator lamp control end of the first indicator lamp control unit.

7. The video processing circuit of claim 6, wherein the first indicator light control unit further comprises: at least one first electrostatic protection device corresponding to the at least one port respectively;

the cathode of each first electrostatic protection device is respectively connected with one indicator lamp control pin of the first shift register, and the anodes of all the first electrostatic protection devices are grounded.

8. A video processing circuit according to claim 3, wherein the second indicator light control unit comprises: the sixteenth resistor, the seventeenth resistor, the eighteenth resistor, the third capacitor, the second shift register and at least one second current-limiting resistor corresponding to the at least one port respectively;

the power pin of the second shift register, the first end of the third capacitor, the first end of the sixteenth resistor, the first end of the seventeenth resistor and the first end of the eighteenth resistor are connected to a first power supply in common, the second end of the third capacitor is grounded, the second end of the sixteenth resistor is connected with the serial data transmission pin of the second shift register, the second end of the seventeenth resistor is connected with the data shift clock pin of the second shift register, the second end of the eighteenth resistor is connected with the register clock pin of the second shift register, the serial data transmission pin, the data shift clock pin and the register clock pin of the second shift register form a controlled end of the second indicator lamp control unit, and each indicator lamp control pin of the second shift register is connected with the first end of one second current-limiting resistor respectively, and the second end of each second current-limiting resistor is an indicator lamp control end of the second indicator lamp control unit.

9. The video processing circuit of claim 8, wherein the second indicator light control unit further comprises: at least one second electrostatic protection device corresponding to the at least one port, respectively;

and the cathode of each second electrostatic protection device is respectively connected with one indicator lamp control pin of the second shift register, and the anodes of all the second electrostatic protection devices are grounded.

10. A video surveillance apparatus, comprising: a display device, a video capture device, and a video processing circuit as claimed in any one of claims 1 to 9; the video processing circuit is connected with the display device and the video acquisition device; the video acquisition device is used for acquiring video data and sending the video data to the video processing circuit through the at least one port.