CN115865113A - Millimeter wave self-homodyne receiver - Google Patents
Millimeter wave self-homodyne receiver Download PDFInfo
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Abstract
The invention discloses a millimeter wave self-homodyne receiver, which comprises: a variable gain low noise amplifier for adjusting a gain according to a power of an input radio frequency signal; the baud clock locking loop is used for recovering a baud clock from the radio frequency signal, generating quenching signals of all super regenerative amplifiers and providing a sampling clock; the super-regenerative delay phase-shifting circuit is used for realizing long delay and phase shifting through a super-regenerative amplifier and outputting IQ two paths of output signals delayed by one code element time; the system comprises an I path of output signal, a Q path of output signal, a Baud clock locking loop and a power supply, wherein the I path of output signal is mixed with a radio frequency signal output by the Baud clock locking loop; and the intermediate frequency sampling amplifying circuit is used for sampling and amplifying the two paths of mixing signals. The invention uses the super-regenerative delay phase-shifting circuit to replace a passive delay line which is difficult to integrate, and realizes the front end of a fully integrated self-homodyne receiver. The invention can be widely applied to the technical field of communication.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a millimeter wave self-homodyne receiver.
Background
The Sub-6GHz spectrum resource is gradually exhausted, and the millimeter wave communication technology becomes one of key technologies for realizing the intelligent and deep interconnection and intercommunication of everything and constructing the air, space, earth and sea integrated network due to the ultra-wide continuous available spectrum. However, the communication distance is limited by the lower gain of the millimeter wave amplifier and the higher propagation path loss in the air in the millimeter wave frequency band, and a receiver or a transmitter using the multistage cascade amplifier can achieve a rated gain, which makes the millimeter wave communication system complicated and inefficient, and especially in a high-speed communication system requiring a large bandwidth, the problem is more serious. Phased array technology is another solution, but large-scale arrays also present many problems, such as local oscillator distribution networks, which are particularly critical to heterodyne receivers, becoming inefficient and difficult to design in such large-scale arrays. Furthermore, in large-scale high-speed interconnect applications, the need to synchronize the clocks of the terminals significantly increases the complexity of the system.
Disclosure of Invention
To solve at least one of the technical problems in the prior art to a certain extent, the present invention provides a millimeter wave self-homodyne receiver.
The technical scheme adopted by the invention is as follows:
a millimeter wave self-homodyne receiver comprising:
the variable gain low noise amplifier is used for adjusting gain according to the power of an input radio frequency signal so as to maintain the output power of the variable gain low noise amplifier at a preset power;
the baud clock locking loop is used for recovering a baud clock from the radio frequency signal, generating quenching signals of the super regenerative amplifiers and providing a sampling clock; the Baud clock locking loop comprises a first super regenerative amplifier, and a radio frequency signal output by the variable gain low noise amplifier passes through the first super regenerative amplifier and is output to a super regenerative delay phase-shifting circuit;
the super-regenerative delay phase-shifting circuit is used for realizing long delay and phase shifting through a super-regenerative amplifier and outputting IQ two paths of output signals delayed by one code element time; the first mixer is used for mixing the I path output signal and a radio frequency signal output by the baud clock locking loop, and the second mixer is used for mixing the Q path output signal and a radio frequency signal output by the baud clock locking loop;
and the intermediate frequency sampling amplifying circuit is used for sampling and amplifying the two paths of mixing signals.
Further, the baud clock locking loop further comprises a third mixer, a low-pass filter, a subtractor, a voltage-controlled oscillator and a waveform shaper;
the output end of the variable gain low noise amplifier is respectively connected to the input end of the first super regenerative amplifier and the radio frequency input end of the third mixer, the output end of the third mixer is connected to the input end of the low-pass filter, the output end of the low-pass filter is connected to the negative input end of the subtracter, the positive input end of the subtracter is connected to the reference voltage, the output end of the subtracter is connected to the tuning control end of the voltage-controlled oscillator, the output end of the voltage-controlled oscillator is connected to the input end of the waveform shaper, and the output end of the waveform shaper outputs quenching signals of the super regenerative amplifiers.
Further, the millimeter wave self-homodyne receiver is an orthogonal self-homodyne receiver or a non-orthogonal self-homodyne receiver.
Further, a comparator is used to replace the subtractor.
Further, the working principle of the baud clock locking loop is as follows:
the radio frequency signal is mixed with the radio frequency signal sampled and amplified by the first super regenerative amplifier through the third mixer, the sampling and amplification of the first super regenerative amplifier generate delay, the mixing output consists of the self-mixing quantity of the previous code element and the mixing quantities of the front code element and the rear code element, and the DC component of the mixing quantities of the front code element and the rear code element of the digital modulation scheme is 0; wherein, the self-mixing amount of a code element is reduced along with the backward movement of the sampling position;
the principle of loop locking is as follows: when the output signal of the voltage-controlled oscillator lags, the output delay of the first super regenerative amplifier is increased, the DC component output by the third mixer is reduced, the oscillation frequency of the voltage-controlled oscillator is controlled to be increased, and the output signal lag of the voltage-controlled oscillator is reduced; on the contrary, when the output signal of the voltage-controlled oscillator leads, the output delay of the first super regenerative amplifier is reduced, the DC component output by the third mixer is increased, the oscillation frequency of the voltage-controlled oscillator is controlled to be smaller, and the output signal of the voltage-controlled oscillator leads and reduces.
Further, the super regenerative delay phase shift circuit comprises a tunable super regenerative amplifier, a driving amplifier, a multi-phase filter and a quadrature super regenerative amplifier;
the output end of the first regenerative amplifier is connected to the input end of the tunable super regenerative amplifier, the output end of the tunable super regenerative amplifier is connected to the input end of the drive amplifier, the input end of the drive amplifier is connected to the input end of the multi-phase filter, and the outputs of the I path and the Q path of the multi-phase filter are respectively connected to the injection ends of the I path and the Q path of the orthogonal super regenerative amplifier;
the quenching signal of the tunable super regenerative amplifier lags behind the first regenerative amplifier, the quenching signal of the quadrature super regenerative amplifier lags behind the tunable super regenerative amplifier, the duty ratio of the quenching signal of the tunable super regenerative amplifier is higher than that of the quenching signal of the first regenerative amplifier, and the sum of the delay generated by the tunable super regenerative amplifier and the delay generated by the quadrature super regenerative amplifier is one symbol time.
Furthermore, a control end of the tunable super regenerative amplifier is connected with a control voltage V PHS ；
Reducing the control voltage V when the output phase of the tunable super regenerative amplifier is advanced PHS Increasing the control voltage V when the output phase of the tunable super regenerative amplifier lags PHS 。
Further, the polyphase filter is replaced with a quadrature signal generating circuit.
Further, a regenerative amplifier stage is added between the tunable super regenerative amplifier and the quadrature super regenerative amplifier.
Furthermore, the intermediate frequency sampling amplifying circuit comprises an I path, a Q path sampling holding amplifier and a sampling clock generator, wherein the sampling clock of the sampling holding amplifier is generated by the baud clock locking loop and the sampling clock generator together;
the output ends of the I-path and Q-path frequency mixers are respectively connected to the input ends of the I-path and Q-path sampling and holding amplifiers, and the output ends of the I-path and Q-path sampling and holding amplifiers are used as the output ends of the millimeter wave self-homodyne receiver;
the sampling clock provided by the baud clock locking loop is connected to the input end of the sampling clock generator, and the differential clock output end of the sampling clock generator is connected to the differential clock input ends of the I-path and Q-path sampling hold amplifiers.
Further, the sampling clock generator comprises an inverter delay circuit, an edge detector, and a schmitt trigger with input buffering; the clock input end is connected to the input end of the phase inverter delay circuit and the first input end of the edge detector, the output end of the phase inverter delay circuit is connected to the second input end of the edge detector, the output end of the phase inverter delay circuit is connected to the input end of the Schmitt trigger, and the output end of the Schmitt trigger outputs a differential clock;
the sampling holding amplifier comprises an input isolation amplifier, a sampling switch and an active current mirror; the input end of the input isolation amplifier is used as the input end of the sampling hold amplifier, the output end of the input isolation amplifier is connected to the input end of the sampling switch, the differential clock is connected to the clock input end of the sampling switch, the output end of the sampling switch is connected to the input end of the active current mirror, and the output end of the active current mirror is used as the output end of the millimeter wave self-homodyne receiver.
The invention has the beneficial effects that: the super-regenerative delay phase-shifting circuit replaces a passive delay line which is difficult to integrate, and the front end of a fully-integrated self-homodyne receiver is realized; in addition, the gain is adjusted through the variable gain low noise amplifier, so that the stable work of the receiver is ensured, and the dynamic range is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description is made on the drawings of the embodiments of the present invention or the related technical solutions in the prior art, and it should be understood that the drawings in the following description are only for convenience and clarity of describing some embodiments in the technical solutions of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic block diagram of a super-regenerative amplifier implementing long delay and phase shift according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a super-regenerative amplifier implementing long delay and phase shift according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a super regenerative delay and phase shift circuit in an embodiment of the present invention;
FIG. 4 is a schematic diagram of a Baud clock lock loop in an embodiment of the present invention;
FIG. 5 is a schematic diagram illustrating the implementation of sample position detection by delayed self-mixing according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a sampling and amplification circuit in an embodiment of the invention;
fig. 7 is a block diagram of a self-homodyne receiver in an embodiment of the present invention;
FIG. 8 is a diagram of first transient simulation results from a homodyne receiver in an embodiment of the present invention;
FIG. 9 is a diagram of second transient simulation results from a homodyne receiver in an embodiment of the present invention;
FIG. 10 is a diagram of third transient simulation results from a homodyne receiver in an embodiment of the present invention;
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention. The step numbers in the following embodiments are provided only for convenience of illustration, the order between the steps is not limited at all, and the execution order of each step in the embodiments can be adapted according to the understanding of those skilled in the art.
In the description of the present invention, it should be understood that the orientation or positional relationship referred to in the description of the orientation, such as the upper, lower, front, rear, left, right, etc., is based on the orientation or positional relationship shown in the drawings, and is only for convenience of description and simplification of description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
In the description of the present invention, the meaning of a plurality of means is one or more, the meaning of a plurality of means is two or more, and larger, smaller, larger, etc. are understood as excluding the number, and larger, smaller, inner, etc. are understood as including the number. If the first and second are described for the purpose of distinguishing technical features, they are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
In the description of the present invention, unless otherwise specifically limited, terms such as set, installation, connection and the like should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above terms in the present invention by combining the specific contents of the technical solutions.
To avoid the need for clock synchronization, some millimeter wave transceivers employ an OOK modulation and demodulation scheme to achieve noncoherent communication. The scheme also avoids the difficult problem of local oscillator generation and distribution, and reduces the area, complexity and power consumption of the transceiver. However, OOK transceivers have some drawbacks: 1) The gain of the millimeter wave OOK demodulator is low, and a low-noise amplifier requiring large power consumption is often added at the front stage to improve the sensitivity of the receiver; 2) The transmitter has a larger peak-to-average power ratio (PAPR), so that the energy efficiency ratio of the transmitter is reduced; 3) The very low spectral efficiency makes it very difficult to design a baseband amplifier at radio frequency and broadband, which requires a larger bandwidth to achieve the same communication rate; 4) To meet the high-speed communication demand, OOK transceivers require high sampling rate, high power consumption digital-to-analog/analog-to-digital converters. These reasons have led to OOK modem schemes that are currently primarily aimed at on-chip or inter-chip wired or short-range wireless communications.
The super-regenerative receiver receives attention because it can realize a large gain with low power consumption, and the prior art scheme also shows the capability of the super-regenerative receiver to realize 16QAM or even 64QAM demodulation for high-speed communication, and can realize low power consumption and high sensitivity. The defects of the existing super-regenerative receiver mainly comprise the following two points: 1) A coherent demodulation super-regenerative receiver needs an additional quenching signal for control, and the quenching signal needs to be synchronous with a baud rate clock of a radio frequency input signal and has a determined relative phase, so that the overall clock scheme of the system becomes complex; 2) Due to the working characteristics of start-up period start-up and stop of oscillation of the super-regenerative amplifier, an intermediate frequency signal of the super-regenerative receiver also shows periodic oscillation and return-to-zero, and is similar to a return-to-zero code, so that difficulty is brought to ADC sampling in a high-speed communication system, the ADC needs to sample the signal at a position with large oscillation amplitude of the intermediate frequency signal, and accurate clock generation is difficult.
Having mentioned the frequency sources and their distribution system of the communication system, it is explained here in more detail: the existing microwave millimeter wave communication system mostly adopts a phase-locked loop as a frequency source, which consumes a large area and power consumption, the phase noise of the millimeter wave phase-locked loop is difficult to satisfy, in addition, a reference clock of the phase-locked loop is often generated by a crystal oscillator, which consumes at least tens of milliwatts of power consumption, is difficult to integrate, and is one of the most expensive and large-sized off-chip elements of a transceiver. Some researchers have proposed receivers that use crystal-less oscillators, mainly of the following two types: 1) The crystal oscillator is replaced by an integratable oscillator such as an LC or relaxation oscillator, and the main defects of the schemes are that the power consumption is still large and the PVT is too sensitive; 2) By adopting the carrier recovery technology, the transceiver does not need a crystal oscillator, and the transceiver usually adopts a carrier recovery loop to replace a phase-locked loop, and it needs to be noted that, because the frequencies of different crystal oscillators have deviation, in a frequency synthesis scheme adopting the crystal oscillator and the phase-locked loop, the digital baseband needs to compensate the frequency deviation of the crystal oscillator. The carrier recovery technique avoids many problems of crystal oscillators, which no longer require complex local oscillator distribution networks, but these problems still exist in the prior art: 1) Too long locking time results in interference being easily received; 2) The locking range is smaller; 3) With a complexity and power consumption comparable to that of a PLL.
Self-homodyne detection is a signal receiving technology in the field of coherent optical communication, and has the characteristic of eliminating phase noise, and even if a received signal comes from a free-running oscillator, the error rate of a receiver cannot be obviously deteriorated. The self-homodyne receiver is ideally suitable for designing a communication system without a crystal oscillator or a reference clock because the self-homodyne receiver does not need local oscillator signals for demodulation, but two key problems exist in the self-homodyne receiver, so that the self-homodyne receiver is difficult to apply to a microwave/millimeter wave communication system: 1) The 1-symbol delay line required by the self-homodyne receiving is difficult to integrate, even if the 1-symbol delay line is integrated on a chip by adopting an advanced process, the huge area and loss of the 1-symbol delay line are unacceptable, and the next symbol periods are different under different symbol rates, and even if an off-chip element is adopted for realizing the self-homodyne receiving, the self-homodyne receiving is difficult; 2) Self-homodyne mixing shows the characteristics of square-law mixing and is difficult to apply in the modulation scene of simultaneous amplitude and phase modulation.
In order to solve the above technical problems, embodiments of the present invention provide an integratable millimeter wave self-homodyne receiver scheme, a clock recovery method and a circuit thereof to implement self-synchronous self-homodyne demodulation, and based on the above methods and circuits, the present embodiment also provides a self-synchronous receiver scheme that does not require an intrinsic input or a phase-locked loop to perform clock synchronization.
The technical scheme provided by the embodiment of the invention comprises the following steps: a long delay and phase shift circuit (SRDPS) implemented by a Super Regenerative Amplifier (SRA), a baud rate locked loop (BLL), a sample-and-hold amplifier with self-aligned sample positions, and a self-homodyne receiver employing these methods or circuits.
(1) The embodiment of the invention provides a method for realizing long delay and phase shift by a super regenerative amplifier and a circuit thereof
As shown in fig. 1, two or more stages of super regenerative amplifiers generate a large delay, and the phase shift is realized by tuning a preceding stage of super regenerative amplifier, and the delay and phase shift principle is shown in fig. 2: the SRA1 output is delayed compared with the input RFin, the SRA2 output is delayed compared with the SRA1 output, and the RFout delay compared with the RFin is the sum of the delays of the two stages of super regenerative amplifiers; SRA1 tuning control voltage V PHS At high time, its oscillation frequencyThe sensitivity function of the high and super regenerative amplifier determines the characteristic of sampling amplification, and the SRA2 output RFout is at V PHS High time advance, whereas RFout is at V PHS Low time lag. The method utilizes the super regenerative amplifier working in a saturated state to realize amplification and delay, and solves the problem of frequency mixing of a delay line and a square law. The phase adjustment is realized by adjusting the oscillation frequency of the preceding stage super regenerative amplifier in the delay circuit, the complexity of the system is reduced, and the PVT robustness of the system is improved. Compared with the prior art, the scheme adopts two or more super regenerative amplifiers to realize larger phase shift; the scheme realizes continuous phase adjustment by tuning the pre-stage super regenerative amplifier.
Based on fig. 1, the long delay and phase shift circuit implemented by the super regenerative amplifier employed in the self-synchronous receiver is shown in fig. 3, and is composed of a Tunable Super Regenerative Amplifier (TSRA), a driver amplifier, a poly-phase filter (PPF), and a Quadrature Super Regenerative Amplifier (QSRA). This configuration is an example of the method of fig. 1, which uses QSRA to generate quadrature output signals, and adds a driver amplifier and a polyphase filter between QSRA and TSRA to drive QSRA, where the polyphase filter may be used to generate quadrature signals for injection into QSRA. The polyphase filter can be replaced by other types of quadrature signal generating circuits such as a quadrature coupler, or the like, or the number of stages of a super regenerative amplifier is increased, a driving amplifier is added or removed, or quadrature coupler output quadrature signals are used for replacing variants of the circuits of QSRA and other circuits for performing long delay and phase shift derived based on the schematic block diagram shown in FIG. 1, and the method for performing long delay and phase shift realized by the super regenerative amplifier shown in FIG. 1 and FIG. 2 provided by the invention is still adopted.
(2) The embodiment of the invention provides a method for recovering a clock from a radio frequency signal and a circuit thereof
As shown in fig. 4, the radio frequency signal recovery clock circuit used in the self-synchronizing receiver is composed of a super regenerative amplifier (SRA 1), a mixer, a comparator, a low-pass filter, a voltage-controlled oscillator, and a quench signal shaping circuit. The working principle is shown in fig. 5: the radio frequency signal is mixed with the radio frequency signal amplified by SRA sampling through a mixer, the SRA sampling amplification brings certain delay, the mixing output is composed of the self-mixing quantity of the previous code element and the next code element, the DC component of the mixing quantity of the previous code element and the next code element of most digital modulation schemes is 0, and the self-mixing quantity of one code element is reduced along with the backward movement of the sampling position. The above principle can be derived from the following equations (14) to (17).
The SRA sampling position is determined by the quenching signal, the output of the mixer is filtered by a low-pass filter, and compared and amplified by a subtracter (active balun) to control a voltage-controlled oscillator for generating the quenching signal, wherein the voltage-controlled oscillator can adopt an LC oscillator, a ring oscillator and the like. The principle of loop locking is as follows: when the VCO output signal lags, the SRA output delay is increased, the DC component output by the mixer is reduced, the oscillation frequency of the control VCO is increased, and the lag of the VCO output signal is reduced, otherwise, when the VCO output signal leads, the SRA output delay is reduced, the DC component output by the mixer is increased, the oscillation frequency of the control VCO is smaller, and the lead of the VCO output signal is reduced.
It should be noted that other various changes to the circuit shown in fig. 4, in accordance with the method and its concept of the present invention, should be made within the scope of the claimed invention, such as: the comparator may be implemented by various circuits with subtraction function (analog or digital) or just by an inverter, the pulse shaping circuit may be implemented by various simple (inverter) or complex signal shaping and generating circuits, or directly with the unshaped signal as clock output.
(3) The embodiment of the invention provides an intermediate frequency signal sampling amplifying circuit, which is used for solving the problem that the intermediate frequency signal in a super-regenerative receiver also shows periodic swing and return-to-zero to bring difficulty to ADC (analog to digital converter) sampling
As shown in fig. 6, the sampling amplifying circuit is composed of a self-aligned sampling clock generating circuit and a sample-and-hold amplifier. The input of the self-aligned sampling clock generating circuit is from the output of a baud clock locking loop, sampling clock signals with certain pulse width and the same period as a baud rate clock are generated through two paths of paths with different delays, and sampling at the position of an intermediate frequency peak can be realized through reasonable circuit design without an additional calibration circuit. Generating the sample-and-hold circuit clock directly based on the clock synchronized with the quench signal is the key to achieving self-aligned sampling. The sampling holding amplifier consists of a driving amplifier, a sampling switch and an output driving amplifier and plays the roles of sampling and amplifying the output signal of the mixer and converting the output signal into a single-ended signal for output. The circuit solves the problem that an intermediate frequency signal of the super-regenerative receiver also shows periodic swing and return to zero, and has great advantages in the aspects of system complexity, power consumption and the like compared with a scheme of performing oversampling by using a high sampling rate ADC.
Based on the foregoing method and circuit, the present invention provides a self-homodyne receiver, as shown in fig. 7, which comprises a variable gain amplifier (VGLNA), a baud rate locked loop, a super-regenerative delay and phase shift circuit, a mixer, a sampling clock generation circuit, and a sample-and-hold amplifier. The structure is a self-homodyne (self-homodyne) receiver for quadrature demodulation, when the receiver works, a radio frequency signal is amplified by the VGLNA, and by adjusting the gain of the VGLNA, stable output power of the VGLNA can be kept under different input powers, and the normal operation of the receiver is ensured. The output signal of VGLNA is sampled and amplified by SRA, and the BLL restores baud clock and generates quenching signals of SRA, TSRA and QSRA, and the relative positions of the quenching signals, the sampling clock and the input radio frequency signal code element can be moved by adjusting the reference voltage of the BLL. The SRA output signal is input to SRDPS, the output signal of which is delayed by one symbol time with respect to the input, by adjusting a phase modulation control voltage V in the SRDPS PHS The relative phase adjustment of the delayed signal and the signal before the delay can be realized. The SRA output signal is respectively mixed with IQ two output signals of the SRDPS, the intermediate frequency output of the IQ two mixers is sampled, held and amplified by a sampling amplifying circuit, and an input clock of the sampling and holding amplifying circuit is also generated by BLL.
The self-homodyne receiver adopts a new receiver architecture, combines a super-regenerative receiver and the self-homodyne receiver, and has the main differences from the prior art that: the structure generates delay by a super regenerative amplifier to carry out delay self-homodyne; the self-homodyne reception of the structure is orthogonal; the structure performs clock recovery at radio frequency. Variations of the self-homodyne receiver described above may be generated based on this technique, such as generating a quadrature signal from the SRA output, which is then delayed from homodyne with an in-phase one symbol delayed signal.
As shown in fig. 7, an embodiment of the present invention provides a self-synchronizing millimeter wave self-homodyne receiver, including:
variable Gain Low Noise Amplifier (VGLNA): the gain is adjusted to ensure the stable operation of the receiver and improve the dynamic range.
Baud clock locked loop (BLL): the method has the functions of recovering a baud clock from a radio frequency signal, generating quenching signals of various super regenerative amplifiers and providing a reference clock for a sampling clock generator, wherein the super regenerative amplifiers are also amplifiers on a radio frequency link. It includes: mixer, SRA, low pass filter, subtracter, VCO, waveform shaper.
Super regenerative delay phase shift circuit (SRDPS): acts to generate orthogonal radio frequency signals that are time delayed from a code required for quadrature homodyne demodulation. It includes: TSRA, driver amplifier, polyphase filter, QSRA.
A mixer: as a mixer for a quadrature self-homodyne receiver.
Intermediate frequency sampling amplifier circuit: and sampling and amplifying the intermediate frequency signal. It includes: a sampling clock generator, a sample-and-hold amplifier.
The connection relationship of each part in the receiver is as follows: radio frequency signal RFin is connected to VGLNA input end, VGLNA output end is connected to BLL's radio frequency input end, BLL radio frequency output end is connected to TSRA's among SRDPS radio frequency input end, I way and Q way mixer radio frequency input end respectively, BLL reference voltage is connected to BLL reference voltage input end, BLL quenching signal output 1, 2, 3 are connected to SRA quenching signal input end respectively, TSRA quenching signal input end among SRDPS, QSRA's among SRDPS quenching signal input end, BLL sampling reference clock output end is connected to sampling clock generator input end. And the differential clock output end of the sampling clock generator is connected to the differential clock input ends of the I-path and Q-path sampling hold amplifiers. Phase regulated voltage V PHS Is connected to the tuning control end of TSRA in SRDPS, and the I-path and Q-path output ends of QSRA in SRDPS are respectively connected to the I-path and Q-path mixer local oscillator outputsAnd (6) entering the terminal. The output ends of the I-path and Q-path frequency mixers are respectively connected to the input ends of the I-path and Q-path sampling holding amplifiers, and the output ends of the I-path and Q-path sampling holding amplifiers are connected to the intermediate frequency output ends of the I-path and Q-path of the receiver.
When the receiver works, a radio frequency signal is amplified by the VGLNA and the SRA and then is input into the IQ two-way frequency mixing to form a radio frequency input end, the radio frequency signal is amplified by the VGLNA and the SRA, then a quadrature radio frequency signal delaying for one code element time is generated by the SRDPS, the quadrature radio frequency signal is input into the local oscillation input ends of the IQ two-way frequency mixer, the intermediate frequency input of the frequency mixer is processed by the intermediate frequency sampling amplifying circuit, and the quenching signals of the SRA, the TSRA and the QSRA and the reference clock of the sampling amplifying circuit in the receiver are all generated by the BLL.
The SRDPS internal connection relationship is as follows: the output end of the TSRA is connected to the input end of the drive amplifier, the input end of the drive amplifier is connected to the input end of the multi-phase filter, and the outputs of the I path and the Q path of the multi-phase filter are respectively connected to the injection ends of the I path and the Q path of the QSRA. The quenching signal of the TSRA lags behind the SRA, the quenching signal of the QSRA lags behind the TSRA, and the duty cycle of the TSRA quenching signal is higher than that of the SRA, and the sum of the delay generated by the TSRA and the delay generated by the QSRA is one symbol time. The SRDPS phase adjusting method comprises the following steps: lowering V when QSRA output phase advances PHS Increasing V when the QSRA output phase lags PHS 。
The BLL internal connection relation is: the radio frequency input end is connected to the SRA input end, the mixer radio frequency input end, the SRA output end is connected to the mixer local oscillator input end, the mixer output end is connected to the input end of a low-pass filter (first-order RC low-pass filter), the low-pass filter output end is connected to the negative input end of a subtracter, the reference voltage input is connected to the positive input end of the subtracter, the output of the subtracter (active current mirror amplifier) is connected to a VCO tuning control end, the VCO output end is connected to the waveform shaper input end, the waveform shaper output ends 1, 2 and 3 are connected to the quenching signal output ends 1, 2 and 3 (the output end 1 is connected to the SRA), and the waveform shaper output end 4 is connected to the sampling reference clock output end. The waveform shaper is realized by 4 groups of cascaded inverters with different stages, the duty ratio of an output signal can be adjusted by adjusting the bias of the inverters, and different delays can be generated by adjusting the stages.
The sampling clock generator includes: the inverter delay circuit, the edge detector (NAND gate), the Schmitt trigger with input buffer (inverter, transmission gate) are connected as follows: the clock input end is connected to the input end of the inverter delay circuit and the input end 2 of the edge detector, the output end of the inverter delay circuit is connected to the input end 1 of the edge detector, the output end of the inverter delay circuit is connected to the input end of the inverter of the Schmitt trigger and the input end of the transmission gate, the output ends of the inverter delay circuit and the transmission gate are connected to the input end 1 and the input end 2 of the Schmitt trigger, and the output end 1 and the output end 2 of the Schmitt trigger serve as differential clock output.
The sample-and-hold amplifier includes: the device comprises an input isolation amplifier (a differential common source amplifier), a sampling switch and an active current mirror. The connection relation is as follows: the input end of the sampling holding amplifier is connected to the differential input end of the input isolation amplifier, the output end of the input isolation amplifier is connected to the input end of the sampling switch, the input end of the sampling clock is connected to the input end of the sampling switch clock, the output end of the sampling switch is connected to the input end of the active current mirror, and the output end of the active current mirror is connected to the intermediate frequency output end.
As can be seen from the above, the present invention applies VGLNA to a self-homodyne receiver. Specifically, the VGLNA gain is increased when the input power is low, and the VGLNA gain is decreased when the input power is high, so that the output power of the VGLNA can be maintained at a stable power (the average power is stable rather than the real-time power is constant). The stable power output ensures the normal work of the BLL and the SRDPS. In addition, the VGLNA can improve the isolation degree and prevent the SRA from leaking to the radio frequency input end.
The above receiver is a quadrature delay self-homodyne receiver structure, which uses the SRDPS proposed by the present invention to realize one-symbol delay and perform self-homodyne mixing, and the following simplified theoretical analysis is given:
the radio frequency input signal is an amplitude-modulated and phase-modulated signal with a carrier frequency of omega RF Symbol period of T symbol The amplitude information:
the phase information is as follows:
the radio frequency signal may be represented in the form:
the signals amplified by the VGLNA and the SRA are as follows:
wherein G is LNA Is VGLNA gain, G SRA1 Is the SRA gain, ω SRA1 For SRA free-running oscillation frequency, ENV SRA1 (t) is the normalized envelope function of the SRA, which in typical applications should be small enough not to produce smearing at the next super-regenerative sampling amplification.
The free-running frequency of the SRA coincides with the radio frequency signal carrier frequency:
ω SRA1 ＝ω RF (5)
the output signals of the TSRA are:
wherein, the tau SRA1 is the delay of TSRA sampling time compared with SRA, the omega SRA2 is TSRA free oscillation frequency, ENV SRA2 (t) is the normalized envelope function of the TSRA. It should be noted that the TSRA may operate in a mode close to saturation, with gain and A k]And (4) correlating.
The I path and Q path outputs of QSRA are respectively:
wherein, the [ tau ] SRA2 is the delay of QSRA sampling time to TSRA, the [ omega ] SRA3 is the TSRA free oscillation frequency, ENV SRA3 (t) is the normalized envelope function of the QSRA.
The free oscillation frequency of the QSRA is consistent with the carrier frequency of the radio frequency signal:
ω SRA3 ＝ω RF (9)
by tuning the oscillation frequency of the TSRA, the condition given by:
ω RF τ SRA1 +ω SRA2 τ SRA2 ＝ω RF T symbol (10)
the above equation also illustrates the principle of delay generation and phase adjustment by the SRDPS.
The TSRA oscillation frequency is still close to the carrier frequency:
ω SRA2 ≈ω RF (11)
the I-channel intermediate frequency output is obtained by mixing the SRA output signal with the I-channel output signal of QSRA, and it is necessary to note that QSRA output is saturated:
similar Q-path intermediate frequency output is obtained by mixing an SRA output signal and a Q-path output signal of QSRA:
the present invention proposes a baud rate locked loop (BLL), the principle and technical solution of which have been described above, supplemented by some circuit implementations and theoretical analyses, in order to better understand the invention by the skilled person:
the rf signal is given by equation 3, and the VGLNA output is:
the BLL provided by the invention detects the leading or lagging of the quenching signal by mixing the output of the VGLNA and the output of the SRO:
assuming the quenching signal produces a deviation δ:
the output of the VGLNA mixed with the SRO output is:
after the output of the mixer is subjected to low-pass filtering, the output is:
the above formula assumes
This condition is satisfied in conventional modulation methods such as QPSK, QAM, 8PSK, and the like. In the scope of observation, S LP (δ) is a monotonic function with respect to δ. Assuming that the control voltage when the VCO is synchronized with the baud clock is V 0 When delta =0, the output of the subtracter is V REF -S LP (0)＝V 0 BLL works in locked state; delta>When 0, VCO phase is advanced, at this moment, the output of subtracter is V REF -S LP (δ)<V 0 The VCO oscillation frequency is decreased until phase lock; delta<At 0, the VCO phase lags, at which time the subtractor output is V REF -S LP (δ)>V 0 The VCO oscillation frequency increases until phase lock.
Fig. 8, 9, and 10 are simulation verification results of several keys of the self-homodyne receiver: fig. 8 shows the VCO control voltage (up) and VCO output waveform (down) in the BLL after power-up, which shows that the VCO needs about 20ns for starting oscillation, the BLL tracking time is about 40nS, and the BLL can complete locking after power-up for 60 nS. Fig. 9 is an eye diagram of the Q-path if output waveform under QPSK modulation.
Fig. 10 shows (1) VGLNA output, (2) SRA quench signal, (3) SRA output, (4) TSRA quench signal, (5) TSRA output, (6) QSRA quench signal, (7) QSRA output, (8) Q mixer output, (9) sampling clock, and (10) Q intermediate frequency output during receiver operation.
In summary, compared with the prior art, the present embodiment has the following advantages and beneficial effects:
(1) Easy to integrate
The invention provides a fully integrated self-homodyne receiver front end, which is realized by replacing a passive delay line which is difficult to integrate by the super-regenerative delay phase-shifting method and the circuit thereof provided by the invention.
(2) Has a large dynamic range
The low noise amplifier in the embodiment of the invention can realize gain adjustment so as to ensure that each part in the receiver can stably operate under different input powers, and the receiver has higher sensitivity and larger dynamic range.
(3) Without reference clock input
The embodiment of the invention adopts a self-homodyne architecture, and the baud clock locking loop provided by the embodiment of the invention can recover a baud clock from a radio frequency signal, thereby generating a quenching signal and a sampling clock required by a receiver, and providing a self-synchronizing clock scheme without reference clock input.
(4) Reduced need for high speed ADCs
The intermediate frequency signal sampling amplifying circuit with the self-alignment characteristic, which is suitable for the super-regenerative receiver, solves the problem that the intermediate frequency signal in the super-regenerative receiver also shows periodic swing and return to zero to bring difficulty to ADC sampling, and reduces the requirement on a high-speed ADC.
In the foregoing description of the specification, reference to the description of "one embodiment/example," "another embodiment/example," or "certain embodiments/examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.
While the preferred embodiments of the present invention have been illustrated and described, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (8)
1. A millimeter wave self-homodyne receiver, comprising:
the variable gain low noise amplifier is used for adjusting gain according to the power of an input radio frequency signal so as to maintain the output power of the variable gain low noise amplifier at a preset power;
the baud clock locking loop is used for recovering a baud clock from the radio frequency signal, generating quenching signals of the super regenerative amplifiers and providing a sampling clock; the Baud clock locking loop comprises a first super regenerative amplifier, and a radio frequency signal output by the variable gain low noise amplifier passes through the first super regenerative amplifier and is output to a super regenerative delay phase-shifting circuit;
the super-regenerative delay phase-shifting circuit is used for realizing long delay and phase shifting through a super-regenerative amplifier and outputting IQ two paths of output signals delayed by one code element time; the first mixer is used for mixing the I path output signal and the radio frequency signal output by the baud clock locking loop, and the second mixer is used for mixing the Q path output signal and the radio frequency signal output by the baud clock locking loop;
and the intermediate frequency sampling amplifying circuit is used for sampling and amplifying the two paths of mixing signals.
2. A millimeter wave self-homodyne receiver according to claim 1, wherein the millimeter wave self-homodyne receiver is a quadrature self-homodyne receiver or a non-quadrature self-homodyne receiver.
3. The millimeter wave self-homodyne receiver of claim 1, wherein the baud clock-locked loop further comprises a third mixer, a low-pass filter, a subtractor, a voltage controlled oscillator, and a waveform shaper;
the output end of the variable gain low noise amplifier is respectively connected with the input end of the first super regenerative amplifier and the radio frequency input end of the third mixer, the output end of the third mixer is connected with the input end of the low-pass filter, the output end of the low-pass filter is connected with the negative input end of the subtracter, the positive input end of the subtracter is connected with the reference voltage, the output end of the subtracter is connected with the tuning control end of the voltage-controlled oscillator, the output end of the voltage-controlled oscillator is connected with the input end of the waveform shaper, and the output end of the waveform shaper outputs quenching signals of the super regenerative amplifiers.
4. A millimeter wave self-homodyne receiver according to claim 3, wherein the working principle of the baud clock locked loop is as follows:
the radio frequency signal is mixed with the radio frequency signal sampled and amplified by the first super regenerative amplifier through the third mixer, the sampling and amplification of the first super regenerative amplifier generate delay, the mixing output consists of the self-mixing quantity of the previous code element and the mixing quantities of the front code element and the rear code element, and the DC component of the mixing quantities of the front code element and the rear code element of the digital modulation scheme is 0; wherein, the self-mixing amount of a code element is reduced along with the backward movement of the sampling position;
the principle of loop locking is as follows: when the output signal of the voltage-controlled oscillator lags, the output delay of the first super regenerative amplifier is increased, the DC component output by the third mixer is reduced, the oscillation frequency of the voltage-controlled oscillator is controlled to be increased, and the output signal lag of the voltage-controlled oscillator is reduced; on the contrary, when the output signal of the voltage-controlled oscillator leads, the output delay of the first super regenerative amplifier is reduced, the DC component output by the third mixer is increased, the oscillation frequency of the voltage-controlled oscillator is controlled to be smaller, and the output signal of the voltage-controlled oscillator leads to be reduced.
5. The millimeter wave self-homodyne receiver of claim 1, wherein the super-regenerative delay phase-shifting circuit comprises a tunable super-regenerative amplifier, a driver amplifier, a polyphase filter and a quadrature super-regenerative amplifier;
the output end of the first regenerative amplifier is connected to the input end of the tunable super regenerative amplifier, the output end of the tunable super regenerative amplifier is connected to the input end of the drive amplifier, the input end of the drive amplifier is connected to the input end of the multi-phase filter, and the outputs of the I path and the Q path of the multi-phase filter are respectively connected to the injection ends of the I path and the Q path of the orthogonal super regenerative amplifier;
the quenching signal of the tunable super regenerative amplifier is lagged behind the first regenerative amplifier, the quenching signal of the quadrature super regenerative amplifier is lagged behind the tunable super regenerative amplifier, and the sum of the delay generated by the tunable super regenerative amplifier and the delay generated by the quadrature super regenerative amplifier is one code element time.
6. A millimeter wave self-homodyne receiver according to claim 5, wherein a regenerative amplifier stage is added between the tunable super regenerative amplifier and the quadrature super regenerative amplifier.
7. The millimeter wave self-homodyne receiver of claim 1, wherein the intermediate frequency sampling amplifying circuit comprises an I-path sampling holding amplifier, a Q-path sampling holding amplifier and a sampling clock generator, and a sampling clock of the sampling holding amplifier is generated by the baud clock locking loop and the sampling clock generator together.
8. A millimeter wave self-homodyne receiver according to claim 7, wherein the sampling clock generator comprises an inverter delay circuit, an edge detector, a schmitt trigger with input buffering; the clock input end is connected to the input end of the phase inverter delay circuit and the first input end of the edge detector, the output end of the phase inverter delay circuit is connected to the second input end of the edge detector, the output end of the phase inverter delay circuit is connected to the input end of the Schmitt trigger, and the output end of the Schmitt trigger outputs a differential clock;
the sampling holding amplifier comprises an input isolation amplifier, a sampling switch and an active current mirror; the input end of the input isolation amplifier is used as the input end of the sampling hold amplifier, the output end of the input isolation amplifier is connected to the input end of the sampling switch, the differential clock is connected to the clock input end of the sampling switch, the output end of the sampling switch is connected to the input end of the active current mirror, and the output end of the active current mirror is used as the output end of the millimeter wave self-homodyne receiver.
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