CN115865113B - Millimeter wave self-homodyne receiver - Google Patents
Millimeter wave self-homodyne receiver Download PDFInfo
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- CN115865113B CN115865113B CN202211376071.2A CN202211376071A CN115865113B CN 115865113 B CN115865113 B CN 115865113B CN 202211376071 A CN202211376071 A CN 202211376071A CN 115865113 B CN115865113 B CN 115865113B
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Abstract
The invention discloses a millimeter wave self-homodyne receiver, which comprises: a variable gain low noise amplifier for adjusting a gain according to the power of an input radio frequency signal; a baud clock locking loop for recovering the baud clock from the radio frequency signal, generating a quench signal for each super regenerative amplifier, and providing a sampling clock; the super-regenerative delay phase shifting circuit is used for realizing long delay and phase shifting through the super-regenerative amplifier and outputting IQ two paths of output signals delayed by one symbol time; the output signal of the I path is mixed with the radio frequency signal output by the Bode clock locking loop, and the output signal of the Q path is mixed with the radio frequency signal output by the Bode clock locking loop; and the intermediate frequency sampling and amplifying circuit is used for sampling and amplifying the two paths of mixed signals. The super-regenerative delay phase-shifting circuit replaces a passive delay line which is difficult to integrate, and the front end of the fully integrated self-homodyne receiver is realized. The invention can be widely applied to the technical field of communication.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a millimeter wave self-homodyne receiver.
Background
Sub-6GHz frequency spectrum resources are gradually exhausted, and millimeter wave communication technology becomes one of key technologies for realizing intelligent and deep interconnection of everything and constructing an air, world and sea integrated network due to ultra-wide continuous available frequency spectrum. However, the communication distance is limited by the lower gain of the millimeter wave amplifier and the higher propagation path loss in the air of the millimeter wave frequency band, and the receiver or the transmitter adopting the multistage cascade amplifier can reach the rated gain, which makes the millimeter wave communication system complex and inefficient, and especially in a high-speed communication system requiring a large bandwidth, the problem is more serious. Phased array technology is another solution, but large-scale arrays will also present a number of problems, such as local oscillator distribution networks that are particularly critical to the external receiver becoming inefficient and difficult to design in such large-scale arrays. In addition, in large-scale high-speed interconnection applications, the synchronization requirement of the clocks of each terminal significantly increases the complexity of the system.
Disclosure of Invention
In order to solve at least one of the technical problems existing in the prior art to a certain extent, the invention aims to provide a millimeter wave self-homodyne receiver.
The technical scheme adopted by the invention is as follows:
a millimeter wave self-homodyne receiver, comprising:
the variable gain low noise amplifier is used for adjusting the gain according to the power of the input radio frequency signal so as to maintain the output power of the variable gain low noise amplifier at a preset power;
a baud clock locking loop for recovering the baud clock from the radio frequency signal, generating a quench signal for each super regenerative amplifier, and providing a sampling clock; the Bot clock locking loop comprises a first super regenerative amplifier, and the radio frequency signal output by the variable gain low noise amplifier is output to the super regenerative delay phase shifting circuit after passing through the first super regenerative amplifier;
the super-regenerative delay phase shifting circuit is used for realizing long delay and phase shifting through the super-regenerative amplifier and outputting IQ two paths of output signals delayed by one symbol time; the output signal of the I path and the radio frequency signal output by the Bode clock locking loop are mixed by a first mixer, and the output signal of the Q path and the radio frequency signal output by the Bode clock locking loop are mixed by a second mixer;
and the intermediate frequency sampling and amplifying circuit is used for sampling and amplifying the two paths of mixed signals.
Further, the baud clock locking loop further comprises a third mixer, a low-pass filter, a subtracter, a voltage-controlled oscillator and a waveform shaper;
the output end of the variable gain low noise amplifier is respectively connected to the input end of the first super regenerative amplifier and the input end of the third mixer radio frequency, the output end of the third mixer is connected to the input end of the low pass filter, the output end of the low pass filter is connected to the negative input end of the subtracter, the positive input end of the subtracter is connected to the reference voltage, the output of the subtracter is connected to the tuning control end of the voltage-controlled oscillator, the output end of the voltage-controlled oscillator is connected to the input end of the waveform shaper, and the output end of the waveform shaper outputs quenching signals of the super regenerative amplifiers.
Further, the millimeter wave self-homodyne receiver is an orthogonal self-homodyne receiver or a non-orthogonal self-homodyne receiver.
Further, a comparator is used to replace the subtractor.
Further, the working principle of the baud clock locking loop is as follows:
the radio frequency signal is mixed with the radio frequency signal sampled and amplified by the first super regenerative amplifier through the third mixer, the first super regenerative amplifier samples and amplifies to generate delay, the mixed output consists of the self-mixing quantity of the previous code element and the mixing quantity of the front code element and the rear code element, and the DC component of the mixing quantity of the front code element and the rear code element is 0 for the digital modulation scheme; wherein the self-mixing amount of a code element is reduced along with the backward movement of the sampling position;
the principle of loop completion locking is: when the output signal of the voltage-controlled oscillator lags, the output delay of the first super-regenerative amplifier increases, the DC component output by the third mixer decreases, the oscillation frequency of the voltage-controlled oscillator is controlled to increase, and the output signal lag of the voltage-controlled oscillator decreases; on the contrary, when the output signal of the voltage controlled oscillator leads, the output delay of the first super regenerative amplifier is reduced, the DC component output by the third mixer is increased, the oscillation frequency of the controlled oscillator is smaller, and the output signal of the voltage controlled oscillator leads to be reduced.
Further, the super-regenerative delay phase-shifting circuit comprises a tunable super-regenerative amplifier, a driving amplifier, a multiphase filter and a quadrature super-regenerative amplifier;
the output end of the first regenerative amplifier is connected to the input end of the tunable super regenerative amplifier, the output end of the tunable super regenerative amplifier is connected to the input end of the driving amplifier, the input end of the driving amplifier is connected to the input end of the multi-phase filter, and the I-path and Q-path outputs of the multi-phase filter are respectively connected to the injection ends of the I-path and the Q-path of the quadrature super regenerative amplifier;
the quenching signal of the tunable super-regenerative amplifier is lagged compared with the quenching signal of the first regenerative amplifier, the quenching signal of the quadrature super-regenerative amplifier is lagged compared with the quenching signal of the tunable super-regenerative amplifier, the duty ratio of the quenching signal of the tunable super-regenerative amplifier is higher than that of the quenching signal of the first regenerative amplifier, and the sum of the delay generated by the tunable super-regenerative amplifier and the delay generated by the quadrature super-regenerative amplifier is one symbol time.
Further, the control end of the tunable super-regenerative amplifier is connected with a control voltage V PHS ；
When the output phase of the tunable super regenerative amplifier advances, the control voltage V is reduced PHS When the output phase of the tunable super regenerative amplifier lags, the control voltage V is increased PHS 。
Further, the polyphase filter is replaced with a quadrature signal generation circuit.
Further, a regenerative amplifier stage number is increased between the tunable super regenerative amplifier and the quadrature super regenerative amplifier.
Further, the intermediate frequency sampling amplifying circuit comprises an I path, a Q path sampling hold amplifier and a sampling clock generator, wherein the sampling clock of the sampling hold amplifier is generated together with the sampling clock generator through a Bode clock locking loop;
the output ends of the I-path mixer and the Q-path mixer are respectively connected to the input ends of the I-path sampling and holding amplifier and the output ends of the I-path sampling and holding amplifier and the Q-path sampling and holding amplifier are used as the output ends of the millimeter wave self-homodyne receiver;
the sampling clock provided by the Bode clock locking loop is connected to the input end of the sampling clock generator, and the differential clock output end of the sampling clock generator is connected to the differential clock input ends of the I-path and Q-path sampling and holding amplifiers.
Further, the sampling clock generator comprises an inverter delay circuit, an edge detector, and a schmitt trigger with an input buffer; the clock input end is connected to the input end of the inverter delay circuit and the first input end of the edge detector, the output end of the inverter delay circuit is connected to the second input end of the edge detector, the output end of the inverter delay circuit is connected to the input end of the Schmitt trigger, and the output end of the Schmitt trigger outputs a differential clock;
the sample-and-hold amplifier comprises an input isolation amplifier, a sampling switch and an active current mirror; the input end of the input isolation amplifier is used as the input end of the sample-and-hold amplifier, the output end of the input isolation amplifier is connected to the input end of the sampling switch, the differential clock is connected to the clock input end of the sampling switch, the output end of the sampling switch is connected to the input end of the active current mirror, and the output end of the active current mirror is used as the output end of the millimeter wave self-homodyne receiver.
The beneficial effects of the invention are as follows: the super-regenerative delay phase-shifting circuit replaces a passive delay line which is difficult to integrate, and realizes the front end of the fully integrated self-homodyne receiver; in addition, the gain is regulated by the variable gain low noise amplifier so as to ensure the stable operation of the receiver and improve the dynamic range.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description is made with reference to the accompanying drawings of the embodiments of the present invention or the related technical solutions in the prior art, and it should be understood that the drawings in the following description are only for convenience and clarity of describing some embodiments in the technical solutions of the present invention, and other drawings may be obtained according to these drawings without the need of inventive labor for those skilled in the art.
FIG. 1 is a schematic block diagram of a super regenerative amplifier implementing long delay and phase shifting in an embodiment of the present invention;
FIG. 2 is a schematic diagram of a super regenerative amplifier implementing long delay and phase shifting in an embodiment of the present invention;
FIG. 3 is a schematic diagram of a super regenerative delay and phase shift circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a Bott clock lock loop in an embodiment of the present invention;
FIG. 5 is a schematic diagram of a delay self-mixing implementation of sampling position detection in an embodiment of the present invention;
FIG. 6 is a schematic diagram of a sampling and amplifying circuit according to an embodiment of the present invention;
fig. 7 is a block diagram of a self homodyne receiver according to an embodiment of the present invention;
FIG. 8 is a graph of first transient simulation results from a homodyne receiver in an embodiment of the present invention;
FIG. 9 is a graph of second transient simulation results from a homodyne receiver in an embodiment of the present invention;
FIG. 10 is a diagram of third transient simulation results from a homodyne receiver in an embodiment of the present invention;
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the invention. The step numbers in the following embodiments are set for convenience of illustration only, and the order between the steps is not limited in any way, and the execution order of the steps in the embodiments may be adaptively adjusted according to the understanding of those skilled in the art.
In the description of the present invention, it should be understood that references to orientation descriptions such as upper, lower, front, rear, left, right, etc. are based on the orientation or positional relationship shown in the drawings, are merely for convenience of description of the present invention and to simplify the description, and do not indicate or imply that the apparatus or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present invention.
In the description of the present invention, a number means one or more, a number means two or more, and greater than, less than, exceeding, etc. are understood to not include the present number, and above, below, within, etc. are understood to include the present number. The description of the first and second is for the purpose of distinguishing between technical features only and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
In the description of the present invention, unless explicitly defined otherwise, terms such as arrangement, installation, connection, etc. should be construed broadly and the specific meaning of the terms in the present invention can be reasonably determined by a person skilled in the art in combination with the specific contents of the technical scheme.
To avoid the need for clock synchronization, some millimeter wave transceivers employ OOK modulation and demodulation schemes to achieve incoherent communication. The scheme also avoids the difficult problems of local oscillation generation and distribution, and reduces the area, complexity and power consumption of the transceiver. However, OOK transceivers suffer from several drawbacks: 1) The millimeter wave OOK demodulator has lower gain, and to improve the sensitivity of the receiver, a low noise amplifier with larger power consumption is often needed to be added in the front stage; 2) The transmitter has a larger peak-to-average power ratio (PAPR), which reduces the energy efficiency ratio of the transmitter; 3) The very low spectral efficiency makes it necessary to achieve the same communication rate with a larger bandwidth, and the design of a wideband baseband amplifier is very difficult not only at radio frequency; 4) To meet the high-speed communication requirements, OOK transceivers require high sample rate, high power consumption digital-to-analog/analog converters. These reasons have led to OOK modem schemes currently aimed primarily at wired or short-range wireless communication on-chip or between chips.
The super-regenerative receiver receives attention from people because of the fact that the super-regenerative receiver can realize larger gain with low power consumption, and the prior art scheme also shows the capability of the super-regenerative receiver for realizing 16QAM even 64QAM demodulation and high-speed communication, and can realize low power consumption and high sensitivity. The defects of the existing super-regenerative receiver are mainly caused by the following two points: 1) The coherent demodulation super regenerative receiver requires an additional quench signal to control, which needs to be clock synchronized with the baud rate of the radio frequency input signal and have a certain relative phase, which complicates the overall clocking scheme of the system; 2) The super-regenerative amplifier also shows periodic oscillation and zero setting due to the working characteristics of periodic oscillation starting and extinguishing, and similar to a zero setting code, in a high-speed communication system, the ADC brings difficulty to ADC sampling, the ADC needs to sample signals at a position with larger oscillation amplitude of the intermediate frequency signal, and accurate clock generation has difficulty.
The frequency sources of the communication system and their distribution system have been mentioned above and are described in more detail here: the existing microwave and millimeter wave communication system mostly adopts a phase-locked loop as a frequency source, which consumes a larger area and power consumption, the phase noise of the millimeter wave phase-locked loop is also unsatisfactory, in addition, the reference clock of the phase-locked loop is often generated by a crystal oscillator, which consumes at least tens of milliwatts of power consumption, and is difficult to integrate, thus the phase-locked loop is one of the most expensive and large-size off-chip elements of a transceiver. Some researchers have proposed receivers using crystal-less oscillators, mainly of the following two types: 1) The crystal oscillator is replaced by an integratable oscillator such as an LC or relaxation oscillator, the main drawbacks of these schemes are that they still have a large power consumption and PVT is too sensitive; 2) The carrier recovery technology is adopted, so that a transceiver does not need a crystal oscillator, a carrier recovery loop is often adopted to replace a phase-locked loop, and it is noted that, due to the frequency deviation of different crystal oscillators, in a frequency synthesis scheme adopting the crystal oscillator and the phase-locked loop, the digital baseband needs to compensate the frequency deviation of the crystal oscillator. The carrier recovery technique avoids many of the problems of crystal oscillators, which do not require complex local oscillator distribution networks, but the prior art still suffers from these problems: 1) The locking time is too long, so that the interference is easy to receive; 2) The locking range is smaller; 3) With comparable complexity and power consumption as PLLs.
The self-homodyne detection is a signal receiving technology in the field of coherent optical communication, has the characteristic of eliminating phase noise, and even if a received signal comes from a free-running oscillator, the error rate of a receiver is not obviously deteriorated. The self homodyne receiver is ideally well suited for designing a communication system without a crystal oscillator or a reference clock because of no need of demodulating a local oscillator signal, however, two key problems exist that make it difficult to apply the self homodyne receiver in a microwave/millimeter wave communication system: 1) The 1-symbol delay line required for self-homodyne reception is difficult to integrate, even if the 1-symbol delay line is integrated on a chip by adopting an advanced process, the huge area and loss are not acceptable, and the next symbol period is different at different symbol rates, so that the 1-symbol delay line is difficult to realize by adopting an off-chip element; 2) The self-homodyne mixing is characterized by square law mixing, and is difficult to apply to a modulation scene of simultaneous amplitude modulation and phase modulation.
In order to solve the above technical problems, the embodiments of the present invention provide an integrable millimeter wave self-homodyne receiver scheme, a clock recovery method and a circuit thereof to realize self-synchronous self-homodyne demodulation, and based on the above methods and circuits, the present invention further provides a self-synchronous receiver scheme that does not need an intrinsic input or a phase-locked loop to perform clock synchronization.
The technical scheme provided by the embodiment of the invention comprises the following steps: a long delay and phase shift circuit (SRDPS) implemented by a Super Regenerative Amplifier (SRA), a baud rate locked loop (BLL), a sample-and-hold amplifier with self-aligned sample positions, and a self-homodyne receiver employing these methods or circuits.
(1) The embodiment of the invention provides a method for realizing long delay and phase shift by a super regenerative amplifier and a circuit thereof
As shown in fig. 1, the two or more stages of super regenerative amplifiers generate a large delay, and the phase shift is realized by tuning the pre-stage super regenerative amplifier, and the delay and phase shift principle is as shown in fig. 2: the output of the SRA1 is delayed compared with the input RFin, the output of the SRA2 is delayed compared with the output of the SRA1, and the RFout is the sum of the delays of the two stages of super-regenerative amplifiers compared with the RFin; SRA1 tuning control voltage V PHS When high, the oscillation frequency is high, the sensitivity function of the super regenerative amplifier determines that the SRA2 output RFout has the characteristics of sampling amplification, and therefore, the SRA2 output RFout is at V PHS Advance at high, otherwise RFout is at V PHS Low time hysteresis. The method utilizes the super regenerative amplifier working in the saturated state to realize amplification and delay, thereby solving the problem of mixing the delay line and the square law. Phase adjustment is realized by adjusting the oscillation frequency of a pre-stage super-regenerative amplifier in a delay circuit, so that the complexity of the system is reduced and the PVT robustness of the system is improvedStick property. Different from the prior art, the scheme adopts two or more than two stages of super regenerative amplifiers to realize larger phase shift; the scheme realizes continuous phase adjustment by tuning the pre-stage super regenerative amplifier.
Based on fig. 1, a long delay and phase shift circuit implemented by a super regenerative amplifier employed in a self-synchronous receiver is shown in fig. 3, which is composed of a Tunable Super Regenerative Amplifier (TSRA), a driving amplifier, a polyphase filter (PPF), and a Quadrature Super Regenerative Amplifier (QSRA). This architecture is an example of the method shown in fig. 1, which uses QSRA to generate quadrature output signals, and to drive the QSRA, a drive amplifier and a polyphase filter are added between QSRA and TSRA, wherein the polyphase filter can be used to generate quadrature signals to inject into the QSRA. The multiphase filter can be replaced by other types of quadrature signal generating circuits such as a quadrature coupler, or the number of stages of a super regenerative amplifier is increased, or a driving amplifier is added or removed, or the quadrature coupler is adopted to output quadrature signals to replace QSRA (quad small form factor) circuits and other circuits for performing long delay and phase shift based on the schematic diagram shown in the figure 1, and the long delay and phase shift method realized by the super regenerative amplifier shown in the figures 1 and 2 provided by the invention is still adopted.
(2) The embodiment of the invention provides a method for recovering a clock from a radio frequency signal and a circuit thereof
As shown in fig. 4, the radio frequency signal recovery clock circuit employed in the self-synchronizing receiver is composed of a super regenerative amplifier (SRA 1), a mixer, a comparator, a low pass filter, a voltage controlled oscillator, and a quench signal shaping circuit. The working principle is as shown in figure 5: the radio frequency signal is mixed with the radio frequency signal amplified by the SRA sampling through the mixer, the SRA sampling is amplified to bring a certain delay, the mixed output consists of the self-mixing quantity of the previous code element and the mixing quantity of the front code element and the rear code element, the DC component of the mixing quantity of the front code element and the rear code element is 0 for most digital modulation schemes, and the self-mixing quantity of one code element is reduced along with the backward movement of the sampling position. The above principle can be derived from the following formulas (14) to (17).
The SRA sampling position is determined by the quenching signal, the output of the mixer is filtered by a low-pass filter, and then is compared and amplified by a subtracter (active balun) for controlling a voltage-controlled oscillator for generating the quenching signal, wherein the voltage-controlled oscillator can adopt an LC oscillator, a ring oscillator and the like. The principle of loop completion locking is: when the VCO output signal is lagged, the SRA output delay is increased, the DC component of the mixer output is reduced, the VCO oscillation frequency is controlled to be increased, and the VCO output signal is lagged to be reduced.
It should be noted that various other modifications of the circuit shown in fig. 4 according to the method and the concept of the present invention should be made within the scope of the claims, for example: the comparator may be implemented by various types of circuits (analog or digital) with subtraction function or by just an inverter, the pulse shaping circuit may be implemented by various simple (inverter) or complex signal shaping and generating circuits, or directly with the unshaped signal as clock output.
(3) The embodiment of the invention provides an intermediate frequency signal sampling amplifying circuit which is used for solving the problem that the intermediate frequency signal in a super-regenerative receiver also shows periodic swing and zero return to bring difficulty to ADC sampling
As shown in fig. 6, the sampling amplification circuit is composed of a self-aligned sampling clock generation circuit and a sampling hold amplifier. The input of the self-aligned sampling clock generation circuit comes from the output of the baud clock locking loop, the sampling clock signal with a certain pulse width and the same period as the baud rate clock is generated through two paths of different delays, and the sampling at the intermediate frequency peak value can be realized through reasonable circuit design without an additional calibration circuit. The direct generation of the sample-and-hold circuit clock based on synchronizing with the quench signal is critical to achieving self-aligned sampling. The sampling and holding amplifier consists of a driving amplifier, a sampling switch and an output driving amplifier, and has the functions of sampling and amplifying the output signal of the mixer and converting the output signal into single-ended signal output. The circuit solves the problems that intermediate frequency signals of the super-regenerative receiver also show periodic swing and return to zero, and has great advantages in the aspects of system complexity, power consumption and the like compared with a scheme of oversampling by using a high sampling rate ADC.
Based on the foregoing method and circuit, the present invention provides a self-homodyne receiver, as shown in fig. 7, which is composed of a variable gain amplifier (VGLNA), a baud rate locked loop, a super-regenerative delay and phase shift circuit, a mixer, a sampling clock generation circuit, and a sample-hold amplifier. The structure is a quadrature demodulation self-homodyne (VGLNA) receiver, when the receiver works, radio frequency signals are amplified by the VGLNA, and the stable VGLNA output power can be maintained under different input powers by adjusting the gain of the VGLNA, so that the normal operation of the receiver is ensured. The VGLNA output signal is amplified by SRA sampling, and the BLL recovers the Bode clock and generates a quench signal of SRA, TSRA, QSRA, by adjusting the BLL reference voltage, the relative positions of the quench signal and the sampling clock and the input RF signal symbols can be shifted. The SRA output signal is input to the SRDPS, the output signal of the SRDPS is delayed by one symbol time relative to the input signal by adjusting the phase modulation control voltage V in the SRDPS PHS The adjustment of the relative phase of the post-delay signal and the pre-delay signal can be achieved. The SRA output signals are mixed with IQ two paths of output signals of the SRDPS respectively, intermediate frequency output of the IQ two paths of mixers is sampled, held and amplified by a sampling amplifying circuit, and an input clock of the sampling, holding and amplifying circuit is also generated by BLL.
The above self-homodyne receiver adopts a new receiver architecture, which combines a super regenerative receiver with the self-homodyne receiver, and has the following main differences from the prior art: the structure is characterized in that a super regenerative amplifier generates delay to carry out delay self-homodyne; the self-homodyne reception of the structure is orthogonal; the structure performs clock recovery at the radio frequency. Variations of the self-homodyne receiver described above may be generated based on this technique, such as generating a quadrature signal from the SRA output, and then delaying the self-homodyne signal with the in-phase delayed one symbol signal.
As shown in fig. 7, an embodiment of the present invention provides a self-synchronizing millimeter wave self-homodyne receiver, including:
variable Gain Low Noise Amplifier (VGLNA): the gain is regulated to ensure the stable operation of the receiver and improve the dynamic range.
Baud clock locked loop (BLL): the super regenerative amplifier also serves as an amplifier on the radio frequency link, and serves to recover the baud clock from the radio frequency signal, generate each super regenerative amplifier quench signal, and provide a reference clock for the sampling clock generator. It comprises the following steps: mixer, SRA, low pass filter, subtractor, VCO, waveform shaper.
Super regenerative delay phase shift circuit (SRDPS): functioning to generate the quadrature radio frequency signal of one-code original time delay required for quadrature self-homodyne demodulation. It comprises the following steps: TSRA, driver amplifier, polyphase filter, QSRA.
A mixer: used as a mixer for an orthogonal self-homodyne receiver.
An intermediate frequency sampling amplifying circuit: and sampling and amplifying the intermediate frequency signal. It comprises the following steps: sampling clock generator, sample hold amplifier.
The connection relation of each part in the receiver is as follows: the radio frequency signal RFin is connected to the VGLNA input end, the VGLNA output end is connected to the radio frequency input end of BLL, the BLL radio frequency output end is respectively connected to the radio frequency input end of TSRA in SRDPS, the I-path and Q Lu Hunpin ware radio frequency input end, the BLL reference voltage is connected to the BLL reference voltage input end, BLL quenching signal outputs 1, 2 and 3 are respectively connected to the SRA quenching signal input end, the TSRA quenching signal input end in SRDPS and the quenching signal input end of QSRRA in SRDPS, and the BLL sampling reference clock output end is connected to the sampling clock generator input end. The differential clock output end of the sampling clock generator is connected to the differential clock input ends of the I-path and Q-path sampling and holding amplifiers. Phase adjustment voltage V PHS The output ends of the I path and the Q path of the QSRA in the SRDPS are respectively connected to the local oscillation input ends of the I path and the Q Lu Hunpin device. The output ends of the I-path and Q-path mixers are respectively connected to the input ends of the I-path and Q-path sample-and-hold amplifiers, and the output ends of the I-path and Q-path sample-and-hold amplifiers are connected to the I-path and Q-path intermediate frequency output ends of the receiver.
When the receiver works, radio frequency signals are amplified by VGLNA and SRA and input into IQ two paths of mixing frequency to be radio frequency input ends, the radio frequency signals are amplified by VGLNA and SRA, then quadrature radio frequency signals delayed by one code element time are generated by SRDPS, the quadrature radio frequency signals are input into the local oscillation input ends of the IQ two paths of mixers, intermediate frequency input of the mixers is processed by an intermediate frequency sampling amplifying circuit, and quenching signals of SRA, TSRA, QSRA and reference clocks of the sampling amplifying circuit in the receiver are generated by BLL.
The SRDPS internal connection relations are: the output end of the TSRA is connected to the input end of the driving amplifier, the input end of the driving amplifier is connected to the input end of the multiphase filter, and the I-path and Q-path outputs of the multiphase filter are respectively connected to the I-path and Q-path injection ends of the QSRA. The quench signal of the TSRA lags the SRA, the quench signal of the QSRA lags the TSRA, and the duty cycle of the TSRA quench signal is higher than the SRA, the sum of the delay produced by the TSRA and the delay produced by the QSRA being one symbol time. The SRDPS phase adjustment method comprises the following steps: reducing V when QSRA output phase advances PHS Increasing V when QSRA output phase lags PHS 。
The BLL internal connection relationship is: the radio frequency input end is connected to the SRA input end, the mixer radio frequency input end, the SRA output end is connected to the mixer local oscillator input end, the mixer output end is connected to the low pass filter (first order RC low pass filter) input end, the low pass filter output end is connected to the subtracter negative input end, the reference voltage input is connected to the subtracter positive input end, the subtracter (active current mirror amplifier) output is connected to the VCO tuning control end, the VCO output end is connected to the waveform shaper input end, the waveform shaper output ends 1, 2 and 3 are connected to the quenching signal output ends 1, 2 and 3 (the output end 1 is connected to the SRA), and the waveform shaper output end 4 is connected to the sampling reference clock output end. The waveform shaper is implemented by 4 groups of cascaded inverters with different stages, the duty cycle of the output signal can be adjusted by adjusting the bias of the inverters, and different delays can be generated by adjusting the stages.
The sampling clock generator includes: inverter delay circuit, edge detector (NAND gate), schmitt trigger with input buffer (inverter, transmission gate), the connection relation is: the clock input end is connected to the input end of the inverter delay circuit and the input end 2 of the edge detector, the output end of the inverter delay circuit is connected to the input end 1 of the edge detector, the output end of the inverter delay circuit is connected to the input end of the inverter of the schmitt trigger and the input end of the transmission gate, the output ends of the inverter delay circuit and the output end of the transmission gate are connected to the input end 1 and the input end 2 of the schmitt trigger, and the output ends 1 and 2 of the schmitt trigger serve as differential clock output.
The sample-and-hold amplifier includes: an input isolation amplifier (differential common source amplifier), a sampling switch, and an active current mirror. The connection relation is as follows: the input end of the sampling hold amplifier is connected to the differential input end of the input isolation amplifier, the output end of the input isolation amplifier is connected to the input end of the sampling switch, the input end of the sampling clock is connected to the input end of the sampling clock, the output end of the sampling switch is connected to the input end of the active current mirror, and the output end of the active current mirror is connected to the intermediate frequency output end.
From the above, it can be seen that the present invention applies VGLNA to a self homodyne receiver. Specifically, when the input power is low, the VGLNA gain is increased, and when the input power is high, the VGLNA gain is decreased, so that the VGLNA output power can be maintained at a stable power (average power is stable rather than real-time power being constant). The stable power output ensures normal operation of the BLL and SRDPS. In addition, VGLNA can improve isolation and prevent SRA from leaking to the radio frequency input end.
The above-mentioned receiver is a quadrature delay self-homodyne receiver structure, which implements one symbol delay by using the SRDPS proposed by the present invention, and performs self-homodyne mixing, and the following simplified theoretical analysis is given:
the radio frequency input signal is an amplitude-modulated phase-modulated signal with a carrier frequency omega RF The symbol period is T symbol Amplitude information thereof:
its phase information:
the radio frequency signal may be expressed in the form of:
the signals amplified by VGLNA and SRA are:
wherein G is LNA For VGLNA gain, G SRA1 For SRA gain, ω SRA1 For SRA free oscillation frequency, ENV SRA1 (t) is a normalized envelope function of the SRA, which in a typical application should be small enough not to produce smearing at the next super-regenerative sampling amplification.
The free oscillation frequency of the SRA corresponds to the carrier frequency of the radio frequency signal:
ω SRA1 ＝ω RF (5)
the output signal of the TSRA is:
wherein τSRA1 is the delay of TSRA sampling time compared with SRA, ωSRA2 is TSRA free oscillation frequency, ENV SRA2 (t) is a normalized envelope function of TSRA. It should be noted that the TSRA may operate in a mode that is close to saturation, with a gain that is equal to Ak]And (5) correlation.
The outputs of the I path and the Q path of QSRA are respectively:
wherein τSRA2 is delay of QSRA sampling time compared with TSRA, ωSRA3 is free oscillation frequency of TSRA, and ENV SRA3 (t) is a normalized envelope function of QSRA.
The free oscillation frequency of the QSRA is consistent with the carrier frequency of the radio frequency signal:
ω SRA3 ＝ω RF (9)
the condition given by the following equation can be satisfied by tuning the oscillation frequency of the TSRA:
ω RF τ SRA1 +ω SRA2 τ SRA2 ＝ω RF T symbol (10)
the above equation also illustrates the principle of SRDPS generation delay and phase adjustment.
The TSRA oscillation frequency is still close to the carrier frequency:
ω SRA2 ≈ω RF (11)
the I-way intermediate frequency output is obtained by mixing the SRA output signal with the I-way QSRA output signal, and attention should be paid to the saturation of the QSRA output:
a similar Q-way intermediate frequency output is obtained by mixing the SRA output signal with the Q-way output signal of QSRA:
the present invention proposes a baud rate locked loop (BLL), the principles and technical solutions of which have been described in the foregoing, and some circuit implementations and theoretical analyses are supplemented here to facilitate a better understanding of the present invention by the skilled person:
the radio frequency signal is given by equation 3, VGLNA output is:
the BLL proposed by the present invention detects whether the quench signal is leading or lagging by mixing the VGLNA output with the SRO output:
assume that the quench signal produces a bias delta:
the VGLNA output and SRO output mixed output is:
the mixer output is low pass filtered and then output is:
the above-mentioned method assumesThis condition is satisfied in conventional modulation methods such as QPSK, QAM, 8PSK, etc. Within the scope of observation, S LP (delta) is a monotonic function with respect to delta. Assume that the control voltage when the VCO is synchronized with the baud clock is V 0 When δ=0, the subtractor outputs V REF -S LP (0)＝V 0 BLL is operated in a locked state; delta>At 0, the VCO phase advances, and the subtractor output is V REF -S LP (δ)<V 0 The VCO oscillation frequency decreases until phase lock; delta<0, the VCO phase lags, at which time the subtractor output is V REF -S LP (δ)>V 0 The VCO oscillation frequency increases until phase lock.
Fig. 8, 9, and 10 are simulation verification results of several key of the self-homodyne receiver: fig. 8 shows the VCO control voltage (up) and VCO output waveform (down) waveforms in the BLL after power-up, and it can be seen that the VCO needs about 20nS for oscillation start, the BLL tracking time is about 40nS, and the BLL can be locked after power-up for 60 nS. Fig. 9 is a waveform eye diagram of Q-path intermediate frequency output under QPSK modulation.
Fig. 10 shows (1) VGLNA output, (2) SRA quench signal, (3) SRA output, (4) TSRA quench signal, (5) TSRA output, (6) QSRA quench signal, (7) QSRA output, (8) Q mixer output, (9) sample clock, and (10) Q intermediate frequency output during receiver operation.
In summary, compared with the prior art, the embodiment has the following advantages and beneficial effects:
(1) Easy to integrate
The invention provides a front end of a fully integrated self-homodyne receiver, which is realized by replacing a passive delay line which is difficult to integrate by the super-regenerative delay phase shifting method and the circuit thereof.
(2) With a large dynamic range
The low-noise amplifier in the embodiment of the invention can realize gain adjustment so as to ensure that each part in the receiver can stably operate under different input powers, the receiver has higher sensitivity, and the receiver has larger dynamic range.
(3) Without reference clock input
The embodiment of the invention adopts a self-homodyne architecture, and the Bode clock locking loop provided by the embodiment of the invention can recover the Bode clock from the radio frequency signal, and thereby generate the quenching signal and the sampling clock required by the receiver, and provides a self-synchronizing clock scheme without reference clock input.
(4) Demand reduction for high speed ADC
The intermediate frequency signal sampling amplifying circuit with the self-alignment characteristic, which is suitable for the super-regenerative receiver, solves the problem that the intermediate frequency signal in the super-regenerative receiver also presents periodic swing and zero resetting to cause difficulties in ADC sampling, and reduces the requirement for high-speed ADC.
In the foregoing description of the present specification, reference has been made to the terms "one embodiment/example", "another embodiment/example", "certain embodiments/examples", and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that: many changes, modifications, substitutions and variations may be made to the embodiments without departing from the spirit and principles of the invention, the scope of which is defined by the claims and their equivalents.
While the preferred embodiment of the present invention has been described in detail, the present invention is not limited to the above embodiments, and various equivalent modifications and substitutions can be made by those skilled in the art without departing from the spirit of the present invention, and these equivalent modifications and substitutions are intended to be included in the scope of the present invention as defined in the appended claims.
Claims (8)
1. A millimeter wave self-homodyne receiver, comprising:
the variable gain low noise amplifier is used for adjusting the gain according to the power of the input radio frequency signal so as to maintain the output power of the variable gain low noise amplifier at a preset power;
a baud clock locking loop for recovering the baud clock from the radio frequency signal, generating a quench signal for each super regenerative amplifier, and providing a sampling clock; the Bot clock locking loop comprises a first super regenerative amplifier, and the radio frequency signal output by the variable gain low noise amplifier is output to the super regenerative delay phase shifting circuit after passing through the first super regenerative amplifier;
the super-regenerative delay phase shifting circuit is used for realizing long delay and phase shifting through the super-regenerative amplifier and outputting IQ two paths of output signals delayed by one symbol time; the output signal of the I path and the radio frequency signal output by the Bode clock locking loop are mixed by a first mixer, and the output signal of the Q path and the radio frequency signal output by the Bode clock locking loop are mixed by a second mixer;
and the intermediate frequency sampling and amplifying circuit is used for sampling and amplifying the two paths of mixed signals.
2. A millimeter wave self-homodyne receiver according to claim 1, characterized in that the millimeter wave self-homodyne receiver is an orthogonal self-homodyne receiver or a non-orthogonal self-homodyne receiver.
3. The millimeter wave self-homodyne receiver according to claim 1, wherein said baud clock locking loop further comprises a third mixer, a low pass filter, a subtractor, a voltage controlled oscillator, and a waveform shaper;
the output end of the variable gain low noise amplifier is respectively connected to the input end of the first super regenerative amplifier and the input end of the third mixer radio frequency, the output end of the third mixer is connected to the input end of the low pass filter, the output end of the low pass filter is connected to the negative input end of the subtracter, the positive input end of the subtracter is connected to the reference voltage, the output of the subtracter is connected to the tuning control end of the voltage-controlled oscillator, the output end of the voltage-controlled oscillator is connected to the input end of the waveform shaper, and the output end of the waveform shaper outputs quenching signals of the super regenerative amplifiers.
4. A millimeter wave self-homodyne receiver according to claim 3, wherein the baud clock locking loop operates on the principle of:
the radio frequency signal is mixed with the radio frequency signal sampled and amplified by the first super regenerative amplifier through the third mixer, the first super regenerative amplifier samples and amplifies to generate delay, the mixed output consists of the self-mixing quantity of the previous code element and the mixing quantity of the front code element and the rear code element, and the DC component of the mixing quantity of the front code element and the rear code element is 0 for the digital modulation scheme; wherein the self-mixing amount of a code element is reduced along with the backward movement of the sampling position;
the principle of loop completion locking is: when the output signal of the voltage-controlled oscillator lags, the output delay of the first super-regenerative amplifier increases, the DC component output by the third mixer decreases, the oscillation frequency of the voltage-controlled oscillator is controlled to increase, and the output signal lag of the voltage-controlled oscillator decreases; on the contrary, when the output signal of the voltage controlled oscillator leads, the output delay of the first super regenerative amplifier is reduced, the DC component output by the third mixer is increased, the oscillation frequency of the controlled oscillator is smaller, and the output signal of the voltage controlled oscillator leads to be reduced.
5. The millimeter wave self-homodyne receiver according to claim 1, wherein said super-regenerative delay phase shift circuit comprises a tunable super-regenerative amplifier, a driver amplifier, a polyphase filter, and a quadrature super-regenerative amplifier;
the output end of the first super-regenerative amplifier is connected to the input end of the tunable super-regenerative amplifier, the output end of the tunable super-regenerative amplifier is connected to the input end of the driving amplifier, the input end of the driving amplifier is connected to the input end of the multi-phase filter, and the I-path and Q-path outputs of the multi-phase filter are respectively connected to the injection ends of the I-path and the Q-path of the quadrature super-regenerative amplifier;
wherein the quench signal of the tunable super-regenerative amplifier lags the first regenerative amplifier, the quench signal of the quadrature super-regenerative amplifier lags the tunable super-regenerative amplifier, and the sum of the delay generated by the tunable super-regenerative amplifier and the delay generated by the quadrature super-regenerative amplifier is a symbol time.
6. A millimeter wave self-homodyne receiver according to claim 5, wherein a regenerative amplifier stage number is added between the tunable super regenerative amplifier and the quadrature super regenerative amplifier.
7. The millimeter wave self-homodyne receiver according to claim 1, wherein said intermediate frequency sampling amplification circuit comprises I-way, Q-way sample-and-hold amplifiers and a sampling clock generator, the sampling clock of the sample-and-hold amplifiers being co-generated with the sampling clock generator by a baud clock locking loop.
8. The millimeter wave self-homodyne receiver according to claim 7, wherein said sampling clock generator comprises an inverter delay circuit, an edge detector, a schmitt trigger with input buffering; the clock input end is connected to the input end of the inverter delay circuit and the first input end of the edge detector, the output end of the inverter delay circuit is connected to the second input end of the edge detector, the output end of the inverter delay circuit is connected to the input end of the Schmitt trigger, and the output end of the Schmitt trigger outputs a differential clock;
the sample-and-hold amplifier comprises an input isolation amplifier, a sampling switch and an active current mirror; the input end of the input isolation amplifier is used as the input end of the sample-and-hold amplifier, the output end of the input isolation amplifier is connected to the input end of the sampling switch, the differential clock is connected to the clock input end of the sampling switch, the output end of the sampling switch is connected to the input end of the active current mirror, and the output end of the active current mirror is used as the output end of the millimeter wave self-homodyne receiver.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009064478A2 (en) * | 2007-11-13 | 2009-05-22 | Oewaves, Inc. | Photonic based cross-correlation homodyne detection with low phase noise |
| CN101689831A (en) * | 2007-07-10 | 2010-03-31 | 高通股份有限公司 | Have a plurality of SR devices that are tuned to superregenerative in parallel (SR) amplifier of different frequencies |
| CN107634814A (en) * | 2017-09-13 | 2018-01-26 | 吉林大学 | The removing method of carrier path crosstalk in a kind of mode division multiplexing system from homodyne detection |
| CN109743068A (en) * | 2018-12-27 | 2019-05-10 | 复旦大学 | The super renewable receiver of dynamic regulation of the wake-up receiver of 5G millimeter wave |
| CN113992221A (en) * | 2021-12-29 | 2022-01-28 | 华南理工大学 | Millimeter wave super-regenerative receiver with high data rate |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7263138B2 (en) * | 2003-09-25 | 2007-08-28 | Microchip Technology Incorporated | Q-quenching super-regenerative receiver |
| US8055234B2 (en) * | 2008-06-27 | 2011-11-08 | Telefonaktiebolaget Lm Ericsson (Publ) | Methods and apparatus for suppressing strong-signal interference in low-IF receivers |
| WO2014070763A1 (en) * | 2012-10-30 | 2014-05-08 | Anayas360.Com, Llc | Compact and low-power millimeter-wave integrated vco-up/down- converter with gain-boosting |
| US9178551B2 (en) * | 2013-08-12 | 2015-11-03 | The Trustees Of Columbia University In The City Of New York | Circuits and methods for pulse radio receivers |
| US9621270B2 (en) * | 2013-09-24 | 2017-04-11 | Zte Corporation | System and methods for fiber and wireless integration |
-
2022
- 2022-11-04 CN CN202211376071.2A patent/CN115865113B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101689831A (en) * | 2007-07-10 | 2010-03-31 | 高通股份有限公司 | Have a plurality of SR devices that are tuned to superregenerative in parallel (SR) amplifier of different frequencies |
| WO2009064478A2 (en) * | 2007-11-13 | 2009-05-22 | Oewaves, Inc. | Photonic based cross-correlation homodyne detection with low phase noise |
| CN107634814A (en) * | 2017-09-13 | 2018-01-26 | 吉林大学 | The removing method of carrier path crosstalk in a kind of mode division multiplexing system from homodyne detection |
| CN109743068A (en) * | 2018-12-27 | 2019-05-10 | 复旦大学 | The super renewable receiver of dynamic regulation of the wake-up receiver of 5G millimeter wave |
| CN113992221A (en) * | 2021-12-29 | 2022-01-28 | 华南理工大学 | Millimeter wave super-regenerative receiver with high data rate |
Non-Patent Citations (2)
| Title |
|---|
| Millimeter-Wave Radio-Over-Fiber System Based on Heterodyned Unlocked Light Sources and Self-Homodyned RF Receiver;A. H. M. Razibul Islam;IEEE PHOTONICS TECHNOLOGY LETTERS;第23卷(第8期);459-460 * |
| 基于级联MZM的12倍频抑制载波全双工RoF系统;王现彬;王颖莉;杨洁;康元元;;实验技术与管理(06);148-152 * |
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