CN115864794A - Drive circuit, related control method, synchronous boost circuit and electronic equipment - Google Patents

Abstract

The application discloses a driving circuit, a floating gate voltage clamping control method, a synchronous booster circuit and an electronic device, which can reduce power consumption and area and are simple in circuit structure and easy to adjust. The drive circuit includes: one end of the feedback module is connected to a source electrode of a PMOS power tube in the synchronous booster circuit and used for obtaining output voltage of the PMOS power tube, and the other end of the feedback module is connected to a grid electrode of the PMOS power tube and used for outputting driving voltage according to the output voltage so as to control grid voltage obtained by the grid electrode of the PMOS power tube.

Description

Driving circuit, related control method, synchronous boost circuit and electronic equipment

Technical Field

The application relates to the field of power supplies, in particular to a driving circuit, a floating gate voltage clamping control method, a synchronous booster circuit and electronic equipment.

Background

And both an NMOS power tube and a PMOS power tube in the synchronous booster circuit need a driving power supply. If the output voltage output by the source electrode of the PMOS power tube in the synchronous booster circuit is higher, the grid voltage of the PMOS power tube needs to be driven, and the PMOS power tube is prevented from being broken down by the overhigh grid-source voltage. The common scheme is to clamp the driving voltage input to the gate of the PMOS power transistor in the range of gate-source voltage that the PMOS power transistor can bear by using an LDO as a floating ground power supply. The grid source voltage range can ensure that the PMOS tube works in a safe area, and can also ensure that the PMOS tube has smaller on-resistance when being switched on. However, the scheme using LDO as the floating ground power source has some disadvantages, such as: 1. strong driving capability is needed, and the static power consumption of the circuit is large; 2. good transient response capability is required, so that the area of the capacitor and the power tube are large, and the whole capacitor needs a large area; 3. the loop regulation is involved, and the circuit structure is complex.

It is highly desirable to find a solution that can reduce the power consumption of the PMOS power transistor during the floating control of the gate voltage, and reduce the area occupied by the control circuit, and at the same time, the circuit structure is simple and easy to adjust.

Disclosure of Invention

In view of this, the present application provides a driving circuit, a floating gate voltage clamp control method, a synchronous boost circuit and an electronic device, which can reduce power consumption and area, and have a simple circuit structure and are easy to implement.

The application provides a drive circuit, includes: one end of the feedback module is connected to a source electrode of a PMOS power tube in the synchronous booster circuit and used for obtaining output voltage of the PMOS power tube, and the other end of the feedback module is connected to a grid electrode of the PMOS power tube and used for outputting driving voltage according to the output voltage so as to control grid voltage obtained by the grid electrode of the PMOS power tube.

Optionally, the feedback module includes: one end of the first voltage reduction unit is connected to a source electrode of the PMOS power tube, and the other end of the first voltage reduction unit is used for outputting a reduced voltage of the output voltage; one end of the pull-down unit is connected to the grid electrode of the PMOS power tube and used for grounding the grid electrode of the PMOS power tube when the grid voltage of the PMOS power tube is larger than a first preset value so as to reduce the grid voltage of the PMOS power tube; and one end of the pull-up unit is connected to the grid electrode of the PMOS power tube, and the other end of the pull-up unit is connected to the source electrode of the PMOS power tube, and the pull-up unit is used for acquiring the output voltage and outputting the driving voltage according to the output voltage when the grid voltage of the PMOS power tube is smaller than a second preset value, so that the grid voltage of the PMOS power tube is at least a third preset value.

Optionally, the pull-down unit includes: the source electrode of the first PMOS tube is connected to the grid electrode of the PMOS power tube, the drain electrode of the first PMOS tube is grounded through a first resistor, and the grid electrode of the first PMOS tube is connected to the output end of the voltage reduction unit; and the drain electrode of the first NMOS tube is connected to the grid electrode of the PMOS power tube, the source electrode of the first NMOS tube is grounded, and the grid electrode of the first NMOS tube is connected to the connection point of the first resistor and the first PMOS tube.

Optionally, the pull-up unit includes: the drain electrode of the second NMOS tube is connected to the source electrode of the PMOS power tube through a second resistor, the grid electrode of the second NMOS tube is connected to the source electrode of the PMOS power tube through a third resistor, and the source electrode of the second NMOS tube is connected to the grid electrode of the PMOS power tube; and the source electrode of the second PMOS tube is connected with the source electrode of the PMOS power tube, the grid electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube, and the drain electrode of the second PMOS tube is connected with the grid electrode of the PMOS power tube.

Optionally, the pull-up unit further includes: a third PMOS tube and a third NMOS tube; the grid electrode and the drain electrode of the third NMOS tube are mutually connected, the source electrode of the third NMOS tube is connected to the source electrode of the third PMOS tube, the drain electrode is connected to the output end of the PMOS power tube through a third resistor, the drain electrode of the third PMOS tube is grounded, and the grid electrode is connected to the first voltage reduction unit.

Optionally, the first voltage reducing unit includes: the cathode of the first Zener diode is connected to the source electrode of the PMOS power tube, and the anode of the first Zener diode is grounded through a fourth resistor; and the upper polar plate of the first capacitor is connected to the cathode of the first Zener diode, and the lower polar plate of the first capacitor is connected to the anode of the first Zener diode.

Optionally, the feedback module further includes: a second voltage reduction unit; the second voltage decreasing unit includes: the cathode of the second Zener diode is connected to the source electrode of the PMOS power tube, and the anode of the second Zener diode is connected to the source electrode of the first PMOS tube; and the upper polar plate of the second capacitor is connected to the cathode of the second Zener diode, and the lower polar plate of the second capacitor is connected to the anode of the second Zener diode.

Optionally, the feedback module further includes: the first switch is arranged between the grid electrode of the first NMOS tube and the drain electrode of the first PMOS tube and is closed when the output voltage output by the source electrode of the PMOS power tube is higher than a fourth preset value.

Optionally, the feedback module further includes: the second switch is arranged between a preset power supply and the grid electrode of the first NMOS tube and is used for being closed when the output voltage output by the source electrode of the PMOS power tube is smaller than or equal to a fourth preset value; and the third switch is arranged between the pull-up unit and the ground and is used for being closed when the output voltage output by the source electrode of the PMOS power tube is less than or equal to a fourth preset value, so that the pull-up unit is turned off.

Optionally, the feedback module further includes: the output unit is connected to the grid electrode of the PMOS power tube and provided with a first end used for obtaining the output voltage of the PMOS power tube, a second end which is grounded and a third end which is connected to the output ends of the pull-up unit and the pull-down unit, and the output unit is used for controlling the grid voltage of the PMOS power tube according to signals output by the output ends of the pull-up unit and the pull-down unit.

Optionally, the output unit includes a fourth PMOS transistor, a fifth PMOS transistor and a fourth NMOS transistor, and the fifth PMOS transistor, the fourth PMOS transistor and the fourth NMOS transistor are sequentially connected through a drain and a source, and are connected to the gate of the PMOS power transistor through the connection point of the fifth PMOS transistor and the fourth PMOS transistor, and: the grid electrode of the fourth PMOS tube is used as the third end and is connected to the output ends of the pull-up unit and the pull-down unit; the source electrode of the fifth PMOS tube is used as the first end to obtain the output voltage of the PMOS power tube, and the grid electrode of the fifth PMOS tube is used for obtaining a first switching signal; and the source electrode of the fourth NMOS tube is used as the second end and is grounded, and the grid electrode of the fourth NMOS tube is used for acquiring a second switching signal.

The application also provides a floating gate voltage clamping control method, which comprises the following steps:

acquiring the grid voltage of a PMOS power tube in the synchronous booster circuit;

when the grid voltage of the PMOS power tube is larger than a first preset value, grounding the grid electrode of the PMOS power tube to reduce the grid voltage of the PMOS power tube;

and when the grid voltage of the PMOS power tube is smaller than a second preset value, outputting the driving voltage according to the output voltage, so that the grid voltage of the PMOS power tube is at least a third preset value.

Optionally, the floating gate voltage clamping control method further includes: and acquiring the output voltage output by the source electrode of the PMOS power tube, and providing a driving voltage for the grid electrode of the PMOS power tube when the output voltage is greater than a fourth preset value.

Optionally, when the output voltage is less than or equal to the fourth preset value, the gate of the PMOS power transistor is controlled to be continuously grounded.

Optionally, when a driving voltage is provided to the gate of the PMOS power transistor, the driving voltage is a step-down of the output voltage.

The application also provides a synchronous booster circuit, which comprises any one of the drive circuits.

The present application also provides an electronic device including any one of the above-described drive circuits or any one of the above-described synchronous boost circuits.

The driving circuit, the floating gate voltage clamping control method, the synchronous booster circuit and the electronic equipment feedback module are simple in structure, can reduce power consumption compared with the prior art, and are small in area.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic diagram of a driving circuit according to an embodiment of the present application.

Fig. 2 is a schematic structural diagram of a feedback module in an embodiment of the present application.

Fig. 3 is a schematic circuit structure diagram of a feedback module according to an embodiment of the present application.

FIG. 4 is a flowchart illustrating a floating gate voltage clamp control method according to a second embodiment of the present application.

Detailed Description

The following describes a driving circuit, a floating gate voltage clamp control method, a synchronous boost circuit, and an electronic device with reference to the accompanying drawings and embodiments.

Fig. 1 is a schematic diagram of a driving circuit according to an embodiment of the invention.

In this embodiment, the drive circuit includes: and the feedback module 100 is provided with one end connected to the source electrode of the PMOS power tube, and is used for acquiring the output voltage VHV of the PMOS power tube and controlling the gate voltage of the PMOS power tube according to the output voltage VHV in a floating manner.

Please refer to fig. 2, which is a schematic structural diagram of the feedback module 100 according to an embodiment of the present application.

The feedback module 100 includes a first voltage dropping unit 201, one end of the first voltage dropping unit 201 is connected to the source of the PMOS power transistor, and the other end is used for outputting a dropped voltage of the output voltage VHV, and the first voltage dropping unit 201 provides the dropped voltage to the gate of the PMOS power transistor, so as to prevent the gate of the PMOS power transistor from being damaged by a high gate voltage due to an excessive gate voltage applied to the gate of the PMOS power transistor.

The first voltage-reducing unit 201 includes a first zener diode D1 and a first capacitor C1. The negative electrode of the first zener diode D1 is connected to the source electrode of the PMOS power transistor, and the positive electrode is grounded through a fourth resistor R4, so as to step down and output an output voltage VHV output by the source electrode of the PMOS power transistor. An upper polar plate of the first capacitor C1 is connected to a cathode of the first zener diode D1, a lower polar plate of the first capacitor C1 is connected to an anode of the first zener diode D1, and a voltage difference between two ends of the first zener diode D1 charges the first capacitor C1, so that voltages at two ends of the first zener diode D1 can be effectively stabilized.

In this embodiment, when the voltage difference across the first zener diode D1 is large enough, the first zener diode D1 is broken down to generate a voltage drop of 5.6V, that is, when the voltage of the cathode of the first zener diode D1 is the output voltage VHV, the voltage of the anode is the output voltage VHV minus 5.6V. The voltage of 5.6V is a common withstand voltage value of the PMOS power tube, and the PMOS power tube can be effectively prevented from being broken down when the output voltage VHV is directly supplied to the grid electrode of the PMOS power tube.

In other embodiments, the step-down amplitude of the first zener diode D1 can also be set as required.

In an embodiment, the feedback module 100 further includes a pull-down unit 202, where one end of the pull-down unit 202 is connected to the gate of the PMOS power transistor, and is configured to ground the gate of the PMOS power transistor when the gate voltage of the PMOS power transistor is greater than a first preset value, so as to reduce the gate voltage of the PMOS power transistor. Optionally, if the gate of the PMOS power transistor is further connected to a corresponding isolation transistor (e.g., a subsequent MP4 transistor, etc.), one end of the pull-down unit 202 is connected to the gate of the corresponding isolation transistor, so as to achieve the purpose of pulling down the gate voltage of the PMOS power transistor by controlling the gate voltage of the isolation transistor. Optionally, the first preset value may be determined according to factors such as connection characteristics corresponding to the PMOS power transistor, for example, if the gate of the PMOS power transistor is not provided with the relevant output unit or the relevant isolation transistor, the first preset value may be set to an upper voltage limit (e.g., 5V) corresponding to the gate of the PMOS power transistor, and for example, if the gate of the PMOS power transistor is provided with the isolation transistor such as MP4, the first preset value may be set according to working characteristics of the isolation transistor.

Please refer to fig. 3, which is a schematic circuit diagram of the feedback module 100 according to an embodiment of the present application.

In the embodiment shown in fig. 3, the pull-down unit 202 includes the first PMOS transistor MP1 and the first NMOS transistor MN1. The source of the first PMOS transistor MP1 is connected to the gate of the PMOS power transistor, the drain is grounded through a first resistor R1, and the gate is connected to the output end of the first voltage-reducing unit 201. The drain electrode of the first NMOS transistor MN1 is connected to the grid electrode of the PMOS power transistor, the source electrode of the first NMOS transistor MN1 is grounded, and the grid electrode of the first NMOS transistor MN1 is connected to the connection point of the first resistor R1 and the first PMOS transistor MP 1. Specifically, if the output unit includes a fourth PMOS transistor MP4, the feedback module 100 includes a first switch S1, a drain of the first NMOS transistor MN1 is connected to a gate of the fourth PMOS transistor MP4, a source is grounded, and the gate is connected to a connection point of the first resistor R1 and the first PMOS transistor MP1 through the first switch S1.

When the step-down voltage is at a low level, the first PMOS transistor MP1 is turned on. If there is a large charge on the gate of the PMOS power transistor, the large charge flows through the first PMOS transistor MP1 and is grounded through the first resistor R1. At this time, the drain voltage of the first PMOS transistor MP1 is relatively large, so that the gate voltage of the first NMOS transistor MN1 is greater than the turn-on threshold of the first NMOS transistor MN1, the first NMOS transistor MN1 is turned on, the gate of the PMOS power transistor is grounded through the first NMOS transistor MN1, and the charge of the gate of the PMOS power transistor is released to the ground, for example, the charge of the gate of the isolation transistor at the gate of the PMOS power transistor is released to the ground.

When the electric charge of the grid electrode of the PMOS power tube is released to a certain degree, the drain electrode voltage of the first PMOS tube MP1 is smaller than the conduction threshold value of the first NMOS tube MN1, and the electric charge of the grid electrode of the PMOS power tube is not released to the ground any more. Therefore, in this embodiment, the second preset value is determined by the breakdown voltage of the first zener diode D1 and the threshold voltage of the first PMOS transistor MP 1.

The feedback module 100 further includes a pull-up unit 203, where one end of the pull-up unit 203 is connected to a gate of the PMOS power transistor, and the other end of the pull-up unit 203 is connected to a source of the PMOS power transistor, and is configured to obtain the output voltage VHV, and output the driving voltage according to the output voltage VHV when a gate voltage of the PMOS power transistor is smaller than a second preset value, so that the gate voltage of the PMOS power transistor is at least a third preset value. Optionally, the second preset value may determine a value according to factors such as connection characteristics corresponding to the PMOS power transistor, for example, no relevant output unit or no relevant isolation transistor is provided on the gate of the PMOS power transistor, and the second preset value may be set as a lower voltage limit corresponding to the gate of the PMOS power transistor, and so on.

The pull-up unit 203 includes a second NMOS transistor MN2 and a second PMOS transistor MP2.

The drain electrode of the second NMOS transistor MN2 is connected to the source electrode of the PMOS power transistor through a second resistor R2, the source electrode is connected to the grid electrode of the PMOS power transistor or the grid electrode of an isolation transistor arranged at the grid electrode of the PMOS power transistor, and the grid electrode of the second NMOS transistor MN2 is connected to the source electrode of the PMOS power transistor through a third resistor R3.

The grid electrode of the second PMOS tube MP2 is connected to the drain electrode of the second NMOS tube MN2, the source electrode is connected to the source electrode of the PMOS power tube, and the drain electrode is connected to the grid electrode of the PMOS power tube.

Optionally, when the output voltage VHV is smaller than a second preset value, the second NMOS transistor MN2 is turned on, the first PMOS transistor MP1 is also turned on, and a gate voltage of the second PMOS transistor MP2 is R2 × VHV/(R1 + R2), where R2 is a resistance value of the second resistor R2, R1 is a resistance value of the first resistor R1, and VHV is an output voltage VHV output by the source of the PMOS power transistor. Here, if the output unit 205 includes the fourth PMOS transistor MP4 as an isolation transistor at the gate of the PMOS power transistor, when the gate voltage of the fourth PMOS transistor MP4 is smaller than the second preset value, the second NMOS transistor MN2 is turned on, and when the voltage drop across the second resistor R2 is larger than the threshold voltage of the second PMOS transistor MP2. At this time, the gate voltage of the second PMOS transistor MP2 is smaller than the conduction threshold of the second PMOS transistor MP2, the second PMOS transistor MP2 is turned on, and the output voltage VHV is applied to the gate of the isolation transistor MP4, so as to pull up the gate voltage of the PMOS power transistor.

In an example, referring to fig. 3, the pull-up unit 203 further includes a third PMOS transistor MP3 and a third NMOS transistor MN3. The gate and the drain of the third NMOS transistor MN3 are connected to each other, the source of the third NMOS transistor MN3 is connected to the source of the third PMOS transistor MP3, the drain is connected to the VHV (i.e., the output terminal of the PMOS power transistor) through a third resistor R3, the drain of the third PMOS transistor MP3 is grounded, the gate is connected to the first voltage-dropping unit, and the gate of the third PMOS transistor MP3 may be specifically connected to the anode of the first zener diode D1.

The width-to-length ratio of the third NMOS transistor MN3 is greater than that of the second NMOS transistor MN2, and the width-to-length ratio of the third NMOS transistor MN3 is usually set to be 5 to 10 times of the size of the second NMOS transistor MN2, so as to avoid instability of a branch where the second NMOS transistor MN2 and the first PMOS transistor MP1 are located and unnecessary static power consumption of the branch. The width-to-length ratio setting can also ensure that the second NMOS transistor MN2 is closed when the grid electrode of the PMOS power transistor does not discharge charges.

The conduction threshold values of the first PMOS tube MP1 and the third PMOS tube MP3 are the same. The third PMOS transistor MP3 is turned on continuously, and provides a bias voltage to the gate of the second NMOS transistor MN2 through the third NMOS transistor MN3 and the third resistor R3. The magnitude of the bias voltage is VP plus the gate-source voltage of the third PMOS transistor MP3 and the gate-source voltage of the third NMOS transistor MN3, where VP is the step-down voltage output by the first step-down unit 201. The bias voltage is used to control the second NMOS transistor MN2 to be weakly turned on, and even when the gate voltage obtained by the second NMOS transistor MN2 through the third resistor R3 is small, the second NMOS transistor MN2 may be turned on, so as to limit the pull-down amplitude of the pull-down unit 202.

In one embodiment, the feedback module 100 further includes a second voltage reduction unit 204.

The second voltage reducing unit 204 includes a second zener diode D2 and a second capacitor C2. The cathode of the second zener diode D2 is connected to the source of the PMOS power transistor, the anode of the second zener diode D2 is connected to the source of the first PMOS transistor MP1, and the second capacitor C2 is connected to two ends of the second zener diode D2 to stabilize the voltage difference between the two ends of the second zener diode D2.

In this embodiment, the breakdown voltage of the second zener diode D2 is equal to the breakdown voltage of the first zener diode D1. Because the anode of the first zener diode D1 is further connected to the gate of the first PMOS transistor MP1, the source of the first PMOS transistor MP1 is connected to the gate of the PMOS power transistor or the corresponding isolation transistor. Therefore, when the voltage difference between the two ends of the first zener diode D1 is VP, the voltage difference between the two ends of the second zener diode D2 is VP minus the gate-source voltage of the first PMOS transistor MP1, the voltage difference between the two ends of the second zener diode D2 is smaller than the voltage difference between the two ends of the first zener diode D1, and the two ends of the second zener diode D2 are not broken down when the potential of the gate of the PMOS power transistor is not changed.

In other embodiments, the second zener diode D2 may also be selected as needed, so that no breakdown occurs across the second zener diode D2 when the potential of the second zener diode D2 at the gate of the PMOS power transistor is not changed.

Since the breakdown clamping speed of the zener diode is extremely high, the second zener diode D2 is inserted between the gate and the source of the PMOS power transistor or the corresponding isolation transistor, so that the undershoot of the gate voltage of the PMOS power transistor can be rapidly reduced, and the transient response characteristic is improved.

In an embodiment, the feedback module 100 further includes three switches, wherein a first switch S1 is disposed between the first resistor R1 in the pull-down unit 202 and the gate of the first NMOS transistor MN1, and is configured to be closed when the output voltage VHV output by the source of the PMOS power transistor is higher than a fourth preset value, so that the first NMOS transistor MN1 is turned on or off according to the charge accumulation condition of the PMOS power transistor or the isolation transistor disposed at the gate. The fourth preset value may be a gate-source safe voltage threshold (about 5V, or other safe voltage thresholds) of the PMOS power transistor. Specifically, the fourth preset value may be used to close the first switch S1, open the second switch S2, and provide the floating ground potential for the feedback module 100 when the gate-source voltage of the PMOS power transistor is too high (for example, the output voltage VHV is higher than the fourth preset value); otherwise, the first switch S1 is turned off, the second switch S2 is turned on, and the first NMOS transistor MN1 is connected to the VDD voltage (preset high level of the power VDD), and connects the floating ground to the 0-potential ground.

The second switch S2 is disposed between the gate of the first NMOS transistor MN1 and a preset power supply VDD, where the preset power supply VDD is a high level and is greater than or equal to a turn-on threshold of the first NMOS transistor MN1. The second switch S2 is closed when the output voltage VHV output by the source electrode of the PMOS power tube is smaller than or equal to a fourth preset value, and is opened when the output voltage VHV is larger than the fourth preset value. When the output voltage VHV output by the source electrode of the PMOS power tube is smaller than or equal to a fourth preset value, the grid electrode of the first NMOS tube MN1 acquires the preset power supply VDD, so that the grid electrode low level of the isolation tube at the grid electrode of the PMOS power tube or the PMOS power tube is the ground.

The third switch S3 is disposed between the gates of the second NMOS transistor MN2 and the third NMOS transistor MN3 and the ground, that is, between the pull-up unit 203 and the ground, and is closed when an output voltage VHV output by the source of the PMOS power transistor is less than or equal to a fourth preset value, so as to pull down the gates of the second NMOS transistor MN2 and the third NMOS transistor MN3, thereby turning off the pull-up unit 203, and preventing the pull-up unit 203 from pulling up the gate of the PMOS power transistor or the corresponding isolation transistor when the output voltage VHV is less than the fourth preset value, thereby causing a gate-source voltage difference of the PMOS power transistor to be too low.

Alternatively, the present embodiment may control the second switch S2 and the third switch S3 synchronously, that is, the second switch S2 and the third switch S3 are controlled in the same manner, and the first switch S1 and the third switch S3 are controlled in the opposite manner.

In some embodiments, the feedback module 100 further comprises: and the output unit 205 is connected to the gate of the PMOS power transistor, and has a first end for obtaining the output voltage of the PMOS power transistor, a second end connected to the ground, and a third end connected to the output ends of the pull-up unit 203 and the pull-down unit 202, and is configured to control the gate voltage of the PMOS power transistor according to the signals output by the output ends of the pull-up unit 203 and the pull-down unit 202.

In some embodiments, the output unit includes a fourth PMOS transistor MP4, a fifth PMOS transistor MP5 and a fourth NMOS transistor MN4, and the fifth PMOS transistor MP5, the fourth PMOS transistor MP4 and the fourth NMOS transistor MN4 are sequentially connected through a drain and a source, and are connected to a gate of the PMOS power transistor by a connection point of the fifth PMOS transistor MP5 and the fourth PMOS transistor MP4, and: the fourth PMOS transistor MP4 may be used as an isolation transistor at the gate of the PMOS power transistor, and the gate of the fourth PMOS transistor MP4 is used as a third terminal, and is connected to the output terminals of the pull-up unit 203 and the pull-down unit 202; a source electrode of the fifth PMOS transistor MP5 is used as the first end to obtain an output voltage of the PMOS power transistor, and a gate electrode is used to obtain a first switching signal DRVP; the source of the fourth NMOS transistor MN4 is used as the second terminal to be grounded, and the gate is used to obtain the second switching signal DRVN.

The embodiment of the application also provides a floating gate voltage clamping control method, and the gate voltage of the PMOS power tube is controlled by adopting the driving circuit in any embodiment.

Please refer to fig. 4, which is a flowchart illustrating a step of a floating gate voltage clamping control method according to an embodiment of the present application.

In this embodiment, the floating gate voltage clamp control method includes the steps of:

step S401: acquiring the grid voltage of a PMOS power tube in the synchronous booster circuit;

step S402: when the grid voltage of the PMOS power tube is larger than a first preset value, grounding the grid electrode of the PMOS power tube to reduce the grid voltage of the PMOS power tube;

step S403: and when the grid voltage of the PMOS power tube is smaller than a second preset value, outputting the driving voltage according to the output voltage, so that the grid voltage of the PMOS power tube is at least a third preset value.

In fact, in order to prevent the gate of the PMOS power transistor from being supplied with the driving voltage determined by the output voltage VHV when the output voltage VHV is small, in some embodiments, the driving voltage is supplied to the gate of the PMOS power transistor only when the output voltage VHV is greater than a fourth preset value and greater than a second preset value. Accordingly, in one embodiment, the floating gate voltage clamp control method further comprises: and obtaining an output voltage VHV output by the source electrode of the PMOS power tube, and providing a driving voltage for the grid electrode of the PMOS power tube when the output voltage is greater than a fourth preset value.

In this embodiment, the driving voltage is provided by the pull-up unit 203 in the embodiment shown in fig. 3, so that, if it is to be prevented that the output voltage VHV is very small, the driving voltage determined by the output voltage VHV is provided to the gate of the PMOS power transistor, and therefore, when the output voltage VHV is less than or equal to the fourth preset value, the gate of the PMOS power transistor is controlled to be continuously grounded, for example, the pull-up unit 203 may be turned off by a switch, and the gate of the PMOS power transistor or the corresponding isolation transistor is directly grounded at a low level.

In this embodiment, in order to prevent the PMOS power transistor from being damaged due to the fact that the output voltage VHV is too large when the output voltage VHV is directly applied to the gate of the PMOS power transistor, when the drive voltage is applied to the gate of the PMOS power transistor, the output voltage VHV is reduced, and the reduced voltage is applied to the gate of the PMOS power transistor as the drive voltage.

The application also provides a synchronous booster circuit, which comprises the driving circuit in any embodiment. Optionally, the synchronous boost circuit may further include a PMOS power transistor.

The present application further provides an electronic device including the driving circuit 5 according to any of the above embodiments or the synchronous boost circuit according to any of the above embodiments.

In the driving circuit, the floating gate voltage clamping control method, the synchronous boost circuit and the electronic device, the feedback module 100 has a simple structure and a relatively fast response speed, and can reduce power consumption and have a small area compared with the prior art.

The above description is only an embodiment of the present application and is not intended to limit the scope of the present application, and all changes in equivalent structures or equivalent processes, such as mutual combination of technical features between various embodiments, or direct or indirect application to other related technical fields, which are made by using the contents of the specification and the drawings of the present application, are also included in the scope of the present application.

Claims (17)

1. A driver circuit, comprising:

one end of the feedback module is connected to a source electrode of a PMOS power tube in the synchronous booster circuit and used for obtaining output voltage of the PMOS power tube, and the other end of the feedback module is connected to a grid electrode of the PMOS power tube and used for outputting driving voltage according to the output voltage so as to control grid voltage obtained by the grid electrode of the PMOS power tube.

2. The driving circuit of claim 1, wherein the feedback module comprises:

one end of the first voltage reduction unit is connected to the source electrode of the PMOS power tube, and the other end of the first voltage reduction unit is used for outputting the reduced voltage of the output voltage;

one end of the pull-down unit is connected to the grid of the PMOS power tube and used for grounding the grid of the PMOS power tube when the grid voltage of the PMOS power tube is larger than a first preset value so as to reduce the grid voltage of the PMOS power tube;

and one end of the pull-up unit is connected to the grid electrode of the PMOS power tube, the other end of the pull-up unit is connected to the source electrode of the PMOS power tube, the pull-up unit is used for acquiring the output voltage, and when the grid voltage of the PMOS power tube is smaller than a second preset value, the pull-up unit outputs the driving voltage according to the output voltage, so that the grid voltage of the PMOS power tube is at least a third preset value.

3. The driving circuit according to claim 2, wherein the pull-down unit comprises:

the source electrode of the first PMOS tube is connected to the grid electrode of the PMOS power tube, the drain electrode of the first PMOS tube is grounded through a first resistor, and the grid electrode of the first PMOS tube is connected to the output end of the voltage reduction unit;

and the drain electrode of the first NMOS tube is connected to the grid electrode of the PMOS power tube, the source electrode of the first NMOS tube is grounded, and the grid electrode of the first NMOS tube is connected to the connection point of the first resistor and the first PMOS tube.

4. The driving circuit according to claim 2, wherein the pull-up unit comprises:

the drain electrode of the second NMOS tube is connected to the source electrode of the PMOS power tube through a second resistor, the grid electrode of the second NMOS tube is connected to the source electrode of the PMOS power tube through a third resistor, and the source electrode of the second NMOS tube is connected to the grid electrode of the PMOS power tube;

and the source electrode of the second PMOS tube is connected with the source electrode of the PMOS power tube, the grid electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube, and the drain electrode of the second PMOS tube is connected with the grid electrode of the PMOS power tube.

5. The driving circuit according to claim 4, wherein the pull-up unit further comprises: a third PMOS tube and a third NMOS tube;

the grid electrode and the drain electrode of the third NMOS tube are mutually connected, the source electrode of the third NMOS tube is connected to the source electrode of the third PMOS tube, the drain electrode is connected to the output end of the PMOS power tube through a third resistor, the drain electrode of the third PMOS tube is grounded, and the grid electrode is connected to the first voltage reduction unit.

6. The drive circuit according to claim 2, wherein the first voltage-reducing unit includes:

the cathode of the first Zener diode is connected to the source electrode of the PMOS power tube, and the anode of the first Zener diode is grounded through a fourth resistor;

and the upper polar plate of the first capacitor is connected to the cathode of the first Zener diode, and the lower polar plate of the first capacitor is connected to the anode of the first Zener diode.

7. The driving circuit of claim 3, wherein the feedback module further comprises: a second voltage reduction unit;

the second voltage reduction unit includes:

the cathode of the second Zener diode is connected to the source electrode of the PMOS power tube, and the anode of the second Zener diode is connected to the source electrode of the first PMOS tube;

and the upper polar plate of the second capacitor is connected to the cathode of the second Zener diode, and the lower polar plate of the second capacitor is connected to the anode of the second Zener diode.

8. The driving circuit of claim 3, wherein the feedback module further comprises:

the first switch is arranged between the grid electrode of the first NMOS tube and the drain electrode of the first PMOS tube and is closed when the output voltage output by the source electrode of the PMOS power tube is higher than a fourth preset value.

9. The driving circuit of claim 3, wherein the feedback module further comprises:

the second switch is arranged between a preset power supply and the grid electrode of the first NMOS tube and is used for being closed when the output voltage output by the source electrode of the PMOS power tube is smaller than or equal to a fourth preset value;

and the third switch is arranged between the pull-up unit and the ground and is used for being closed when the output voltage output by the source electrode of the PMOS power tube is less than or equal to a fourth preset value, so that the pull-up unit is turned off.

10. The driving circuit of claim 2, wherein the feedback module further comprises:

the output unit is connected to the grid electrode of the PMOS power tube and provided with a first end used for obtaining the output voltage of the PMOS power tube, a second end which is grounded and a third end which is connected to the output ends of the pull-up unit and the pull-down unit, and the output unit is used for controlling the grid voltage of the PMOS power tube according to signals output by the output ends of the pull-up unit and the pull-down unit.

11. The driving circuit of claim 10, wherein the output unit comprises a fourth PMOS transistor, a fifth PMOS transistor and a fourth NMOS transistor, and the fifth PMOS transistor, the fourth PMOS transistor and the fourth NMOS transistor are sequentially connected through a drain and a source, and are connected to a gate of the PMOS power transistor by a connection point of the fifth PMOS transistor and the fourth PMOS transistor, and:

the grid electrode of the fourth PMOS tube is used as the third end and is connected to the output ends of the pull-up unit and the pull-down unit;

the source electrode of the fifth PMOS tube is used as the first end to obtain the output voltage of the PMOS power tube, and the grid electrode of the fifth PMOS tube is used for obtaining a first switching signal;

and the source electrode of the fourth NMOS tube is used as the second end and is grounded, and the grid electrode of the fourth NMOS tube is used for acquiring a second switching signal.

12. A floating gate voltage clamp control method, comprising the steps of:

acquiring the grid voltage of a PMOS power tube in a synchronous booster circuit;

when the grid voltage of the PMOS power tube is larger than a first preset value, grounding the grid electrode of the PMOS power tube to reduce the grid voltage of the PMOS power tube;

and when the grid voltage of the PMOS power tube is smaller than a second preset value, outputting the driving voltage according to the output voltage, so that the grid voltage of the PMOS power tube is at least a third preset value.

13. The floating gate voltage clamp control method of claim 12, further comprising: and acquiring the output voltage output by the source electrode of the PMOS power tube, and providing a driving voltage for the grid electrode of the PMOS power tube when the output voltage is greater than a fourth preset value.

14. The method of claim 13, wherein the gate of the PMOS power transistor is controlled to be continuously grounded when the output voltage is less than or equal to the fourth predetermined value.

15. The method of claim 12, wherein the driving voltage is a step-down of the output voltage when the driving voltage is provided to the gate of the PMOS power transistor.

16. A synchronous boost circuit comprising the drive circuit of any one of claims 1 to 11.

17. An electronic device comprising the drive circuit of any one of claims 1 to 11 or the synchronous boost circuit of claim 16.

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