CN115863348A - 绝缘体覆硅基板及其制作方法 - Google Patents

绝缘体覆硅基板及其制作方法 Download PDF

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CN115863348A
CN115863348A CN202111119692.8A CN202111119692A CN115863348A CN 115863348 A CN115863348 A CN 115863348A CN 202111119692 A CN202111119692 A CN 202111119692A CN 115863348 A CN115863348 A CN 115863348A
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substrate
silicon
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祁春媛
张晟
陈星星
冯健奇
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United Microelectronics Corp
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Abstract

本发明提出了一种绝缘体覆硅基板及其制作方法，其中该绝缘体覆硅基板包含一承载基板、一多晶硅捕陷层形成在该承载基板上、一氧化层形成在该多晶硅捕陷层上、以及一单晶硅层直接形成在该氧化层上，其中该单晶硅层与该氧化层之间为接合界面。

Description

绝缘体覆硅基板及其制作方法
技术领域
本发明涉及一种绝缘体覆硅基板及其制作方法有关，更具体言之，其涉及一种具有捕陷层的绝缘体覆硅基板及其制作方法。
背景技术
智能手机以及5G通讯网络技术的兴起推动了业界对于绝缘体覆硅(silicon-on-insulator,SOI)基板的巨大需求，特别是射频绝缘体覆硅(RF-SOI)基板。RF-SOI是专门用于制造智能手机和其他产品中特定射频芯片(如开关和天线调谐器)的基板，相当于SOI技术的射频版本。与用于数字芯片的全耗尽型SOI(fully depleted,FD-SOI)不同，RF-SOI基板中会设置一特别的捕陷层(trap-rich layer)，其功能在于捕陷自由载流子，以改善谐波失真并恢复基底中的高电阻率属性，从而降低射频元件的插入损耗并提高系统的线性度。
目前现有的RF-SOI基板制作方法通常是采用将一元件晶片与一承载晶片接合的做法，其中的元件晶片上会先预先制作好所需的元件层以及金属互连层等电路结构，捕陷层则形成在承载晶片的表面上，如此将承载晶片的捕陷层与元件晶片的金属互连层对接即能完成RF-SOI基板的制作。
由于上述现有技术的对接方式，其接合完成后的RF-SOI基板的正面会是原本元件晶片的背面，也就是硅基底表面，RF-SOI基板内部的电路结构并未被布线至RF-SOI基板表面。为了让内部的电路结构能向外接出，晶片接合制作工艺后还需要制作额外的背侧金属布线层以及连通内部电路与该背侧金属布线的背侧接触件，才能让整个元件得以运作。这些额外的制作工艺不仅繁复，而且成本很高，使得RF-SOI基板的成本居高不下。
发明内容
为了解决射频绝缘体覆硅(RF-SOI)基板的成本问题，本发明于此提出了一种新颖的绝缘体覆硅基板结构及其制作方法，其特点在于将元件基板与承载基板之间用于接合的氧化层作为SOI基板的埋入氧化层，接合界面会位于埋入氧化层与元件层之间，且元件层与金属互连层等电路结构是在接合后才开始在基板的正面制作，故此不像现有技术般需要制作额外高成本的背侧接触件与布线。
本发明的面向之一在于提出一种绝缘体覆硅基板，包含一承载基板、一多晶硅捕陷层形成在该承载基板上、一氧化层形成在该多晶硅捕陷层上、以及一单晶硅层直接形成在该氧化层上，其中该单晶硅层与该氧化层之间为接合界面。
本发明的另一面向在于提出一种绝缘体覆硅基板的制作方法，包含在一承载基板上形成一多晶硅捕陷层、在该多晶硅捕陷层上形成一氧化层、将一块体硅晶片接合在该氧化层上、以及对该块体硅晶片进行薄化与修边制作工艺，以在该氧化层上形成一单晶硅层，其中该单晶硅层与该氧化层之间为接合界面。
本发明的这类目的与其他目的在阅者读过下文中以多种图示与绘图来描述的优选实施例的细节说明后应可变得更为明了显见。
附图说明
本说明书含有附图并于文中构成了本说明书的一部分，使阅者对本发明实施例有进一步的了解。该些图示描绘了本发明一些实施例并连同本文描述一起说明了其原理。在该些图示中：
图1至图3为本发明优选实施例中绝缘体覆硅基板的制作流程的截面示意图；以及
图4为本发明优选实施例中绝缘体覆硅基板的截面示意图。
需注意本说明书中的所有图示都为图例性质，为了清楚与方便图示说明之故，图示中的各部件在尺寸与比例上可能会被夸大或缩小地呈现，一般而言，图中相同的参考符号会用来标示修改后或不同实施例中对应或类似的元件特征。
主要元件符号说明
100 承载基板
102 多晶硅捕陷层
104 氧化层
106 元件基板
106a 单晶硅层
108 金属互连层
110 导孔件
112 金属间介电层
120 接合界面
具体实施方式
现在下文将详细说明本发明的示例性实施例，其会参照附图示出所描述的特征以便阅者理解并实现技术效果。阅者将可理解文中的描述仅透过例示的方式来进行，而非意欲要限制本案。本案的各种实施例和实施例中彼此不冲突的各种特征可以以各种方式来加以组合或重新设置。在不脱离本发明的精神与范畴的情况下，对本案的修改、等同物或改进对于本领域技术人员来说是可以理解的，并且旨在包含在本案的范围内。
阅者应能容易理解，本案中的「在…上」、「在…之上」和「在…上方」的含义应当以广义的方式来解读，以使得「在…上」不仅表示「直接在」某物「上」而且还包括在某物「上」且其间有居间特征或层的含义，并且「在…之上」或「在…上方」不仅表示「在」某物「之上」或「上方」的含义，而且还可以包括其「在」某物「之上」或「上方」且其间没有居间特征或层(即，直接在某物上)的含义。此外，诸如「在…之下」、「在…下方」、「下部」、「在…之上」、「上部」等空间相关术语在本文中为了描述方便可以用于描述一个元件或特征与另一个或多个元件或特征的关系，如在附图中示出的。
如本文中使用的，术语「基底」是指向其上增加后续材料的材料。可以对基底自身进行图案化。增加在基底的顶部上的材料可以被图案化或可以保持不被图案化。此外，基底可以包括广泛的半导体材料，例如硅、锗、砷化镓、磷化铟等。或者，基底可以由诸如玻璃、塑胶或蓝宝石晶片的非导电材料制成。
如本文中使用的，术语「层」是指包括具有厚度的区域的材料部分。层可以在下方或上方结构的整体之上延伸，或者可以具有小于下方或上方结构范围的范围。此外，层可以是厚度小于连续结构的厚度的均质或非均质连续结构的区域。例如，层可以位于在连续结构的顶表面和底表面之间或在顶表面和底表面处的任何水平面对之间。层可以水准、竖直和/或沿倾斜表面延伸。基底可以是层，其中可以包括一个或多个层，和/或可以在其上、其上方和/或其下方具有一个或多个层。层可以包括多个层。例如，互连层可以包括一个或多个导体和接触层(其中形成触点、互连线和/或通孔)和一个或多个介电层。
阅者通常可以至少部分地从上下文中的用法理解术语。例如，至少部分地取决于上下文，本文所使用的术语「一或多个」可以用于以单数意义描述任何特征、结构或特性，或者可以用于以多个意义描述特征、结构或特性的组合。类似地，至少部分地取决于上下文，诸如「一」、「一个」、「该」或「所述」之类的术语同样可以被理解为传达单数用法或者传达多个用法。另外，术语「基于」可以被理解为不一定旨在传达排他性的因素集合，而是可以允许存在不一定明确地描述的额外因素，这同样至少部分地取决于上下文。
阅者更能了解到，当「包含」与/或「含有」等词用于本说明书时，其明定了所陈述特征、区域、整体、步骤、操作、要素以及/或部件的存在，但并不排除一或多个其他的特征、区域、整体、步骤、操作、要素、部件以及/或其组合的存在或添加的可能性。
首先请参照图1至图3，其为根据本发明优选实施例中一绝缘体覆硅基板(SOI)的制作流程的截面示意图。如图1所示，本发明的制作工艺从一承载基板(handler)100开始。在实施例中，承载基板100可为一硅晶片或一玻璃基板等，较佳为一高阻值硅基板，如电阻值介于3000～20000Ω·cm的硅基板，其可降低信号传递损耗，有利于射频电路(RFIC)与混合信号的应用。其他的半导体材料如III-V族半导体材料、碳化硅(SiC)、硅锗(SiGe)、锗(Ge)等也可作为承载基板100的材料。
复参照图1。承载基板100上会形成一捕陷层(trap-rich layer，或称富阱层)，如一未掺杂或碳掺杂的多晶硅捕陷层102，其功用在于捕捉埋入氧化层(buried oxide)中累积的电荷，避免串扰或射频信号非线性失真的情形发生。多晶硅的晶界通常可以提供不错的捕陷态，其内部可能产生的结晶缺陷如错位(dislocation)及/或氧化引致叠差(oxidation induced stacking faults,OISF)等也可以产生捕陷态，以此来捕捉载流子，避免载流子沿着承载基板100的顶面累积。在实施例中，多晶硅捕陷层102可以沉积方式形成在承载基板100表面，如低压化学气相沉积(LPCVD)、常压化学气相沉积(APCVD)、等离子体辅助化学气相沉积(PECVD)等，其厚度可介于
Figure BDA0003276596980000051
之间。
复参照图1。在多晶硅捕陷层102形成后，接下来在多晶硅捕陷层102的表面形成一氧化层104，如一四乙氧基硅烷(tetraethoxysilane,TEOS)氧化层。在本发明实施例中，氧化层104同时作为SOI基板的埋入氧化层(buried oxide)以及基板对接时的接合层之用。在其他实施例中，氧化层104的材料也可以是其他有机硅烷类材料，如四甲基硅烷(Si(CH3)4)、四甲基环四硅氧烷(TMCTS)、八甲基环四硅氧烷(OMCTS)、六甲基二硅氮烷(HMDS)、三乙氧基硅烷(SiH(OC2H5)3)、三(二甲胺基)硅烷(SiH(N(CH3)2)3)等，或是氧化铝等高介电(high-k)材料。氧化层104可以沉积方式形成在多晶硅捕陷层102表面，例如等离子体辅助化学气相沉积(PECVD)、次常压化学气相沉积(SACVD)、低压化学气相沉积(LPCVD)、原子层沉积(ALD)等。在氧化层104形成后还可对其进行一化学机械抛光(CMP)制作工艺，以将氧化层104磨到所需厚度并提供平坦的接合面，其厚度可介于
Figure BDA0003276596980000052
之间。
接着请参照图2。在氧化层104形成后，接下来将一元件基板106接合到氧化层104上。在本发明实施例中，元件基板106可为一单晶硅基板。有机硅烷类的氧化层104的平坦表面以及亲水特性可以很容易地形成键结将元件基板106与多晶硅捕陷层102接合在一起。接合制作工艺中可包含进行等离子体处理来活化接合面，并且在接合后进行半小时到数小时不到的热处理，以形成较强的键结。在其他实施例中，元件基板106也可使用其他的半导体材料，如III-V族半导体材料、碳化硅(SiC)、硅锗(SiGe)、锗(Ge)等。
接着请参照图3。在将元件基板106接合到氧化层104上后，接下来对元件基板106进行一研磨制作工艺，以将元件基板106磨成一定目标厚度的元件层，如单晶硅层106a，以允许后续元件堆叠和高密度的IC封装。研磨制作工艺可包括粗磨、精磨、化学机械抛光(CMP)等步骤，其可将厚度大于50μm的单晶硅基板减薄为厚度大约介于
Figure BDA0003276596980000053
之间的单晶硅层。如此，即完成了本发明SOI基板的制作。在此SOI基板中，单晶硅层106a的电阻值最低，其作为元件层的一部分。多晶硅捕陷层102的电阻值最高，可达10+8Ω·cm。承载基板100的电阻值相对于单晶硅层106a而言是高阻值，约介于3000～20000Ω·cm之间。
接着请参照图4，其为根据本发明优选实施例中绝缘体覆硅基板的截面示意图。如图所示，本发明完成后的SOI基板由下而上依序包含高阻值的承载基板100、多晶硅捕陷层102、氧化层104(作为SOI基板的埋入氧化层)以及单晶硅层106a(薄化后的元件基板106)，其中SOI基板的接合界面120位于氧化层104与单晶硅层106a之间，其有别于现有技术中接合界面位于埋入氧化层与捕陷层之间。完成SOI基板的制作后，之后即可在单晶硅层106a表面进行常规的半导体前段制作工艺(FEOL)与后段制作工艺(BEOL)，来制作出半导体元件(未示出)以及形成在金属间介电层112中的金属互连层108、导孔件(via)110等互连结构。
从上述实施例说明可知，本发明的特点在于将元件基板与承载基板之间用于接合的氧化层作为SOI基板的埋入氧化层，接合界面会位于埋入氧化层与元件层之间，且元件层与金属互连层等电路结构是在接合后才开始在基板的正面制作，故此不像现有技术般需要制作额外高成本的背侧接触件与布线。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (10)

1.一种绝缘体覆硅基板，包含：
承载基板；
多晶硅捕陷层，形成在该承载基板上；
氧化层，形成在该多晶硅捕陷层上；以及
单晶硅层，直接形成在该氧化层上，其中该单晶硅层与该氧化层之间为接合界面。
2.如权利要求1所述的绝缘体覆硅基板，其中该多晶硅捕陷层为碳掺杂多晶硅捕陷层或未掺杂多晶硅捕陷层。
3.如权利要求1所述的绝缘体覆硅基板，其中该承载基板为硅晶片或玻璃基板。
4.如权利要求1所述的绝缘体覆硅基板，其中该单晶硅层的厚度为
Figure FDA0003276596970000011
5.如权利要求1所述的绝缘体覆硅基板，其中该多晶硅捕陷层的厚度为
Figure FDA0003276596970000012
6.如权利要求1所述的绝缘体覆硅基板，其中该TEOS氧化层的厚度为
Figure FDA0003276596970000013
7.一种绝缘体覆硅基板的制作方法，包含：
在承载基板上形成多晶硅捕陷层；
在该多晶硅捕陷层上形成氧化层；
将块体硅晶片接合在该氧化层上；以及
对该块体硅晶片进行薄化与修边制作工艺，以在该氧化层上形成单晶硅层，其中该单晶硅层与该氧化层之间为接合界面。
8.如权利要求7所述的绝缘体覆硅基板的制作方法，还包含在接合该块体硅晶片前对该TEOS氧化层进行化学机械研磨制作工艺。
9.如权利要求7所述的绝缘体覆硅基板的制作方法，还包含对该多晶硅捕陷层进行碳掺杂制作工艺。
10.如权利要求7所述的绝缘体覆硅基板的制作方法，其中该承载基板为硅晶片或玻璃基板。
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