CN115863261A - Semiconductor structure and forming method thereof - Google Patents

Abstract

A semiconductor structure and a method of forming the same, the method comprising: forming a protective layer on the top of the substrate of the isolation region, the side wall of the bulge part closest to the isolation region and the top of the etching stop layer; forming a sacrificial layer on the side wall of the protective layer in the isolation region; removing the protective layer and the sacrificial layer which are higher than the top of the etching stop layer; forming a first isolation layer on the top of the protection layer of the isolation region and in the first groove of the device unit region, wherein the top of the first isolation layer is flush with the top of the etching stop layer; removing the sacrificial layer, and forming an opening surrounded by the side wall of the first isolation layer, the top of the protective layer on the substrate and the side wall of the protective layer in the isolation region; and forming a conductive layer in the opening, wherein the top of the conductive layer is lower than the top of the bottom fin part. The pattern density in the device unit area is increased, the forming area of the semiconductor structure is reduced, and the probability that the fin part in the device unit area is damaged in the process of forming the conducting layer is also reduced.

Description

Semiconductor structure and forming method thereof

Technical Field

Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.

Background

With the rapid growth of the semiconductor Integrated Circuit (IC) industry, semiconductor technology is driven by moore's law to move towards smaller process nodes, so that the integrated circuit is developed towards smaller size, higher circuit precision and higher circuit complexity.

Modern integrated circuits include transistors, capacitors, and other devices formed on a semiconductor substrate. On the substrate, these devices are initially isolated from each other and subsequently interconnected by an interconnect structure to form a functional circuit. Typical interconnect structures include lateral interconnect structures (e.g., metal interconnect lines), and vertical interconnect structures (e.g., via interconnect structures and contacts).

A Buried Power Rail (BPR) structure is an interconnect structure disposed in a substrate, the buried power rail being formed during front end of line (FEOL) processing and through which power is supplied to an integrated circuit. Where the buried power rail may be used as a Vdd power rail or a Vss power rail.

Disclosure of Invention

Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which are beneficial to improving the performance of the semiconductor structure.

To solve the above problem, an embodiment of the present invention provides a semiconductor structure, including: the device comprises a substrate, a plurality of isolation regions and a plurality of device unit regions, wherein the device unit regions are positioned between adjacent isolation regions; the bottom fin part is positioned in the device unit region and protrudes from the top of the substrate; the channel structure is positioned above the top of the bottom fin part; the protective layer is positioned at the top of the substrate of the isolation region and on the side wall of the bottom fin portion closest to the isolation region, and comprises a first sub-protective layer positioned at the top of the substrate and a second sub-protective layer positioned on the side wall of the bottom fin portion; the conducting layer is protruded from the top of the first sub-protective layer and covers the side wall, back to the bottom fin part, of the second sub-protective layer, and the top of the conducting layer is lower than the top of the second sub-protective layer; the first isolation layer is positioned on the substrate between the adjacent bottom fin parts and on the top of the first sub-protection layer exposed out of the conductive layer, and the top of the first isolation layer is flush with the top of the second sub-protection layer; and the second isolation layer is positioned on the top of the conductive layer and covers the second sub-protection layer exposed out of the conductive layer and the side wall of the first isolation layer.

Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises isolation regions and device unit regions, the device unit regions are positioned between adjacent isolation regions, protruding portions protruding from the substrate are formed in the device unit regions, the protruding portions comprise bottom fin portions protruding from the substrate and channel protruding portions positioned at the tops of the bottom fin portions, first grooves are formed by the adjacent protruding portions and the top surface of the substrate in a surrounding mode, channel laminated layers with partial height close to one side of the substrate are formed at the tops of the protruding portions and serve as the bottom fin portions, channel laminated layers with residual height serve as channel structures, first grooves are formed by the adjacent channel laminated layers and the top surface of the substrate in a surrounding mode, and etching stop layers are formed at the tops of the channel laminated layers; forming a protective layer on the top of the substrate of the isolation region, the side wall of the bulge part closest to the isolation region and the top of the etching stop layer, wherein the protective layer also seals the top of the first groove; forming a sacrificial layer on the side wall of the protective layer in the isolation region; after forming the sacrificial layer, removing the protective layer and the sacrificial layer which are higher than the top of the etching stop layer; after removing the protective layer and the sacrificial layer which are higher than the top of the etching stop layer, forming a first isolation layer on the top of the protective layer of the isolation region and in the first groove of the device unit region, wherein the top of the first isolation layer is flush with the top of the etching stop layer; removing the sacrificial layer, and forming an opening surrounded by the side wall of the first isolation layer, the top of the protective layer on the substrate and the side wall of the protective layer in the isolation region; forming a conductive layer in the opening, wherein the top of the conductive layer is lower than the top of the bottom fin part; after forming the conducting layer, filling a second isolating layer in the residual space of the opening; and removing the first isolation layer, the second isolation layer and the protection layer which are higher than the top surface of the bottom fin portion to expose the channel protruding portion.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

compared with the scheme that the conducting layers are formed between the adjacent protruding parts, the pattern density in the device unit area is increased, the forming area of the semiconductor structure is reduced, meanwhile, the probability that the protruding parts in the device unit area are damaged in the process of forming the conducting layers is reduced, and the performance of the semiconductor structure is improved.

Drawings

Fig. 1 to 5 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;

FIG. 6 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention;

fig. 7 to fig. 22 are schematic structural diagrams corresponding to steps of a method for forming a semiconductor structure according to an embodiment of the present invention.

Detailed Description

The performance of semiconductor structures currently needs to be improved. The reason why the performance of a semiconductor structure needs to be improved is analyzed in combination with a method for forming a semiconductor structure.

Fig. 1 to 5 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure.

Referring to fig. 1, a substrate 10 is provided, where the substrate 10 includes an isolation region 10A and a device unit region 10B, the device unit region 10B includes a sub-device region 11B and a partition region 11A, a fin 11 protruding from the substrate 10 is formed in the device unit region 10B, and a fin mask layer 12 is formed on the top of the fin 11.

Referring to fig. 2, a dielectric layer 13 is formed on the substrate 10 where the fin 11 is exposed, and the top of the dielectric layer 13 is flush with the top of the fin mask layer 12.

Referring to fig. 3, the dielectric layer 13 in the isolation region 10A and the isolation region 11A is removed, and a first groove 20 exposing the top of the substrate 10 is formed in the isolation region 10A and the isolation region 11A.

Referring to fig. 4, a protective layer 16 is formed on the sidewalls of the first recess 20.

With continued reference to fig. 4, after the formation of the protection layer 16, a portion of the thickness of the substrate 10 is removed in the isolation region 10A and the isolation region 11A, and a second groove 30 surrounded by the sidewall and the bottom of the remaining substrate 10 is formed.

Referring to fig. 5, after the second groove 30 is formed, the protective layer 16 is removed; after removing the protective layer 16, forming an insulating layer 60 on the sidewall and bottom of the second groove 30 and the sidewall of the first groove 20; after the insulating layer 60 is formed, a conductive layer 17 is formed in the remaining space of the second groove 30 and in a partial space of the first groove 20.

Research shows that, in the process of forming the conductive layer 17, the material forming the conductive layer 17 in the isolation region 10A and the isolation region 11A is etched back, the adopted etching process increases the probability of damage to the fin portion 11 in the device unit region 10B, and meanwhile, the direction perpendicular to the extending direction of the fin portion 11 is taken as the transverse direction, so that under the condition that the transverse dimension of the substrate 10 is fixed, the pattern density in the device unit region 10B is reduced due to the excessive area occupied by the conductive layer 17, and in sum, the performance of the semiconductor structure is reduced in the above two aspects.

In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises isolation regions and device unit regions, the device unit regions are positioned between adjacent isolation regions, protruding portions protruding from the substrate are formed in the device unit regions, the protruding portions comprise bottom fin portions protruding from the substrate and channel protruding portions positioned at the tops of the bottom fin portions, first grooves are formed by the adjacent protruding portions and the top surface of the substrate in a surrounding mode, channel laminated layers with partial height close to one side of the substrate are formed at the tops of the protruding portions and serve as the bottom fin portions, channel laminated layers with residual height serve as channel structures, first grooves are formed by the adjacent channel laminated layers and the top surface of the substrate in a surrounding mode, and etching stop layers are formed at the tops of the channel laminated layers; forming a protective layer on the top of the substrate of the isolation region, the side wall of the bulge part closest to the isolation region and the top of the etching stop layer, wherein the protective layer also seals the top of the first groove; forming a sacrificial layer on the side wall of the protective layer in the isolation region; after forming the sacrificial layer, removing the protective layer and the sacrificial layer which are higher than the top of the etching stop layer; after removing the protective layer and the sacrificial layer which are higher than the top of the etching stop layer, forming a first isolation layer on the top of the protective layer of the isolation region and in the first groove of the device unit region, wherein the top of the first isolation layer is flush with the top of the etching stop layer; removing the sacrificial layer, and forming an opening surrounded by the side wall of the first isolation layer, the top of the protective layer on the substrate and the side wall of the protective layer in the isolation region; forming a conductive layer in the opening, wherein the top of the conductive layer is lower than the top of the bottom fin part; after forming the conducting layer, filling a second isolating layer in the residual space of the opening; and removing the first isolation layer, the second isolation layer and the protection layer which are higher than the top surface of the bottom fin portion to expose the channel protruding portion.

In the forming method provided by the embodiment of the invention, the protective layer is formed on the top of the substrate of the isolation region, the side wall of the bulge part closest to the isolation region and the top of the etching stop layer, the protective layer also seals the top of the first groove, so that the protective layer seals the substrate exposed out of the device unit region, then the sacrificial layer is formed on the side wall of the protective layer in the isolation region, the forming position of the conductive layer is defined through the sacrificial layer, and the conductive layer is formed in the opening after the sacrificial layer is removed.

In order to make the aforementioned objects, features and advantages of the embodiments of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings.

FIG. 6 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention.

The semiconductor structure includes: a substrate 200, the substrate 200 including isolation regions 200A and device cell regions 200B, the device cell regions 200B being located between adjacent isolation regions 200A; a bottom fin 201 in the device cell region 200B and protruding from the top of the substrate 200; a channel structure 290 located over the top of the bottom fin 201; a protection layer 251 located on the top of the substrate 200 of the isolation region 200A and on the sidewall of the bottom fin portion 201 closest to the isolation region 200A, the protection layer 251 including a first sub-protection layer 209 located on the top of the substrate 200 and a second sub-protection layer 250 located on the sidewall of the bottom fin portion 201; a conductive layer 217 protruding from the top of the first sub-passivation layer 209 and covering the sidewalls of the second sub-passivation layer 250 opposite to the bottom fin 201, wherein the top of the conductive layer 217 is lower than the top of the second sub-passivation layer 250; a first isolation layer 213 disposed on the substrate 200 between the adjacent bottom fins 201 and on the top of the first sub-protection layer 209 exposed by the conductive layer 217, wherein the top of the first isolation layer 213 is flush with the top of the second sub-protection layer 250; the second isolation layer 222 is located on top of the conductive layer 217, and covers the sidewalls of the first isolation layer 213 and the second sub-passivation layer 250 exposed by the conductive layer 217.

In this embodiment, the conductive layer 217 protrudes from the top of the first sub-protection layer 209 and covers the sidewall of the second sub-protection layer 250 facing away from the bottom fin portion 201, and the conductive layer 217 is located on both sides of the plurality of bottom fin portions 201, so that the pattern density in the device unit region 200B is increased, the formation area of the semiconductor structure is reduced, and meanwhile, the probability that the bottom fin portion 201 in the device unit region 200B is damaged in the process of forming the conductive layer 217 is also reduced, thereby improving the performance of the semiconductor structure.

In this embodiment, the substrate 200 is made of silicon. In other embodiments, the substrate may also be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be a silicon substrate on an insulator or other types of bases such as a germanium base on an insulator.

In this embodiment, the bottom fin portion 201 protrudes from the substrate 200, and the material of the bottom fin portion 201 is the same as that of the substrate 200, and is silicon.

The channel structure 290 is used to provide the channel of the transistor.

In this embodiment, the substrate 200 is used to form a fin field effect transistor (FinFET). The channel structure 290 includes a channel fin protruding above the top of the bottom fin 201. The channel fin is for acting as a conductive channel in a transistor.

In this embodiment, the channel structure 290 and the bottom fin portion 201 are an integrated structure, and for this reason, the material of the channel structure 290 is the same as that of the bottom fin portion 201.

In other embodiments, the substrate 200 may also be used to form a gate all around transistor (GAA) or a Complementary Field Effect Transistor (CFET), and the channel structure 290 includes a channel stack suspended over the top of the bottom fin, the channel stack including one or more spaced apart channel layers along a normal direction to the surface of the substrate. The channel layer is for acting as a conducting channel in the transistor.

In this embodiment, the substrate 200 includes an isolation region 200A and a device unit region 200B, the device unit region 200B is used for forming a transistor, and the isolation region 200A is used for isolating the adjacent device unit region 200B.

In this embodiment, the device unit region 200B includes sub-device regions 210A and partition regions 210B located between adjacent sub-device regions 210A.

Specifically, adjacent sub-device regions 210A are used to form transistors of a first type and a second type, respectively, the first type and the second type being different. In some embodiments, the first type is N-type and the second type is P-type, and in other embodiments, the first type is P-type and the second type is N-type.

It should be noted that the partition region 210B located between the adjacent sub-device regions 210A is used to isolate the first type transistor and the second type transistor, so as to reduce the probability of inter-diffusion of ions in the well region doped in the substrate of the first type transistor and the second type transistor, which is beneficial to ensuring the respective performance of the first type transistor and the second type transistor, thereby improving the performance of the semiconductor structure.

In this embodiment, the top of the substrate 200 in the isolation region 210B is lower than the top of the substrate 200 in the sub-device region 210A, and a groove (not shown) is defined by the top of the substrate 200 in the isolation region 210B and the sidewall of the substrate 200 in the sub-device region 210A.

Specifically, the top of the substrate 200 in the partition region 210B is lower than the top of the substrate 200 in the sub-device region 210A, and the second isolation layer 222 is filled in the groove, which is beneficial to further reducing the probability of mutual diffusion of ions doped in the substrate of the adjacent sub-device region 210A, and plays a good role in isolation.

The protection layer 251 is located on the top of the substrate 200 of the isolation region 200A and on the sidewall of the bottom fin portion 201 closest to the isolation region 200A, and the protection layer 251 exposes the channel structure 290, so as to ensure that the channel structure 290 can perform a normal function.

The second sub-protection layer 250 covers the sidewall of the bottom fin portion 201 closest to the isolation region 200B, and the second sub-protection layer 250 is used for electrically isolating the bottom fin portion 201 from the conductive layer 217, so that the risk of short circuit between the conductive layer 217 and the bottom fin portion 201 is reduced, the sidewall of the bottom fin portion 201 is protected, and the performance of the semiconductor structure is improved.

The first sub-protection layer 209 is located on the top of the substrate 200 in the isolation region 200A, the first sub-protection layer 209 is used to electrically isolate the conductive layer 217 from the substrate 200, so as to reduce the risk of short circuit between the conductive layer 217 and the substrate 200, and the first sub-protection layer 209 protects the top of the substrate 200 in the process of forming the conductive layer 217.

Through the protection layer 251, the conductive layer 217 can be electrically isolated from the bottom fin portion 201 and the substrate 200.

In this embodiment, in the process of forming the semiconductor structure, the protection layer 251 is formed on the sidewall of the bottom fin portion 201 and extends to cover the top of the substrate 200, that is, the first sub-protection layer 209 is located on the top of the substrate 200 of the isolation region 200A, and the conductive layer 217 is formed on the conductive layer 217, so that the conductive layer 217 is located on the top of the first sub-protection layer 209, that is, the conductive layer 217 is located above the top of the substrate 200.

Note that the thickness of the protective layer 251 is not too large or too small. If the thickness of the protection layer 251 is too large, the spatial position of the conductive layer 217 in the isolation region 200A is easily occupied too much, so that the size of the conductive layer 217 does not meet the process requirement, and accordingly, the electrical performance of the conductive layer 217 is poor, thereby affecting the performance of the semiconductor structure; if the thickness of the protection layer 251 is too small, the isolation effect of the protection layer 251 on the bottom fin portion 201 and the conductive layer 217 is reduced, and the probability of short circuit between the conductive layer 217 and the bottom fin portion 201 is increased, thereby affecting the performance of the semiconductor structure. For this reason, in this embodiment, the thickness of the protection layer 251 is 7 nm to 50 nm.

The protection layer 251 is used to electrically isolate the protrusion 291 from the conductive layer 217, and the protection layer 251 is an insulating material, and for this purpose, the material of the protection layer 251 is one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide. As an example, the material of the protection layer 251 is silicon oxide.

The conductive layer 217 is used to make electrical connections to interconnect structures that are subsequently formed in the isolation region 200A. Specifically, the conductive layer 217 is a Buried Power Rail (BPR) structure.

In this embodiment, the conductive layer 217 is made of tungsten. The resistivity of tungsten is low, which is beneficial to improving the signal delay of the rear RC and improving the processing speed of the chip, and is also beneficial to reducing the resistance of the conductive layer 217, and correspondingly reducing the power consumption. In other embodiments, the material of the conductive layer may also be cobalt, ruthenium, or nickel.

Note that, regarding a direction perpendicular to the extending direction of the bottom fin portion 201 as a lateral direction, the lateral dimension of the conductive layer 217 is not necessarily too large or too small. If the lateral dimension of the conductive layer 217 is too large, under the condition of a certain lateral dimension of the substrate 200, the dimension of the sub-device region 210A is easily made too small, and accordingly, the pattern density in the sub-device region 210A is reduced, thereby affecting the performance of the semiconductor structure; if the lateral dimension of the conductive layer 217 is too small, the aspect ratio of the conductive layer 217 is too small, which increases the filling difficulty of forming the conductive layer 217 in the forming process of the conductive layer 217, and at the same time, the lateral dimension of the conductive layer 217 is too small, which results in that the conductive layer in the isolation region 100A cannot meet the electrical requirement, thereby affecting the performance of the semiconductor structure. For this reason, in the present embodiment, the lateral dimension of the conductive layer 217 is 15 nm to 30 nm, taking the direction perpendicular to the extending direction of the bottom fin 201 as the lateral direction.

It should be noted that the top of the conductive layer 217 is lower than the top of the bottom fin 201, which provides a spatial location for forming the second isolation layer 222 on the top of the conductive layer 217, thereby reducing the probability of damage to the top of the conductive layer 217 in the subsequent process, and improving the performance of the semiconductor structure.

Also, the conductive layer 217 is made to be buried in the second isolation layer 222 and the first isolation layer 213 to ensure the normal operation of the device.

It should be noted that the distance from the top of the conductive layer 217 to the top of the second sub-passivation layer 250 is not too large or too small. If the distance from the top of the conductive layer 217 to the top of the second sub-protection layer 250 is too large, the filling difficulty of forming the second isolation layer 222 on the top of the conductive layer 217 is increased; if the distance from the top of the conductive layer 217 to the top of the second sub-protection layer 250 is too small, it is easy to cause the protection effect of the second isolation layer 222 on the top of the conductive layer 217 to be poor, and the probability that the top of the conductive layer 217 is damaged and the probability that the conductive layer 217 is exposed are increased. For this reason, in this embodiment, the distance from the top of the conductive layer 217 to the top of the second sub-passivation layer 250 is 10 nm to 50 nm.

The first isolation layer 213 electrically isolates adjacent transistors.

The first isolation layer 213 is located on top of the substrate 200 of the sub-device region 210A.

Specifically, the first isolation layer 213 on the top of the substrate 200 in the sub-device region 210A isolates the bottom fin 201 protruding from the sub-device region 210A.

The top of the first isolation layer 213 is flush with the top of the second sub-protection layer 250, thereby providing a spatial location for forming the second isolation layer 222 on top of the conductive layer.

The first isolation layer 213 is an insulating material, and for this purpose, the material of the first isolation layer 213 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride. As an example, the material of the first isolation layer 213 is silicon oxide.

The first isolation layer 213 is located on top of the substrate 200 of the sub-device region 210A.

Specifically, the first isolation layer 213 on the top of the substrate 200 in the sub-device region 210A isolates the bottom fin 201 protruding from the sub-device region 210A.

Specifically, the second isolation layer 222 covers the top of the conductive layer 217, so as to protect the top of the conductive layer 217 in the process of forming the gate structure, thereby reducing the probability of damage to the conductive layer 217.

In this embodiment, the second isolation layer 222 is also located on top of the substrate 200 of the partition region 210B.

Specifically, the second isolation layer 222 is further filled in the groove, so that the second isolation layer 222 located in the partition region 210B can perform a better isolation function, thereby better reducing the probability of inter-diffusion of ions doped in the substrates of the first-type transistor and the second-type transistor.

The second isolation layer 222 is made of an insulating material, and serves as an isolation function for adjacent device regions, and for this purpose, the material of the second isolation layer 222 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride. As an example, the material of the second isolation layer 222 is silicon oxide.

Fig. 7 to fig. 22 are schematic structural diagrams corresponding to steps of a method for forming a semiconductor structure according to an embodiment of the present invention.

Referring to fig. 7 to 9, a substrate 100 is provided, the substrate 100 includes isolation regions 100A and a device unit region 100B, the device unit region 100B is located between adjacent isolation regions 100A, a protruding portion 191 protruding from the substrate 100 is formed in the device unit region 100B, the protruding portion 191 includes a bottom fin 101 protruding from the substrate 100 and a channel protruding portion 190 located at the top of the bottom fin 101, a first groove 106 is defined by the neighboring protruding portion 191 and the top surface of the substrate 100, and an etching stop layer 102 is formed at the top of the protruding portion 191.

The substrate 100 is used to provide a process platform for subsequent process steps.

In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate may also be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

In this embodiment, the protrusion 191 protrudes from the substrate 100, the protrusion 191 with a partial height serves as the bottom fin 101, the bottom fin 101 with a remaining height serves as the channel protrusion 190, and the bottom fin 101 is closer to the substrate 100.

In the present embodiment, the substrate 100 is used to form a fin field effect transistor (FinFET). The channel protrusion 190 comprises a channel fin protruding from the top of the bottom fin 101.

The channel bumps 190 are used in subsequent process steps to act as conductive channels in the transistors.

In this embodiment, the material of the protrusion 191 is the same as that of the substrate 100, and is silicon.

In this embodiment, the step of forming the protrusion 191 protruding from the substrate 100 in the device cell region 100B includes: as shown in fig. 7, a substrate is provided; etching a stop material layer on the top of the substrate; forming the patterned fin mask layer 103 on the tops of the etching stop material layers of the device unit region 100B and the isolation region 100A; patterning the base by taking the fin part mask layer 103 as a mask to form a substrate 100 and a convex part 191 protruding from the substrate 100; as shown in fig. 8, a first mask layer 108 is formed in the device cell area 100B to cover the top and sidewalls of the protruding portion 191, and the first mask layer 108 exposes the protruding portion 191 in the isolation area 100A; taking the first mask layer 108 as a mask, removing the protrusion 191 in the isolation region 100A, forming a protrusion 191 protruding from the substrate 100 in the device unit region 100B, and using the remaining etching stop material layer as the etching stop layer 102.

In the process of forming the fin portion mask layer 103, the etching stop material layer plays a role in stopping etching, and the probability of damage to the material corresponding to the protrusion portion 191 is reduced.

In this embodiment, after removing the protruding portion 191 in the isolation region 100A, the method further includes: the first mask layer 108 is removed.

Specifically, the process of removing the first mask layer 108 includes an ashing process.

In this embodiment, the substrate 100 includes an isolation region 100A and a device unit region 100B, the device unit region 100B is used for forming a transistor, and the isolation region 100A is used for isolating the adjacent device unit regions 100B.

In this embodiment, the device unit region 100B includes sub-device regions 110A and partition regions 110B located between adjacent sub-device regions 110A.

Specifically, adjacent sub-device regions 110A are used to form transistors of a first type and a second type, respectively, the first type and the second type being different. In one embodiment, the first type is N-type, the second type is P-type, and in other embodiments, the first type is P-type and the second type is N-type.

It should be noted that the partition region 110B located between the adjacent sub device regions 110A is used to isolate the first type transistor and the second type transistor, so as to reduce the probability of mutual diffusion of the doped well region ions in the substrates of the first type transistor and the second type transistor, which is beneficial to ensuring the respective performances of the first type transistor and the second type transistor, thereby improving the performances of the semiconductor structure.

In other embodiments, the substrate 100 may also be used to form a gate all around transistor (GAA) or a nanoflake field effect transistor (CFET), the channel bump comprising a stacked structure raised on top of the bottom fin, the stacked structure comprising one or more stacked channel stacks comprising a sacrificial layer and a channel layer on the sacrificial layer.

Meanwhile, in the subsequent process of removing the protective layer and the sacrificial layer which are higher than the top of the etching stop layer 102, the etching stop layer 102 plays a role in stopping etching, and the flatness of the top surfaces of the protective layer and the sacrificial layer is improved.

It should be noted that the first groove 106 formed by the adjacent protrusion 191 and the top surface of the substrate 100 provides a spatial location for the subsequent formation of the first isolation layer.

Referring to fig. 10, a protective layer 109 is formed on top of the substrate 100 of the isolation region 100A, on top of the sidewall of the protrusion 191 closest to the isolation region 100B, and on top of the etch stop layer 102, the protective layer 109 further sealing the top of the first groove 106.

Specifically, the protective layer 109 seals the top of the first groove 106, so that the protective layer 109 seals all the substrate 100 exposed from the device unit region 100B, and the probability of forming a sacrificial layer in the device unit region 100B in the subsequent process of forming the sacrificial layer is reduced.

The protection layer 109 covers the side wall of the protruding portion 191 closest to the isolation region 100B, the protection layer 109 is used for electrically isolating the protruding portion 191 from a subsequently formed conductive layer, the risk of short circuit between the conductive layer and the protruding portion 191 is reduced, and in the process of forming the conductive layer subsequently, the protection layer 109 is also used for protecting the side wall of the bottom fin portion 101, so that the performance of the semiconductor structure is improved.

Moreover, the protection layer 109 is located on top of the substrate 100 in the isolation region 100A, and the protection layer 109 is used to electrically isolate the conductive layer 117 from the substrate 100, reduce the risk of short circuit between the conductive layer 117 and the substrate 100, and protect the top of the substrate 100 by the protection layer 109 in the process of forming the conductive layer 117.

Note that the thickness of the protective layer 109 is not too large or too small. If the thickness of the protection layer 109 is too large, the space position of a conductive layer formed in the isolation region 100A subsequently is easily occupied too much, so that the size of the conductive layer does not meet the process requirement, and accordingly, the electrical performance of the conductive layer is poor, thereby affecting the performance of the semiconductor structure; if the thickness of the protective layer 109 is too small, the effect of the protective layer 109 to electrically isolate the protrusion 191 from the conductive layer is reduced, increasing the probability of a short circuit between the conductive layer and the protrusion 191, thereby affecting the performance of the semiconductor structure. For this reason, in the present embodiment, the thickness of the protection layer 109 is 7 nm to 50 nm.

The protection layer 109 is used to electrically isolate the protrusion 191 from a subsequently formed conductive layer, and the protection layer 109 is an insulating material, and for this purpose, the material of the protection layer 109 is one or more of silicon oxide, silicon nitride, and silicon oxynitride. As an example, the material of the protection layer 109 is silicon oxide.

In this embodiment, the process of forming the protection layer 109 on the top of the substrate 100 of the isolation region 100A, the sidewall of the protrusion 191 closest to the isolation region 100A, and the top of the etch stop layer 102 includes a plasma enhanced chemical vapor deposition process.

As an example, the process of forming the protective layer 109 includes a plasma enhanced chemical vapor deposition process. The plasma enhanced chemical vapor deposition process has the characteristics of low deposition temperature, high uniformity of film deposition thickness, strong film adhesion and the like, and because the distance between the adjacent convex parts 191 is small and the deposition rate of the material forming the protective layer 109 on the convex parts 191 is higher than that on the side walls of the convex parts 191, the protective layer 109 on the tops of the convex parts 191 can be contacted in advance, therefore, by adopting the plasma enhanced chemical vapor deposition process, the protective layer 109 can seal the tops of the first grooves 106, so that the substrate 100 exposed in the device unit area 100B is sealed. As an example, the process of forming the protective layer 109 includes a plasma enhanced chemical vapor deposition process.

Referring to fig. 11 to 12, in the isolation region 100A, a sacrificial layer 111 is formed on a sidewall of the protective layer 109.

Specifically, the forming position of the conductive layer formed subsequently is defined by the sacrificial layer 111, that is, the purpose of controlling the size of the conductive layer can be achieved by controlling the thickness of the sacrificial layer 111, compared with a scheme in which a dielectric layer is formed in the isolation region 100A, an opening is formed in the dielectric layer, and the conductive layer is formed in the opening, the sacrificial layer 111 is a film structure, so that the thickness of the sacrificial layer 111 is easily and precisely controlled, and the size of the conductive layer is favorably and precisely controlled. Moreover, the sacrificial layer 111 is a film structure and covers the sidewall of the protection layer 109, so that conductive layers are formed on two sides of the device unit region and self-alignment is achieved, controllability of a conductive layer forming region is improved, and difficulty in a process of forming the conductive layer is reduced.

In addition, compared with the scheme of forming a dielectric layer in the isolation region 100A, forming an opening in the dielectric layer, and forming a conductive layer in the opening, the embodiment can avoid the photolithography process, thereby reducing the difficulty of the process for forming the conductive layer, and accordingly, can also reduce the probability of damage to the protrusion 191 in the device unit region 100B.

The thickness of the sacrificial layer 111 is not preferably too large or too small in the lateral direction perpendicular to the extending direction of the protrusion 191. If the thickness of the sacrificial layer 111 is too large, under the condition that the lateral dimension of the substrate 100 is fixed, the dimension of the device unit area 100B is easily too small, and accordingly, the pattern density in the device unit area 100B is reduced, thereby affecting the performance of the semiconductor structure; if the thickness of the sacrificial layer 111 is too small, the aspect ratio of the sacrificial layer 111 is increased, and the difficulty of the process for removing the sacrificial layer 111 is increased in the subsequent process for removing the sacrificial layer 111, which correspondingly affects the process effect of the subsequent formation of the conductive layer, thereby affecting the performance of the semiconductor structure. For this reason, in the present embodiment, the thickness of the sacrificial layer 111 is 15 nm to 30 nm, taking the direction perpendicular to the extending direction of the protrusion 191 as a lateral direction.

In order to reduce the difficulty of the subsequent process for removing the sacrificial layer 111, a material that is easy to remove needs to be selected as the material of the sacrificial layer 111, and for this reason, the material of the sacrificial layer 111 in this embodiment includes one or more of Si, siN, and SiC.

In this embodiment, in the isolation region 100A, the step of forming the sacrificial layer 111 on the sidewall of the protection layer 109 includes: as shown in fig. 11, a sacrificial material layer 110 is formed on the top and the sidewall of the protection layer 109; as shown in fig. 12, the sacrificial material layer 110 on the top of the protection layer 109 is removed, and the sacrificial material layer 110 covering the sidewall of the protection layer 109 is left as the sacrificial layer 111.

In this embodiment, the process of forming the sacrificial material layer 110 on the top and the sidewall of the protection layer 109 includes an atomic layer deposition process.

The ald process includes multiple ald cycles, which provides good step coverage, facilitates increasing the thickness uniformity of the sacrificial material layer 110, and enables the sacrificial material layer 110 to cover the top and sidewalls of the protection layer 109. In other embodiments, the sacrificial material layer may also be formed by a Chemical Vapor Deposition (CVD) process.

In this embodiment, an etching process is adopted to remove the sacrificial material layer 110 on the top of the protection layer 109.

Specifically, the sacrificial material layer 110 on the top of the protection layer 109 can be completely removed by using an etching process, and only the sacrificial material layer 110 on the sidewall of the protection layer 109 remains.

Specifically, the etching process is an inductively coupled plasma dry etching process.

Referring to fig. 13, after the sacrificial layer 111 is formed, the protective layer 109 and the sacrificial layer 111 above the top of the etch stop layer 102 are removed.

And removing the protective layer 109 and the sacrificial layer 111 which are higher than the top of the etching stop layer 102, thereby providing a good process basis for the subsequent formation of the first isolation layer.

In this embodiment, the step of removing the protection layer 109 and the sacrificial layer 111 higher than the top of the etching stop layer 102 includes: and with the top of the etching stop layer 102 as a stop position, performing planarization treatment on the sacrificial layer 111 and the protective layer 109 which are higher than the top of the etching stop layer 102.

Compared with the etching process for removing the protective layer 109 and the sacrificial layer 111 which are higher than the top of the etching stop layer 102, the difficulty in selecting the etching rate is increased in the etching process, so that the process steps are complicated, and therefore, the flatness of the top of the protrusion 191 can be improved by adopting the planarization treatment, the process complexity is favorably reduced, and meanwhile, the probability of the flatness of the top of the protrusion 191 is also reduced.

In this embodiment, the planarization process includes a chemical mechanical polishing process.

Referring to fig. 14 to 15, after removing the protection layer 109 and the sacrificial layer 111 above the top of the etch stop layer 102, a first isolation layer 113 is formed on the top of the protection layer 109 of the isolation region 100A and in the first groove 106 of the device unit region 100B, and the top of the first isolation layer 113 is flush with the top of the etch stop layer 102.

Specifically, in the subsequent process of removing the sacrificial layer 111, the first isolation layer 113 protects the top of the substrate 100 and the sidewalls of the protrusions 191 exposed in the device unit region 100B, and meanwhile, by forming the first isolation layer 113 on the top of the protection layer 109 located in the isolation region 100A, after the sacrificial layer 111 is subsequently removed, an opening surrounded by the sidewall of the first isolation layer 113, the top of the protection layer 109 located on the substrate 100, and the sidewall of the protection layer 109 can be formed, that is, a position of a subsequently formed conductive layer is defined, so that the position accuracy of the conductive layer is improved, and thus the performance of the semiconductor structure is improved.

The first isolation layer 113 is made of an insulating material, and plays a role in electrically isolating adjacent device regions, and meanwhile, in the subsequent process of removing the sacrificial layer 111, in order to enable the etching rate of the first isolation layer 113 to be smaller than that of the sacrificial layer, a high etching selection ratio needs to be provided between the first isolation layer 113 and the sacrificial layer 111, and for this reason, the material of the first isolation layer 113 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride. As an example, the material of the first isolation layer 113 is silicon oxide.

In this embodiment, the step of forming the first isolation layer 113 on top of the protection layer 109 of the isolation region 100A and in the first groove 106 of the device unit region 100B includes: as shown in fig. 14, a first isolation material layer 112 is formed on top of the substrate 100, and the first isolation material layer 112 covers the top of the sacrificial layer 111, the protective layer 109 and the etch stop layer 102 and is filled in the first groove 106; as shown in fig. 15, with the top of the etch stop layer 102 as a stop position, the first isolation material layer 112 higher than the top of the etch stop layer 102 is planarized, and the remaining first isolation material layer 112 located on the top of the protection layer 109 and in the first groove 106 serves as the first isolation layer 113.

In this embodiment, the density of the semiconductor structures is increased, and the distance between the adjacent protrusions 191 and other semiconductor structures are correspondingly reduced, so that the first isolation material layer 112 can be formed by a Fluid Chemical Vapor Deposition (FCVD) process in order to achieve sufficient filling of the first isolation material layer 112. In other embodiments, the process of forming the first isolation material layer 112 may further include an atomic layer deposition process or a combination of an atomic layer deposition process and a fluid chemical vapor deposition process.

Referring to fig. 16, the sacrificial layer 111 is removed, and an opening 116 surrounded by a sidewall of the first isolation layer 113, a top of the protection layer 109 on the substrate 100, and a sidewall of the protection layer 109 is formed in the isolation region 100A.

The openings 116 provide a spatial location for the subsequent formation of the conductive layer, and at the same time, the conductive layer is formed only on both sides of the plurality of protrusions 191, so that the pattern density in the device cell region 100B is increased, and the formation area of the semiconductor structure is reduced.

Moreover, the opening 116 is formed by removing the sacrificial layer 111, so that self-alignment can be achieved, and at the same time, the protection layer 109 protects the protrusion 191, thereby reducing the probability that the protrusion 191 in the device unit region 100B is damaged in the process of forming the opening 116 and the conductive layer, and improving the performance of the semiconductor structure.

In this embodiment, the process of removing the sacrificial layer 111 includes a wet etching process.

The wet etching process has the characteristics of an isotropic etching process, has the characteristics of strong etching target, high etching efficiency, strong transverse etching capability and the like, and can reduce the damage to the protective layer 109 at the bottom of the opening 116 and the first isolation layer 113 on the side wall of the opening 116 in the process of transversely removing the sacrificial layer 111.

In other embodiments, the sacrificial layer may also be removed using an ashing process.

Referring to fig. 17, a conductive layer 117 is formed in the opening 116, and the top of the conductive layer 117 is lower than the top of the bottom fin 101.

The conductive layer 117 is used to make electrical connections to interconnect structures subsequently formed in the isolation region 100A.

Specifically, the conductive layer 117 is a Buried Power Rail (BPR) structure.

In this embodiment, the conductive layer 117 is made of tungsten. The lower resistivity of tungsten is beneficial to improving the signal delay of the rear-stage RC and improving the processing speed of the chip, and is also beneficial to reducing the resistance of the conductive layer 117, so that the power consumption is correspondingly reduced. In other embodiments, the material of the conductive layer may also be cobalt, ruthenium, or nickel.

In this embodiment, the step of forming the conductive layer 117 in the opening 116 includes: filling a conductive material layer (not shown) in the opening 116; a portion of the thickness of the conductive material layer is etched back, and the remaining conductive material layer in the opening 116 serves as the conductive layer 117.

In this embodiment, the process of etching back the conductive material layer with a certain thickness includes an anisotropic dry etching process.

Specifically, the anisotropic dry etching process has the characteristic of anisotropic etching, the longitudinal etching rate of the anisotropic dry etching process is far greater than the transverse etching rate, quite accurate pattern transfer can be obtained, the appearance quality of the side wall of the opening 116 is improved, meanwhile, the dry etching process has high process controllability, and the probability of damage to the protective layer 109 and the first isolation layer 113 on the side wall of the opening 116 is reduced in the process of back etching the conductive material layer with partial thickness.

It should be noted that the top of the conductive layer 117 is lower than the top of the bottom fin 101, so as to provide a spatial location for forming a second isolation layer on the top of the conductive layer 117 in the following process, thereby reducing the probability of damage to the top of the conductive layer 117 in the following process, and improving the performance of the semiconductor structure.

Meanwhile, the conductive layer 117 is made to be buried in the first isolation layer 113, and a second isolation layer formed later.

Referring to fig. 18 to fig. 19, after forming the conductive layer 117, before subsequently filling the second isolation layer in the remaining space of the opening 116, the method further includes: the protrusions 191 and the first isolation layer 113 of the partition region 110B are removed.

Specifically, as can be seen from the foregoing, since the adjacent sub-device regions 110A are used to form a first type transistor and a second type transistor, respectively, the first type and the second type are different. In order to reduce the probability of inter-diffusion of ions doped in the substrates of the first type transistor and the second type transistor, which is beneficial to ensuring the respective performances of the first type transistor and the second type transistor, the protrusion 191 and the first isolation layer 113 of the partition region 110B are removed to provide a spatial location for forming a second isolation layer in the partition region 110B subsequently.

In this embodiment, the step of removing the protrusion 191 and the first isolation layer 113 of the partition region 110B includes: as shown in fig. 18, in the sub-device region 110A and the isolation region 100A, a second mask layer 118 is formed on top of the first isolation layer 113, the etch stop layer 102, the protection layer 109, and the conductive layer 117, and the second mask layer 118 exposes the first isolation layer 113 and the protrusion 191 in the isolation region 110B; as shown in fig. 19, the second mask layer 118 is used as a mask to remove the protrusion 191 and the first isolation layer 113 in the isolation region 110B.

In this embodiment, the removing the protrusion 191 and the first isolation layer 113 of the blocking region 110B includes a dry etching process.

It should be noted that, in the step of removing the protrusions 191 and the first isolation layer 113 of the isolation region 110B, a part of the thickness of the substrate 100 of the isolation region 110B is also removed, and a second groove 120 is formed in the substrate 100.

In order to better reduce the probability of mutual diffusion of well region ions doped in the substrates of the first type transistor and the second type transistor, the substrate 100 of the partition region 110B is also removed by a part of the thickness, so that a second isolation layer formed in the second groove 120 in the partition region 110B subsequently can play a better isolation role.

It should be further noted that, after removing the protrusion 191 and the first isolation layer 113 of the isolation region 110B, the method for forming a semiconductor structure further includes: the second mask layer 118 is removed.

In this embodiment, the process of removing the second mask layer 118 includes an ashing process.

Referring to fig. 20 to 21, after the conductive layer 117 is formed, a second isolation layer 122 is filled in the remaining space of the opening 116.

Specifically, the second isolation layer 122 covers the top of the conductive layer 117, and plays a role in protecting the top of the conductive layer 117 in a subsequent process for forming a gate structure, thereby reducing the probability of damage to the conductive layer 117.

In this embodiment, the step of filling the remaining space of the opening 116 with the second isolation layer 122 includes: as shown in fig. 20, a second isolation material layer 121 is formed in the opening 116, and the second isolation material layer 121 also covers the top of the first isolation layer 113, the etch stop layer 102 and the protection layer 109; as shown in fig. 21, with the top of the etch stop layer 102 as an etch stop position, the second isolation material layer 121 higher than the top of the etch stop layer 102 is planarized, and the second isolation material layer 121 remaining in the opening 116 serves as the second isolation layer 122.

In this embodiment, in the step of filling the second isolation layer 122 in the remaining space of the opening 116, the second isolation layer 122 is further formed on the substrate 100 of the partition region 110B, and the top of the second isolation layer 122 of the partition region 110B is flush with the top of the second isolation layer 122 in the opening 116.

The second isolation layer 122 in the partition region 110B isolates the transistors in the adjacent sub-device region 110A, and meanwhile, the top of the second isolation layer 122 in the partition region 110B is flush with the top of the second isolation layer 122 in the opening 116, so that the flatness of the top surface of the second isolation layer 122 is high, and a good process foundation is provided for the subsequent process.

In this embodiment, in the step of forming the second isolation layer 122, the second isolation layer 122 is further filled in the second groove 120.

Specifically, the second isolation layer 122 filled in the second groove 120 reduces the probability of inter-diffusion of well region ions doped in the substrate of the adjacent sub-device region 110A, thereby performing a good isolation function.

The second isolation layer 122 is made of an insulating material, and serves to isolate adjacent device regions, and for this purpose, the material of the second isolation layer 122 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride. As an example, the material of the second isolation layer 122 is silicon oxide.

Referring to fig. 22, the first isolation layer 113, the second isolation layer 122 and the protection layer 109 above the top surface of the bottom fin 101 are removed to expose the channel protrusion 190.

Specifically, the channel protrusion 190 is exposed, which provides a process base for a subsequent process for forming a gate structure.

It should be noted that the materials of the first isolation layer 113, the second isolation layer 122 and the protection layer 109 are the same, and therefore, in the same step, the first isolation layer 113, the second isolation layer 122 and the protection layer 109 higher than the top surface of the bottom fin 101 can be removed at the same time under the same etching selection ratio.

In this embodiment, the process of removing the first isolation layer 113, the second isolation layer 122 and the protection layer 109 higher than the top surface of the bottom fin 101 includes a dry etching process.

With continued reference to fig. 22, after removing the first isolation layer 113, the second isolation layer 122 and the protection layer 109 above the top surface of the bottom fin 101, the method further includes: the etch stop layer 102 on top of the channel bump 190 is removed.

In this embodiment, the process of removing the etching stop layer 102 includes a dry etching process.

In other embodiments, the process of removing the etch stop layer 102 may also be a wet etching process.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected by one skilled in the art without departing from the spirit and scope of the invention, as defined in the appended claims.

Claims (26)

1. A semiconductor structure, comprising:

a substrate including isolation regions and device cell regions, the device cell regions being located between adjacent isolation regions;

the bottom fin part is positioned in the device unit area and protrudes from the top of the substrate;

a channel structure located above the top of the bottom fin portion;

the protective layer is positioned on the top of the substrate of the isolation region and on the side wall of the bottom fin portion closest to the isolation region, and comprises a first sub protective layer positioned on the top of the substrate and a second sub protective layer positioned on the side wall of the bottom fin portion;

the conducting layer protrudes from the top of the first sub-protection layer and covers the side wall, back to the bottom fin portion, of the second sub-protection layer, and the top of the conducting layer is lower than the top of the second sub-protection layer;

the first isolation layer is positioned on the substrate between the adjacent bottom fin parts and on the top of the first sub-protection layer exposed out of the conductive layer, and the top of the first isolation layer is flush with the top of the second sub-protection layer;

and the second isolation layer is positioned at the top of the conducting layer and covers the exposed side walls of the second sub-protection layer and the first isolation layer of the conducting layer.

2. The semiconductor structure of claim 1, wherein the device cell region comprises sub-device regions and partition regions between adjacent sub-device regions, the bottom fin protruding above a substrate of the sub-device regions;

the first isolation layer is positioned on the top of the substrate of the sub-device region;

the second isolation layer is also positioned on the top of the substrate of the partition area.

3. The semiconductor structure of claim 2, wherein the substrate top of the exclusion region is lower than the substrate top of the sub-device region, the substrate top of the exclusion region and the substrate sidewalls of the sub-device region enclosing a recess;

the second isolation layer is also filled in the groove.

4. The semiconductor structure of claim 1, wherein a lateral dimension of the conductive layer is 15 nm to 30 nm in a lateral direction perpendicular to an extension direction of the bottom fin.

5. The semiconductor structure of claim 1, wherein the conductive layer comprises a buried power rail structure.

6. The semiconductor structure of claim 1, wherein a material of the conductive layer comprises one or more of tungsten, cobalt, copper, and aluminum.

7. The semiconductor structure of claim 1, wherein a distance from a top of the conductive layer to a top of the second sub-passivation layer is between 10 nm and 50 nm.

8. The semiconductor structure of claim 1, wherein the protective layer has a thickness of 7 nm to 50 nm.

9. The semiconductor structure of claim 1, wherein a material of the protective layer comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.

10. The semiconductor structure of claim 1, wherein a material of the first isolation layer comprises one or more of silicon oxide, silicon nitride, and silicon carbide.

11. The semiconductor structure of claim 1, wherein a material of the second isolation layer comprises one or more of silicon oxide and silicon oxynitride.

12. The semiconductor structure of claim 1, wherein the channel structure comprises a channel fin protruding from a top of the bottom fin or a channel stack suspended over a top of the bottom fin, the channel stack comprising one or more spaced apart channel layers along a normal to a surface of the substrate.

13. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein the substrate comprises isolation regions and device unit regions, the device unit regions are located between adjacent isolation regions, protruding portions protruding from the substrate are formed in the device unit regions, the protruding portions comprise bottom fin portions protruding from the substrate and channel protruding portions located at the tops of the bottom fin portions, first grooves are formed by the adjacent protruding portions and the top surface of the substrate in a surrounding mode, the channel lamination layers with partial height close to one side of the substrate are formed at the tops of the protruding portions and serve as the bottom fin portions, the channel lamination layers with the residual height serve as channel structures, first grooves are formed by the adjacent channel lamination layers and the top surface of the substrate in a surrounding mode, and etching stop layers are formed at the tops of the channel lamination layers;

forming a protective layer on the top of the substrate of the isolation region, the side wall of the protruding part closest to the isolation region and the top of the etching stop layer, wherein the protective layer also seals the top of the first groove;

forming a sacrificial layer on the side wall of the protective layer in the isolation region;

after the sacrificial layer is formed, removing the protective layer and the sacrificial layer which are higher than the top of the etching stop layer;

after the protective layer and the sacrificial layer which are higher than the top of the etching stop layer are removed, forming a first isolation layer on the top of the protective layer of the isolation region and in the first groove of the device unit region, wherein the top of the first isolation layer is flush with the top of the etching stop layer;

removing the sacrificial layer, and forming an opening surrounded by the side wall of the first isolation layer, the top of the protective layer on the substrate and the side wall of the protective layer in the isolation region;

forming a conductive layer in the opening, wherein the top of the conductive layer is lower than the top of the bottom fin portion;

after the conductive layer is formed, filling a second isolation layer in the residual space of the opening;

and removing the first isolation layer, the second isolation layer and the protection layer which are higher than the top surface of the bottom fin portion to expose the channel protruding portion.

14. The method of forming a semiconductor structure of claim 13, wherein forming a conductive layer in the opening comprises: filling a conductive material layer in the opening; and etching back part of the thickness of the conductive material layer, wherein the conductive material layer left in the opening is used as the conductive layer.

15. The method of forming a semiconductor structure of claim 13, wherein forming a sacrificial layer on sidewalls of the protective layer in the isolation region comprises: forming a sacrificial material layer on the top and the side wall of the protective layer; and removing the sacrificial layer material layer on the top of the protective layer, and taking the sacrificial layer material layer covering the side wall of the protective layer as the sacrificial layer.

16. The method of forming a semiconductor structure of claim 13, wherein removing the protective layer and sacrificial layer above the top of the etch stop layer comprises: and taking the top of the etching stop layer as a stop position, and carrying out planarization treatment on the sacrificial layer and the protective layer which are higher than the top of the etching stop layer.

17. The method of forming a semiconductor structure of claim 13, wherein forming a first isolation layer on top of the protective layer of the isolation region and in the first recess of the device cell region comprises: forming a first isolation material layer on the top of the substrate, wherein the first isolation material layer covers the tops of the sacrificial layer, the protective layer and the etching stop layer and is filled in the first groove; and with the top of the etching stop layer as a stop position, carrying out planarization treatment on the first isolation material layer higher than the top of the etching stop layer, and taking the rest first isolation material layer positioned on the top of the protection layer and in the first groove as the first isolation layer.

18. The method of forming a semiconductor structure according to claim 13, wherein the step of filling a second isolation layer in the remaining space of the opening comprises: forming a second isolation material layer in the opening, wherein the second isolation material layer also covers the tops of the first isolation layer, the etching stop layer and the protection layer; and taking the top of the etching stop layer as an etching stop position, carrying out planarization treatment on the second isolation material layer higher than the top of the etching stop layer, and taking the second isolation material layer left in the opening as the second isolation layer.

19. The method of claim 13, wherein forming a protective layer on top of the substrate of the isolation region, on sidewalls of the raised portions closest to the isolation region, and on top of the etch stop layer comprises a plasma enhanced chemical vapor deposition process.

20. The method of forming a semiconductor structure of claim 15, wherein the process of forming a layer of sacrificial material on top and sidewalls of the protective layer comprises an atomic layer deposition process.

21. The method of forming a semiconductor structure according to claim 17, wherein the process of forming the first spacer material layer comprises an atomic layer deposition process, a fluid chemical vapor deposition process, or a combination of an atomic layer deposition process and a fluid chemical vapor deposition process.

22. The method of forming a semiconductor structure of claim 13, wherein the process of removing the sacrificial layer comprises a wet etch process.

23. The method of forming a semiconductor structure according to claim 13, wherein in the step of forming the sacrificial layer, a material of the sacrificial layer includes one or more of Si, siN, and SiC.

24. The method of forming a semiconductor structure of claim 13, wherein in the step of providing a substrate, the channel bump comprises a channel fin protruding on top of the bottom fin or a stacked structure protruding on top of the bottom fin, the stacked structure comprising one or more stacked channel stacks, the channel stack comprising a sacrificial layer and a channel layer on the sacrificial layer.

25. The method of forming a semiconductor structure of claim 13, wherein in the step of providing a substrate, the device cell region comprises a sub-device region and a spacer region located between adjacent sub-device regions;

after the conductive layer is formed, before the second isolation layer is filled in the remaining space of the opening, the method further includes: removing the bulge part and the first isolation layer of the partition area;

and in the step of filling the residual space of the opening with a second isolation layer, the second isolation layer is also formed on the substrate of the partition area, and the top of the second isolation layer of the partition area is flush with the top of the second isolation layer in the opening.

26. The method of forming a semiconductor structure according to claim 25, wherein in the step of removing the projections and the first isolation layer of the exclusion region, a portion of the thickness of the substrate of the exclusion region is also removed, forming a second recess in the substrate;

in the step of forming the second isolation layer, the second isolation layer is further filled in the second groove.

Images