CN115863152A - Patterning method, patterning structure and semiconductor device - Google Patents

Abstract

The invention discloses a patterning method, a patterning structure and a semiconductor device, wherein the patterning method comprises the following steps: providing a substrate; forming a graphoepitaxy induction structure on one surface of the substrate, wherein the graphoepitaxy induction structure comprises first intervals and first bulges separated by the first intervals, and the material of the first bulges is a block copolymer; filling an inducing layer in the first interval, and performing directional self-assembly on the block copolymer forming the first bump to form a plurality of modified regions; and selectively removing part of the modified region in the block copolymer to form a patterned structure, wherein the space size of the patterned structure is the same as that of the first space. The patterning method and the patterning structure can be applied to the production of semiconductor devices, and the space utilization rate of the semiconductor devices can be improved.

Description

Patterning method, patterning structure and semiconductor device

Technical Field

The invention relates to the technical field of semiconductor device manufacturing, in particular to a patterning method, a patterning structure and a semiconductor device.

Background

As the degree of integration of a semiconductor device increases, the area of the entire chip gradually increases as the capacity of a memory increases, but actually the layout pattern area of each memory cell in the semiconductor device becomes smaller and smaller. The pitch (pitch) of a layout pattern, such as a Critical Dimension (CD) of a certain pattern or a pitch between patterns, becomes smaller as semiconductor devices are scaled down.

DSA (Directed self-assembly) techniques deposit a Block Copolymer (BCP) or polymer blend on a substrate, typically by spin coating, and through an annealing process to "direct" it into an ordered structure. Under certain conditions, the blocks of such copolymer phases separate into microdomains (also referred to as "domains"), and in the process, nanofeatures of different chemical compositions can be formed, thus enabling the formation of pitch patterns with nanofeatures by DSA techniques. However, the critical dimension or pitch of the patterns manufactured by the existing DSA technology is still large, and further breakthrough cannot be made.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, it is an object of the present invention to provide a patterning method, a patterning structure and a semiconductor device, so as to form a patterned structure with a critical dimension smaller than 28nm.

In order to achieve the above and other related objects, the present invention provides a patterning method, including:

providing a substrate;

forming a graphoepitaxy induction structure on one surface of the substrate, wherein the graphoepitaxy induction structure comprises first intervals and first bulges separated by the first intervals, and the material of the first bulges is a block copolymer;

filling an inducing layer in the first interval, and carrying out directional self-assembly on the block copolymer forming the first bulges to form a plurality of modified regions, wherein the material of the inducing layer is the same as the property of a certain section of copolymer in the block copolymer;

and selectively removing part of the modified region in the block copolymer to form a patterned structure, wherein the space size of the patterned structure is the same as that of the first space.

Optionally, forming a graphoepitaxy inducing structure on a surface of the substrate, the graphoepitaxy inducing structure including a first space and a first protrusion spaced apart by the first space, comprising:

forming a pattern structure on a surface of a substrate by means of nanoimprinting, the pattern structure including first protrusions 'spaced apart by first spaces';

filling a dielectric layer in the first interval 'to form a second protrusion, and removing the first protrusion' to form a second interval;

the second spacers are filled with the block copolymer to form first protrusions, and the second protrusions are removed to form first spacers.

Optionally, the first spacing is between 28nm in size.

Optionally, the first spacing has a dimension between 5nm and 28nm.

Optionally, the first spacing has a dimension of less than 5nm.

Alternatively, the block copolymer has a molecular weight of 5000 to 7000 and the Flory Huggins parameter X1 of the block copolymer has a value of 0.18 to 0.20.

Optionally, the block copolymer forming the first protrusion is directionally self-assembled to form a plurality of modified regions, including:

and annealing the block copolymer to generate self-assembled polymerization arrangement of the high molecular materials in the block copolymer.

Alternatively, the modified region is formed as a first modified region and a second modified region, and the material of the inducing layer is the same as that of the first modified region or the second modified region.

Optionally, selectively removing a portion of the modified region in the block copolymer to form a patterned structure, comprising:

and selectively removing part of the modified region by adopting a wet etching method or a dry etching method.

Alternatively, the co-block polymer comprises polystyrene-b-polycarbonate.

Optionally, the block copolymer is polystyrene-b-polycarbonate, and annealing the block copolymer to generate a self-assembled polymeric arrangement of the polymeric materials in the block copolymer comprises:

the polystyrene-b-polycarbonate is annealed to form a modified region into a first modified region composed of polystyrene and a second modified region composed of polycarbonate.

Optionally, selectively removing a portion of the modified region in the block copolymer to form a patterned structure, comprising:

and selectively removing the second modifying region composed of polycarbonate to form a patterned structure.

Optionally, the material of the inducing layer comprises polystyrene.

The invention also provides a patterned structure formed by any one of the patterning methods in the above schemes. The invention also provides a semiconductor device which is provided with the first metal interconnection layer structure, the Fin structure or the grid structure, wherein the first metal interconnection layer structure, the Fin structure or the grid structure is provided with the graphical structure.

As described above, the patterning method, the patterning structure, and the semiconductor device according to the present invention have at least the following advantageous effects:

according to the patterning method, a graphoepitaxy induction structure with the interval size smaller than 28nm is formed on the surface of a substrate, and the embedded copolymer in the graphoepitaxy induction structure is subjected to directional self-assembly on the basis of the graphoepitaxy induction structure, so that a patterning structure with the size smaller than 28nm is formed. The patterning structure can be applied to the production of semiconductor devices, and the space utilization rate of the semiconductor devices is improved.

Further, the block copolymer used in the patterning method of the present invention is polystyrene-b-polycarbonate, and the interface energy of the block copolymer at the time of the directed self-assembly is the same as the interface energy of the substrate, and stable micro-phase separation can be achieved without performing a neutralization treatment on the substrate. Therefore, the invention does not need to arrange a neutral layer for changing the surface energy of the substrate, simplifies the process steps and reduces the production cost.

Furthermore, the patterning method firstly forms a first graph structure 'which is not easy to deform, then forms a second graph structure on the basis of the first graph structure', and transfers the second graph structure to form a graph epitaxial induction structure formed by a block copolymer material, so that the invention reduces the etching process of directly etching the graph epitaxial induction structure and the block copolymer as much as possible, and avoids the adverse effect of irregular graphs on small-size processes.

The patterning structure and the semiconductor device are manufactured by the patterning method, and the technical effects are also achieved.

Drawings

FIG. 1 is a flow chart of a patterning method according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a hard mask layer and a nanoimprint layer sequentially formed on a substrate in an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a nanoimprint layer imprinted by a nanoimprint method in an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of a hard mask layer after etching in an embodiment of the present invention;

fig. 5 and 6 are schematic structural diagrams illustrating a first space' of a hard mask layer filled with a dielectric layer according to an embodiment of the present invention;

FIG. 7 is a schematic structural diagram illustrating a first bump formed by removing the hard mask layer according to an embodiment of the present invention;

FIG. 8 is a schematic view of a second spacer filled with a chimeric copolymer according to an embodiment of the present invention;

FIG. 9 is a schematic structural view of an embodiment of the present invention after removing the second bump to form a first space;

FIG. 10 is a schematic structural view after an inducing layer is formed in the first spacer according to an embodiment of the present invention;

FIG. 11 is a schematic structural diagram illustrating the formation of multiple modified regions by directed self-assembly of a chimeric copolymer according to an embodiment of the present invention;

fig. 12 is a schematic structural diagram of the embodiment of the invention after removing part of the modified region.

List of reference numerals:

100. substrate and method of manufacturing the same

200. Hard mask layer

211. First protrusion'

212. First interval'

300. Nanoimprint layer

301. Embossing zone

302. Non-embossed areas

400. Dielectric layer

411. Second projection

412. Second interval

500. Block copolymer

510. First bump

512. First interval

600. Inducing layer

701. A first modifying region

702. A second modifying region

801. Third bump

802. Third interval

Detailed Description

The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will become apparent to those skilled in the art from the present disclosure. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present application. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.

It should be understood that the drawings provided in the embodiments of the present invention are only for illustrating the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation can be changed freely, and the layout of the components can be more complicated. The structures, proportions, and dimensions shown in the drawings and described in the specification are for the understanding of those skilled in the art, and are not intended to limit the scope of the present disclosure, which is defined in the appended claims, and therefore, they are not intended to limit the scope of the present disclosure in any way.

The block copolymer is a polymer formed by connecting two or more than two high molecular chain segments with different chemical properties through covalent bonds. Since the molecules of the different block copolymers move spontaneously to reach a thermal equilibrium state and are arranged in a periodically ordered structure. This process is known as self-assembly of block copolymers. Currently, when the self-assembled structure of the block copolymer is used as a template for etching a substrate, the self-assembled structure must form a vertical structure to enable efficient selective etching of the substrate. In order to allow the block copolymer to form vertical phase separation, a neutral layer is generally formed between the substrate and the block copolymer to neutralize the substrate, and thus the substrate surface energy is equal to the block copolymer surface energy, thereby achieving vertical phase separation of the block copolymer. However, different block copolymers require neutral layer materials with different components, and the surface energy can be accurately regulated and controlled only by accurately controlling the thickness and the density of the neutral layer, so that the optimal phase separation effect is achieved; therefore, the process steps for preparing the neutral layer are complicated, and the preparation cost is high.

In order to solve the technical problems of the background art and the above technical problems, the present embodiment provides a patterning method, which can form a pattern structure with a critical dimension smaller than 28nm, and can achieve a good phase separation effect without providing a neutral layer during the patterning process.

The patterning method described in this embodiment, with reference to fig. 1, includes:

s101: providing a substrate;

referring to fig. 2, a substrate 100 is provided, and the substrate 100 includes, but is not limited to, a Si substrate, a Ge substrate, a SiGe substrate, a SiC substrate, etc., and in the present embodiment, a silicon substrate is taken as an example for explanation.

S102: forming a graphoepitaxy induction structure on one surface of the substrate, wherein the graphoepitaxy induction structure comprises first intervals and first bulges separated by the first intervals, and the material of the first bulges is embedded copolymer;

specifically, referring to fig. 2, a hard mask layer 200 is formed on one surface of a substrate 100, and a nanoimprint layer 300 is formed over the hard mask layer 200; the hard mask layer 200 may be made of one or more of a nitride layer, silicon oxynitride, and metal nitride. The nanoimprint layer 300 may be a photoresist layer, or may be a combination of one or more of a thermoplastic polymer and a hardening resin. In the present embodiment, the hard mask layer 200 is a titanium nitride layer, and the nanoimprint layer 300 is a photoresist layer. The hard mask layer 200 and the nanoimprint layer 300 may be formed by spin coating (spin coating), dip coating (immersion coating), roll coating, physical Vapor Deposition (PVD), or other coating methods.

Referring to fig. 3, an imprinting area 301 and a non-imprinting area 302 are formed in a nanoimprinting layer 300 by means of nanoimprinting, which may be thermal imprinting, ultraviolet imprinting, or the like. In this embodiment, the nanoimprinting is performed by hot embossing. During the imprinting process, a template is first provided having a surface that forms the imprinting surface, which may be made of a rigid or semi-rigid material. The imprinting surface of the template has a nano-sized imprinting pattern having a nano-imprinting dimension of less than 28nm. After the nanoimprinting is completed, an imprinted region 301 and a non-imprinted region 302 are formed on the nanoimprinting layer 300, and the imprinted size of the imprinted region 301 is less than 28nm.

Referring to fig. 3 and 4, the hard mask layer 200 is etched to the surface of the substrate 100 along the windows formed in the imprinting area 301 and the nanoimprint layer 300 is removed, forming a first pattern structure'. The first pattern structure ' includes first spaces '212 and first protrusions '211 spaced apart by the first spaces '212, the first spaces '212 having a size of less than 28nm. Optionally, the first spacing' 212 is between 5nm and 28nm in size. Optionally, the size of the first spacing' 212 is less than 5nm.

Block copolymer materials or other less hard material layers tend to shrink back during the etching process to form a non-uniform surface. In this embodiment, a hard mask layer is formed below the photoresist layer, and the hard mask layer is used for pattern conversion, thereby preventing pattern retraction caused by directly etching the block copolymer or other material layers, and avoiding formation of an uneven pattern structure. In order to further prevent the pattern defects caused by the retraction of the pattern and the non-uniform pattern formation in the pattern preparation process, the second pattern structure is formed on the basis of the first pattern structure', and then the second pattern structure is transferred to form a pattern epitaxy induction structure formed by the block copolymer material, so that the adverse effect of the irregular pattern on the small-size process is avoided. Specifically, referring to fig. 5 and 6, a dielectric layer 400 is filled in the first space '212 of the first pattern structure' to form a second protrusion 412. In this process, a chemical mechanical polishing process is required to remove the deposited excess dielectric layer 400. The first protrusions' 211 are removed to form second spaces, and finally, a second pattern structure is formed, as shown in fig. 7. The material of the dielectric layer 400 may be any material suitable for pattern transfer. In the present embodiment, the material of the dielectric layer 400 is silicon dioxide.

And transferring the second graph structure to form a graph epitaxial induction structure. Specifically, referring to fig. 8, the block copolymer 500 is filled in the second space of the second pattern structure to form the first protrusion 511, and referring to fig. 9, the second protrusion 411 is removed to form the first space 512. Wherein, optionally, the molecular weight of the block copolymer 500 is from 5000 to 7000 and the Flory Huggins parameter X1 of the block copolymer 500 has a value of from 0.18 to 0.20. Since the molecular weight of the block copolymer 500 and the Flory Huggins parameter X1 have an effect on the micro-phase separation of the block copolymer 500 during the directed self-assembly, which may affect the size of the modified region, the molecular weight and the Flory Huggins parameter X1 within the above ranges are selected to enable the block copolymer 500 to form micro-phase separation with a critical dimension of less than 28nm during the phase separation. In this example, the block copolymer 500 is a diblock copolymer of polystyrene-b-polycarbonate, having a molecular weight of 7000 and a Flory Huggins parameter X1 of 0.19.

S103: filling an inducing layer in the first interval, and carrying out directional self-assembly on the block copolymer forming the first bulges so as to form a plurality of modified regions, wherein the material of the inducing layer is the same as the property of a certain section of copolymer in the block copolymer;

specifically, referring to fig. 10, the first spacer 512 is filled with an inducing layer 600, and the material of the inducing layer 600 has the same property as that of a certain segment of the block copolymer 500. Thus, when the directed self-assembly is performed, the inducing layer 600 can induce a phase-separated structure around the inducing layer, and a copolymer having a property different from that of the inducing layer is formed around the inducing layer. In the present embodiment, the material of the inducing layer 600 is polystyrene.

Referring to fig. 11, the block copolymer 500 forming the first protrusions 511 is directionally self-assembled by the inducing layer 600 to form a plurality of modified regions. Specifically, the block copolymer 500 is annealed to generate self-assembly alignment of the polymer material in the block copolymer 500. The modifying region includes a first modifying region 701 having a first property and a second modifying region 702 having a second property, wherein the first modifying region 701 and the second modifying region 702 have different physicochemical properties. For example, the first property and the second property may each independently comprise a hydrophilic property, a hydrophobic property, a temperature-sensitive property, or an acid-base sensitive property. In this embodiment, the polystyrene-b-polycarbonate is annealed to form modified regions into a first modified region 701 composed of polystyrene and a second modified region 702 composed of polycarbonate. Since the polystyrene-b-polycarbonate used in this example has a small molecular weight and a high value of the Flory Huggins parameter X1, the surface energy of the block copolymer 500 is almost equal to the interfacial energy of the substrate 100 during annealing, and thus, the block copolymer has a good micro-phase separation capability.

S104: and selectively removing part of the modified region in the block copolymer to form a patterned structure, wherein the space size of the patterned structure is the same as that of the first space.

And selectively removing part of the modified region in the block copolymer 500 by adopting a wet etching or dry etching method to form a patterned structure, wherein the etching resistance of the annealed block copolymer is improved, and a regular pattern surface can be formed. In the present embodiment, referring to fig. 12, the second modifying region 702 composed of polycarbonate is selectively removed to form a patterned structure. The patterned structure includes third spaces 802 and third protrusions 801 spaced by the third spaces 802, and the size of the third spaces 802 is the same as that of the first spaces 512. The third spacing 802 is less than 28nm in size. Optionally, the third spacing 802 is between 5nm and 28nm in size. Optionally, the size of the third gap 802 is less than 5nm.

An embodiment of the present invention further provides a patterned structure, and the patterned structure is formed by using the above-mentioned patterning method.

For example, an embodiment of the present invention further provides a semiconductor device, where the semiconductor device has a first metal interconnection layer structure, a Fin structure, or a gate structure, and the first metal interconnection layer structure, the Fin structure, or the gate structure employs the patterned structure, so as to improve a space utilization rate of the semiconductor device.

In summary, the patterning method according to the present invention first forms a graphoepitaxy induction structure with a spacing dimension smaller than 28nm on the surface of the substrate, and performs directional self-assembly on the chimeric copolymer in the graphoepitaxy induction structure on the basis of the graphoepitaxy induction structure, thereby forming a patterned structure with a dimension smaller than 28nm. The patterning structure can be applied to the production of semiconductor devices, and the space utilization rate of the semiconductor devices is improved.

Further, the block copolymer used in the patterning method of the present invention is polystyrene-b-polycarbonate, and the interface energy of the block copolymer at the time of the directed self-assembly is the same as the interface energy of the substrate, and stable micro-phase separation can be achieved without performing a neutralization treatment on the substrate. Therefore, the invention does not need to arrange a neutral layer for changing the surface energy of the substrate, simplifies the process steps and reduces the production cost.

Furthermore, the patterning method firstly forms a first graph structure 'which is not easy to deform, then forms a second graph structure on the basis of the first graph structure', and transfers the second graph structure to form a graph epitaxial induction structure formed by a block copolymer material, so that the invention reduces the etching process of directly etching the graph epitaxial induction structure and the block copolymer as much as possible, and avoids the adverse effect of irregular graphs on small-size processes.

The patterning structure and the semiconductor device are manufactured by the patterning method, and the technical effects are also achieved.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and scope of the present invention as defined in the appended claims.

Claims (15)

1. A patterning method, comprising:

providing a substrate;

forming a graphoepitaxy inducing structure on one surface of the substrate, wherein the graphoepitaxy inducing structure comprises first intervals and first bulges separated by the first intervals, and the material of the first bulges is a block copolymer;

filling an inducing layer in the first interval, and performing directional self-assembly on the block copolymer forming the first bump to form a plurality of modified regions, wherein the inducing layer is made of a material which has the same property with a certain section of copolymer in the block copolymer;

and selectively removing part of the modified region in the block copolymer to form a patterned structure, wherein the interval size of the patterned structure is the same as that of the first interval.

2. The patterning process of claim 1, wherein forming a graphoepitaxy inducing structure on a surface of the substrate, the graphoepitaxy inducing structure including first spaces and first protrusions spaced apart by the first spaces, comprises:

forming a pattern structure on a surface of the substrate by means of nanoimprinting, the pattern structure including first protrusions' spaced apart by first spaces;

filling a dielectric layer in the first interval 'to form a second bulge, and removing the first bulge' to form a second interval;

and filling the block copolymer in the second interval to form a first bump, and removing the second bump to form a first interval.

3. The patterning process of claim 1, wherein the first spacers have a dimension of less than 28nm.

4. The patterning process of claim 1, wherein the first spacers have a size between 5nm and 28nm.

5. The patterning process of claim 1, wherein the first spaces have a dimension of less than 5nm.

6. The patterning process of claim 1, wherein the block copolymer has a molecular weight of 5000 to 7000 and the block copolymer has a Flory Huggins parameter X1 having a value of 0.18 to 0.20.

7. The patterning method of claim 1, wherein directionally self-assembling the block copolymer forming the first protrusions to form a plurality of modified regions comprises:

and annealing the block copolymer to enable the high molecular materials in the block copolymer to generate self-assembled polymerization arrangement.

8. The patterning method according to claim 1, wherein the modified region is formed as a first modified region and a second modified region, and a material of the inducing layer is the same as that of the first modified region or the second modified region.

9. The patterning method according to claim 1, wherein selectively removing a portion of the modified region in the block copolymer to form a patterned structure comprises:

and selectively removing part of the modified region by adopting a wet etching method or a dry etching method.

10. The patterning process of claim 1, wherein the co-block polymer comprises polystyrene-b-polycarbonate.

11. The patterning process of claim 7, wherein the block copolymer is polystyrene-b-polycarbonate, and annealing the block copolymer to produce a self-assembled polymeric arrangement of the polymeric material in the block copolymer comprises:

and annealing the polystyrene-b-polycarbonate to form the modified region into a first modified region composed of polystyrene and a second modified region composed of polycarbonate.

12. The patterning process of claim 11, wherein selectively removing a portion of the modified region in the block copolymer to form a patterned structure comprises:

selectively removing the second modifying region composed of polycarbonate to form the patterned structure.

13. The patterning method according to claim 12, wherein the material of the inducing layer comprises polystyrene.

14. A patterned structure formed by the patterning method according to any one of claims 1 to 13.

15. A semiconductor device having a first metal interconnection layer structure, a Fin structure or a gate structure, wherein the first metal interconnection layer structure, the Fin structure or the gate structure is applied with the patterning structure of claim 14.

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