CN115859902A - Clock tree growing method based on D-tree virtual clock structure - Google Patents
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Abstract
The invention provides a clock tree growing method based on a D-tree virtual clock structure. The method comprises the following steps: step 1: determining the total number M of registers in a target module; step 2: dividing a target module into T register clusters, wherein each register cluster is used as a tail end unit; and step 3: constructing an H-tree clock tree by taking each 4 terminal units as a group; and 4, step 4: evaluating the clock skew, the clock tree length and the clock tree common path length of the current clock tree; and 5: judging whether the current clock tree meets the given clock skew requirement, the clock tree length requirement and the clock tree common path length requirement, if not, executing the step 6; otherwise, executing step 7; step 6: dividing each current tail end unit into 4 register clusters again, taking each register cluster as a new tail end unit, and returning to execute the step 3; and 7: and taking the clock tree at the moment as the final clock tree of the target module.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a clock tree and clock skew compensation technology of a large-scale integrated circuit, and specifically relates to a clock tree growing method based on a D-tree virtual clock structure.
Background
The method for clock tree layout flow in an integrated circuit and the clock tree deviation compensation device disclosed in patent CN109376467A propose to perform reasonable level splitting on the integrated circuit design, design the level after splitting into a hard module, perform data extraction on the internal clock of the hard module, then perform clock tree generation on the top layer, and reduce clock skew by setting a clock deviation device at the root clock of the hard module. The disadvantages of this method are: 1. carrying out secondary difference on the hierarchical module, and forming a hard module by secondary physical design, so that the design time of a project is increased, and the workload of an engineer is increased; 2. sequence checking is performed among all layering modules, and the time sequence among the layers is difficult to converge due to the fact that the layering modules are divided blindly.
The top layer of the traditional physical design can split the design according to functions, and a set of complex clock structure is still arranged in each functional module. For the clock tree structure inside the module, the existing method generally adopts a mode of setting clock constraint to make an EDA tool automatically design, and the clock tree constructed by the method faces several technical problems to be solved as follows: 1. too many memory cells are clocked. These all result in increased levels of clock trees, increased delay of clock trees, increased power consumption, and increased area; 2. due to the clock tree deviation and the OCV influence, the effective time window of time sequence convergence is reduced, and more time and energy are needed for repairing; 3. once the timing result brought by the clock structure automatically generated by the EDA tool is difficult to converge, the digital back-end engineer can only return the design to the place stage before the clock structure is made, modify the clock tree constraint and then redesign the clock tree again, resulting in a large amount of time waste.
Disclosure of Invention
The invention provides a clock tree generation method based on a D-tree virtual clock structure, aiming at the problems of large clock skew, multiple clock tree layers and high power consumption in the existing clock tree generation method.
The invention provides a clock tree growing method based on a D-tree virtual clock structure, which comprises the following steps:
step 1: determining the total number M of registers needing timing sequence check in a target module;
step 2: dividing a target module into T register clusters by taking every N registers as a cluster, wherein each register cluster is taken as an end unit; wherein T = ceil (M/N), ceil representing the rounding-up operation;
and step 3: constructing an H-tree clock tree by taking each 4 terminal units as a group;
and 4, step 4: determining the length of the H-tree clock tree of the nearest layer of the clock port of each trigger, calculating the value of each trigger clock port needing to be adjusted according to the length and clock constraint conditions, and further evaluating the clock skew, the clock tree length and the clock tree common path length of the current clock tree;
and 5: judging whether the current clock tree meets the given clock skew requirement, the clock tree length requirement and the clock tree common path length requirement, if not, executing the step 6; otherwise, executing step 7;
step 6: dividing each current tail end unit into 4 register clusters again, taking each register cluster as a new tail end unit, and returning to execute the step 3;
and 7: and taking the clock tree at the moment as the final clock tree of the target module.
Further, step 3 comprises:
if the number of the tail end units is less than 4, virtualizing the lacking tail end units, constructing an H-tree clock tree according to the 4 tail end units as a group, and pruning the H-tree clock tree according to the actual distribution condition of the tail end units.
Further, when cluster division is performed, each register cluster obtained after division is square in whole.
The invention has the beneficial effects that:
the invention can construct the mathematical model of the D-tree virtual clock structure based on the H-tree before the formal clock tree is established, thereby effectively reducing the clock tree level, reducing the difficulty of clock tree balance, reducing clock skew, shortening the design period of engineering and reducing the difficulty of time sequence convergence. The invention can accelerate the time sequence convergence period, improve the chip performance and shorten the time for the chip to appear on the market.
Drawings
FIG. 1 is a schematic flow chart of a clock tree growing method based on a D-tree virtual clock structure according to an embodiment of the present invention;
fig. 2 is a schematic diagram of cluster partitioning a target module according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating an H-tree clock tree constructed based on cluster partition results according to an embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating pruning of a clock tree for constructing an H-tree according to actual register distribution according to an embodiment of the present invention;
fig. 5 is a schematic diagram of cluster partitioning a target module again according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions in the embodiments of the present invention will be described clearly below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the clock tree structure designed by the present invention is a clock tree structure capable of selecting iteration times according to the clock skew requirement, the clock tree length requirement and the clock tree common path length requirement, that is, a dynamic clock tree structure, and therefore, is called a D-tree; d represents Dynamic.
As shown in fig. 1, an embodiment of the present invention provides a clock tree growing method based on a D-tree virtual clock structure, including the following steps:
s101: as shown in fig. 2, determining the total number M of registers in the target module that need to be subjected to timing check;
s102: as shown in fig. 2, every N registers are used as a cluster, the target module is divided into T register clusters, and each register cluster is used as an end unit; wherein T = ceil (M/N), ceil representing the rounding-up operation;
s103: as shown in FIG. 3, each 4 terminal units are used as a group to construct an H-tree clock tree, and T is obtained by co-construction 1 = ceil (T/4) H-tree clock trees, the T 1 The H-tree clock tree is the top H-tree clock tree;
specifically, if there is a group of less than 4 end units, the missing end unit is virtualized first, then an H-tree clock tree is constructed according to the group of 4 end units, and finally the H-tree clock tree is pruned according to the actual distribution of the end units, as shown in fig. 4.
It should be noted that the leaf node of the H-tree clock tree should be located at the center of each register cluster, so as to facilitate circuit evaluation.
S104: determining the length of the H-tree clock tree of the nearest layer of the clock port of each trigger, calculating the value of each trigger clock port needing to be adjusted according to the length and clock constraint conditions, and further evaluating the clock skew, the clock tree length and the clock tree common path length of the current clock tree;
s105: judging whether the current clock tree meets the given clock skew requirement, the clock tree length requirement and the clock tree common path length requirement, if not, executing the step S106; otherwise, step S107 is executed;
in particular, high quality clock trees generally require as little clock skew as possible, as short a clock tree length as possible, and as long a clock tree common path as possible.
S106: dividing each current end unit into 4 register clusters again, taking each register cluster as a new end unit, and returning to execute the step S103;
specifically, as shown in fig. 2, the target module is divided for the first time, and each end unit includes N host cellsA storage device; as shown in fig. 5, the end units obtained by the first division are divided again for the second time, and each new end unit comprises N/4 registers; and by analogy, the terminal unit obtained by the t-1 th division is divided again at the t-th time, and each new terminal unit comprises N/4 t -1 A register.
S107: and taking the clock tree at the moment as a final clock tree of the target module, and realizing by adopting an EDA tool.
Example 2
On the basis of the above embodiment, this embodiment explains the clock tree generation method of the encryption module by taking the encryption module with a process of 16nm and a total number of time sequence units of 20 ten thousand as an example, and includes the following steps:
s201: after place, dividing one cluster by 128 time sequence units, wherein the area occupied by each time sequence unit cluster is approximately square; dividing the remaining time sequence units which are less than 128 into a cluster, wherein 1563 clusters are formed in total;
s202: calculating the coordinates of the central point of each time sequence unit cluster;
s203: constructing an H-tree according to the number of the current time sequence unit clusters and the distribution of the clusters;
specifically, it is required that there must be one CLKBUFFV32_9T18L at the center position of each timing cell cluster, the CLKBUFFV32_9T18L being the main driving unit of the clock tree;
s204: trimming an H-tree structure;
specifically, an H-tree structure can be constructed only by 4 time sequence unit clusters; and 1563 divided by 4 equals 390 and 3, which means that there are 3 sequential cell clusters that cannot construct a complete H-tree structure; based on this situation, the last 3 sequential cell clusters can be constructed in an H-tree, and then the clock CLKB FFV32_9T18L without sequential cell locations can be deleted.
S205: dividing the time sequence unit cluster with 128 time sequence units into 4 new time sequence unit clusters, wherein each new time sequence unit cluster has 32 time sequence units; then, an H-tree structure is constructed again for each 4 new timing unit clusters.
Specifically, according to the last time of constructing the H-tree structure, the center point coordinates of each new time sequence unit cluster are still determined, then a CLKB FFV8_9T18L is placed at the center point, and the CLKB FFV8_9T18L buffer is driven by the CLKB FFV32_9T18L on the H-tree.
S206: determining the length of the H-tree clock tree of the closest layer of the clock port of each time sequence unit, and calculating the value of each trigger clock port needing to be adjusted according to the length and clock constraint conditions;
specifically, the CK end coordinates (x 1, y 1) of each time sequence unit in each new time sequence unit cluster obtained in step S205 and the output ZN end coordinates (x 2, y 2) of the CLKBUFFV8_9T18L closest to the CK end are calculated, and the distance between the two coordinates is found as: | x1-x2| + | y1-y2|, CK represents the clock port. Then, according to the Wire Load Mode in the lib library, the capacitance Load under the unit length is obtained through table lookup calculation, and the specific calculation method is as follows: an interconnection line with a fan-out of 32 uses a w120 model in a lib library, and slope is a parameter of different models in the library;
interconnection line length = interconnection line length + corresponding to fan-out 1 (32-1) × slope
Interconnect capacitance = interconnect length x interconnect unit capacitance
Interconnect resistance = length of interconnect line x unit resistance of interconnect line
Estimating the delay on the interconnection line according to net delay = -3R C; r denotes the interconnect resistance, C denotes the interconnect capacitance, and net delay denotes the delay on the interconnect. Wherein "=to" means approximately equal to.
The delay of the timing unit connected to the output ZN of the clkbufffv 8_9T18L is referred to the value of the third row and the third column in the cell _ rise (delay _ template9x 9) model in lib.
Determining the delay net delay on the interconnection line connected behind the output ZN end of the CLKB FFV8_9T18L and the delay of the timing unit connected behind the output ZN end of the CLKB BUFFV8_9T18L as cell delay by the method; and the delay sumx _ delay of each timing unit in the new timing unit cluster reaching the output ZN end of the clkbufffv 8_9T 18L; wherein x =1,2, \8230; \ 8230;, 32.
Then, calculating to obtain the total delay sum _ delay = sum1_ delay + sum2_ delay + sum3_ delay ] of each new time sequence unit cluster reaching the output ZN end of the clkbufffv 8_9T 18L; and further calculating to obtain the average delay average _ delay = sum _ delay/32.
Finally, comparing the submx _ delay and average _ delay of each timing unit, if the average _ delay-submx _ delay is more than 10p, adding a CLKB FFV4_9T18L between the timing unit and the CLKB FFV8_9T18L line; if sumx _ delay-average _ delay > 10p, then specify in the spec file of the interventional clock tree build: the cadence manufacturer's innovus tool is used for clock guidance using a set _ ccopt _ property command in the innovus tool. Such as: set _ ccopt _ property _ inst name/CK inst _ delay | sumx _ delay-average _ delay | to reduce the value of sumx _ delay.
S207: and evaluating the quality of the current D-tree virtual clock tree according to the clock skew requirement, the clock tree length requirement and the clock tree common path length requirement, returning to S203 to reconstruct the virtual sub-clock if the quality of the current D-tree virtual clock tree is not met, and realizing the current D-tree virtual clock through an EDA tool if the quality of the current D-tree virtual clock tree is met.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (3)
1. A clock tree growing method based on a D-tree virtual clock structure is characterized by comprising the following steps:
step 1: determining the total number M of registers needing timing sequence check in a target module;
step 2: dividing a target module into T register clusters by taking every N registers as a cluster, wherein each register cluster is taken as an end unit; wherein T = ceil (M/N), ceil representing the rounding-up operation;
and 3, step 3: constructing an H-tree clock tree by taking each 4 terminal units as a group;
and 4, step 4: determining the length of the H-tree clock tree of the nearest layer of the clock port of each trigger, calculating the value of each trigger clock port needing to be adjusted according to the length and clock constraint conditions, and further evaluating the clock skew, the clock tree length and the clock tree common path length of the current clock tree;
and 5: judging whether the current clock tree meets the given clock skew requirement, the clock tree length requirement and the clock tree common path length requirement, if not, executing the step 6; otherwise, executing step 7;
step 6: dividing each current tail end unit into 4 register clusters again, taking each register cluster as a new tail end unit, and returning to execute the step 3;
and 7: and taking the clock tree at the moment as the final clock tree of the target module.
2. The method as claimed in claim 1, wherein the step 3 comprises:
if the number of the tail end units is less than 4, virtualizing the lacking tail end units, constructing an H-tree clock tree according to the 4 tail end units as a group, and pruning the H-tree clock tree according to the actual distribution condition of the tail end units.
3. The clock tree growing method based on the D-tree virtual clock structure as claimed in claim 1, wherein when the clusters are divided, each register cluster obtained after the division is square as a whole.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040196081A1 (en) * | 2003-04-01 | 2004-10-07 | Sandeep Srinivasan | Minimization of clock skew and clock phase delay in integrated circuits |
| US9135375B1 (en) * | 2012-11-30 | 2015-09-15 | Cadence Design Systems, Inc. | Methods for construction and optimization of a clock tree plan for reduced power consumption |
| CN105138735A (en) * | 2015-07-30 | 2015-12-09 | 中山大学 | Clock tree synthesis method for multi-macrocell multi-clock chip |
| CN105930591A (en) * | 2016-04-26 | 2016-09-07 | 东南大学 | Realization method for register clustering in clock tree synthesis |
| CN106547929A (en) * | 2015-09-16 | 2017-03-29 | 马云利 | A kind of FPGA clock networks design |
| CN112036102A (en) * | 2019-05-15 | 2020-12-04 | 北京兆易创新科技股份有限公司 | Clock control method and device for multi-bit register |
| CN112331243A (en) * | 2020-11-26 | 2021-02-05 | 安徽省东科半导体有限公司 | Logic decoupling method of registers under same clock domain |
| CN114239475A (en) * | 2021-12-17 | 2022-03-25 | 郑州信大华芯信息科技有限公司 | Low-frequency digital-analog mixed module clock structure and scan chain design method |
-
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- 2022-12-26 CN CN202211675082.0A patent/CN115859902B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040196081A1 (en) * | 2003-04-01 | 2004-10-07 | Sandeep Srinivasan | Minimization of clock skew and clock phase delay in integrated circuits |
| US9135375B1 (en) * | 2012-11-30 | 2015-09-15 | Cadence Design Systems, Inc. | Methods for construction and optimization of a clock tree plan for reduced power consumption |
| CN105138735A (en) * | 2015-07-30 | 2015-12-09 | 中山大学 | Clock tree synthesis method for multi-macrocell multi-clock chip |
| CN106547929A (en) * | 2015-09-16 | 2017-03-29 | 马云利 | A kind of FPGA clock networks design |
| CN105930591A (en) * | 2016-04-26 | 2016-09-07 | 东南大学 | Realization method for register clustering in clock tree synthesis |
| CN112036102A (en) * | 2019-05-15 | 2020-12-04 | 北京兆易创新科技股份有限公司 | Clock control method and device for multi-bit register |
| CN112331243A (en) * | 2020-11-26 | 2021-02-05 | 安徽省东科半导体有限公司 | Logic decoupling method of registers under same clock domain |
| CN114239475A (en) * | 2021-12-17 | 2022-03-25 | 郑州信大华芯信息科技有限公司 | Low-frequency digital-analog mixed module clock structure and scan chain design method |
Non-Patent Citations (3)
| Title |
|---|
| S.TAM 等: "Clock generation and distribution for the first IA-64 microprocessor", 《IEEE》, pages 1545 - 1552 * |
| 伍艳春: "一种clock mesh与H-tree混合时钟树设计方法", 《电子技术与软件工程》, no. 06, pages 94 - 96 * |
| 吴江啸: "基于柔性H树的CPU时钟树分析及优化", 《中国优秀硕士论文电子期刊网 信息科技辑》, no. 2, pages 135 - 331 * |
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