CN112036102A - Clock control method and device for multi-bit register - Google Patents
Clock control method and device for multi-bit register Download PDFInfo
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Abstract
The invention discloses a clock control method and a clock control device for a multi-bit register. The method comprises the following steps: grouping the multi-bit registers according to bits to obtain at least two bit groups; and if the target bit group meeting the clock starting condition exists in each bit group, starting a clock corresponding to the target bit group. The method can reduce the power consumption caused by the inversion of the clock signal of the multi-bit register.
Description
Technical Field
The embodiment of the invention relates to the technical field of sequential circuits, in particular to a clock control method and a clock control device for a multi-bit register.
Background
With the rapid development of sequential circuit technology, multi-bit registers are widely used. A multi-bit register, which is a very important type of memory cell in an integrated circuit, is usually composed of flip-flops.
However, when the multi-bit register works, the clock is always in an open state, the clock tree corresponding to the multi-bit register is a huge clock network, and when the clock signal is inverted, a large dynamic power consumption is generated, so that the power consumption of the multi-bit register is increased.
Disclosure of Invention
The embodiment of the invention provides a clock control method and a clock control device for a multi-bit register, which are used for reducing power consumption caused by clock signal inversion of the multi-bit register.
In a first aspect, an embodiment of the present invention provides a method for clocking a multi-bit register, including:
grouping the multi-bit registers according to bits to obtain at least two bit groups;
and if the target bit group meeting the clock starting condition exists in each bit group, starting a clock corresponding to the target bit group.
Optionally, after grouping the multi-bit registers by bit to obtain at least two bit groups, the method further includes:
a corresponding clock is assigned to each of the bit groups.
Optionally, the clock turn-on condition includes: there are data bits to be adjusted in the bit group.
Optionally, the clock control method of the multi-bit register further includes:
when the target bit group finishes the function operation, closing a clock corresponding to the target bit group;
and continuously monitoring whether a target bit group meeting the clock starting condition exists in each bit group.
Optionally, the multi-bit register is a multi-bit counter.
In a second aspect, an embodiment of the present invention provides a clock control apparatus for a multi-bit register, including:
the grouping module is used for grouping the multi-bit registers according to bits to obtain at least two bit groups;
and the starting module is used for starting a clock corresponding to the target bit group if the target bit group meeting the clock starting condition exists in each bit group.
Optionally, the clock control apparatus for a multi-bit register further includes:
the distribution module is used for distributing a corresponding clock for each bit group after grouping the multi-bit register according to bits to obtain at least two bit groups.
Optionally, the starting module is specifically configured to: if a target bit group meeting a clock starting condition exists in each bit group, starting a clock corresponding to the target bit group, wherein the clock starting condition comprises: there are data bits to be adjusted in the bit group.
Optionally, the clock control apparatus for a multi-bit register further includes:
the execution module is used for closing a clock corresponding to the target bit group when the target bit group finishes the function operation;
and continuously monitoring whether a target bit group meeting the clock starting condition exists in each bit group.
Optionally, the multi-bit register is a multi-bit counter.
The embodiment of the invention provides a clock control method and a clock control device for a multi-bit register, which can group the multi-bit register according to bits by utilizing the technical scheme to obtain at least two bit groups; then when each bit group meets the clock starting condition, the corresponding clock is started without starting the clocks of each bit of the multi-bit register. Thereby reducing dynamic power consumption caused by multi-bit register clock signal toggling.
Drawings
Fig. 1 is a schematic flowchart illustrating a clock control method for a multi-bit register according to an embodiment of the present invention;
fig. 2 is a schematic flowchart of a clock control method for a multi-bit register according to a second embodiment of the present invention;
fig. 3 is a schematic structural diagram of a clock control apparatus for a multi-bit register according to a third embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Before discussing exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the operations (or steps) as a sequential process, many of the operations can be performed in parallel, concurrently or simultaneously. In addition, the order of the operations may be re-arranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figure. The processes may correspond to methods, functions, procedures, subroutines, and the like.
Example one
Fig. 1 is a schematic flowchart of a clock control method for a multi-bit register according to an embodiment of the present invention, where the method is applicable to reduce power consumption of the multi-bit register, and in particular, the method is applicable to reduce dynamic power consumption caused by clock inversion of the multi-bit register. The method may be performed by a multi-bit register clocked device, wherein the device may be implemented by software and/or hardware and is typically connected to an integrated circuit, which in this embodiment includes but is not limited to: multi-bit registers, etc.
As shown in fig. 1, a clock control method for a multi-bit register according to an embodiment of the present invention includes the following steps:
s101, grouping the multi-bit registers according to bits to obtain at least two bit groups.
In this embodiment, a register, which is a very important storage unit in an integrated circuit, is usually composed of flip-flops and is used for registering a set of binary codes. The number of flip-flops may determine the number of bits in the register. An N-bit register may be composed of N flip-flops, and accordingly, may be capable of storing a set of N-bit binary codes. A group of bits is understood to be a group formed by grouping the data bits of a multi-bit register.
Before controlling the clock of the multi-bit register, the multi-bit register may be grouped according to bits in this step, and a person skilled in the art may group the multi-bit register according to the function implemented by the multi-bit register without limiting the specific way of grouping the multi-bit register.
Illustratively, the multi-bit register is an 8-bit register, and the function is realized by adding 7, so that the bits 0-2 of the multi-bit register can be divided into one group, namely a low bit group; the 3-7 bits are divided into one group, i.e., the high order group. If the implemented function is plus 15, bits 0-3 of the multi-bit register can be divided into low bit groups and bits 4-7 into high bit groups. As can be seen, based on the partitioning method in this example, the bit groups formed after partitioning include a low bit group and a high bit group.
The number of the bit groups obtained by division is not limited in this step, and those skilled in the art can set the number according to actual situations. In the step, after the multi-bit register is grouped to form at least two bit groups, each bit group can be monitored to determine whether to start the corresponding clock, so that the power consumption caused by the fact that each bit clock is supplied all the time in the working period of the multi-bit register is avoided.
And S102, if a target bit group meeting a clock starting condition exists in each bit group, starting a clock corresponding to the target bit group.
In this embodiment, the clock-on condition may be understood as a condition for determining whether a clock corresponding to each bit group is on. The target bit set may be understood as the bit set to be clocked on. The target bit set may also be understood as the bit set for which the latched data update is to be performed.
The clock-on condition may be used to control the clock state of each bit group. The clock-on condition may not be limited herein, and those skilled in the art may set the condition according to the actual application scenario of the multi-bit register. For example, a person skilled in the art may set the clock-on condition according to the logical relationship between the bit groups, or may set the clock-on condition according to the value latched by the current multi-bit register and the function implemented by the multi-bit register.
After each bit group corresponding to the multi-bit register is obtained, the step can sequentially judge whether a target bit group meeting the clock starting condition exists in each bit group. If yes, the step may start the clock corresponding to the target bit set. The clock corresponding to the target bit group is not limited to be started, and those skilled in the art can select a specific means to implement clock supply according to an actual usage scenario. The supply of the respective bit groups in response to the clock signal is controlled, for example, by means of gates.
In addition, if the multi-bit registers participate in the operation at the same time, the combinational gate circuit is also in a large number of flip states, and thus, the flip of the combinational logic also brings large dynamic power consumption.
The embodiment one of the invention provides a clock control method of a multi-bit register, which can group the multi-bit register according to bits to obtain at least two bit groups; then when each bit group meets the clock starting condition, the corresponding clock is started without starting the clocks of each bit of the multi-bit register. Thereby reducing dynamic power consumption caused by multi-bit register clock signal toggling.
Example two
Fig. 2 is a schematic flow chart of a clock control method for a multi-bit register according to a second embodiment of the present invention, and the present embodiment is optimized based on the foregoing embodiments. In this embodiment, after the grouping the multi-bit registers by bit to obtain at least two bit groups, the optimizing includes: a corresponding clock is assigned to each of the bit groups.
Further, the present embodiment further optimizes the clock turn-on condition as follows: there are data bits to be adjusted in the bit group.
On the basis of the above optimization, the optimization of this embodiment further includes: when the target bit group finishes the function operation, closing a clock corresponding to the target bit group;
and continuously monitoring whether a target bit group meeting the clock starting condition exists in each bit group.
Further, the present embodiment also optimizes the multi-bit register as a multi-bit counter. Please refer to the first embodiment for a detailed description of the present embodiment.
As shown in fig. 2, a clock control method for a multi-bit register according to a second embodiment of the present invention includes the following steps:
s201, grouping the multi-bit registers according to bits to obtain at least two bit groups, wherein the multi-bit registers are multi-bit counters.
In this embodiment, the multi-bit register may be optimized as a multi-bit counter. At least two bit groups can be obtained by grouping the multi-bit counter according to bits, so that each bit group can participate in operation respectively, all bits do not need to participate in operation together, and the power consumption of the multi-bit counter is reduced.
S202, distributing corresponding clocks for the bit groups.
It will be appreciated that in this embodiment, each bit group may be assigned a clock. After the multi-bit registers are grouped according to bits, corresponding clocks can be distributed to each bit group, and each bit group can be controlled by an independent clock, so that the working state of the corresponding bit group can be controlled by controlling the starting state of the clocks, and whether the corresponding bit group is subjected to data latch updating or not can be controlled.
The supply state of each clock may be controlled by a clock control device of the multi-bit register, and the specific manner of control is not limited herein, for example, a gate circuit may be selected by those skilled in the art to control the supply state, i.e., on and off, of each clock.
S203, judging whether a target bit group meeting a clock starting condition exists in each bit group, wherein the clock starting condition comprises the following steps: the data bit to be adjusted exists in the bit group; if yes, executing S204; if not, go to S203.
In this embodiment, the clock-on condition is optimized to the presence of a data bit to be adjusted in the set of bits. The bit group in the clock starting condition can be understood as any one bit group in each bit group obtained by dividing the multi-bit register. The bit group including the data bit to be adjusted can be determined as the target bit group as long as one bit group including the data bit to be adjusted exists in each bit group obtained by dividing the multi-bit register. In this step, the clock corresponding to the target bit set may be started, so that the target bit set updates the latched data.
Judging whether each bit group has a target bit group meeting the clock starting condition, if so, executing S204; otherwise, it may be continuously determined whether there is a target bit set satisfying the clock-on condition in each bit set, that is, S203 is continuously performed.
And S204, starting a clock corresponding to the target bit group.
When the target bit group meeting the clock starting condition exists in each bit group, the step can start the clock corresponding to the target bit group so as to enable the target bit group to complete the functional operation. The functional operation performed by the target byte is not limited, and those skilled in the art can set the functional operation according to the application scenario of the multi-bit register. Such as the multi-bit register functioning as an up counter or a down counter. The corresponding functional operations may be addition or subtraction, and the increased and decreased values may be set according to actual conditions.
S205, judging whether the target bit group executes the function operation, if so, executing S206; if not, go to S205.
After the clock corresponding to the target bit group is started, this step may determine whether the target bit group completes the current functional operation, and here, how to determine whether the target bit group completes the current functional operation is not limited. If the function operation is finished, the operation time can be set to determine whether the target bit group executes the function operation; and the specific numerical value of the data latched by the target bit group can be verified to verify whether the execution of the function operation is finished.
When the target bit group finishes the function operation, the subsequent operation can be continuously executed, that is, the step S206 can be executed; when the target byte does not complete the present functional operation, it may continue to monitor whether the target byte completes the present functional operation, i.e. continue to execute S205.
S206, closing the clock corresponding to the target bit group, and continuing to execute S203.
After the target bit group executes the function operation, the clock corresponding to the target bit group can be closed in the step, so that power consumption caused by continuously opening the clock corresponding to the target bit group is reduced.
The specific means for turning off the clock corresponding to the target bit group is not limited herein, and those skilled in the art may select the specific means for turning off the clock according to the actual application scenario, for example, the clock may be controlled to be turned off by a gate circuit.
After the clock corresponding to the target bit group is closed, it may be continuously determined whether a target bit group satisfying the clock opening condition exists in each bit group, that is, S203 may be performed to further determine the subsequent bit group requiring the clock opening.
It is to be understood that the clocking method of the multi-bit register in the present embodiment may be performed all the time during the operation of the multi-bit register. That is, as long as the multi-bit register operates, the present embodiment can always determine whether a target bit set satisfying the clock-on condition exists in each bit set.
For ease of understanding, the present embodiment is described by way of example below:
when the multi-bit register works, a clock is always in an open state, a corresponding clock tree is a huge clock network, great dynamic power consumption can be generated when the clock is turned over, if the multi-bit register simultaneously participates in operation, a great amount of combination gate circuits are also in a turning state, and therefore turning of combination logic can bring great dynamic power consumption. The clock control method for the multi-bit register proposed in this embodiment may be regarded as a low power consumption design method for the multi-bit register, and may include the following steps:
step 1: the multi-bit registers are grouped (two or more) into a multi-bit counter, for example, such as a group of lower 8 bits (where 8 bits are merely for illustrative purposes and do not specify 8 bits), upper bits, and data bits other than the lower 8 bits.
Step 2: the counters in the group share a clock source, for example, the low bit group shares a clock source denoted as CLK _ L, and the high bit group shares a clock source denoted as CLK _ H.
And step 3: each group participates in the operation individually, not all bits together. The low bit group is calculated to be +1, the high bit group does not participate in the operation firstly, the high bit group is separated from the low bit group, the high bit group does not participate in any operation of the low bit group, and when the low bit group generates carry, the high bit group performs one operation of + 1.
And 4, step 4: and processing a clock source CLK _ H of the high bit group, closing the CLK _ H when the high bit group does not need to be operated, opening the CLK _ H once when the low bit group carries out the carry to the high bit group, closing the CLK _ H, and opening the CLK _ H again when waiting for the next carry.
The second clock control method for the multi-bit register provided by the embodiment of the invention embodies the clock starting condition and the multi-bit register, and optimizes the operation of distributing the clock and executing the function. By using the method, the combinational logic quantity and the overturning times of the combinational logic can be reduced, the power consumption of the multi-bit register is reduced, and the use experience of a user is improved.
EXAMPLE III
Fig. 3 is a schematic structural diagram of a clock control apparatus for a multi-bit register according to a third embodiment of the present invention, where the apparatus is suitable for reducing power consumption of the multi-bit register, and in particular, the apparatus is suitable for reducing dynamic power consumption caused by clock inversion of the multi-bit register. Wherein, the apparatus can be implemented by software and/or hardware, when the apparatus is implemented by software, the apparatus can be integrated on a control device, such as an IC chip; when the apparatus is implemented by hardware, the specific hardware is not limited. The function of the clocking means of the multi-bit register can be implemented by gates as is known to those skilled in the art.
As shown in fig. 3, the apparatus includes: a grouping module 31 and an opening module 32;
the grouping module 31 is configured to group the multi-bit registers according to bits to obtain at least two bit groups;
the starting module 32 is configured to start a clock corresponding to a target bit group if the target bit group meeting a clock starting condition exists in each bit group.
In this embodiment, the apparatus firstly groups the multi-bit registers by bit through the grouping module 31 to obtain at least two bit groups; and finally, determining, by the starting module 32, that if a target bit group meeting a clock starting condition exists in each bit group, starting a clock corresponding to the target bit group.
The embodiment provides a clock control device of a multi-bit register, which can group the multi-bit register according to bits to obtain at least two bit groups; then when each bit group meets the clock starting condition, the corresponding clock is started without starting the clocks of each bit of the multi-bit register. Thereby reducing dynamic power consumption caused by multi-bit register clock signal toggling.
Further, the clock control device of the multi-bit register optimizes and comprises the following steps: the distribution module is used for distributing a corresponding clock for each bit group after grouping the multi-bit register according to bits to obtain at least two bit groups.
On the basis of the above optimization, the starting module 32 is specifically configured to: if a target bit group meeting a clock starting condition exists in each bit group, starting a clock corresponding to the target bit group, wherein the clock starting condition comprises: there are data bits to be adjusted in the bit group.
Further, the clock control device of the multi-bit register optimizes and comprises the following steps: the execution module is used for closing a clock corresponding to the target bit group when the target bit group finishes the function operation;
and continuously monitoring whether a target bit group meeting the clock starting condition exists in each bit group.
Based on the technical scheme, the multi-bit register is optimized to be a multi-bit counter.
The clock control device of the multi-bit register can execute the clock control method of the multi-bit register provided by any embodiment of the invention, and has corresponding functional modules and beneficial effects of the execution method.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A method of clocking a multi-bit register, comprising:
grouping the multi-bit registers according to bits to obtain at least two bit groups;
and if the target bit group meeting the clock starting condition exists in each bit group, starting a clock corresponding to the target bit group.
2. The method of claim 1, wherein after said bitwise grouping of the multi-bit registers into at least two groups of bits, further comprising:
a corresponding clock is assigned to each of the bit groups.
3. The method of claim 1, wherein the clock-on condition comprises: there are data bits to be adjusted in the bit group.
4. The method of claim 1, further comprising:
when the target bit group finishes the function operation, closing a clock corresponding to the target bit group;
and continuously monitoring whether a target bit group meeting the clock starting condition exists in each bit group.
5. The method of any of claims 1-4, wherein the multi-bit register is a multi-bit counter.
6. An apparatus for clocking a multi-bit register, comprising:
the grouping module is used for grouping the multi-bit registers according to bits to obtain at least two bit groups;
and the starting module is used for starting a clock corresponding to the target bit group if the target bit group meeting the clock starting condition exists in each bit group.
7. The apparatus of claim 6, further comprising:
the distribution module is used for distributing a corresponding clock for each bit group after grouping the multi-bit register according to bits to obtain at least two bit groups.
8. The apparatus according to claim 6, wherein the opening module is specifically configured to: if a target bit group meeting a clock starting condition exists in each bit group, starting a clock corresponding to the target bit group, wherein the clock starting condition comprises: there are data bits to be adjusted in the bit group.
9. The apparatus of claim 6, further comprising:
the execution module is used for closing a clock corresponding to the target bit group when the target bit group finishes the function operation;
and continuously monitoring whether a target bit group meeting the clock starting condition exists in each bit group.
10. The apparatus of any of claims 6-9, wherein the multi-bit register is a multi-bit counter.
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| CN117274844A (en) * | 2023-11-16 | 2023-12-22 | 山东科技大学 | Rapid extraction method for field peanut seedling emergence condition by using unmanned aerial vehicle remote sensing image |
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| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Address after: Room 101, Floor 1-5, Building 8, Yard 9, Fenghao East Road, Haidian District, Beijing 100094 Applicant after: Zhaoyi Innovation Technology Group Co.,Ltd. Address before: 100083 12 Floors, Block A, Tiangong Building, Science and Technology University, 30 College Road, Haidian District, Beijing Applicant before: GIGADEVICE SEMICONDUCTOR(BEIJING) Inc. |