CN115858446B - Method, device and system for serial peripheral interface bus data transmission - Google Patents
Method, device and system for serial peripheral interface bus data transmission Download PDFInfo
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Abstract
The application relates to the technical field of data transmission, and discloses a method for serial peripheral interface bus data transmission, which comprises the following steps: obtaining an actual path delay of the serial peripheral interface bus data transmission; under the condition that the actual path delay is larger than the preset path delay, obtaining a clock frequency division parameter; and adjusting the duty ratio and the sampling time of data transmission according to the clock frequency division parameters. And detecting the actual path delay of the serial peripheral interface bus data transmission, and adjusting the duty ratio and the sampling time of the data transmission according to the clock frequency division parameter when the actual path delay is larger than the preset path delay. Therefore, when the data transmission rate of the serial peripheral interface SPI is higher, the influence caused by path delay is reduced by adjusting the duty ratio and the sampling time of data transmission, and the sampling accuracy can be obviously improved. The application also discloses a device and a system for serial peripheral interface bus data transmission.
Description
Technical Field
The present invention relates to the field of data transmission technologies, and for example, to a method, an apparatus, and a system for serial peripheral interface bus data transmission.
Background
A serial peripheral interface (serial peripheral interface, SPI), an 8-bit data register in a Master (SPI Master) and an 8-bit data register in a Slave (SPI Slave) are connected by a Master-to-Slave data line (masteroutput Slave input, MOSI) and a Slave-to-Master data line (masteroutput Slave input, MISO) to form a 16-bit data register. When the 16-bit register performs data transmission operation, the data of the registers in the Master and Slave are exchanged by serially shifting 8bits according to a clock Signal (SCLK) provided by the Master, and a communication process is completed. In the related art, the data transmission rate of the SPI is increased by increasing the frequency of the clock Signal (SCLK) of the SPI.
In the process of implementing the embodiments of the present disclosure, it is found that at least the following problems exist in the related art:
when the data transmission rate of the serial peripheral interface SPI is high, sampling inaccuracy is easily caused.
It should be noted that the information disclosed in the foregoing background section is only for enhancing understanding of the background of the present application and thus may include information that does not form the prior art that is already known to those of ordinary skill in the art.
Disclosure of Invention
The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview, and is intended to neither identify key/critical elements nor delineate the scope of such embodiments, but is intended as a prelude to the more detailed description that follows.
The embodiment of the disclosure provides a method, a device and a system for data transmission of a serial peripheral interface bus, so as to improve sampling accuracy of a serial peripheral interface SPI when a data transmission rate is high.
In some embodiments, a method for serial peripheral interface bus data transfer includes: obtaining an actual path delay of the serial peripheral interface bus data transmission; under the condition that the actual path delay is larger than the preset path delay, obtaining a clock frequency division parameter; and adjusting the duty ratio and the sampling time of data transmission according to the clock frequency division parameters.
In some embodiments, an apparatus for serial peripheral interface bus data transfer includes: a processor and a memory storing program instructions, the processor being configured to perform the aforementioned method for serial peripheral interface bus data transfer when executing the program instructions.
In some embodiments, a system for serial peripheral interface bus data transfer includes a data input module, a data cache module, a data output module, a peripheral bus interface module, and a conditioning module, wherein: the data input module is configured to receive data; the data caching module is electrically connected with the data input module and is configured to cache data; the data output module is electrically connected with the data cache module and is configured to output data; the peripheral bus interface module is electrically connected with the data input module, the data cache module and the data output module and is configured to provide clocks for the data input module, the data cache module and the data output module; the adjusting module is electrically connected with the peripheral bus interface module and comprises the device for transmitting the serial peripheral interface bus data.
The method, the device and the system for transmitting the serial peripheral interface bus data provided by the embodiment of the disclosure can realize the following technical effects:
in the technical scheme of the disclosure, the actual path delay of the serial peripheral interface bus data transmission is detected, and when the actual path delay is greater than the preset path delay, the duty ratio and the sampling time of the data transmission are adjusted according to the clock frequency division parameter. Therefore, when the data transmission rate of the serial peripheral interface SPI is higher, the influence caused by path delay is reduced by adjusting the duty ratio and the sampling time of data transmission, and the sampling accuracy can be obviously improved.
The foregoing general description and the following description are exemplary and explanatory only and are not restrictive of the application.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which like reference numerals refer to similar elements, and in which:
FIG. 1 is a flow chart of a method for serial peripheral interface bus data transfer provided by an embodiment of the present disclosure;
FIG. 2 is a flow chart of another method for serial peripheral interface bus data transfer provided by an embodiment of the present disclosure;
FIG. 3 is a flow chart of another method for serial peripheral interface bus data transfer provided by an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of sampling instants for a serial peripheral interface bus data transfer provided by an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of sampling instants for another serial peripheral interface bus data transfer provided by an embodiment of the present disclosure;
FIG. 6 is a schematic diagram of sampling instants for another serial peripheral interface bus data transfer provided by an embodiment of the present disclosure;
FIG. 7 is a timing diagram of a serial peripheral interface bus data transfer provided by an embodiment of the present disclosure;
FIG. 8 is a schematic diagram of a serial peripheral interface bus data shift request state switch provided by an embodiment of the present disclosure;
FIG. 9 is a schematic diagram of an apparatus for serial peripheral interface bus data transfer provided in accordance with an embodiment of the present disclosure;
FIG. 10 is a schematic diagram of a system for serial peripheral interface bus data transfer provided in accordance with an embodiment of the present disclosure;
fig. 11 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure.
Detailed Description
So that the manner in which the features and techniques of the disclosed embodiments can be understood in more detail, a more particular description of the embodiments of the disclosure, briefly summarized below, may be had by reference to the appended drawings, which are not intended to be limiting of the embodiments of the disclosure. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may still be practiced without these details. In other instances, well-known structures and devices may be shown simplified in order to simplify the drawing.
The terms first, second and the like in the description and in the claims of the embodiments of the disclosure and in the above-described figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe embodiments of the present disclosure. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion.
The term "plurality" means two or more, unless otherwise indicated. In the embodiment of the present disclosure, the character "/" indicates that the front and rear objects are an or relationship. For example, A/B represents: a or B. The term "and/or" is an associative relationship that describes an object, meaning that there may be three relationships. For example, a and/or B, represent: a or B, or, A and B. The term "corresponding" may refer to an association or binding relationship, and the correspondence between a and B refers to an association or binding relationship between a and B.
The maximum clock frequency of the serial peripheral interface SPI is typically divided by the PLL (Phase Locked Loop, phase locked loop or phase locked loop) of the chip. The PLL clock is typically 200-300M. Since the CPU configures a shift register (shift register) to shift data into or out of an internal buffer (SPI buffer) according to the SPI CLOCK, the SPI CLOCK is generally obtained by dividing the bus CLOCK when data is transmitted through the SPI data line. There are four basic transmission timings for SPI, depending on the combination of clock polarity CPOL and clock phase CPHA, for example, when cpol=0, cpha=0, the data is sampled at the first transition edge. When the data transmission rate of the SPI is high, the data is inaccurate in sampling due to path delay when the data is input and output. According to the embodiment of the disclosure, the influence caused by path delay can be reduced by adjusting the clock duty ratio and the sampling time, and the accuracy of data sampling is obviously improved.
Referring to fig. 1, an embodiment of the present disclosure provides a method for serial peripheral interface bus data transmission, including the steps of:
s101, obtaining the actual path delay of the serial peripheral interface bus data transmission.
Path delay, also called path time, refers to the time it takes for a signal to travel from a start outage to a termination endpoint. In practical application, the actual path delay of serial peripheral interface SPI data transmission is obtained.
S102, obtaining a clock frequency division parameter under the condition that the actual path delay is larger than the preset path delay.
The preset path delay may be a path delay where the data samples tested under the higher baud rate communication are more accurate. With this path delay, the sampling error rate of the data transmission is within an acceptable range. When the acquired actual path delay is larger than the preset path delay, acquiring a clock frequency division parameter, and adjusting the duty ratio and the sampling time of data transmission to improve the accuracy of data sampling.
Here, the clock division parameters include a first clock division parameter, a second clock division parameter, and a third clock division parameter. The first clock division parameter, the second clock division parameter and the third clock division parameter define a sampling period, wherein the first clock division parameter defines a synchronous segment of the sampling period, the second clock division parameter defines a propagation segment of the sampling period, and the third clock division parameter defines a buffer segment of the sampling period.
S103, the duty ratio and the sampling time of data transmission are adjusted according to the clock frequency division parameters.
Optionally, adjusting the duty cycle of the data transmission according to the clock division parameter includes calculating the duty cycle according to the following formula:
S=EconA/(EconB+EconC)
wherein S is the duty cycle, econA is the first clock frequency division parameter, econB is the second clock frequency division parameter, and EconC is the third clock frequency division parameter.
Referring to fig. 4, when the first clock dividing parameter EconA is equal to the sum of the second clock dividing parameter EconB and the third clock dividing parameter EconC, that is, econa=econb+econc, the duty ratio of the data transmission sampling clock is 50%. In practical applications, those skilled in the art may also adjust the duty cycle of the data transmission sampling clock according to the actual requirements, which is not limited herein.
Optionally, adjusting the sampling time of the data transmission according to the clock division parameter includes: determining a first sampling period according to a first clock division parameter; determining a second sampling period according to the second clock frequency dividing parameter and the third clock frequency dividing parameter; wherein the second sampling period is located after the first sampling period; the control sampling instant is within the second sampling period.
As shown in connection with fig. 4, when econa=4, econb=0, econc=3, the synchronization period t is set Q Sampling is carried out after the end; when econa=2, econb=0, econc=2, in the synchronization period t Q Sampling is carried out after the end; when econa=4, econb=1, econc=3, in the synchronization period t Q Sampling after the ending first time period; when econa=3, econb=3, econc=1, in the synchronization period t Q Sampling after the third time period is finished; when econa=1, econb=0, econc=1, in the synchronization period t Q Sampling is performed after the end.
In practical application, as shown in fig. 5, the sampling time of the original data transmission is located at the initial stage of each sampling period. After adjusting the sampling time of the data transmission, as shown in fig. 6, the sampling time of the data transmission is located after the first sampling period and within the second sampling period, that is, after the first clock dividing parameter EconA and between the second clock dividing parameter EconB and the third clock dividing parameter EconC. Wherein SCLKO is the interface clock; the MTSR is also called MOSI, and is a data line (output data) output from the master to the slave; MRST is also called MISO, which is a data line (output data) output from slave to master; SLSO is a chip select signal.
By adopting the method for serial peripheral interface bus data transmission provided by the embodiment of the disclosure, the actual path delay of the serial peripheral interface bus data transmission is detected, and when the actual path delay is greater than the preset path delay, the duty ratio and the sampling time of the data transmission are adjusted according to the clock frequency division parameter. Therefore, when the data transmission rate of the serial peripheral interface SPI is higher, the influence caused by path delay is reduced by adjusting the duty ratio and the sampling time of data transmission, and the sampling accuracy can be obviously improved.
Referring to fig. 2, an embodiment of the present disclosure provides a method for serial peripheral interface bus data transmission, in which a manner of determining a clock dividing parameter includes the steps of:
s201, a desired data transmission rate of data transmission is obtained.
S202, determining clock frequency division parameters according to the expected data transmission rate.
Optionally, determining the clock division parameter based on the desired data transfer rate includes calculating the first clock division parameter, the second clock division parameter, and the third clock division parameter according to the following formula:
EconA+EconB+EconC=fper/((GlobalconTQ+1)×(EconQ+1)×BR)-1
that is, econA+EconB+EconC+1=fper/((GlobalconTQ+1) × (EconQ+1) ×BR).
Wherein EconA is a first clock frequency dividing parameter, econB is a second clock frequency dividing parameter, econC is a third clock frequency dividing parameter, globalconTQ is a global clock frequency dividing unit, econQ is a clock frequency dividing quantum unit, fper is a shift clock, BR is a desired data transmission rate.
In practical application, (EconA+EconB+EconC+1) × (EconQ+1) > 4. According to the above formula, the first clock frequency dividing parameter EconA, the second clock frequency dividing parameter EconB, and the third clock frequency dividing parameter EconC may be determined according to the values of the duty ratios determined based on the first clock frequency dividing parameter EconA, the second clock frequency dividing parameter EconB, and the third clock frequency dividing parameter EconC.
In the embodiment of the disclosure, the clock frequency dividing parameter is determined according to the expected data transmission rate, and the data transmission rate can be controlled in the data transmission rate range meeting the actual data transmission requirement while the data sampling accuracy is improved by adjusting the duty ratio and the sampling time of the data sampling according to the clock frequency dividing parameter, so that the greater influence on the sampling accuracy caused by overhigh data transmission baud rate is avoided.
As shown in connection with fig. 3, an embodiment of the present disclosure provides a method for serial peripheral interface bus data transmission, comprising the steps of:
s301, obtaining the actual path delay of the serial peripheral interface bus data transmission.
S302, obtaining a clock frequency division parameter under the condition that the actual path delay is larger than the preset path delay.
S303, the duty ratio and the sampling time of data transmission are adjusted according to the clock frequency division parameters.
S304, obtaining real-time data transmission progress of the data transmission.
Here, the real-time data transmission progress includes a buffer data length and a transmission data function status. The buffer data length, i.e., the number of buffer data, for example, the number of buffer data is 2, and the buffer data length is set to 2; the transmit data function state includes on or off.
S305, switching the current data shift request state according to the real-time data transmission progress.
As shown in connection with fig. 7, the DATA shift request states include a WAIT (WAIT) state, an IDLE (IDLE) state, a DATA preamble (LEAD) state, a DATA transfer (DATA) state, a trace delay (TRAIL) state, and a timeout detection (exit) state.
WAIT (WAIT) state: waiting to write to the Tx FIFO is a phase that is not well-defined and therefore does not reserve the user-adjusted interface.
IDLE (IDLE) state: the clock line polarity is changed at the time when the LDLEA ends and the LDLEB starts.
Data preamble (LEAD) state: in the data preparation state, after the chip select signal is pulled down, the leading stage is immediately entered, and the delay time of the LEAD is configured by the user configuration of the LEAD and the LPRE of the BACON register. After the delay time is over, the SCLK clock arrives and sampling is started.
DATA transfer (DATA) state: the chip select signal is pulled down, the data is shifted according to the polarity change of the clock line, and the data transmission is completed.
Tracking delay (TRAIL) state: and after the transmission of one 8bits or 32bits data is finished, entering a TRAIL state, and waiting for the arrival of the next data. If the configured data is not sent completely, the stage configures the delay time by the user configuring TRAIL and TPRE of the BACON register.
Timeout detection (extract) state: when the shift data is used in the long data mode or in the continuous mode, after one data transmission is finished, the chip select line is not pulled up, and the shift data starts to enter the EXPECT stage and waits for the next shift data. The delay is determined by a user configuration register GLOBALCON. EXPECT, and when the waiting time exceeds the EXPECT time, an error interrupt is generated and is handed to the CPU for processing.
Optionally, switching the current data shift request state according to the real-time data transmission progress includes: under the condition that the length of the cached data reaches the idle length, switching the current data shift request state to a data preamble state; under the condition that the buffer data length reaches the transmission length, switching the current data shift request state to a data transmission state; wherein the transmission length is greater than the idle length.
Optionally, switching the current data shift request state according to the real-time data transmission progress includes: switching the current data shift request state to a pause state under the condition that the buffer data length reaches the delay length and the data transmission function state is closed; and under the condition that the length of the cached data reaches the delay length and the data transmission function state is started, switching the current data shift request state to the waiting state.
In practical application, as shown in fig. 8, the data transmission state of the serial peripheral interface SPI is switched as follows:
in the case that the current data shift request state of the SPI is the PAUSE state: when the SPI module is enabled and configured into a main mode, the current data shift request state is switched to a WAIT state; when the SPI module is enabled, the slave mode is configured, and the chip select signal is in an active state, the current data shift request state is switched to a slave SLAVES state.
In the case that the current data shift request state of the SPI is the WAIT state: when the phase compensation FIFO register TXFIFO is not empty, switching the current data shift request state to the data preamble IDLEA state; when the TXFIFO is empty, the current data shift request state is kept in a WAIT state.
In the case that the current data shift request state of the SPI is the idle IDLEA state: when the buffer data length reaches the configured IDLE IDLE length, switching the current data shift request state to an IDLE IDLEB state; when the buffered data length does not reach the configured idle length, the current data shift request state is maintained as an idle IDLEA state.
In the case that the current data shift request state of the SPI is the idle IDLEB state: when the buffer data length reaches the configured IDLE IDLE length and the delay delayed mode is started, switching the current data shift request state to a data preamble IEADS state; and when the buffer data length reaches the configured IDLE IDLE length and the delay delayed mode is started, switching the current data shift request state to the data preamble IEAD state.
In the case that the current data shift request state of the SPI is the data preamble state: when the buffer data length reaches the configured preparation STROBE length, switching the current data shift request state to a data preamble IEAD state; when the buffered data length does not reach the configured ready length, the current data shift request state is maintained as the data preamble IEADS state.
In the case where the current data shift request state of the SPI is the data preamble LEAD state: when the buffer DATA length reaches the configured LEAD length, switching the current DATA shift request state to a DATA transmission DATA state; when the buffered data length does not reach the configured preamble LEAD length, the current data shift request state is maintained as the data preamble LEAD state.
In the case of the current DATA shift request state of the SPI being the DATA transfer DATA state: when the buffer DATA length reaches the configured transmission DATA length and the DATA transmission is completed, switching the current DATA shift request state to a tracking delay TRAIL state; when the buffered DATA length does not reach the configured transmission DATA length and the TXFIFO is empty, the current DATA shift request state is switched to the timeout detection exit state.
In the case that the current data shift request state of the SPI is the trace delay TRAIL state: when the buffer data length reaches the configured delay TRAIL length, the buffer data length is reduced to 0 in the end of the frame or in the point-to-point MC mode, and the delay mode is started, the current data shift request state is switched to the tracking delay TRAILS state; when the buffer data length reaches the configured delay TRAIL length, the buffer data length is reduced to 0 in the end of the frame or in the point-to-point MC mode, and the delay mode is closed and the data transmission function state is opened, the current data shift request state is switched to the WAIT state; when the buffer data length reaches the configured delay TRAIL length, the buffer data length is reduced to 0 in the end of the frame or in the point-to-point MC mode, and the delay mode is closed and the data transmission function state is closed, the current data shift request state is switched to the PAUSE state; when the buffer data length reaches the configured delay TRAIL length, the buffer data length is reduced to 0 in the end of frame or point-to-point MC mode, and the TXFIFO is not empty, the current data shift request state is switched to the data transmission DATAT state; when the buffer data length reaches the configured delay TRAIL length, the buffer data length is decremented to 0 in the end of frame or point-to-point MC mode, and the TXFIFO is empty, the current data shift request state is switched to the timeout detection EXPECT state.
In the case that the current data shift request state of the SPI is the trace delay state: when the buffer data length reaches the configured delay length and the data transmission function state is closed, switching the current data shift request state to a PAUSE state; and when the buffer data length reaches the configured delay TRAILS length and the data transmission function state is started, switching the current data shift request state to the WAIT state.
In the case where the current data shift request state of the SPI is the slave status: when the slave chip selection is invalid or the data transmission function state is closed, switching the current data shift request state to a PAUSE state; when the SLAVE chip selection is valid, the transmit data function state is on, and a SLAVE clock rising edge is detected, the current data shift request state is switched to the SLAVE SLAVE state.
In the case that the current data shift request state of the SPI is the SLAVE state: when the slave chip selection is invalid, the current data shift request state is switched to a PAUSE state; when the slave chip selection is effective and the buffer DATA length reaches the configured transmission DATA length, switching the current DATA shift request state to a slave SLAVES state; when the SLAVE chip selection is valid and the buffered DATA length does not reach the configured transmission DATA length, the current DATA shift request state is maintained as the SLAVE SLAVE state.
By adopting the method for data transmission of the serial peripheral interface bus, which is provided by the embodiment of the invention, when the data transmission rate of the serial peripheral interface SPI (bus) is higher, the influence caused by path delay is reduced by adjusting the duty ratio and the sampling time of the serial peripheral interface bus data transmission, and the sampling accuracy can be obviously improved; meanwhile, the current data shift request state is switched according to the real-time data transmission progress of SPI data transmission, so that the data transmission can be completed in time, the data congestion can be effectively avoided, and the data transmission rate can be improved.
As shown in connection with fig. 9, an embodiment of the present disclosure provides an apparatus for serial peripheral interface bus data transfer, including a processor (processor) 90 and a memory (memory) 91, and may further include a communication interface (Communication Interface) 92 and a bus 93. The processor 90, the communication interface 92, and the memory 91 may communicate with each other via a bus 93. The communication interface 92 may be used for information transfer. The processor 90 may invoke logic instructions in the memory 91 to perform the method for serial peripheral interface bus data transfer of the above-described embodiments.
Further, the logic instructions in the memory 91 may be implemented in the form of software functional units and may be stored in a computer readable storage medium when sold or used as a separate product.
The memory 91 is a computer readable storage medium, and may be used to store a software program, a computer executable program, such as program instructions/modules corresponding to the methods in the embodiments of the present disclosure. The processor 90 performs functional applications and data processing by executing program instructions/modules stored in the memory 91, i.e. implements the method for serial peripheral interface bus data transfer in the method embodiments described above.
The memory 91 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, at least one application program required for functions; the storage data area may store data created according to the use of the terminal device, etc. In addition, the memory 91 may include a high-speed random access memory, and may also include a nonvolatile memory.
By adopting the device for serial peripheral interface bus data transmission provided by the embodiment of the disclosure, the actual path delay of the serial peripheral interface bus data transmission is detected, and when the actual path delay is greater than the preset path delay, the duty ratio and the sampling time of the data transmission are adjusted according to the clock frequency division parameter. Therefore, when the data transmission rate of the serial peripheral interface SPI is higher, the influence caused by path delay is reduced by adjusting the duty ratio and the sampling time of data transmission, and the sampling accuracy can be obviously improved.
As shown in conjunction with fig. 10, an embodiment of the present disclosure provides a system for serial peripheral interface bus data transmission, including a data input module 1001, a data buffer module 1002, a data output module 1003, a peripheral bus interface module 1004, and a conditioning module 1005, wherein: the data input module 1001 is configured to receive data; the data buffer module 1002 is electrically connected to the data input module 1001 and configured to buffer data; the data output module 1003 is electrically connected with the data buffer module 1002 and configured to output data; the peripheral bus interface module 1004 is electrically connected to the data input module 1001, the data buffer module 1002, and the data output module 1003, and configured to provide clocks to the data input module 1001, the data buffer module 1002, and the data output module 1003; the adjustment module 1005, electrically connected to the peripheral bus interface module 1004, includes the above-mentioned means for serial peripheral interface bus data transmission.
The data input module 1001 and the data output module 1003 include a master-to-slave MISO, a slave-to-master MOSI, a chip select, and a clock channel for performing with an external device. For the SPI in the embodiments of the present disclosure, when the SPI is the master, simultaneous control of 16 slaves is supported; when the SPI is used as a slave, 7 input devices are supported to be mounted simultaneously. The SPI can automatically control the multi-path slave chip selection, and the chip selection signals are automatically switched through the configuration of the write queue.
The data buffer module 1002 is configured to buffer temporary data and store the data into a FIFO (First in first out ) register, thereby completing data exchange. The data bit width may be configured as 2-32bits or 2-32bytes. In the main mode, a user can realize various data formats and delay control by writing different configurations. At the same time, the FIFO supports configuring different modes to trigger DMA (Direct Memory Access ) or interrupts to enable data transfer.
The peripheral bus interface module 1004 provides clocks for the data input module 1001, the data buffer module 1002, and the data output module 1003. The data buffer module 1002 is synchronized with the peripheral PLL clock, which can be up to 300M, and frequency division is implemented by a frequency division register in the user interface of the SPI, and finally clocks the SPI data shift.
The adjustment module 1005 is built with a 4-bit Tx FIFO (phase compensation FIFO) and an Rx FIFO (clock compensation FIFO) for data buffering during duplex communication, and further includes the aforementioned means for serial peripheral interface bus data transmission for configuring a data transmission mode and performing timing control.
As shown in connection with fig. 11, embodiments of the present disclosure provide an electronic device (e.g., computer, server, etc.) comprising an electronic device body 1100; and the above-described apparatus 900 for serial peripheral interface bus data transmission is mounted to the electronic device main body 1100.
Embodiments of the present disclosure provide a computer readable storage medium storing computer executable instructions configured to perform the above-described method for serial peripheral interface bus data transfer.
The disclosed embodiments provide a computer program product comprising a computer program stored on a computer readable storage medium, the computer program comprising program instructions which, when executed by a computer, cause the computer to perform the above-described method for testing alarm sensor limit parameters.
The computer readable storage medium may be a transitory computer readable storage medium or a non-transitory computer readable storage medium.
Embodiments of the present disclosure may be embodied in a software product stored on a storage medium, including one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of a method according to embodiments of the present disclosure. And the aforementioned storage medium may be a non-transitory storage medium including: a plurality of media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or a transitory storage medium.
The above description and the drawings illustrate embodiments of the disclosure sufficiently to enable those skilled in the art to practice them. Other embodiments may involve structural, logical, electrical, process, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in, or substituted for, those of others. The scope of the embodiments of the present disclosure encompasses the full ambit of the claims, as well as all available equivalents of the claims. When used in this application, although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without changing the meaning of the description, so long as all occurrences of the "first element" are renamed consistently and all occurrences of the "second element" are renamed consistently. The first element and the second element are both elements, but may not be the same element. Moreover, the terminology used in the present application is for the purpose of describing embodiments only and is not intended to limit the claims. As used in the description of the embodiments and the claims, the singular forms "a," "an," and "the" (the) are intended to include the plural forms as well, unless the context clearly indicates otherwise. Similarly, the term "and/or" as used in this application is meant to encompass any and all possible combinations of one or more of the associated listed. Furthermore, when used in this application, the terms "comprises," "comprising," and/or "includes," and variations thereof, mean that the stated features, integers, steps, operations, elements, and/or components are present, but that the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof is not precluded. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method or apparatus comprising such elements. In this context, each embodiment may be described with emphasis on the differences from the other embodiments, and the same similar parts between the various embodiments may be referred to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method sections disclosed in the embodiments, the description of the method sections may be referred to for relevance.
Those of skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. The skilled artisan may use different methods for each particular application to achieve the described functionality, but such implementation should not be considered to be beyond the scope of the embodiments of the present disclosure. It will be clearly understood by those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein.
In the embodiments disclosed herein, the disclosed methods, articles of manufacture (including but not limited to devices, apparatuses, etc.) may be practiced in other ways. For example, the apparatus embodiments described above are merely illustrative, and for example, the division of the units may be merely a logical function division, and there may be additional divisions when actually implemented, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. In addition, the coupling or direct coupling or communication connection shown or discussed with each other may be through some interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form. The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to implement the present embodiment. In addition, each functional unit in the embodiments of the present disclosure may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. In the description corresponding to the flowcharts and block diagrams in the figures, operations or steps corresponding to different blocks may also occur in different orders than that disclosed in the description, and sometimes no specific order exists between different operations or steps. For example, two consecutive operations or steps may actually be performed substantially in parallel, they may sometimes be performed in reverse order, which may be dependent on the functions involved. Each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
Claims (6)
1. A method for serial peripheral interface bus data transfer, comprising:
obtaining an actual path delay of the serial peripheral interface bus data transmission;
obtaining a clock frequency division parameter under the condition that the actual path delay is larger than a preset path delay;
adjusting the duty ratio and sampling time of data transmission according to the clock frequency division parameters;
the clock frequency dividing parameters comprise a first clock frequency dividing parameter, a second clock frequency dividing parameter and a third clock frequency dividing parameter; adjusting the duty cycle of the data transmission according to the clock division parameter, including calculating the duty cycle according to the following formula: s=econa/(econb+econc), where S is the duty cycle, econA is the first clock division parameter, econB is the second clock division parameter, and EconC is the third clock division parameter;
adjusting the sampling time of the data transmission according to the clock frequency division parameter comprises the following steps: determining a first sampling period according to the first clock division parameter; determining a second sampling period according to the second clock division parameter and the third clock division parameter; wherein the second sampling period is located after the first sampling period; controlling the sampling moment to be in the second sampling period;
the clock divide parameter is determined as follows: obtaining a desired data transmission rate for the data transmission; determining the clock frequency division parameter according to the expected data transmission rate; the determining the clock division parameter according to the desired data transmission rate includes calculating the first clock division parameter, the second clock division parameter, and the third clock division parameter according to the following formula: econA+EconB+EconC=fper/((GlobalconTQ+1) × (EconQ+1) ×BR) -1, where EconA is the first clock dividing parameter, econB is the second clock dividing parameter, econC is the third clock dividing parameter, globalconTQ is the global clock dividing unit, econQ is the clock dividing quantum unit, fper is the shift clock, BR is the desired data transfer rate.
2. The method as recited in claim 1, further comprising:
acquiring real-time data transmission progress of data transmission;
and switching the current data shift request state according to the real-time data transmission progress.
3. The method of claim 2, wherein the real-time data transmission progress comprises a buffered data length; the switching the current data shift request state according to the real-time data transmission progress comprises the following steps:
switching the current data shift request state to a data preamble state under the condition that the buffer data length reaches an idle length;
switching the current data shift request state to a data transmission state under the condition that the buffer data length reaches a transmission length;
wherein the transmission length is greater than the idle length.
4. The method of claim 2, wherein the real-time data transmission progress comprises a buffered data length and a transmission data function status; the switching the current data shift request state according to the real-time data transmission progress comprises the following steps:
when the buffer data length reaches the delay length and the data transmission function state is closed, switching the current data shift request state to a pause state;
and under the condition that the buffer data length reaches the delay length and the data transmission function state is started, switching the current data shift request state to a waiting state.
5. An apparatus for serial peripheral interface bus data transfer comprising a processor and a memory storing program instructions, wherein the processor is configured, when executing the program instructions, to perform the method for serial peripheral interface bus data transfer of any of claims 1 to 4.
6. A system for serial peripheral interface bus data transfer, comprising:
a data input module configured to receive data;
the data caching module is electrically connected with the data input module and is configured to cache data;
the data output module is electrically connected with the data caching module and is configured to output data;
the peripheral bus interface module is electrically connected with the data input module, the data cache module and the data output module and is configured to provide clocks for the data input module, the data cache module and the data output module;
a conditioning module electrically connected to said peripheral bus interface module, comprising the apparatus for serial peripheral interface bus data transfer of claim 5.
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| CN101834715B (en) * | 2010-04-26 | 2013-06-05 | 华为技术有限公司 | Data processing method, data processing system and data processing device |
| KR20210042748A (en) * | 2019-10-10 | 2021-04-20 | 삼성전자주식회사 | A Phase-locked loop circuit and a clock generator including the same |
| US11520940B2 (en) * | 2020-06-21 | 2022-12-06 | Nuvoton Technology Corporation | Secured communication by monitoring bus transactions using selectively delayed clock signal |
| CN114328347A (en) * | 2021-12-17 | 2022-04-12 | 上海爱信诺航芯电子科技有限公司 | Method for improving SPI bus frequency |
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