CN115856414A - Output stage buffer and current sensor - Google Patents
Output stage buffer and current sensor Download PDFInfo
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- CN115856414A CN115856414A CN202310165919.5A CN202310165919A CN115856414A CN 115856414 A CN115856414 A CN 115856414A CN 202310165919 A CN202310165919 A CN 202310165919A CN 115856414 A CN115856414 A CN 115856414A
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Abstract
The application relates to the field of sensors, in particular to an output stage buffer and a current sensor, wherein the output stage buffer comprises an input stage, a bias stage, a main amplification output stage and an auxiliary amplification output stage; and in the digital communication mode, the auxiliary amplification output stage is connected through the output selection terminal. The novel output stage buffer structure is used, the power consumption difference of an analog output mode and a digital communication mode is reduced, extra errors cannot be introduced in a temperature calibration stage, and the high precision of the whole system is ensured.
Description
Technical Field
The present application relates to the field of sensors, and in particular, to an output stage buffer and a current sensor.
Background
Referring to fig. 1, a current sensor in the related art is generally a three-port device: the device comprises a power supply end, a ground end and an analog output end/digital single bus communication end; in actual production, in order to reduce the chip area, the analog output terminal and the digital single bus communication terminal commonly share one output port. The sensor element can sense a magnetic field generated by current to be measured and generate a voltage signal proportional to the magnetic field intensity, the first-stage amplifier is used for preventing the voltage signal from being large, the second-stage amplifier is used for amplifying the prevented voltage signal again to achieve a certain swing amplitude, and finally the voltage signal is output through the output-stage buffer, and the output-stage buffer is mainly used for providing a certain load capacity. Because the sensitivity of the sensor element is different at different temperatures, in order to obtain higher accuracy, the temperature calibration of the sensor element is required, the temperature calibration mainly comprises a temperature sensor, a register, a temperature compensation logic circuit and a digital communication interface, and different values are written into the register through a digital single bus communication end at different temperatures in the stage of mass production test so as to correct the sensitivity of the sensor element.
However, since there is a power consumption difference between the analog output mode and the digital communication mode, an additional error may be introduced in the temperature calibration stage.
Disclosure of Invention
In order to improve the additional error introduced in the temperature calibration stage, the present application provides an output stage buffer and a current sensor.
In a first aspect, the present application provides an output stage buffer, which adopts the following technical solutions:
an output stage buffer comprises an input stage, a bias stage, a main amplification output stage and an auxiliary amplification output stage;
the input stage is provided with a signal input end and an output selection end, the signal input end is used for receiving an input voltage signal, and the input stage is used for converting the input voltage signal into a differential current signal, wherein the differential current signal comprises a first current signal and a second current signal;
the bias stage is coupled to the input stage and is used for copying the first current signal to the main amplification output stage in an analog output mode and copying the first current signal to the auxiliary amplification output stage in a digital communication mode;
the main amplification output stage is used for converting the differential current signal into a first voltage signal when the main amplification output stage is switched on, and simultaneously carrying out secondary amplification on the first voltage signal and outputting the first voltage signal;
the auxiliary amplification output stage is used for converting the differential current signal into a second voltage signal when the auxiliary amplification output stage is switched on and amplifying the second voltage signal for the second time;
and in the digital communication mode, the auxiliary amplification output stage is connected through the output selection terminal.
Optionally, the input stage includes:
the grid electrode of the first P-type transistor PM1 is a first bias control end Vbp1, and the source electrode of the first P-type transistor PM1 is connected with a power supply end VDD;
a second P-type transistor PM2 having a gate serving as the signal input terminal Vin +, and a drain for outputting the second current signal;
a third P-type transistor PM3 having a gate serving as the output selection terminal and a drain for outputting the first current signal; and the source electrode is connected with the drain electrode of the first P-type transistor PM1 and the source electrode of the second P-type transistor PM 2.
Optionally, the bias stage comprises:
a fourth P-type transistor PM4, a source electrode of which is connected with a power supply end VDD;
a gate of the sixth P-type transistor PM6 is a second bias control terminal Vbp2, and a source of the sixth P-type transistor PM6 is connected to the drain of the fourth P-type transistor PM 4;
a third N-type transistor NM3 having a gate serving as a fifth bias control terminal Vbn2 and a drain serving as a bias output terminal of the bias stage and connected to the gate of the fourth P-type transistor PM4 and the drain of the sixth P-type transistor PM 6;
the gate of the first N-type transistor NM1 is a fourth bias control terminal Vbn1, the drain of the first N-type transistor NM1 is connected to the source of the third N-type transistor NM3 and the input stage, and is configured to receive the first current signal, and the source of the first N-type transistor NM1 is grounded.
Optionally, the main amplification output stage includes a main amplification stage and a main output stage, the main amplification stage is configured to convert the differential current signal into a first voltage signal, and the main output stage is configured to amplify and output the first voltage signal for the second time.
Optionally, the main amplification stage includes:
a fifth P-type transistor PM5, a source electrode is connected with a power supply end VDD, and a grid electrode is connected with the bias output end of the bias stage;
a seventh P-type transistor PM7, a source electrode of which is connected to the drain electrode of the fifth P-type transistor PM5, a gate electrode of which is connected in series with the fourth switch S4 and then connected to the second bias control terminal Vbp2, a gate electrode of which is also connected in series with the fifth switch S5 and then connected to the power supply terminal VDD, and a drain electrode of which is connected to the first input terminal of the primary output stage;
a fourth N-type transistor NM4 having a gate connected to the tenth switch S10 in series and then connected to the fifth bias control terminal Vbn2, a gate connected to the eleventh switch S11 in series and then grounded, and a drain connected to the second input terminal of the main output stage;
and a second N-type transistor NM2 having a gate connected to the fourth bias control terminal Vbn1, a drain connected to the source of the fourth N-type transistor NM4 and the input stage, for receiving the second current signal, and a source grounded.
Optionally, the main output stage includes:
the source electrode of the zeroth P-type transistor PM0 is connected with a power supply end VDD, and the grid electrode of the zeroth P-type transistor PM0 is connected with the power supply end VDD after being connected with the zeroth switch S0 in series;
the grid electrode of the eighth P-type transistor PM8 is connected with the third bias control end Vbp3 after being connected with the sixth switch S6 in series, and the grid electrode of the eighth P-type transistor PM8 is also connected with the power supply end VDD after being connected with the seventh switch S7 in series;
a fifth N-type transistor NM5, a gate of which is connected in series with the eighth switch S8 and then connected to the sixth bias control terminal Vbn3, a gate of which is also connected in series with the ninth switch S9 and then grounded, a drain of which is a first input terminal of the main output stage and is connected to the source of the eighth P-type transistor PM8, the gate of the zeroth P-type transistor PM0 and one end of a zeroth capacitor C0, and the other end of the zeroth capacitor C0 is connected to one end of a zeroth resistor R0;
a zeroth N-type transistor NM0, a drain of which is an output terminal of the main output stage and is connected to the drain of the zeroth P-type transistor PM0, the other end of the zeroth resistor R0 and one end of a first resistor R1, a gate of which is a second input terminal of the main output stage and is connected to the source of the fifth N-type transistor NM5, the drain of the eighth P-type transistor PM8 and one end of a first capacitor C1, a gate of which is connected in series with a first switch S1 and then is grounded, a source of which is grounded, and the other end of the first capacitor C1 is connected to the other end of the first resistor R1;
the output selection end of the input stage is connected with the output end of the main output stage after being connected with the second switch S2 in series, and the output end of the main output stage is also used for being connected with the digital communication interface after being connected with the third switch S3 in series.
Optionally, the auxiliary amplification output stage includes an auxiliary amplification stage and an auxiliary output stage, the auxiliary amplification stage is configured to convert the differential current signal into a second voltage signal, and the auxiliary output stage is configured to amplify the second voltage signal for a second time.
Optionally, the auxiliary amplification stage comprises:
a ninth P-type transistor PM9 having a source connected to the power supply terminal VDD, a gate connected in series to the fourteenth switch S14 and then connected to the bias output terminal of the bias stage, and a gate connected in series to the fifteenth switch S15 and then connected to the power supply terminal VDD;
a tenth P-type transistor PM10 having a source connected to the drain of the ninth P-type transistor PM9, a gate connected in series with the sixteenth switch S16 and then connected to the second bias control terminal Vbp2, a gate connected in series with the seventeenth switch S17 and then connected to the power supply terminal VDD, and a drain connected to the first input terminal of the auxiliary output stage;
and a sixth N-type transistor NM6 having a gate connected to the twenty-second switch S22 and then connected to the fifth bias control terminal Vbn2, a gate connected to the twenty-second switch S23 and then grounded, a drain connected to the second input terminal of the auxiliary output stage, and a source connected to the input stage and configured to receive the second current signal.
Optionally, the auxiliary output stage includes:
a twelfth P-type transistor PM12, the source of which is connected to the power supply terminal VDD, and the gate of which is connected to the power supply terminal VDD after being connected in series with the twelfth switch S12;
the grid of the eleventh P-type transistor PM11 is connected in series with the eighteenth switch S18 and then connected with the third bias control terminal Vbp3, and the grid of the eleventh P-type transistor PM11 is also connected in series with the nineteenth switch S19 and then connected with the power supply terminal VDD;
a seventh N-type transistor NM7, a gate of which is connected in series with the twentieth switch S20 and then connected to the sixth bias control terminal Vbn3, a gate of which is also connected in series with the twenty-first switch S21 and then grounded, a drain of which is a first input terminal of the auxiliary output stage and is connected to the source of the eleventh P-type transistor PM11, the gate of the twelfth P-type transistor PM12 and one end of a second capacitor C2, and the other end of the second capacitor C2 is connected to one end of a second resistor R2;
an eighth N-type transistor NM8 having a drain terminal connected to the output terminal of the auxiliary output stage and connected to the drain terminal of the twelfth P-type transistor PM12, the other terminal of the second resistor R2, and one terminal of a third resistor R3, a gate terminal connected to the second input terminal of the auxiliary output stage and connected to the source terminal of the seventh N-type transistor NM7, the drain terminal of the eleventh P-type transistor PM11, and one terminal of a third capacitor C3, a gate terminal connected to the ground after being connected to a thirteenth switch S13, and a source terminal connected to the ground, and the other terminal of the third capacitor C3 connected to the other terminal of the third resistor R3;
the output selection end of the input stage is connected with the output end of the auxiliary output stage after being connected with the twenty-four switches S24 in series.
In a second aspect, the present application further provides a current sensor, which adopts the following technical scheme:
a current sensor comprises a sensor element, a first-stage amplifier, a second-stage amplifier and the output-stage buffer which are sequentially connected in series.
In summary, the present application uses a new output stage buffer structure, a main current is generated and outputted at the main amplification output stage in the analog output mode, an auxiliary current is generated at the auxiliary amplification output stage in the digital communication mode, and the main current and the auxiliary current are close in magnitude, so that the power consumption difference between the analog output mode and the digital communication mode is reduced, no additional error is introduced in the temperature calibration stage, and the high precision of the whole system is ensured.
Drawings
Fig. 1 is a schematic block diagram of a current sensor in the related art.
Fig. 2 is a schematic diagram of an output stage buffer.
Fig. 3 is a schematic diagram of an output stage buffer according to the present application.
Detailed Description
Referring to fig. 2, in order to ensure that there is no interference between the analog signal chain and the digital communication circuit in the output stage buffer, in the analog output mode, the switch S0 of the gate of the P-type transistor PM and the switch S1 of the gate of the N-type transistor NM are opened, the switch S3 between the output pin and the digital communication interface is opened, the switch S2 is closed to ensure the normal operation of the output stage buffer, and at this time, the current flowing through the P-type transistor PM and the N-type transistor NM is Iout (in order to drive a large load, the Iout generally reaches the mA level). In the digital communication mode, the switch S0 and the switch S1 are closed, the switch S2 is opened, the switch S3 is closed, at this time, since the gate terminal of the P-type transistor PM is pulled high and the gate terminal of the N-type transistor NM is pulled low, the output stage buffer is in a high-impedance state, the current flowing through the P-type transistor PM and the N-type transistor NM is 0, and the current when the digital communication interface circuit operates is very small, usually uA.
Under the analog output mode and the digital communication mode, the total current of the chip has a difference of Iout (mA level), large deviation exists in power consumption, large deviation exists in the temperature inside the chip, extra temperature errors can be introduced in the temperature calibration stage, and the digital calibration precision is greatly influenced. For example, with the SOT23 package, a 5.5v,5ma current at the power supply terminal Vdd would cause a 5 ℃ temperature deviation, an additional 5 ℃ temperature error would be introduced during the temperature calibration phase, and the corresponding output may deviate by 2%, which is fatal to a high-precision system. It should be understood that the output stage buffer shown in fig. 2 is for illustrating that the power consumption is poor in the two operation modes, and it cannot be understood that the specific structure of the output stage buffer is the existing structure.
Embodiments of the present application will be described in detail below with reference to the drawings attached hereto, but the embodiments should not be construed as limiting the present application.
The embodiment of the application provides a current sensor, which comprises a sensor element, a first-stage amplifier, a second-stage amplifier and an output-stage buffer, wherein the sensor element, the first-stage amplifier, the second-stage amplifier and the output-stage buffer are sequentially connected in series. It will be appreciated that temperature sensors, registers, temperature compensation logic and a digital communication interface may also be provided to allow for temperature calibration. The output stage buffer described below is to reduce the introduction of additional temperature errors during the temperature calibration phase, ensuring high accuracy of the overall system.
Embodiments of the output stage buffer are described in further detail below in conjunction with a current sensor.
The embodiment of the application provides an output stage buffer, which comprises an input stage, a bias stage, a main amplification output stage and an auxiliary amplification output stage;
the input stage is provided with a signal input end Vin + and an output selection end, the signal input end is used for receiving an input voltage signal, and the input stage is used for converting the input voltage signal into a differential current signal, wherein the differential current signal comprises a first current signal and a second current signal;
the bias stage is coupled to the input stage and is used for copying the first current signal to the main amplification output stage in an analog output mode and copying the first current signal to the auxiliary amplification output stage in a digital communication mode;
the main amplification output stage is used for converting the differential current signal into a first voltage signal when the main amplification output stage is switched on, and simultaneously carrying out secondary amplification on the first voltage signal and outputting the first voltage signal;
the auxiliary amplification output stage is used for converting the differential current signal into a second voltage signal when the auxiliary amplification output stage is switched on and amplifying the second voltage signal for the second time;
and in the digital communication mode, the auxiliary amplification output stage is connected through the output selection terminal.
Specifically, the main amplification output stage or the auxiliary amplification output stage can be selectively switched on through the output selection terminal, and the main amplification output stage is switched on and the auxiliary amplification output stage is switched off in an analog output mode, so that a main current is generated at the main amplification output stage and is output; switching on the auxiliary amplification output stage and switching off the main amplification output stage in a digital communication mode, so as to generate an auxiliary current at the auxiliary amplification output stage, wherein the auxiliary current is similar to the main current in magnitude; it will be appreciated that the auxiliary current is only used to generate a power consumption similar to the main current and not for the actual output. In practical use, the main amplification output stage and the auxiliary amplification output stage can adopt components of the same manufacturer and the same batch so as to enable the main current and the auxiliary current to be similar to each other as much as possible. It can be understood that, since the circuit structures and components of the main amplification output stage and the auxiliary amplification output stage are identical, the main current and the auxiliary current are similar, and therefore, the magnitudes of the first voltage signal and the second voltage signal are identical or similar.
Therefore, the output stage buffer can generate similar power consumption in an analog output mode and a digital communication mode, reduces the power consumption difference between the analog output mode and the digital communication mode, does not introduce extra errors in a temperature calibration stage, and ensures the high precision of the whole system.
Referring to fig. 3, in an embodiment of the present application, the input stage includes:
the grid electrode of the first P-type transistor PM1 is a first bias control end Vbp1, and the source electrode of the first P-type transistor PM1 is connected with a power supply end VDD;
a second P-type transistor PM2 having a gate serving as the signal input terminal Vin +, and a drain for outputting the second current signal;
a third P-type transistor PM3 having a gate serving as the output selection terminal and a drain for outputting the first current signal; the source electrode is connected with the drain electrode of the first P type transistor PM1 and the source electrode of the second P type transistor PM 2.
The biasing stage comprises:
a fourth P-type transistor PM4 having a source connected to a power supply terminal VDD;
a gate of the sixth P-type transistor PM6 is a second bias control terminal Vbp2, and a source thereof is connected to a drain of the fourth P-type transistor PM 4;
a third N-type transistor NM3 having a gate serving as a fifth bias control terminal Vbn2 and a drain serving as a bias output terminal of the bias stage and connected to the gate of the fourth P-type transistor PM4 and the drain of the sixth P-type transistor PM 6;
the gate of the first N-type transistor NM1 is a fourth bias control terminal Vbn1, the drain of the first N-type transistor NM1 is connected to the source of the third N-type transistor NM3 and the drain of the third P-type transistor PM3 (i.e., the input stage), and is configured to receive the first current signal, and the source of the first N-type transistor NM1 is grounded.
Specifically, the main amplification output stage comprises a main amplification stage and a main output stage, wherein the main amplification stage is used for converting the differential current signal into a first voltage signal, and the main output stage is used for secondarily amplifying and outputting the first voltage signal. It will be appreciated that the main amplifier stage is arranged to convert the second current signal and the first current signal copied to the main amplifier stage into a first voltage signal.
With continued reference to fig. 3, the primary amplification stage comprises:
a fifth P-type transistor PM5 having a source connected to the power supply terminal VDD and a gate connected to the drain of the third N-type transistor NM3 (i.e., the bias output terminal of the bias stage);
a seventh P-type transistor PM7, a source electrode of which is connected to the drain electrode of the fifth P-type transistor PM5, a gate electrode of which is connected in series with the fourth switch S4 and then connected to the second bias control terminal Vbp2, a gate electrode of which is also connected in series with the fifth switch S5 and then connected to the power supply terminal VDD, and a drain electrode of which is connected to the first input terminal of the primary output stage;
a fourth N-type transistor NM4 having a gate connected to the tenth switch S10 in series and then connected to the fifth bias control terminal Vbn2, a gate connected to the eleventh switch S11 in series and then grounded, and a drain connected to the second input terminal of the main output stage;
and a second N-type transistor NM2 having a gate connected to the fourth bias control terminal Vbn1, a drain connected to the source of the fourth N-type transistor NM4 and the drain of the second P-type transistor PM2 (i.e., the input stage) for receiving the second current signal, and a source grounded.
With continued reference to fig. 3, the primary output stage includes:
the source electrode of the zeroth P-type transistor PM0 is connected with a power supply end VDD, and the grid electrode of the zeroth P-type transistor PM0 is connected with the power supply end VDD after being connected with the zeroth switch S0 in series;
the grid electrode of the eighth P-type transistor PM8 is connected with the third bias control end Vbp3 after being connected with the sixth switch S6 in series, and is also connected with the power supply end VDD after being connected with the seventh switch S7 in series;
a fifth N-type transistor NM5, a gate of which is connected in series with the eighth switch S8 and then connected to the sixth bias control terminal Vbn3, a gate of which is also connected in series with the ninth switch S9 and then grounded, a drain of which is a first input terminal of the main output stage and is connected to a source of the eighth P-type transistor PM8, a gate of the zeroth P-type transistor PM0, and one end of a zeroth capacitor C0, and the other end of the zeroth capacitor C0 is connected to one end of a zeroth resistor R0;
a zeroth N-type transistor NM0, a drain of which is an output terminal of the main output stage and is connected to the drain of the zeroth P-type transistor PM0, the other end of the zeroth resistor R0 and one end of a first resistor R1, a gate of which is a second input terminal of the main output stage and is connected to the source of the fifth N-type transistor NM5, the drain of the eighth P-type transistor PM8 and one end of a first capacitor C1, a gate of which is connected in series with a first switch S1 and then is grounded, a source of which is grounded, and the other end of the first capacitor C1 is connected to the other end of the first resistor R1;
the output selection end of the input stage is connected with the output end of the main output stage after being connected with the second switch S2 in series, and the output end of the main output stage is also used for being connected with the digital communication interface after being connected with the third switch S3 in series.
Specifically, the auxiliary amplification output stage includes an auxiliary amplification stage and an auxiliary output stage, the auxiliary amplification stage is configured to convert the differential current signal into a second voltage signal, and the auxiliary output stage is configured to secondarily amplify the second voltage signal. It will be appreciated that the auxiliary amplification stage is arranged to convert the second current signal and the first current signal copied to the auxiliary amplification stage into a second voltage signal.
With continued reference to fig. 3, the auxiliary amplification stage comprises:
a ninth P-type transistor PM9 having a source connected to the power supply terminal VDD, a gate connected to the drain of the third N-type transistor NM3 (i.e., the bias output terminal of the bias stage) after being connected in series to the fourteenth switch S14, and a gate connected to the power supply terminal VDD after being connected in series to the fifteenth switch S15;
a tenth P-type transistor PM10 having a source connected to the drain of the ninth P-type transistor PM9, a gate connected in series with the sixteenth switch S16 and then connected to the second bias control terminal Vbp2, a gate connected in series with the seventeenth switch S17 and then connected to the power supply terminal VDD, and a drain connected to the first input terminal of the auxiliary output stage;
and a sixth N-type transistor NM6 having a gate connected to the twenty-second switch S22 in series and then connected to the fifth bias control terminal Vbn2, a gate connected to the twenty-third switch S23 in series and then grounded, a drain connected to the source of the seventh N-type transistor NM7 and the drain of the eleventh P-type transistor PM11 (i.e., the second input terminal of the auxiliary output stage), and a source connected to the drain of the second P-type transistor PM2 (i.e., the input stage) and configured to receive the second current signal.
With continued reference to fig. 3, the auxiliary output stage includes:
a twelfth P-type transistor PM12, the source of which is connected to the power supply terminal VDD, and the gate of which is connected to the power supply terminal VDD after being connected in series with the twelfth switch S12;
the grid of the eleventh P-type transistor PM11 is connected in series with the eighteenth switch S18 and then connected with the third bias control terminal Vbp3, and the grid of the eleventh P-type transistor PM11 is also connected in series with the nineteenth switch S19 and then connected with the power supply terminal VDD;
a seventh N-type transistor NM7, a gate of which is connected in series with the twentieth switch S20 and then connected to the sixth bias control terminal Vbn3, a gate of which is also connected in series with the twenty-first switch S21 and then grounded, a drain of which is a first input terminal of the auxiliary output stage and is connected to the source of the eleventh P-type transistor PM11, the gate of the twelfth P-type transistor PM12 and one end of a second capacitor C2, and the other end of the second capacitor C2 is connected to one end of a second resistor R2;
an eighth N-type transistor NM8 having a drain terminal connected to the output terminal of the auxiliary output stage and connected to the drain terminal of the twelfth P-type transistor PM12, the other terminal of the second resistor R2, and one terminal of a third resistor R3, a gate terminal connected to the second input terminal of the auxiliary output stage and connected to the source terminal of the seventh N-type transistor NM7, the drain terminal of the eleventh P-type transistor PM11, and one terminal of a third capacitor C3, a gate terminal connected to the ground after being connected to a thirteenth switch S13, and a source terminal connected to the ground, and the other terminal of the third capacitor C3 connected to the other terminal of the third resistor R3;
the output selection end of the input stage is connected with the output end of the auxiliary output stage after being connected with the twenty-four switches S24 in series.
In the embodiment of the present application, the first P-type transistor PM1 is used to provide a quiescent current for the second P-type transistor PM2 and the third P-type transistor PM3, which determines the transconductance gm and the noise characteristics of the input stage, and the second P-type transistor PM2 and the third P-type transistor PM3 convert the input voltage signal into a current signal: i = Vin +. Gm.
The first and second N-type transistors NM1 and NM2 are N-tail current sources that supply static currents to the bias stage and the main amplifier stage when the analog operation mode is in use. The third N-type transistor NM3, the fourth N-type transistor NM4, and the sixth N-type transistor NM6 are N-type cascode transistors, and function to increase the impedance from the drain terminal of each transistor to ground.
The fourth P-type transistor PM4 is diode-connected and it copies the differential current signal flowing through the biasing stage, in particular the first current signal thereof, to the main amplifier stage (analog operation mode) via the fifth P-type transistor PM5 and to the auxiliary amplifier stage (digital communication mode) via the ninth P-type transistor PM 9. It is understood that the differential current signal refers to the current difference between the second P-type transistor PM2 and the third P-type transistor PM3, for example, the current of the second P-type transistor PM2 increases by 1uA, the current of the third P-type transistor PM3 decreases by 1uA, and the current difference between the second P-type transistor PM2 and the third P-type transistor PM3 is controlled by the gate voltage (i.e., vin +) of the second P-type transistor PM2 and the gate voltage (Vout) of the third P-type transistor PM 3.
The sixth P-type transistor PM6, the seventh P-type transistor PM7 and the tenth P-type transistor PM10 are P-type cascode transistors, and function to increase the impedance from the drain terminal of each transistor to the power supply.
The eighth P-type transistor PM8, the fifth N-type transistor NM5, the zeroth P-type transistor PM0 and the zeroth N-type transistor NM0 form a main output stage of class ab, and can provide stronger load current driving capability compared with a conventional class a structure. The eighth P-type transistor PM8 and the fifth N-type transistor NM5 provide bias voltages for the zeroth P-type transistor PM0 and the zeroth N-type transistor NM0, and also automatically adjust gate voltages of the zeroth P-type transistor PM0 and the zeroth N-type transistor NM0 when an output current load varies. The zeroth P-type transistor PM0 and the zeroth N-type transistor NM0 serve as output tubes to provide driving capability for the chip load.
The zeroth capacitor C0 and the zeroth resistor R0, the first capacitor C1 and the first resistor R1 which are connected in series are compensation devices of the main output stage, and the purpose is to ensure that the loop can work stably.
The eleventh P-type transistor PM11, the seventh N-type transistor NM7, the twelfth P-type transistor PM12, and the eighth N-type transistor NM8 constitute an auxiliary output stage of the class ab, wherein the eleventh P-type transistor PM11 and the seventh N-type transistor NM7 supply a bias voltage to the twelfth P-type transistor PM12 and the eighth N-type transistor NM 8. The twelfth P-type transistor PM12 and the eighth N-type transistor NM8 serve as output tubes of the auxiliary output stage, and match currents of the zeroth P-type transistor PM0 and the zeroth N-type transistor NM0 when the chip operates in the digital communication mode.
The second capacitor C2, the second resistor R2, the third capacitor C3 and the third resistor R3 connected in series are compensation devices of the auxiliary output stage, and are used for ensuring that the loop can stably operate, and further ensuring that the same or similar current is generated in the analog output mode and the digital communication mode, so that power consumption difference and temperature difference in the analog output mode and the digital communication mode are reduced.
With the output stage buffer of the present application, in the analog output mode, the switches S2, S4, S6, S8, S10, S12, S13, S15, S17, S19, S21, and S23 are all closed, the switches S0, S1, S3, S5, S7, S9, S11, S14, S16, S18, S20, S22, and S24 are all opened, that is, the main amplification output stage is turned on, the auxiliary amplification output stage is turned off, the current flowing through the zeroth P-type transistor PM0 and the zeroth N-type transistor NM0 is Iout, and the current flowing through the twelfth P-type transistor PM12 and the eighth N-type transistor NM8 is 0. In the digital communication mode, the switches S2, S4, S6, S8, S10, S12, S13, S15, S17, S19, S21 and S23 are all turned off, the switches S0, S1, S3, S5, S7, S9, S11, S14, S16, S18, S20, S22 and S24 are all turned on, that is, the auxiliary amplification output stage is turned on and the main amplification output stage is turned off, the current flowing through the zeroth P-type transistor PM0 and the zeroth N-type transistor NM0 is 0, and the current flowing through the twelfth P-type transistor PM12 and the eighth N-type transistor NM8 is Iout. In addition, the current of the digital communication interface is uA level and can be ignored, so that the power consumption deviation is very small and can be ignored in the two working modes of the analog output mode and the digital communication mode, no extra error is introduced in the temperature calibration stage, and the high precision of the whole system is ensured.
It can be understood that the first bias control end Vbp1, the second bias control end Vbp2, the third bias control end Vbp3, the fourth bias control end Vbn1, the fifth bias control end Vbn2, and the sixth bias control end Vbn3 are all configured to receive a bias voltage signal, so that the output stage buffer normally works.
It will be clear to those skilled in the art that, for convenience and simplicity of description, the foregoing division of the functional modules is merely used as an example, and in practical applications, the above function distribution may be performed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to perform all or part of the above described functions. For the specific working processes of the system, the apparatus, and the unit described above, reference may be made to the corresponding processes in the foregoing method embodiments, and details are not described here again.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. The integrated unit, if implemented in the form of a software functional unit and sold or used as a separate product, may be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application, which are essential or part of the technical solutions contributing to the prior art, or all or part of the technical solutions, can be embodied in the form of a software product stored in a storage medium, and including several instructions for causing a computer device or a processor to execute all or part of the steps of the methods described in the embodiments of the present application.
The above embodiments are only used to describe the technical solutions of the present application in detail, but the above embodiments are only used to help understanding the method and the core idea of the present application, and should not be construed as limiting the present application. Those skilled in the art should also appreciate that various modifications and substitutions can be made without departing from the scope of the present disclosure.
Claims (10)
1. An output stage buffer, comprising: the circuit comprises an input stage, a bias stage, a main amplification output stage and an auxiliary amplification output stage;
the input stage is provided with a signal input end and an output selection end, the signal input end is used for receiving an input voltage signal, and the input stage is used for converting the input voltage signal into a differential current signal, wherein the differential current signal comprises a first current signal and a second current signal;
the bias stage is coupled to the input stage and is used for copying the first current signal to the main amplification output stage in an analog output mode and copying the first current signal to the auxiliary amplification output stage in a digital communication mode;
the main amplification output stage is used for converting the differential current signal into a first voltage signal when the main amplification output stage is switched on, and amplifying and outputting the first voltage signal for the second time;
the auxiliary amplification output stage is used for converting the differential current signal into a second voltage signal when the auxiliary amplification output stage is switched on and amplifying the second voltage signal for the second time;
and in the digital communication mode, the auxiliary amplification output stage is connected through the output selection terminal.
2. The output stage buffer of claim 1, wherein the input stage comprises:
the grid electrode of the first P-type transistor PM1 is a first bias control end Vbp1, and the source electrode of the first P-type transistor PM1 is connected with a power supply end VDD;
a second P-type transistor PM2 having a gate serving as the signal input terminal Vin +, and a drain for outputting the second current signal;
a third P-type transistor PM3 having a gate serving as the output selection terminal and a drain for outputting the first current signal; and the source electrode is connected with the drain electrode of the first P-type transistor PM1 and the source electrode of the second P-type transistor PM 2.
3. The output stage buffer of claim 1, wherein the biasing stage comprises:
a fourth P-type transistor PM4 having a source connected to a power supply terminal VDD;
a gate of the sixth P-type transistor PM6 is a second bias control terminal Vbp2, and a source thereof is connected to a drain of the fourth P-type transistor PM 4;
a third N-type transistor NM3 having a gate serving as a fifth bias control terminal Vbn2 and a drain serving as a bias output terminal of the bias stage and connected to the gate of the fourth P-type transistor PM4 and the drain of the sixth P-type transistor PM 6;
the gate of the first N-type transistor NM1 is a fourth bias control terminal Vbn1, the drain of the first N-type transistor NM1 is connected to the source of the third N-type transistor NM3 and the input stage, and is configured to receive the first current signal, and the source of the first N-type transistor NM1 is grounded.
4. The output stage buffer of claim 1, wherein: the main amplification output stage comprises a main amplification stage and a main output stage, the main amplification stage is used for converting the differential current signal into a first voltage signal, and the main output stage is used for carrying out secondary amplification on the first voltage signal and outputting the first voltage signal.
5. The output stage buffer of claim 4, wherein the main amplification stage comprises:
a fifth P-type transistor PM5, the source electrode of which is connected with the power supply end VDD and the grid electrode of which is connected with the bias output end of the bias stage;
a seventh P-type transistor PM7, a source electrode of which is connected to the drain electrode of the fifth P-type transistor PM5, a gate electrode of which is connected in series with the fourth switch S4 and then connected to the second bias control terminal Vbp2, a gate electrode of which is also connected in series with the fifth switch S5 and then connected to the power supply terminal VDD, and a drain electrode of which is connected to the first input terminal of the primary output stage;
a fourth N-type transistor NM4 having a gate connected to the tenth switch S10 in series and then connected to the fifth bias control terminal Vbn2, a gate connected to the eleventh switch S11 in series and then grounded, and a drain connected to the second input terminal of the main output stage;
and a second N-type transistor NM2 having a gate connected to the fourth bias control terminal Vbn1, a drain connected to the source of the fourth N-type transistor NM4 and the input stage, for receiving the second current signal, and a source grounded.
6. The output stage buffer of claim 4, wherein the main output stage comprises:
the source electrode of the zeroth P-type transistor PM0 is connected with a power supply end VDD, and the grid electrode of the zeroth P-type transistor PM0 is connected with the power supply end VDD after being connected with the zeroth switch S0 in series;
the grid electrode of the eighth P-type transistor PM8 is connected with the third bias control end Vbp3 after being connected with the sixth switch S6 in series, and the grid electrode of the eighth P-type transistor PM8 is also connected with the power supply end VDD after being connected with the seventh switch S7 in series;
a fifth N-type transistor NM5, a gate of which is connected in series with the eighth switch S8 and then connected to the sixth bias control terminal Vbn3, a gate of which is also connected in series with the ninth switch S9 and then grounded, a drain of which is a first input terminal of the main output stage and is connected to the source of the eighth P-type transistor PM8, the gate of the zeroth P-type transistor PM0 and one end of a zeroth capacitor C0, and the other end of the zeroth capacitor C0 is connected to one end of a zeroth resistor R0;
a zeroth N-type transistor NM0, a drain of which is an output terminal of the main output stage and is connected to the drain of the zeroth P-type transistor PM0, the other end of the zeroth resistor R0 and one end of a first resistor R1, a gate of which is a second input terminal of the main output stage and is connected to the source of the fifth N-type transistor NM5, the drain of the eighth P-type transistor PM8 and one end of a first capacitor C1, a gate of which is connected in series with a first switch S1 and then is grounded, a source of which is grounded, and the other end of the first capacitor C1 is connected to the other end of the first resistor R1;
the output selection end of the input stage is connected with the output end of the main output stage after being connected with the second switch S2 in series, and the output end of the main output stage is also used for being connected with the digital communication interface after being connected with the third switch S3 in series.
7. The output stage buffer of claim 1, wherein: the auxiliary amplification output stage comprises an auxiliary amplification stage and an auxiliary output stage, the auxiliary amplification stage is used for converting the differential current signal into a second voltage signal, and the auxiliary output stage is used for carrying out secondary amplification on the second voltage signal.
8. The output stage buffer of claim 7, wherein the auxiliary amplification stage comprises:
a ninth P-type transistor PM9 having a source connected to the power supply terminal VDD, a gate connected to the bias output terminal of the bias stage after being connected in series to the fourteenth switch S14, and a gate connected to the power supply terminal VDD after being connected in series to the fifteenth switch S15;
a tenth P-type transistor PM10 having a source connected to the drain of the ninth P-type transistor PM9, a gate connected in series with the sixteenth switch S16 and then connected to the second bias control terminal Vbp2, a gate connected in series with the seventeenth switch S17 and then connected to the power supply terminal VDD, and a drain connected to the first input terminal of the auxiliary output stage;
and a sixth N-type transistor NM6 having a gate connected to the twenty-second switch S22 and then connected to the fifth bias control terminal Vbn2, a gate connected to the twenty-second switch S23 and then grounded, a drain connected to the second input terminal of the auxiliary output stage, and a source connected to the input stage and configured to receive the second current signal.
9. The output stage buffer of claim 7, wherein the auxiliary output stage comprises:
a twelfth P-type transistor PM12, the source of which is connected to the power supply terminal VDD, and the gate of which is connected to the power supply terminal VDD after being connected in series with the twelfth switch S12;
the grid of the eleventh P-type transistor PM11 is connected in series with the eighteenth switch S18 and then connected with the third bias control terminal Vbp3, and the grid of the eleventh P-type transistor PM11 is also connected in series with the nineteenth switch S19 and then connected with the power supply terminal VDD;
a seventh N-type transistor NM7 having a gate connected to the twentieth switch S20 in series and then connected to the sixth bias control terminal Vbn3, a gate connected to the twenty-first switch S21 in series and then grounded, a drain serving as a first input terminal of the auxiliary output stage and connected to the source of the eleventh P-type transistor PM11, the gate of the twelfth P-type transistor PM12 and one end of a second capacitor C2, and the other end of the second capacitor C2 being connected to one end of a second resistor R2;
an eighth N-type transistor NM8 having a drain terminal connected to the output terminal of the auxiliary output stage and connected to the drain terminal of the twelfth P-type transistor PM12, the other terminal of the second resistor R2, and one terminal of a third resistor R3, a gate terminal connected to the second input terminal of the auxiliary output stage and connected to the source terminal of the seventh N-type transistor NM7, the drain terminal of the eleventh P-type transistor PM11, and one terminal of a third capacitor C3, a gate terminal connected to the ground after being connected to a thirteenth switch S13, and a source terminal connected to the ground, and the other terminal of the third capacitor C3 connected to the other terminal of the third resistor R3;
the output selection end of the input stage is connected with the output end of the auxiliary output stage after being connected with the twenty-four switches S24 in series.
10. A current sensor, characterized by: comprising in series in succession a sensor element, a first stage amplifier, a second stage amplifier and an output stage buffer as claimed in any one of claims 1 to 9.
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