CN115856414B - Output stage buffer and current sensor - Google Patents
Output stage buffer and current sensor Download PDFInfo
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- CN115856414B CN115856414B CN202310165919.5A CN202310165919A CN115856414B CN 115856414 B CN115856414 B CN 115856414B CN 202310165919 A CN202310165919 A CN 202310165919A CN 115856414 B CN115856414 B CN 115856414B
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Abstract
The application relates to the field of sensors, in particular to an output stage buffer and a current sensor, wherein the output stage buffer comprises an input stage, a bias stage, a main amplification output stage and an auxiliary amplification output stage; and in the analog output mode, the main amplification output stage is connected and output through the output selection end, and in the digital communication mode, the auxiliary amplification output stage is connected through the output selection end. The novel output stage buffer structure is used, the power consumption difference of an analog output mode and a digital communication mode is reduced, no extra error is introduced in the temperature calibration stage, and the high precision of the whole system is ensured.
Description
Technical Field
The present disclosure relates to the field of sensors, and in particular, to an output stage buffer and a current sensor.
Background
Referring to fig. 1, the current sensor in the related art is typically a three-port device: the system comprises a power supply end, a ground end and an analog output end/digital single bus communication end; in practical production, to reduce the chip area, the analog output and the digital single bus communication terminal typically share one output port. The sensor element can sense a magnetic field generated by current to be measured and generate a voltage signal proportional to the magnetic field intensity, the first-stage amplifier is used for preventing the voltage signal from being large, the second-stage amplifier is used for amplifying the voltage signal which is prevented from being large again to reach a certain swing amplitude, and finally the voltage signal is output through the output-stage buffer which is mainly used for providing a certain load capacity. Since the sensitivity of the sensor element is different at different temperatures, in order to obtain higher accuracy, temperature calibration needs to be performed on the sensor element, and the sensor element mainly comprises a temperature sensor, a register, a temperature compensation logic circuit and a digital communication interface, and different values are written into the register at different temperatures through a digital single bus communication terminal in a mass production test stage to correct the sensitivity of the sensor element.
However, since there is a difference in power consumption in the analog output mode and the digital communication mode, an additional error is introduced in the temperature calibration stage.
Disclosure of Invention
To improve the additional error introduced by the temperature calibration stage, the present application provides an output stage buffer and a current sensor.
In a first aspect, the present application provides an output stage buffer, which adopts the following technical scheme:
an output stage buffer includes an input stage, a bias stage, a main amplification output stage, and an auxiliary amplification output stage;
the input stage is provided with a signal input end and an output selection end, wherein the signal input end is used for receiving an input voltage signal, and the input stage is used for converting the input voltage signal into a differential current signal, and the differential current signal comprises a first current signal and a second current signal;
the bias stage is coupled to the input stage and is used for copying the first current signal to the main amplifying output stage in an analog output mode and copying the first current signal to the auxiliary amplifying output stage in a digital communication mode;
the main amplification output stage is used for converting the differential current signal into a first voltage signal when being connected, and simultaneously carrying out secondary amplification on the first voltage signal and outputting the first voltage signal;
the auxiliary amplification output stage is used for converting the differential current signal into a second voltage signal when being connected and carrying out secondary amplification on the second voltage signal;
and in the analog output mode, the main amplification output stage is connected and output through the output selection end, and in the digital communication mode, the auxiliary amplification output stage is connected through the output selection end.
Optionally, the input stage includes:
the grid electrode of the first P-type transistor PM1 is a first bias control end Vbp1, and the source electrode of the first P-type transistor PM1 is connected with a power supply end VDD;
the second P-type transistor PM2 has a gate which is the signal input terminal vin+ and a drain for outputting the second current signal;
the gate of the third P-type transistor PM3 is the output selection end, and the drain is used for outputting the first current signal; the source electrode is connected with the drain electrode of the first P-type transistor PM1 and the source electrode of the second P-type transistor PM 2.
Optionally, the bias stage includes:
a fourth P-type transistor PM4, the source electrode of which is connected with the power supply end VDD;
the gate of the sixth P-type transistor PM6 is the second bias control terminal Vbp2, and the source is connected to the drain of the fourth P-type transistor PM 4;
the grid electrode of the third N-type transistor NM3 is a fifth bias control end Vbn2, the drain electrode of the third N-type transistor NM3 is a bias output end of the bias stage and is connected with the grid electrode of the fourth P-type transistor PM4 and the drain electrode of the sixth P-type transistor PM 6;
the gate of the first N-type transistor NM1 is a fourth bias control terminal Vbn1, the drain is connected to the source of the third N-type transistor NM3 and the input stage, and the source is grounded.
Optionally, the main amplifying output stage includes a main amplifying stage for converting the differential current signal into a first voltage signal, and a main output stage for secondarily amplifying and outputting the first voltage signal.
Optionally, the main amplifying stage includes:
a fifth P-type transistor PM5, wherein a source electrode is connected with a power supply end VDD, and a grid electrode is connected with a bias output end of the bias stage;
a source electrode of the seventh P-type transistor PM7 is connected to the drain electrode of the fifth P-type transistor PM5, a gate electrode is connected in series with the fourth switch S4 and then is connected to the second bias control terminal Vbp2, a gate electrode is also connected in series with the fifth switch S5 and then is connected to the power supply terminal VDD, and a drain electrode is connected to the first input terminal of the main output stage;
the grid of the fourth N-type transistor NM4 is connected with the fifth bias control end Vbn2 after being connected with the tenth switch S10 in series, the grid of the fourth N-type transistor NM4 is also connected with the eleventh switch S11 in series and then grounded, and the drain of the fourth N-type transistor NM4 is connected with the second input end of the main output stage;
and the grid electrode of the second N-type transistor NM2 is connected with the fourth bias control end Vbn1, the drain electrode of the second N-type transistor NM4 is connected with the source electrode and the input stage, and is used for receiving the second current signal, and the source electrode is grounded.
Optionally, the main output stage includes:
the source electrode of the zeroth P-type transistor PM0 is connected with the power supply end VDD, and the grid electrode of the zeroth P-type transistor PM0 is connected with the power supply end VDD after being connected with the zeroth switch S0 in series;
the eighth P-type transistor PM8 has a grid connected with a third bias control end Vbp3 after being connected with a sixth switch S6 in series, and has a grid connected with a power end VDD after being connected with a seventh switch S7 in series;
a fifth N-type transistor NM5, the gate of which is connected in series with an eighth switch S8 and then connected to a sixth bias control terminal Vbn3, the gate of which is also connected in series with a ninth switch S9 and then grounded, the drain of which is the first input terminal of the main output stage and is connected to the source of the eighth P-type transistor PM8, the gate of the zeroth P-type transistor PM0 and one end of a zeroth capacitor C0, the other end of the zeroth capacitor C0 being connected to one end of a zeroth resistor R0;
a zero-th N-type transistor NM0, the drain electrode is the output end of the main output stage and is connected to the drain electrode of the zero-th P-type transistor PM0, the other end of the zero-th resistor R0 and one end of the first resistor R1, the gate electrode is the second input end of the main output stage and is connected to the source electrode of the fifth N-type transistor NM5, the drain electrode of the eighth P-type transistor PM8 and one end of the first capacitor C1, the gate electrode is connected in series with the first switch S1 and then grounded, the source electrode is grounded, and the other end of the first capacitor C1 is connected to the other end of the first resistor R1;
the output selection end of the input stage is connected with the output end of the main output stage after being connected with the second switch S2 in series, and the output end of the main output stage is also connected with the digital communication interface after being connected with the third switch S3 in series.
Optionally, the auxiliary amplifying output stage includes an auxiliary amplifying stage for converting the differential current signal into a second voltage signal, and an auxiliary output stage for secondarily amplifying the second voltage signal.
Optionally, the auxiliary amplifying stage includes:
the source electrode of the ninth P-type transistor PM9 is connected with the power supply end VDD, the grid electrode is connected with the bias output end of the bias stage after being connected with the fourteenth switch S14 in series, and the grid electrode is also connected with the power supply end VDD after being connected with the fifteenth switch S15 in series;
a tenth P-type transistor PM10, the source electrode of which is connected to the drain electrode of the ninth P-type transistor PM9, the gate electrode of which is connected in series with the sixteenth switch S16 and then is connected to the second bias control terminal Vbp2, the gate electrode of which is also connected in series with the seventeenth switch S17 and then is connected to the power supply terminal VDD, and the drain electrode of which is connected to the first input terminal of the auxiliary output stage;
the sixth N-type transistor NM6 has a gate connected in series with the twenty-second switch S22 and then connected to the fifth bias control terminal Vbn2, a gate connected in series with the twenty-third switch S23 and then grounded, a drain connected to the second input terminal of the auxiliary output stage, and a source connected to the input stage for receiving the second current signal.
Optionally, the auxiliary output stage includes:
the twelfth P-type transistor PM12 has a source connected to the power supply terminal VDD, and a gate connected in series with the twelfth switch S12 and then connected to the power supply terminal VDD;
the eleventh P-type transistor PM11 has a gate connected in series with an eighteenth switch S18 and then connected to the third bias control terminal Vbp3, and a gate connected in series with a nineteenth switch S19 and then connected to the power terminal VDD;
a seventh N-type transistor NM7, the gate is connected in series with the twentieth switch S20 and then connected to the sixth bias control terminal Vbn3, the gate is also connected in series with the twenty-first switch S21 and then grounded, the drain is the first input terminal of the auxiliary output stage and is connected to the source of the eleventh P-type transistor PM11, the gate of the twelfth P-type transistor PM12 and one end of the second capacitor C2, and the other end of the second capacitor C2 is connected to one end of the second resistor R2;
an eighth N-type transistor NM8, the drain electrode is the output end of the auxiliary output stage and is connected to the drain electrode of the twelfth P-type transistor PM12, the other end of the second resistor R2 and one end of the third resistor R3, the gate electrode is the second input end of the auxiliary output stage and is connected to the source electrode of the seventh N-type transistor NM7, the drain electrode of the eleventh P-type transistor PM11 and one end of the third capacitor C3, the gate electrode is further connected in series with the thirteenth switch S13 and then grounded, the source electrode is grounded, and the other end of the third capacitor C3 is connected to the other end of the third resistor R3;
the output selection end of the input stage is connected with the output end of the auxiliary output stage after being connected with the twenty-fourth switch S24 in series.
In a second aspect, the present application further provides a current sensor, which adopts the following technical scheme:
a current sensor comprises a sensor element, a first-stage amplifier, a second-stage amplifier and the output-stage buffer which are sequentially connected in series.
In summary, the present application uses a new output stage buffer structure, in which a main current is generated and output at a main amplifying output stage in an analog output mode, and an auxiliary current is generated at an auxiliary amplifying output stage in a digital communication mode, the main current and the auxiliary current are similar in magnitude, so that the power consumption difference between the analog output mode and the digital communication mode is reduced, no additional error is introduced in a temperature calibration stage, and high precision of the whole system is ensured.
Drawings
Fig. 1 is a schematic block diagram of a current sensor in the related art.
Fig. 2 is a schematic diagram of an output stage buffer.
Fig. 3 is a schematic diagram of an output stage buffer of the present application.
Detailed Description
Referring to fig. 2, in order to ensure that there is no interference between the analog signal chain and the digital communication circuit in the output stage buffer, in the analog output mode, the switch S0 of the gate of the P-type transistor PM and the switch S1 of the gate of the N-type transistor NM are opened, the switch S3 between the output pin and the digital communication interface is opened, and the switch S2 is closed to ensure the normal operation of the output stage buffer, and at this time, the current flowing through the P-type transistor PM and the N-type transistor NM is Iout (for driving a large load, iout usually reaches mA level). In the digital communication mode, the switch S0 and the switch S1 are closed, the switch S2 is opened, and the switch S3 is closed, at this time, since the gate terminal of the P-type transistor PM is pulled high and the gate terminal of the N-type transistor NM is pulled low, the output stage buffer is in a high-resistance state, the current flowing through the P-type transistor PM and the N-type transistor NM is 0, and the current when the digital communication interface circuit works is very small, usually in the uA stage.
Because the total current of the chip is different from Iout (mA level) in the analog output mode and the digital communication mode, the power consumption has larger deviation, the temperature in the chip has larger deviation, and extra temperature error can be introduced in the temperature calibration stage, so that the digital calibration precision is greatly influenced. For example, with the SOT23 package, the power supply Vdd is 5.5v, a current of 5ma may cause a temperature deviation of 5 ℃, an additional temperature error of 5 ℃ may be introduced during the temperature calibration phase, and the corresponding output may deviate by 2%, which is fatal to the high-precision system. It will be appreciated that the output stage buffer shown in fig. 2 is for illustrating that there is a difference in power consumption in two operation modes, and it cannot be understood that the specific structure of the output stage buffer is an existing structure, and in actual production, the output stage buffer may have many different circuit structures, but all have a problem of difference in power consumption.
Embodiments of the present application will be described in detail below with reference to the drawings of the specification, but the embodiments should not be construed as limiting the present application.
The embodiment of the application provides a current sensor, which comprises a sensor element, a first-stage amplifier, a second-stage amplifier and an output-stage buffer which are sequentially connected in series. It will be appreciated that temperature sensors, registers, temperature compensation logic and digital communication interfaces may also be provided to perform temperature calibration. The output stage buffer described below is to reduce the introduction of additional temperature errors during the temperature calibration phase, ensuring high accuracy of the overall system.
Embodiments of the output stage buffer are described in further detail below in conjunction with the current sensor.
The embodiment of the application provides an output stage buffer, which comprises an input stage, a bias stage, a main amplification output stage and an auxiliary amplification output stage;
the input stage is provided with a signal input end Vin+ and an output selection end, wherein the signal input end is used for receiving an input voltage signal, and the input stage is used for converting the input voltage signal into a differential current signal, and the differential current signal comprises a first current signal and a second current signal;
the bias stage is coupled to the input stage and is used for copying the first current signal to the main amplifying output stage in an analog output mode and copying the first current signal to the auxiliary amplifying output stage in a digital communication mode;
the main amplification output stage is used for converting the differential current signal into a first voltage signal when being connected, and simultaneously carrying out secondary amplification on the first voltage signal and outputting the first voltage signal;
the auxiliary amplification output stage is used for converting the differential current signal into a second voltage signal when being connected and carrying out secondary amplification on the second voltage signal;
and in the analog output mode, the main amplification output stage is connected and output through the output selection end, and in the digital communication mode, the auxiliary amplification output stage is connected through the output selection end.
Specifically, the main amplification output stage or the auxiliary amplification output stage can be selectively connected through the output selection end, and the main amplification output stage is connected and the auxiliary amplification output stage is disconnected in the analog output mode, so that main current is generated and output at the main amplification output stage; the auxiliary amplifying output stage is switched on and the main amplifying output stage is switched off in the digital communication mode, so that auxiliary current is generated in the auxiliary amplifying output stage, and the auxiliary current is similar to the main current in size; it will be appreciated that this auxiliary current is only used to generate a power consumption close to the main current and not for the actual output. In practical use, the main amplifying output stage and the auxiliary amplifying output stage can select the same batch of components of the same manufacturer, so that the main current and the auxiliary current are similar as much as possible. It can be understood that, because the circuit structures and components of the main amplifying output stage and the auxiliary amplifying output stage are identical, the main current and the auxiliary current are similar, and therefore, the first voltage signal and the second voltage signal are identical or similar in size.
Therefore, by adopting the output stage buffer, similar power consumption can be generated in the analog output mode and the digital communication mode, the power consumption difference between the analog output mode and the digital communication mode is reduced, no extra error is introduced in the temperature calibration stage, and the high precision of the whole system is ensured.
Referring to fig. 3, in an embodiment of the present application, the input stage includes:
the grid electrode of the first P-type transistor PM1 is a first bias control end Vbp1, and the source electrode of the first P-type transistor PM1 is connected with a power supply end VDD;
the second P-type transistor PM2 has a gate which is the signal input terminal vin+ and a drain for outputting the second current signal;
the gate of the third P-type transistor PM3 is the output selection end, and the drain is used for outputting the first current signal; the source electrode is connected with the drain electrode of the first P-type transistor PM1 and the source electrode of the second P-type transistor PM 2.
The bias stage includes:
a fourth P-type transistor PM4, the source electrode of which is connected with the power supply end VDD;
the gate of the sixth P-type transistor PM6 is the second bias control terminal Vbp2, and the source is connected to the drain of the fourth P-type transistor PM 4;
the grid electrode of the third N-type transistor NM3 is a fifth bias control end Vbn2, the drain electrode of the third N-type transistor NM3 is a bias output end of the bias stage and is connected with the grid electrode of the fourth P-type transistor PM4 and the drain electrode of the sixth P-type transistor PM 6;
the gate of the first N-type transistor NM1 is the fourth bias control terminal Vbn1, the drain is connected to the source of the third N-type transistor NM3 and the drain of the third P-type transistor PM3 (i.e. the input stage), and the source is grounded.
Specifically, the main amplification output stage includes a main amplification stage for converting the differential current signal into a first voltage signal, and a main output stage for secondarily amplifying and outputting the first voltage signal. It will be appreciated that the main amplification stage is arranged to convert the second current signal and the first current signal copied to the main amplification stage into a first voltage signal.
With continued reference to fig. 3, the main amplification stage includes:
a fifth P-type transistor PM5 having a source connected to the power supply terminal VDD and a gate connected to the drain (i.e., the bias output terminal of the bias stage) of the third N-type transistor NM 3;
a source electrode of the seventh P-type transistor PM7 is connected to the drain electrode of the fifth P-type transistor PM5, a gate electrode is connected in series with the fourth switch S4 and then is connected to the second bias control terminal Vbp2, a gate electrode is also connected in series with the fifth switch S5 and then is connected to the power supply terminal VDD, and a drain electrode is connected to the first input terminal of the main output stage;
the grid of the fourth N-type transistor NM4 is connected with the fifth bias control end Vbn2 after being connected with the tenth switch S10 in series, the grid of the fourth N-type transistor NM4 is also connected with the eleventh switch S11 in series and then grounded, and the drain of the fourth N-type transistor NM4 is connected with the second input end of the main output stage;
the gate of the second N-type transistor NM2 is connected to the fourth bias control terminal Vbn1, the drain is connected to the source of the fourth N-type transistor NM4 and the drain (i.e., input stage) of the second P-type transistor PM2, and the source is grounded.
With continued reference to fig. 3, the main output stage includes:
the source electrode of the zeroth P-type transistor PM0 is connected with the power supply end VDD, and the grid electrode of the zeroth P-type transistor PM0 is connected with the power supply end VDD after being connected with the zeroth switch S0 in series;
the eighth P-type transistor PM8 has a grid connected with a third bias control end Vbp3 after being connected with a sixth switch S6 in series, and has a grid connected with a power end VDD after being connected with a seventh switch S7 in series;
a fifth N-type transistor NM5, the gate of which is connected in series with an eighth switch S8 and then connected to a sixth bias control terminal Vbn3, the gate of which is also connected in series with a ninth switch S9 and then grounded, the drain of which is the first input terminal of the main output stage and is connected to the source of the eighth P-type transistor PM8, the gate of the zeroth P-type transistor PM0 and one end of a zeroth capacitor C0, the other end of the zeroth capacitor C0 being connected to one end of a zeroth resistor R0;
a zero-th N-type transistor NM0, the drain electrode is the output end of the main output stage and is connected to the drain electrode of the zero-th P-type transistor PM0, the other end of the zero-th resistor R0 and one end of the first resistor R1, the gate electrode is the second input end of the main output stage and is connected to the source electrode of the fifth N-type transistor NM5, the drain electrode of the eighth P-type transistor PM8 and one end of the first capacitor C1, the gate electrode is connected in series with the first switch S1 and then grounded, the source electrode is grounded, and the other end of the first capacitor C1 is connected to the other end of the first resistor R1;
the output selection end of the input stage is connected with the output end of the main output stage after being connected with the second switch S2 in series, and the output end of the main output stage is also connected with the digital communication interface after being connected with the third switch S3 in series.
Specifically, the auxiliary amplifying output stage includes an auxiliary amplifying stage for converting the differential current signal into a second voltage signal and an auxiliary output stage for secondarily amplifying the second voltage signal. It will be appreciated that the auxiliary amplifier stage is arranged to convert the second current signal and the first current signal copied to the auxiliary amplifier stage into a second voltage signal.
With continued reference to fig. 3, the auxiliary amplification stage includes:
the source electrode of the ninth P-type transistor PM9 is connected with the power supply end VDD, the grid electrode of the ninth P-type transistor PM9 is connected with the drain electrode (namely the bias output end of the bias stage) of the third N-type transistor NM3 after being connected with the fourteenth switch S14 in series, and the grid electrode of the ninth P-type transistor PM9 is also connected with the power supply end VDD after being connected with the fifteenth switch S15 in series;
a tenth P-type transistor PM10, the source electrode of which is connected to the drain electrode of the ninth P-type transistor PM9, the gate electrode of which is connected in series with the sixteenth switch S16 and then is connected to the second bias control terminal Vbp2, the gate electrode of which is also connected in series with the seventeenth switch S17 and then is connected to the power supply terminal VDD, and the drain electrode of which is connected to the first input terminal of the auxiliary output stage;
the sixth N-type transistor NM6 has a gate connected in series to the twenty-second switch S22 and then connected to the fifth bias control terminal Vbn2, a gate connected in series to the twenty-third switch S23 and then grounded, a drain connected to the source of the seventh N-type transistor NM7 and the drain of the eleventh P-type transistor PM11 (i.e., the second input terminal of the auxiliary output stage), and a source connected to the drain of the second P-type transistor PM2 (i.e., the input stage) for receiving the second current signal.
With continued reference to fig. 3, the auxiliary output stage includes:
the twelfth P-type transistor PM12 has a source connected to the power supply terminal VDD, and a gate connected in series with the twelfth switch S12 and then connected to the power supply terminal VDD;
the eleventh P-type transistor PM11 has a gate connected in series with an eighteenth switch S18 and then connected to the third bias control terminal Vbp3, and a gate connected in series with a nineteenth switch S19 and then connected to the power terminal VDD;
a seventh N-type transistor NM7, the gate is connected in series with the twentieth switch S20 and then connected to the sixth bias control terminal Vbn3, the gate is also connected in series with the twenty-first switch S21 and then grounded, the drain is the first input terminal of the auxiliary output stage and is connected to the source of the eleventh P-type transistor PM11, the gate of the twelfth P-type transistor PM12 and one end of the second capacitor C2, and the other end of the second capacitor C2 is connected to one end of the second resistor R2;
an eighth N-type transistor NM8, the drain electrode is the output end of the auxiliary output stage and is connected to the drain electrode of the twelfth P-type transistor PM12, the other end of the second resistor R2 and one end of the third resistor R3, the gate electrode is the second input end of the auxiliary output stage and is connected to the source electrode of the seventh N-type transistor NM7, the drain electrode of the eleventh P-type transistor PM11 and one end of the third capacitor C3, the gate electrode is further connected in series with the thirteenth switch S13 and then grounded, the source electrode is grounded, and the other end of the third capacitor C3 is connected to the other end of the third resistor R3;
the output selection end of the input stage is connected with the output end of the auxiliary output stage after being connected with the twenty-fourth switch S24 in series.
In the embodiment of the present application, the first P-type transistor PM1 is used to provide the second P-type transistor PM2 and the third P-type transistor PM3 with a quiescent current, which determines the transconductance gm and the noise characteristics of the input stage, and the second P-type transistor PM2 and the third P-type transistor PM3 convert the input voltage signal into a current signal: i=vin+gm.
The first N-type transistor NM1 and the second N-type transistor NM2 are N-tube tail current sources that provide quiescent currents for the bias stage and the main amplification stage when the mode of operation is simulated. The third N-type transistor NM3, the fourth N-type transistor NM4 and the sixth N-type transistor NM6 are N-type cascode transistors, and function to increase the impedance from the drain terminal of each transistor to the ground.
The fourth P-type transistor PM4 is connected in the form of a diode which copies the differential current signal flowing through the bias stage, in particular the first current signal thereof, through the fifth P-type transistor PM5 to the main amplification stage (analog operation mode) and through the ninth P-type transistor PM9 to the auxiliary amplification stage (digital communication mode). It is understood that the differential current signal refers to the current difference between the second P-type transistor PM2 and the third P-type transistor PM3, for example, the second P-type transistor PM2 current increases by 1uA, the third P-type transistor PM3 current decreases by 1uA, and the current difference between the second P-type transistor PM2 and the third P-type transistor PM3 is controlled by the second P-type transistor PM2 gate voltage (i.e., vin+) and the third P-type transistor PM3 gate voltage (Vout).
The sixth P-type transistor PM6, the seventh P-type transistor PM7, and the tenth P-type transistor PM10 are P-type cascode transistors, which function to increase the impedance of each transistor drain to the power supply.
The eighth P-type transistor PM8, the fifth N-type transistor NM5, the zeroth P-type transistor PM0, and the zeroth N-type transistor NM0 constitute a main output stage of the class ab, and can provide a stronger load current driving capability than the conventional class a structure. The eighth P-type transistor PM8 and the fifth N-type transistor NM5 provide bias voltages for the zeroth P-type transistor PM0 and the zeroth N-type transistor NM0, and can also automatically adjust the gate voltages of the zeroth P-type transistor PM0 and the zeroth N-type transistor NM0 when the output current load changes. The zeroth P-type transistor PM0 and the zeroth N-type transistor NM0 serve as output pipes to provide driving capability for the chip load.
The zeroth capacitor C0 and the zeroth resistor R0, the first capacitor C1 and the first resistor R1 which are connected in series are used as compensation devices of the main output stage, so that stable operation of a loop can be ensured.
The eleventh P-type transistor PM11, the seventh N-type transistor NM7, the twelfth P-type transistor PM12, and the eighth N-type transistor NM8 constitute an auxiliary output stage of class ab, wherein the eleventh P-type transistor PM11 and the seventh N-type transistor NM7 supply bias voltages to the twelfth P-type transistor PM12 and the eighth N-type transistor NM 8. The twelfth P-type transistor PM12 and the eighth N-type transistor NM8 serve as output pipes of the auxiliary output stage, and match the currents of the zeroth P-type transistor PM0 and the zeroth N-type transistor NM0 when the chip operates in the digital communication mode.
The second capacitor C2, the second resistor R2, the third capacitor C3 and the third resistor R3 connected in series are compensation devices of the auxiliary output stage, so as to ensure that the loop can stably work, and also to further ensure that the same or similar current is generated in the analog output mode and the digital communication mode, thereby reducing the power consumption difference and the temperature difference in the analog output mode and the digital communication mode.
With the output stage buffer of the present application, in the analog output mode, the switches S2, S4, S6, S8, S10, S12, S13, S15, S17, S19, S21 and S23 are all closed, the switches S0, S1, S3, S5, S7, S9, S11, S14, S16, S18, S20, S22 and S24 are all open, i.e. the main amplification output stage is turned on, the auxiliary amplification output stage is turned off, the current flowing through the zeroth P-type transistor PM0 and the zeroth N-type transistor NM0 is Iout, and the current flowing through the twelfth P-type transistor PM12 and the eighth N-type transistor NM8 is 0. In the digital communication mode, the switches S2, S4, S6, S8, S10, S12, S13, S15, S17, S19, S21 and S23 are all open, the switches S0, S1, S3, S5, S7, S9, S11, S14, S16, S18, S20, S22 and S24 are all closed, i.e. the auxiliary amplification output stage is turned on, the main amplification output stage is turned off, the current flowing through the zeroth P-type transistor PM0 and the zeroth N-type transistor NM0 is 0, and the current flowing through the twelfth P-type transistor PM12 and the eighth N-type transistor NM8 is Iout. In addition, because the current of the digital communication interface is of uA level and can be ignored, the power consumption deviation is small and can be ignored in the two working modes of the analog output mode and the digital communication mode, and no extra error is introduced in the temperature calibration stage, so that the high precision of the whole system is ensured.
It can be understood that the first bias control terminal Vbp1, the second bias control terminal Vbp2, the third bias control terminal Vbp3, the fourth bias control terminal Vbn1, the fifth bias control terminal Vbn2 and the sixth bias control terminal Vbn3 are all configured to receive bias voltage signals, so that the output stage buffer normally works, and specific control logic and timing are well known in the art, which is not improved by the technical scheme of the present application and will not be repeated herein.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional modules is illustrated, and in practical application, the above-described functional allocation may be performed by different functional modules according to needs, i.e. the internal structure of the apparatus is divided into different functional modules to perform all or part of the functions described above. The specific working process of the system, the device and the unit described above may refer to the corresponding process in the foregoing method embodiment, and will not be described herein.
In the several embodiments provided in the present application, it should be understood that the disclosed systems, apparatuses, and methods may be implemented in other manners. The integrated units, if implemented in the form of software functional units and sold or used as separate products, may be stored in a computer readable storage medium. Based on this understanding, the technical solution of the present application may be embodied essentially or in part or all of the technical solution or part of the technical solution that contributes to the prior art, in the form of a software product, which is stored in a storage medium, comprising several instructions for causing a computer device or processor to execute all or part of the steps of the methods described in the various embodiments of the present application.
The foregoing embodiments are only used for describing the technical solution of the present application in detail, but the descriptions of the foregoing embodiments are only used for helping to understand the method and the core idea of the present application, and should not be construed as limiting the present application. Variations or alternatives that are readily contemplated by those skilled in the art within the scope of the present disclosure are intended to be encompassed within the scope of the present disclosure.
Claims (10)
1. An output stage buffer, characterized by: the device comprises an input stage, a bias stage, a main amplification output stage and an auxiliary amplification output stage;
the input stage is provided with a signal input end and an output selection end, wherein the signal input end is used for receiving an input voltage signal, and the input stage is used for converting the input voltage signal into a differential current signal, and the differential current signal comprises a first current signal and a second current signal;
the bias stage is coupled to the input stage and is used for copying the first current signal to the main amplifying output stage in an analog output mode and copying the first current signal to the auxiliary amplifying output stage in a digital communication mode;
the main amplification output stage is used for converting the differential current signal into a first voltage signal when being connected, and simultaneously carrying out secondary amplification on the first voltage signal and outputting the first voltage signal;
the auxiliary amplification output stage is used for converting the differential current signal into a second voltage signal when being connected and carrying out secondary amplification on the second voltage signal;
when in analog output mode, the main amplification output stage is connected and output through the output selection end, when in digital communication mode, the auxiliary amplification output stage is connected through the output selection end, the circuit structures and components of the main amplification output stage and the auxiliary amplification output stage are consistent, the main current and the auxiliary current are similar, the first voltage signal and the second voltage signal are also consistent or similar in size, similar power consumption can be generated in the analog output mode and the digital communication mode, the power consumption difference between the analog output mode and the digital communication mode is reduced, and extra errors are not introduced in the temperature calibration stage.
2. The output stage buffer of claim 1 wherein the input stage comprises:
the grid electrode of the first P-type transistor PM1 is a first bias control end Vbp1, and the source electrode of the first P-type transistor PM1 is connected with a power supply end VDD;
the second P-type transistor PM2 has a gate which is the signal input terminal vin+ and a drain for outputting the second current signal;
the gate of the third P-type transistor PM3 is the output selection end, and the drain is used for outputting the first current signal; the source electrode is connected with the drain electrode of the first P-type transistor PM1 and the source electrode of the second P-type transistor PM 2.
3. The output stage buffer of claim 1 wherein the bias stage comprises:
a fourth P-type transistor PM4, the source electrode of which is connected with the power supply end VDD;
the gate of the sixth P-type transistor PM6 is the second bias control terminal Vbp2, and the source is connected to the drain of the fourth P-type transistor PM 4;
the grid electrode of the third N-type transistor NM3 is a fifth bias control end Vbn2, the drain electrode of the third N-type transistor NM3 is a bias output end of the bias stage and is connected with the grid electrode of the fourth P-type transistor PM4 and the drain electrode of the sixth P-type transistor PM 6;
the gate of the first N-type transistor NM1 is a fourth bias control terminal Vbn1, the drain is connected to the source of the third N-type transistor NM3 and the input stage, and the source is grounded.
4. The output stage buffer of claim 1 wherein: the main amplification output stage comprises a main amplification stage and a main output stage, wherein the main amplification stage is used for converting the differential current signal into a first voltage signal, and the main output stage is used for carrying out secondary amplification on the first voltage signal and outputting the first voltage signal.
5. The output stage buffer of claim 4 wherein the main amplification stage comprises:
a fifth P-type transistor PM5, wherein a source electrode is connected with a power supply end VDD, and a grid electrode is connected with a bias output end of the bias stage;
a source electrode of the seventh P-type transistor PM7 is connected to the drain electrode of the fifth P-type transistor PM5, a gate electrode is connected in series with the fourth switch S4 and then is connected to the second bias control terminal Vbp2, a gate electrode is also connected in series with the fifth switch S5 and then is connected to the power supply terminal VDD, and a drain electrode is connected to the first input terminal of the main output stage;
the grid of the fourth N-type transistor NM4 is connected with the fifth bias control end Vbn2 after being connected with the tenth switch S10 in series, the grid of the fourth N-type transistor NM4 is also connected with the eleventh switch S11 in series and then grounded, and the drain of the fourth N-type transistor NM4 is connected with the second input end of the main output stage;
and the grid electrode of the second N-type transistor NM2 is connected with the fourth bias control end Vbn1, the drain electrode of the second N-type transistor NM4 is connected with the source electrode and the input stage, and is used for receiving the second current signal, and the source electrode is grounded.
6. The output stage buffer of claim 4 wherein the main output stage comprises:
the source electrode of the zeroth P-type transistor PM0 is connected with the power supply end VDD, and the grid electrode of the zeroth P-type transistor PM0 is connected with the power supply end VDD after being connected with the zeroth switch S0 in series;
the eighth P-type transistor PM8 has a grid connected with a third bias control end Vbp3 after being connected with a sixth switch S6 in series, and has a grid connected with a power end VDD after being connected with a seventh switch S7 in series;
a fifth N-type transistor NM5, the gate of which is connected in series with an eighth switch S8 and then connected to a sixth bias control terminal Vbn3, the gate of which is also connected in series with a ninth switch S9 and then grounded, the drain of which is the first input terminal of the main output stage and is connected to the source of the eighth P-type transistor PM8, the gate of the zeroth P-type transistor PM0 and one end of a zeroth capacitor C0, the other end of the zeroth capacitor C0 being connected to one end of a zeroth resistor R0;
a zero-th N-type transistor NM0, the drain electrode is the output end of the main output stage and is connected to the drain electrode of the zero-th P-type transistor PM0, the other end of the zero-th resistor R0 and one end of the first resistor R1, the gate electrode is the second input end of the main output stage and is connected to the source electrode of the fifth N-type transistor NM5, the drain electrode of the eighth P-type transistor PM8 and one end of the first capacitor C1, the gate electrode is connected in series with the first switch S1 and then grounded, the source electrode is grounded, and the other end of the first capacitor C1 is connected to the other end of the first resistor R1;
the output selection end of the input stage is connected with the output end of the main output stage after being connected with the second switch S2 in series, and the output end of the main output stage is also connected with the digital communication interface after being connected with the third switch S3 in series.
7. The output stage buffer of claim 1 wherein: the auxiliary amplifying output stage comprises an auxiliary amplifying stage and an auxiliary output stage, wherein the auxiliary amplifying stage is used for converting the differential current signal into a second voltage signal, and the auxiliary output stage is used for carrying out secondary amplification on the second voltage signal.
8. The output stage buffer of claim 7 wherein the auxiliary amplification stage comprises:
the source electrode of the ninth P-type transistor PM9 is connected with the power supply end VDD, the grid electrode is connected with the bias output end of the bias stage after being connected with the fourteenth switch S14 in series, and the grid electrode is also connected with the power supply end VDD after being connected with the fifteenth switch S15 in series;
a tenth P-type transistor PM10, the source electrode of which is connected to the drain electrode of the ninth P-type transistor PM9, the gate electrode of which is connected in series with the sixteenth switch S16 and then is connected to the second bias control terminal Vbp2, the gate electrode of which is also connected in series with the seventeenth switch S17 and then is connected to the power supply terminal VDD, and the drain electrode of which is connected to the first input terminal of the auxiliary output stage;
the sixth N-type transistor NM6 has a gate connected in series with the twenty-second switch S22 and then connected to the fifth bias control terminal Vbn2, a gate connected in series with the twenty-third switch S23 and then grounded, a drain connected to the second input terminal of the auxiliary output stage, and a source connected to the input stage for receiving the second current signal.
9. The output stage buffer of claim 7 wherein the auxiliary output stage comprises:
the twelfth P-type transistor PM12 has a source connected to the power supply terminal VDD, and a gate connected in series with the twelfth switch S12 and then connected to the power supply terminal VDD;
the eleventh P-type transistor PM11 has a gate connected in series with an eighteenth switch S18 and then connected to the third bias control terminal Vbp3, and a gate connected in series with a nineteenth switch S19 and then connected to the power terminal VDD;
a seventh N-type transistor NM7, the gate is connected in series with the twentieth switch S20 and then connected to the sixth bias control terminal Vbn3, the gate is also connected in series with the twenty-first switch S21 and then grounded, the drain is the first input terminal of the auxiliary output stage and is connected to the source of the eleventh P-type transistor PM11, the gate of the twelfth P-type transistor PM12 and one end of the second capacitor C2, and the other end of the second capacitor C2 is connected to one end of the second resistor R2;
an eighth N-type transistor NM8, the drain electrode is the output end of the auxiliary output stage and is connected to the drain electrode of the twelfth P-type transistor PM12, the other end of the second resistor R2 and one end of the third resistor R3, the gate electrode is the second input end of the auxiliary output stage and is connected to the source electrode of the seventh N-type transistor NM7, the drain electrode of the eleventh P-type transistor PM11 and one end of the third capacitor C3, the gate electrode is further connected in series with the thirteenth switch S13 and then grounded, the source electrode is grounded, and the other end of the third capacitor C3 is connected to the other end of the third resistor R3;
the output selection end of the input stage is connected with the output end of the auxiliary output stage after being connected with the twenty-fourth switch S24 in series.
10. A current sensor, characterized by: comprising a sensor element, a first stage amplifier, a second stage amplifier and an output stage buffer according to any of claims 1-9, in series.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310165919.5A CN115856414B (en) | 2023-02-27 | 2023-02-27 | Output stage buffer and current sensor |
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| CN202310165919.5A CN115856414B (en) | 2023-02-27 | 2023-02-27 | Output stage buffer and current sensor |
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| CN115856414B true CN115856414B (en) | 2023-05-19 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6066985A (en) * | 1998-09-10 | 2000-05-23 | Seiko Epson Corporation | Large swing input/output analog buffer |
| US6377110B1 (en) * | 1999-09-10 | 2002-04-23 | Keystone Thermometrics | Low-cost temperature sensor providing relatively high accuracy, a wide dynamic range and high linearity |
| EP1237279A1 (en) * | 2001-02-21 | 2002-09-04 | STMicroelectronics S.r.l. | Output buffer with automatic control of the switching speed as a function of the supply voltage and temperature |
| KR100495667B1 (en) * | 2003-01-13 | 2005-06-16 | 삼성전자주식회사 | Input output buffer providing analog/digital input mode |
| EP1801975A1 (en) * | 2005-12-21 | 2007-06-27 | STMicroelectronics S.r.l. | Output buffer |
| JP4786605B2 (en) * | 2007-07-19 | 2011-10-05 | ローム株式会社 | Signal amplification circuit and audio system using the same |
| EP2515123B1 (en) * | 2011-04-21 | 2016-07-13 | Abb Ag | Current sensor operating in accordance with the principe of compensation |
| TWI492541B (en) * | 2012-07-05 | 2015-07-11 | Novatek Microelectronics Corp | Output buffer |
| US9991792B2 (en) * | 2014-08-27 | 2018-06-05 | Intersil Americas LLC | Current sensing with RDSON correction |
| CN104237623B (en) * | 2014-10-08 | 2017-04-12 | 武汉弈飞科技有限公司 | High-precision current sensor detecting circuit and detecting method thereof |
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