CN115840075A

CN115840075A - Current detection comparison circuit

Info

Publication number: CN115840075A
Application number: CN202310131504.6A
Authority: CN
Inventors: 姜玉才
Original assignee: Ziguang Tongxin Microelectronics Co Ltd
Current assignee: Ziguang Tongxin Microelectronics Co Ltd
Priority date: 2023-02-17
Filing date: 2023-02-17
Publication date: 2023-03-24
Anticipated expiration: 2043-02-17
Also published as: CN115840075B

Abstract

The application discloses current detection comparison circuit, this current detection comparison circuit is through dividing into a plurality of power tubes with the power tube of electric current circulation to add the timing module, come the closed/open state of a plurality of power tubes of control through fixed switching cycle, thereby make the voltage difference at power tube both ends (current input end and current output end promptly) can enlarge the comparison, realized automatic electric current comparison function, promoted the current comparison precision simultaneously.

Description

Current detection comparison circuit

Technical Field

The application relates to the technical field of circuits, in particular to a current detection comparison circuit.

Background

In modern society, portable devices are more and more, and especially, lithium batteries are used for supplying power. When the capacity of the lithium battery is small, the direction of common efforts of people is formed for prolonging the service life of the battery to the greater extent, reducing power consumption and improving efficiency. For example, the capacity of a storage battery of a TWS Bluetooth headset is about 400mAh, and the capacity of a battery of a single headset is about 50mAh, and in the method of reducing power, except for improving the structure, the working boundary of a circuit module can be further narrowed by improving the current sampling precision, so that the efficiency is improved. Like in the TWS storehouse of charging, for charging for the earphone usually can integrate Boost function, and the current value sampling accuracy of the internal power tube of Boost often can determine the height of efficiency.

There are generally two types of existing solutions. The first is a single-tube single-reference scheme, as shown in fig. 1, which includes a power tube M0, an amplifier I0, a comparator I1, and a resistor R0. The working principle of the first scheme is as follows: when energy is transmitted from A to B or from B to A, namely current is transmitted from A (or B) to B (or A) through the power tube M0, and the product of the conduction impedance and the current is the voltage difference between the points A and B because M0 is in a conduction state. And I0 amplifies the differential pressure between the points A and B, sends the amplified differential pressure to an I1 comparator, and compares the amplified differential pressure with VREF to obtain a current comparison result. When the voltage difference between the A and the B is small, the precision is reduced, and the I0 output voltage cannot represent the voltage difference between the A and the B due to the fact that the input offset voltage of the I0 is close to or lower than the input offset voltage of the I0, so that the judgment result of the I1 output cannot be guaranteed to be correct. For example, when the A, B differential pressure range is below 3mV, and the input mismatch of I0 is 5mV, then I0 will be amplified by 8mV instead of 3mV. If amplification of 3mV is desired, the input mismatch of I0 needs to be reduced below 0.5mV, which inevitably results in an exponential increase in circuit difficulty and complexity as I0 is changed from a conventional structure to a structure with a smaller input mismatch voltage.

Another approach is a single tube multi-reference approach, as shown in fig. 2. The scheme comprises a power tube M0, an amplifier I0, a comparator I1, a resistor R0 and a Switch module Switch. In the scheme, a Switch module is added to the scheme in fig. 2, and the sampling current comparison is performed by using multiple paths of reference voltages: when the current flowing through M0 increases, a higher VREF is selected, and a lower reference voltage is selected. However, the same I0 is still sampled, and the situation that a and B are small in voltage still cannot be solved.

The two schemes are essentially one scheme, and the second scheme is only evolved on the first scheme, does not solve the most fundamental bottleneck, and cannot solve the problem of accuracy reduction caused by the pressure difference of A and B when the current is small.

Disclosure of Invention

The application provides a current detection comparison circuit to can realize making the voltage difference at power tube both ends (current input end and current output end promptly) can enlarge the comparison, realize automatic electric current comparison function, promote the current comparison precision simultaneously.

In a first aspect, the present application provides a current detection comparison circuit, including: the circuit comprises a plurality of power tubes, amplifiers, resistors, comparators, a timing module and a switch module;

one end of each power tube is electrically connected with the current input end through a first node, and the other end of each power tube is electrically connected with the current output end through a second node; the power tube is used for conducting current between the current input end and the current output end and detecting a voltage difference between the current input end and the current output end;

a first input end of the amplifier is electrically connected with the first node, a second input end of the amplifier is electrically connected with the second node, an output end of the amplifier is electrically connected with a negative input end of the comparator, and an output end of the amplifier is grounded through the resistor; the amplifier is used for amplifying the voltage difference between the current input end and the current output end;

the positive input end of the comparator is electrically connected with the reference voltage output end; the output end of the comparator is electrically connected with the input end of the timing module; the comparator is used for comparing the voltage difference between the current input end and the current output end with the reference voltage output by the reference voltage output end;

the output end of the timing module is electrically connected with the input end of the switch module; the timing module is used for timing cycle time;

the switch module is electrically connected with the signal input end of each power tube; the switch module outputs a comparison result signal; the switch module is used for sending a control turning signal to the power tube so as to adjust the conduction impedance of the power tube when the period time is met, and outputting a comparison result of the voltage difference between the current input end and the current output end and the reference voltage output by the reference voltage output end.

Optionally, the timing module includes an edge detection circuit and a pulse transmission circuit.

Optionally, an input end of the edge detection circuit is electrically connected to an output end of the comparator; the input end of the edge detection circuit is electrically connected with the output end of the pulse sending circuit;

the input end of the pulse sending circuit is electrically connected with the output end of the edge detection circuit; and the output end of the pulse sending circuit is electrically connected with the input end of the switch module.

Optionally, the circuit further comprises a first buffer; the output end of the comparator outputs a comparison result of a voltage difference between the current input end and the current output end and the reference voltage output by the reference voltage output end through the first buffer.

Optionally, the circuit further includes a first and gate circuit; the first AND gate circuit comprises a first input end, a second input end, an enable end and an output end;

the output end of the first AND circuit is electrically connected with the input end of the edge detection circuit, and the first output end of the pulse sending circuit is electrically connected with the first input end of the first AND circuit, so that the input end of the edge detection circuit is electrically connected with the first output end of the pulse sending circuit;

the second output end of the pulse sending circuit is electrically connected with the first input end of the first AND gate circuit, the output end of the first AND gate circuit is electrically connected with the input end of the switch module, and the second output end of the pulse sending circuit is electrically connected with the input end of the switch module;

and the output end of the comparator is electrically connected with the second input end of the first AND gate circuit.

Optionally, the edge detection circuit includes a first not gate circuit, a first capacitor, a second buffer, and a first nand gate;

the input end of the first NOT gate circuit is electrically connected with the output end of the comparator; the output end of the first NOT gate circuit is grounded through the first capacitor and is connected with the input end of the second buffer; the first input end of the first NAND gate is electrically connected with the output end of the comparator, the second input end of the first NAND gate is connected with the output end of the second buffer, and the output end of the first NAND gate is electrically connected with the input end of the pulse sending circuit.

Optionally, the pulse transmitting circuit includes a second not-gate circuit, a second capacitor, a third buffer, and a second nand gate;

the input end of the second NOT gate circuit is electrically connected with the output end of the edge detection circuit; the output end of the second NOT gate circuit is grounded through the second capacitor and is connected with the input end of the third buffer; the first input end of the second NAND gate is electrically connected with the output end of the edge detection circuit, the second input end of the second NAND gate is connected with the output end of the third buffer,

the output end of the second NAND gate is electrically connected with the input end of the edge detection circuit; and the output end of the second NAND gate is electrically connected with the input end of the switch module.

Optionally, the switch module includes: a plurality of switch units; each switch unit comprises a trigger and a NAND gate circuit;

for each switch unit, a clock signal input end of a trigger in the switch unit is electrically connected with an output end of the pulse sending circuit, and a Q end of the trigger in the switch unit is electrically connected with a signal input end of a power tube corresponding to the switch unit; and the signal input end of the NAND gate circuit in the switch unit is electrically connected with the Q end of the trigger in the adjacent previous switch unit.

Optionally, the switch module includes: a plurality of switch units; each switch unit comprises a D-type trigger and a NAND gate circuit;

for each switch unit, a clock signal input end of a D-type trigger in the switch unit is electrically connected with an output end of the pulse transmitting circuit, and a QN end of the D-type trigger in the switch unit is electrically connected with a signal input end of a power tube corresponding to the switch unit; and the first input end of the NAND gate circuit in the switch unit is electrically connected with the Q end of the D-type trigger in the adjacent previous switch unit.

Optionally, the current detection comparing circuit includes n power transistors, and the switch module includes n +1 switch units.

It can be seen from the above technical solution that the present application provides a current detection comparison circuit, the current detection comparison circuit includes: the circuit comprises a plurality of power tubes, an amplifier, a resistor, a comparator, a timing module and a switch module. One end of each power tube is electrically connected with the current input end through a first node, and the other end of each power tube is electrically connected with the current output end through a second node; the power tube is used for conducting current between the current input end and the current output end and detecting a voltage difference between the current input end and the current output end; a first input end of the amplifier is electrically connected with the first node, a second input end of the amplifier is electrically connected with the second node, an output end of the amplifier is electrically connected with a negative input end of the comparator, and an output end of the amplifier is grounded through the resistor; the amplifier is used for amplifying the voltage difference between the current input end and the current output end; the positive input end of the comparator is electrically connected with the reference voltage output end; the output end of the comparator is electrically connected with the input end of the timing module; the comparator is used for comparing the voltage difference between the current input end and the current output end with the reference voltage output by the reference voltage output end; the output end of the timing module is electrically connected with the input end of the switch module; the timing module is used for timing cycle time; the switch module is electrically connected with the signal input end of each power tube; the switch module outputs a comparison result signal; the switch module is used for sending a control turning signal to the power tube so as to adjust the conduction impedance of the power tube when the period time is met, and outputting a comparison result of the voltage difference between the current input end and the current output end and the reference voltage output by the reference voltage output end. It can be seen that, this application is through dividing into a plurality of power tubes with the power tube of electric current circulation to add the timing module, come the closed/open state of a plurality of power tubes of control through fixed switching cycle, thereby make the voltage difference of power tube both ends (be electric current input end and electric current output end) can enlarge the comparison, realized automatic electric current comparison function, promoted electric current comparison accuracy simultaneously.

Further effects of the above-mentioned unconventional preferred modes will be described below in conjunction with specific embodiments.

Drawings

In order to more clearly illustrate the embodiments or prior art solutions of the present application, the drawings needed for describing the embodiments or prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present application, and that other drawings can be obtained by those skilled in the art without inventive exercise.

FIG. 1 is a schematic diagram of a circuit structure in the prior art;

FIG. 2 is a schematic diagram of a circuit structure in the prior art;

fig. 3 is a schematic circuit diagram of a current detection comparison circuit according to the present application;

fig. 4 is a schematic circuit diagram of a current detection comparison circuit according to the present application;

fig. 5 is a schematic circuit diagram of a switch module in a current detection comparison circuit according to the present application;

FIG. 6 is a schematic circuit diagram of a switch module in another current detection comparison circuit according to the present application;

fig. 7 is a signal and time diagram of a current detection comparison circuit according to the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be described in detail and completely with reference to the following embodiments and accompanying drawings. It should be apparent that the described embodiments are only a few embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Various non-limiting embodiments of the present application are described in detail below with reference to the accompanying drawings.

Referring to fig. 1, a current detection comparison circuit in an embodiment of the present application is shown, where the current detection comparison circuit includes: a plurality of power transistors (i.e., M1, M2, \ 8230; \ 8230;, mn), an amplifier I0, a resistor R0, a comparator I1, a timing module (i.e., timer), and a Switch module (i.e., switch Logic). Namely, the power tube is divided into M1-Mn with different proportions.

One end of each power tube is electrically connected with the current input end A through a first junction J1, and the other end of each power tube is electrically connected with the current output end B through a second junction J2. The power tube is used for conducting current between the current input end A and the current output end B and detecting voltage difference between the current input end A and the current output end B. It is understood that a plurality of power transistors (i.e., M1, M2, \8230;, mn) are connected in parallel between the current input terminal a and the current output terminal B.

A first input end of the amplifier I0 is electrically connected to the first junction J1, a second input end of the amplifier I0 is electrically connected to the second junction J2, an output end of the amplifier I0 is electrically connected to a negative input end of the comparator I1, and an output end of the amplifier I0 is grounded through the resistor R0; the amplifier I0 is configured to amplify a voltage difference between the current input terminal a and the current output terminal B.

The positive input end of the comparator I1 is electrically connected with the reference voltage output end VERF; the output end of the comparator I1 is electrically connected with the input end of the Timer module Timer. The comparator I1 is configured to compare a voltage difference between the current input terminal a and the current output terminal B with a reference voltage output by the reference voltage output terminal VERF.

The output end of the timing module Timer is electrically connected with the input end of the Switch module Switch Logic. The timing module Timer is used for timing cycle time.

The Switch module Switch Logic is electrically connected to the signal input terminal of each power transistor (e.g., the signal input terminal G1 of the power transistor M1, the signal input terminal G2 of the power transistor M2, \ 8230; \8230;, the signal input terminal Gn of the power transistor Mn). The Switch module Switch Logic outputs a comparison result signal VO; the Switch module Switch Logic is configured to send a control flip signal to the power transistor to adjust the on-resistance of the power transistor when the cycle time is satisfied, and output a comparison result between the voltage difference between the current input terminal a and the current output terminal B and the reference voltage output by the reference voltage output terminal VERF. Therefore, the Switch module Switch Logic can determine which specific power tube is in the open state by timing through the timing module Timer.

In one implementation, as shown in fig. 4, the circuit further includes a first buffer I20; the output terminal of the comparator I1 outputs a comparison result VO of the voltage difference between the current input terminal a and the current output terminal B and the reference voltage output by the reference voltage output terminal VREF through the first buffer I20.

In one implementation, as shown in fig. 3, the Timer module Timer includes an Edge detection circuit (i.e., edge Detect) and a Pulse transmission circuit (i.e., pulse GEN).

As shown in fig. 4, an input terminal of the Edge Detect circuit Edge Detect is electrically connected to an output terminal of the comparator I1; and the input end of the Edge Detect circuit Edge Detect is electrically connected with the output end of the Pulse sending circuit Pulse GEN.

The input end of the Pulse GEN is electrically connected with the output end of the Edge detection circuit Edge Detect; and the output end of the Pulse GEN of the Pulse sending circuit is electrically connected with the input end of the switch module.

In one implementation, as shown in fig. 4, the Edge Detect circuit Edge Detect may include a first not gate circuit I2, a first capacitor C1, a second buffer I3, and a first nand gate I4.

The input end of the first NOT gate circuit I2 is electrically connected with the output end of the comparator I1; the output end of the first not gate circuit I2 is grounded through the first capacitor C1, and is connected with the input end of the second buffer I3; the first input end of the first nand gate I2 is electrically connected with the output end of the comparator I1, the second input end of the first nand gate I2 is connected with the output end of the second buffer I3, and the output end of the first nand gate I2 is electrically connected with the input end of the Pulse GEN of the Pulse sending circuit.

In one implementation, as shown in fig. 4, the Pulse generator GEN includes a second not gate circuit I5, a second capacitor C2, a third buffer I6, and a second nand gate I7.

The input end of the second NOT gate circuit I5 is electrically connected with the output end of the Edge Detect circuit Edge Detect; the output end of the second not-gate circuit I5 is grounded through the second capacitor C2, and is connected with the input end of the third buffer I6; a first input end of the second nand gate I7 is electrically connected to an output end of the Edge Detect circuit Edge Detect, and a second input end of the second nand gate I7 is connected to an output end of the third buffer I6. The output end of the second NAND gate I7 is electrically connected with the input end of the Edge Detect circuit Edge Detect; the output end of the second nand gate I7 is electrically connected with the input end of the Switch Logic.

It can be seen that, as shown in fig. 3, the timing module Timer includes an Edge Detect circuit Edge Detect and a Pulse transmit circuit Pulse GEN. The Edge detection circuit Edge Detect outputs a flag signal D when an Edge of an input signal (C or F) comes, and the Pulse sending circuit Pulse GEN generates a Pulse width signal E with a duration T2 according to the signal D. And the Switch module Switch Logic controls the power tubes M1-Mn according to the E signal. As shown in fig. 7, the delay time generated by the Edge Detect circuit Edge Detect is T1, and the delay time and T2 together form the total time T of the Timer module Timer. Before the voltage of the resistor R0 does not reach VREF, a timing module Timer outputs a control turning signal Mx through a Switch Logic at each interval T, so that the on-resistance between the current input end A and the current output end B is changed, the voltage difference between the two ends of the current input end A and the current output end B is adjusted, and the amplification is carried out through an amplifier I0. In this way, the voltage difference between the current input terminal a and the current output terminal B can be much higher than the input mismatch voltage VREF of the amplifier I0, thereby avoiding inaccurate amplification, and solving the structural bottleneck of fig. 1 and 2. When the voltage of the resistor R0 exceeds VREF for the first time, the comparison result signal VO is the required comparison result. The switching order of the power tubes may set the directivity according to a specific application scenario, and the application is not discussed herein too much. Meanwhile, the current detection comparison of the N-type power tube and the P-type power tube can adopt the circuit structure provided by the embodiment. Regardless of the current, the structure can obtain enough voltage difference between the current input end A and the current output end B, so that the traditional amplifier and comparator circuit can meet the functional requirement without complex and high-cost schemes.

In one implementation, as shown in fig. 5, the Switch module Switch Logic includes: a plurality of switch units; each switch unit comprises a trigger and a NAND gate circuit; in one implementation, if the current detection comparison circuit includes n power transistors, the switch module includes n +1 switch units.

For each switch unit, a clock signal input end of a trigger in the switch unit is electrically connected with an output end of the Pulse GEN, a Q end of the trigger in the switch unit is electrically connected with a signal input end of a power tube corresponding to the switch unit, a signal input end of a NAND gate circuit in the switch unit is electrically connected with a Q end of a trigger in an adjacent previous switch unit, and the trigger in a first switch unit is not connected with the signal input end of any power tube. For example, as shown in fig. 5, a clock signal input terminal CLK of a flip-flop I1_2 in a first switch unit is electrically connected to an output terminal of the Pulse generator GEN, a Q terminal of the flip-flop I1_2 in the switch unit is electrically connected to a signal input terminal of a nand gate circuit I9 in an adjacent next switch unit, a D terminal of the flip-flop I1_2 in the first switch unit is connected to a power supply VDD, an RN terminal of the flip-flop I1_2 in the first switch unit is connected to an output terminal of a nand gate circuit in the first switch unit, and an input terminal of the nand gate circuit in the first switch unit receives an enable signal; the Q end of a trigger I8 in the second switch unit is electrically connected with the signal input G1 end of the power tube M1 corresponding to the switch unit, and the signal input end of a NAND gate circuit I9 in the second switch unit is electrically connected with the Q end of a trigger I1_2 in the adjacent previous switch unit; the connection between the flip-flops and the nand gate circuits in the other switch units is similar to the connection between the flip-flops and the nand gate circuits in the second switch unit, which is not repeated herein.

Fig. 5 includes an amplifier I0, a resistor R0, and a comparator I1, which implement the amplification and comparison of the voltage difference between the current input terminal a and the current output terminal B. The Edge detection circuit Edge Detect can include a first not gate circuit I2, a first capacitor C1, a second buffer I3 and a first NAND gate I4, the Pulse sending circuit Pulse GEN includes a second not gate circuit I5, a second capacitor C2, a third buffer I6 and a second NAND gate I7, the Switch module Switch Logic is composed of n identical Switch units, each Switch unit is composed of a trigger (for example, I8) and a NAND gate circuit (for example, I9), wherein the Q end of the trigger can control the signal input ends G1-Gn of the power tubes M1-Mn. The output signal of the comparator I1 passes through the first buffer I20 to be the final comparison result signal VO. The EN signal is also present to start the Timer function via I1_ 1.

The working process of the whole example is that an EN signal is low level, all triggers are in a reset state, signals G1-Gn are low level, so that M1-Mn are in an open state, impedance between a current input end A and a current output end B is low, therefore, the voltage difference between the current input end A and the current output end B is small, after being amplified by an amplifier I0, the voltage of a resistor R0 is lower than VREF, namely, the output signal of a comparator I1 is low level. In a default state, the Pulse generator GEN outputs a high level, so that only EN at the input of the first and circuit I1_1 is high, the other two signals are high, and the output of the first and circuit I1_1 is a low level. When the EN signal changes from low to high, the E signal output by the first and circuit I1_1 flips to high, triggering the Q terminal of I1_2 to output high level, and leaving I8 in the state of receiving the E signal. And meanwhile, the Edge Detect module is triggered, the I4 outputs a low Pulse width of time T1 and then returns to a high level, as shown in a D signal waveform in FIG. 7, a rising Edge of the D signal waveform immediately triggers Pulse GEN to work, the I7 outputs a low Pulse width of time T2 and then returns to a high level, and the signal is directly output through the I1_1, as shown in an E signal waveform in FIG. 7. The signal E serves as CLK to trigger the signal G1 at the Q end of the I8 to become high level, so that the power tube M1 is closed, meanwhile, the signal E also triggers the Edge Detect module to work, and a new round of timing is repeated. If the output of I1 is still high during time T (i.e., T1+ T2), the output signal G2 of I10 goes high, M2 is turned off, and the next time is started until the output signal VO of I1 goes low and the timing is ended. The system can judge the current numerical value information between the current input end A and the current output end B at the moment according to the VO and G1-Gn signals.

In one implementation, as shown in fig. 6, the switch module includes: a plurality of switch units; each switch unit comprises a D-type trigger and a NAND gate circuit; in one implementation, if the current detection comparison circuit includes n power transistors, the switch module includes n +1 switch units.

For each switch unit, a clock signal input end of a D-type trigger in the switch unit is electrically connected with an output end of the Pulse GEN, and a QN end of the D-type trigger in the switch unit is electrically connected with a signal input end of a power tube corresponding to the switch unit; and the first input end of the NAND gate circuit in the switch unit is electrically connected with the Q end of the D type flip-flop in the previous adjacent switch unit. For example, as shown in fig. 6, the clock signal input terminal CLK of the D-type flip-flop I1_2 in the first switch unit is electrically connected to the output terminal of the Pulse GEN, the Q terminal of the D-type flip-flop I1_2 in the switch unit is electrically connected to the signal input terminal of the nand gate circuit I9 in the next adjacent switch unit, the D terminal of the D-type flip-flop I1_2 in the first switch unit is connected to the power supply VDD, the RN terminal of the D-type flip-flop I1_2 in the first switch unit is connected to the output terminal of the nand gate circuit in the first switch unit, and the input terminal of the nand gate circuit in the first switch unit receives the enable signal; the QN end of a D-type trigger I8 in the second switch unit is electrically connected with the signal input end G1 of the power tube M1 corresponding to the switch unit, the first input end of a NAND gate circuit in the second switch unit is electrically connected with the Q end of a D-type trigger I1_2 in the adjacent previous switch unit, and the signal input end of the NAND gate circuit in the second switch unit receives an enable signal; the QN end of a D-type trigger I10 in the third switch unit is electrically connected with the signal input end G2 of the power tube M2 corresponding to the switch unit, the first input end of a NAND gate circuit in the third switch unit is electrically connected with the Q end of a D-type trigger I8 in the previous adjacent switch unit, and the signal input end of the NAND gate circuit in the third switch unit receives an enable signal; the connection mode of the D-type flip-flops and the nand gate circuits in the other switch units is similar to that of the D-type flip-flops and the nand gate circuits in the second and third switch units, and further description is omitted here.

In accordance with the teachings herein, fig. 6 provides a detection circuit diagram suitable for an N-type power tube. The power supply circuit also comprises Edge _ Detect, pulse _ GEN and Switch Logic, and different from the graph 5, the control signals of the M1-Mn power tubes are provided by the QN end of a D-type trigger.

In one implementation, the circuit further includes a first and gate I1_1; the first and circuit I1_1 includes a first input terminal, a second input terminal, an enable terminal, and an output terminal.

The output end of the first AND gate circuit I1_1 is electrically connected with the input end of the Edge detection circuit Edge Detect, and the first output end of the Pulse sending circuit Pulse GEN is electrically connected with the first input end of the first AND gate circuit I1_1, so that the input end of the Edge detection circuit Edge Detect is electrically connected with the first output end of the Pulse sending circuit Pulse GEN.

The second output end of the Pulse GEN of the Pulse sending circuit is electrically connected with the first input end of the first AND-gate circuit I1_1, the output end of the first AND-gate circuit I1_1 is electrically connected with the input end of the Switch module Switch Logic, and the second output end of the Pulse GEN of the Pulse sending circuit is electrically connected with the input end of the Switch module Switch Logic; the output end of the comparator I1 is electrically connected with the second input end of the first AND gate circuit I1_ 1.

It can be seen from the above technical solution that the present application provides a current detection comparison circuit, which includes: the circuit comprises a plurality of power tubes, an amplifier, a resistor, a comparator, a timing module and a switch module. One end of each power tube is electrically connected with the current input end through a first node, and the other end of each power tube is electrically connected with the current output end through a second node; the power tube is used for conducting current between the current input end and the current output end and detecting a voltage difference between the current input end and the current output end; a first input end of the amplifier is electrically connected with the first node, a second input end of the amplifier is electrically connected with the second node, an output end of the amplifier is electrically connected with a negative input end of the comparator, and an output end of the amplifier is grounded through the resistor; the amplifier is used for amplifying the voltage difference between the current input end and the current output end; the positive input end of the comparator is electrically connected with the reference voltage output end; the output end of the comparator is electrically connected with the input end of the timing module; the comparator is used for comparing the voltage difference between the current input end and the current output end with the reference voltage output by the reference voltage output end; the output end of the timing module is electrically connected with the input end of the switch module; the timing module is used for timing cycle time; the switch module is electrically connected with the signal input end of each power tube; the switch module outputs a comparison result signal; the switch module is used for sending a control turning signal to the power tube so as to adjust the conduction impedance of the power tube when the period time is met, and outputting a comparison result of the voltage difference between the current input end and the current output end and the reference voltage output by the reference voltage output end. It can be seen that, this application is through dividing into a plurality of power tubes with the power tube of electric current circulation to add the timing module, come the closed/open state of a plurality of power tubes of control through fixed switching cycle, thereby make the voltage difference of power tube both ends (be electric current input end and electric current output end) can enlarge the comparison, realized automatic electric current comparison function, promoted electric current comparison accuracy simultaneously. The Total Width of the power tube consisting of M1, M2 \8230- \8230andMn is consistent with that of M0; the Timer function consists of Edge Detect, pulse GEN and a feedback channel C; edge Detect is used for realizing input signal Edge detection, and Pulse GEN is used for realizing Pulse width signal output according to an Edge Detect output signal; the Switch Logic realizes the control of M1-Mn; this application falls into M1~ Mn through the power tube with the electric current circulation to add the timing module Timer including EdgeDetect, pulse GEN, control the closure/open state of M1~ Mn through fixed switching cycle, thereby make the power tube both ends current input end A with the comparison can be enlargied to the electric current numerical value information voltage difference between the current output end B, realized the automatic current function of comparing, promoted the current comparison precision simultaneously.

It should be noted that, in the present specification, all the embodiments are described in a progressive manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments. The above-described apparatus and system embodiments are merely illustrative, in that elements described as separate components may or may not be physically separate. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.

The above description is only for the preferred embodiment, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A current sense comparison circuit, comprising: the circuit comprises a plurality of power tubes, amplifiers, resistors, comparators, a timing module and a switch module;

2. The circuit of claim 1, wherein the timing module comprises an edge detection circuit and a pulse transmission circuit.

3. The circuit of claim 2, wherein an input of the edge detection circuit is electrically connected to an output of the comparator; the input end of the edge detection circuit is electrically connected with the output end of the pulse sending circuit;

4. The circuit of claim 1, further comprising a first buffer; the output end of the comparator outputs a comparison result of the voltage difference between the current input end and the current output end and the reference voltage output by the reference voltage output end through the first buffer.

5. The circuit of claim 2, further comprising a first and gate circuit; the first AND gate circuit comprises a first input end, a second input end, an enable end and an output end;

the output end of the first AND gate circuit is electrically connected with the input end of the edge detection circuit, and the first output end of the pulse sending circuit is electrically connected with the first input end of the first AND gate circuit, so that the input end of the edge detection circuit is electrically connected with the first output end of the pulse sending circuit;

6. The circuit of claim 2, wherein the edge detection circuit comprises a first not gate circuit, a first capacitor, a second buffer, and a first nand gate;

7. The circuit of claim 2, wherein the pulse transmit circuit comprises a second not gate circuit, a second capacitor, a third buffer, and a second nand gate;

8. The circuit of claim 2, wherein the switch module comprises: a plurality of switch units; each switch unit comprises a trigger and a NAND gate circuit;

9. The circuit of claim 2, wherein the switch module comprises: a plurality of switch units; each switch unit comprises a D-type trigger and a NAND gate circuit;

10. The circuit of claim 8 or 9, wherein the current detection comparison circuit comprises n power transistors, and the switch module comprises n +1 switch units.