CN115835624B - Memory and manufacturing method thereof - Google Patents

Memory and manufacturing method thereof Download PDF

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Publication number
CN115835624B
CN115835624B CN202211486602.3A CN202211486602A CN115835624B CN 115835624 B CN115835624 B CN 115835624B CN 202211486602 A CN202211486602 A CN 202211486602A CN 115835624 B CN115835624 B CN 115835624B
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layer
semiconductor
silicon substrate
dielectric layer
groove
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CN115835624A (en
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李永杰
赵超
王桂磊
毛淑娟
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Beijing Superstring Academy of Memory Technology
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Beijing Superstring Academy of Memory Technology
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Priority to CN202211486602.3A priority Critical patent/CN115835624B/en
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Priority to PCT/CN2023/093542 priority patent/WO2024108920A1/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)

Abstract

A memory and a method of manufacturing the same, the memory including a silicon substrate; a plurality of transistors on the silicon substrate and distributed in an array along a row direction and a column direction, the transistors including a semiconductor pillar; adjacent two columns of semiconductor columns are separated by a first groove extending along the column direction, and adjacent two rows of semiconductor columns are separated by a second groove extending along the row direction; grooves extending in the column direction are formed in the silicon substrate below a column of semiconductor columns; and a plurality of bit lines extending along the column direction and arranged at intervals in the row direction, wherein each bit line is positioned in one groove and connected with the bottom end of the semiconductor column, and a heavily doped layer positioned between the bit line and the inner wall of the groove is contacted with at least part of the region of the bit line. According to the memory, the heavily doped layer is arranged, so that ohmic contact is formed between the heavily doped layer and the bit line, contact resistance between the bottom of the semiconductor column and the bit line is reduced, and the performance of the memory is improved.

Description

Memory and manufacturing method thereof
Technical Field
The present invention relates to the field of semiconductor devices, and more particularly, to a memory device and a method for fabricating the same.
Background
Dynamic random access memory (Dynamic Random Access Memory, DRAM) is a common system memory that is widely used in personal computers, notebooks, and consumer electronics. The DRAM stores data in a memory cell having a capacitor and an array transistor. Vertical Gate-All-Around Field Effect Transistor (vgafet) has great advantages in 3D integration and routing, and is often used in DRAM.
Disclosure of Invention
The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the application.
In one aspect, exemplary embodiments of the present application provide a memory comprising: a silicon substrate having an upper surface and a lower surface; a plurality of transistors on the silicon substrate and distributed in an array in a row direction and a column direction on the silicon substrate; each transistor comprises a semiconductor column extending on the upper surface of the silicon substrate along the direction perpendicular to the upper surface; adjacent two columns of semiconductor columns are separated by a first groove extending along the column direction, and adjacent two rows of semiconductor columns are separated by a second groove extending along the row direction; grooves extending in a column direction are formed in the silicon substrate below a column of semiconductor columns; a plurality of bit lines extending along the column direction and arranged at intervals in the row direction, each bit line being located in one of the grooves and connected to the bottom end of the semiconductor column; a plurality of heavily doped layers positioned between the bit lines and the inner walls of the grooves and contacted with at least partial areas of the bit lines; the heavily doped layer is formed of N-type doped silicon.
In an exemplary embodiment, each of the grooves includes a plurality of sub-grooves communicating with each other in a column direction, each of the sub-grooves being located in the silicon substrate under one of the second grooves and extending to under the semiconductor pillars on both sides of the second groove; and the inner wall of each sub-groove is distributed with one heavily doped layer.
In an exemplary embodiment, each of the heavily doped layers extends between the semiconductor pillar and the silicon substrate.
In an exemplary embodiment, the heavily doped layer is disposed on the inner wall surface of the groove or is used as the heavily doped layer by the outermost layer of the inner wall itself of the groove.
In an exemplary embodiment, the material of the heavily doped layer includes silicon heavily doped with phosphorus.
In an exemplary embodiment, an adhesion layer and a barrier layer are further disposed between the bit line and the heavily doped layer, and the adhesion layer is disposed between the heavily doped layer and the barrier layer; the bit line, the adhesion layer and the barrier layer all contain metal elements, and the metal elements are selected from any one or more of titanium, cobalt, nickel, tungsten, copper and aluminum.
In another aspect, exemplary embodiments of the present application provide a method of manufacturing a memory, comprising: providing a silicon substrate having an upper surface and a lower surface;
forming a semiconductor column on the upper surface of the silicon substrate, wherein the semiconductor column extends on the upper surface of the silicon substrate along a direction perpendicular to the upper surface; adjacent two columns of semiconductor columns are separated by a first groove extending along the column direction, and adjacent two rows of semiconductor columns are separated by a second groove extending along the row direction;
forming a groove extending along the column direction in the silicon substrate below a column of the semiconductor columns;
providing a heavily doped layer on the inner wall surface of the groove of the silicon substrate or forming a heavily doped layer on the outermost layer of the groove of the silicon substrate by using a mask on the top surface and the side wall of each semiconductor pillar;
filling bit lines in the grooves to form bit lines extending along the column direction, enabling the heavily doped layers to be in contact with partial areas of the bit lines, and enabling each bit line to be connected with the bottom end of a corresponding column of semiconductor columns;
and forming a grid electrode on the side wall of the semiconductor column.
In an exemplary embodiment, forming a semiconductor pillar on an upper surface of the silicon substrate includes the steps of:
providing a silicon substrate, wherein the silicon substrate is provided with an upper surface and a lower surface, and a first conductive layer, a semiconductor layer and a second conductive layer are sequentially deposited on the upper surface of the silicon substrate;
etching a plurality of first grooves extending along the column direction and spaced along the row direction on the second conductive layer, and enabling the first grooves to penetrate through the second conductive layer, the semiconductor layer, the first conductive layer and the silicon substrate to be exposed, wherein a semiconductor wall is formed between two adjacent first grooves;
filling the first trench with a first dielectric material to form a first dielectric layer;
depositing a second dielectric material over a plurality of the semiconductor walls and the first dielectric layer, forming a second dielectric layer overlying the semiconductor walls and the first dielectric layer;
and etching a plurality of second trenches extending in the row direction and spaced in the column direction on the second dielectric layer, enabling the second trenches to penetrate through the semiconductor walls, the first dielectric layer and the upper surface of the silicon substrate, enabling each semiconductor wall to be spaced into a plurality of semiconductor columns by the plurality of second trenches, and enabling the semiconductor columns and the first dielectric layer between two adjacent second trenches to form blocking walls extending in the row direction, wherein the plurality of blocking walls are spaced by the second trenches in the column direction.
In an exemplary embodiment, forming a groove extending along a column direction in the silicon substrate under a column of the semiconductor pillars specifically includes:
depositing a third dielectric material on the bottom surface of the second groove and the side walls on two sides of the barrier wall to form a third dielectric layer;
removing the third dielectric layer on the bottom surface of the second trench by etching to expose the upper surface of the silicon substrate and the first dielectric layer alternately arranged along the row direction;
etching the exposed silicon substrate to form a groove extending along the column direction under one column of the semiconductor columns.
In an exemplary embodiment, the etching the exposed silicon substrate such that forming a groove extending in a column direction under a column of the semiconductor pillars includes: etching the exposed silicon substrate to form sub-grooves extending to the lower parts of the semiconductor columns at two sides of each second groove in the silicon substrate below each second groove, and forming a groove by mutually communicating a plurality of sub-grooves arranged along the column direction.
In an exemplary embodiment, using a mask on the top surface and the side wall of each semiconductor pillar, a heavily doped layer is provided on the inner wall surface of the recess of the silicon substrate or a heavily doped layer is formed on the outermost layer of the recess itself of the silicon substrate, specifically including:
selectively epitaxially growing N-type heavily doped silicon on the inner wall of the groove by using the second dielectric layer on the top surface of the baffle wall and the third dielectric layer on the side wall as masks to form a heavily doped layer; the N-type heavily doped silicon is obtained by doping substances to be doped into the silicon in a plasma doping mode; or alternatively, the first and second heat exchangers may be,
depositing a substance to be doped on the inner wall of the groove in the silicon substrate by adopting an atomic layer deposition method, and diffusing the substance to be doped into the silicon substrate by adopting heating driving; or alternatively, the first and second heat exchangers may be,
and converting the dopant to be doped into vapor, and diffusing the vapor of the dopant to be doped onto the inner wall of the groove by adopting a sub-atmospheric pressure chemical vapor deposition method.
In an exemplary embodiment, forming a gate on a sidewall of the semiconductor pillar specifically includes:
removing the third dielectric layers on the side walls at two sides of the barrier wall by etching;
depositing a fourth dielectric material on the bottom surface of the second groove, the side walls on the two sides and the top surface of the baffle wall to form a fourth dielectric layer;
depositing a fifth dielectric material in the second trench to form a fifth dielectric layer;
etching the fifth dielectric layer in the second groove back to a certain height, and removing the fourth dielectric layer at the upper parts of the side walls at the two sides of the barrier wall;
depositing a sixth dielectric material on the surface of the fifth dielectric layer in the second groove and on the side walls of the two sides of the barrier wall to form a sixth dielectric layer;
filling a seventh dielectric material in the second groove to form a seventh dielectric layer;
removing the second dielectric layer on the top surface of the barrier wall by etching, and etching the sixth dielectric layer on the side walls on two sides of the barrier wall and the first dielectric layer between two adjacent semiconductor columns back to a certain height, so that space is vacated around the semiconductor columns;
depositing a gate insulating layer on the side wall of the semiconductor column, and filling a gate material in the space around the semiconductor column;
and etching the gate insulating layer and the gate material back to a certain height, wherein the rest gate material forms a gate.
In another aspect, exemplary embodiments of the present application provide an electronic device comprising a memory as described in any one of the above.
In an exemplary embodiment, the electronic device includes a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power source.
According to the memory, the groove is excavated in the silicon substrate below the semiconductor column, the heavily doped layer grows on the inner wall surface of the groove or forms the heavily doped layer at the outermost layer of the groove of the silicon substrate, ohmic contact is formed between the heavily doped layer and the bit line, contact resistance between the bottom of the semiconductor column and the bit line is reduced, and the performance of the transistor is enhanced.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. Other advantages of the present application may be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
The accompanying drawings are included to provide an understanding of the technical aspects of the present application, and are incorporated in and constitute a part of this specification, illustrate the technical aspects of the present application and together with the examples of the present application, and not constitute a limitation of the technical aspects of the present application.
FIG. 1 is a perspective schematic view of a memory provided in accordance with an exemplary embodiment of the present application;
FIG. 2 is a schematic partial enlarged view at M in FIG. 1;
FIG. 3A is a schematic perspective view of an intermediate product resulting from an intermediate step of a method of manufacturing a memory provided in accordance with an exemplary embodiment of the present application;
FIG. 3B is a schematic cross-sectional view taken along the A-A direction in FIG. 3A;
FIG. 3C is a schematic cross-sectional view taken along the direction B-B in FIG. 3A;
FIG. 4A is a schematic perspective view of an intermediate product resulting from an intermediate step of a method of manufacturing a memory provided in accordance with an exemplary embodiment of the present application;
FIG. 4B is a schematic cross-sectional view taken along the A-A direction in FIG. 4A;
FIG. 5A is a schematic perspective view of an intermediate product resulting from an intermediate step of a method of manufacturing a memory provided in accordance with an exemplary embodiment of the present application;
FIG. 5B is a schematic cross-sectional view taken along the A-A direction in FIG. 5A;
FIG. 6A is a schematic perspective view of an intermediate product resulting from an intermediate step of a method of manufacturing a memory provided in accordance with an exemplary embodiment of the present application;
FIG. 6B is a schematic cross-sectional view taken along the A-A direction in FIG. 6A;
FIG. 6C is a schematic cross-sectional view taken along the direction B-B in FIG. 6A;
FIG. 7A is a schematic perspective view of an intermediate product resulting from an intermediate step of a method of manufacturing a memory provided in accordance with an exemplary embodiment of the present application;
FIG. 7B is a schematic cross-sectional view taken along the direction B-B in FIG. 7A;
FIG. 8A is a schematic perspective view of an intermediate product resulting from an intermediate step of a method of manufacturing a memory provided in accordance with an exemplary embodiment of the present application;
FIG. 8B is a schematic cross-sectional view taken along the direction B-B in FIG. 8A;
FIG. 9A is a schematic perspective view of an intermediate product resulting from an intermediate step of a method of manufacturing a memory provided in accordance with an exemplary embodiment of the present application;
FIG. 9B is a schematic cross-sectional view taken along the direction B-B in FIG. 9A;
FIG. 10A is a schematic perspective view of an intermediate product resulting from an intermediate step of a method of manufacturing a memory provided in accordance with an exemplary embodiment of the present application;
FIG. 10B is a schematic partial enlarged view at N in FIG. 10A;
FIG. 11A is a schematic perspective view of an intermediate product resulting from an intermediate step of a method of manufacturing a memory provided in accordance with an exemplary embodiment of the present application;
FIG. 11B is a schematic cross-sectional view taken along the direction B-B in FIG. 11A;
FIG. 12A is a schematic perspective view of an intermediate product resulting from an intermediate step of a method of manufacturing a memory provided in accordance with an exemplary embodiment of the present application;
FIG. 12B is a schematic cross-sectional view taken along the direction B-B in FIG. 12A;
FIG. 13A is a schematic perspective view of an intermediate product resulting from an intermediate step of a method of manufacturing a memory provided in accordance with an exemplary embodiment of the present application;
FIG. 13B is a schematic cross-sectional view taken along the direction B-B in FIG. 13A;
FIG. 14A is a schematic perspective view of an intermediate product resulting from an intermediate step of a method of manufacturing a memory provided in accordance with an exemplary embodiment of the present application;
FIG. 14B is a schematic cross-sectional view taken along the direction B-B in FIG. 14A;
FIG. 15A is a schematic perspective view of an intermediate product resulting from an intermediate step of a method of manufacturing a memory provided in accordance with an exemplary embodiment of the present application;
FIG. 15B is a schematic cross-sectional view taken along the direction B-B in FIG. 15A;
FIG. 16 is a schematic cross-sectional view of an intermediate product resulting from an intermediate step of a method of manufacturing a memory provided in accordance with an exemplary embodiment of the present application;
FIG. 17A is a schematic perspective view of an intermediate product resulting from an intermediate step of a method of manufacturing a memory provided in accordance with an exemplary embodiment of the present application;
FIG. 17B is a schematic cross-sectional view taken along the direction B-B in FIG. 17A;
FIG. 18A is a schematic perspective view of an intermediate product resulting from an intermediate step of a method of manufacturing a memory provided in accordance with an exemplary embodiment of the present application; and
fig. 18B is a schematic cross-sectional view taken along the direction B-B in fig. 18A.
Reference numerals illustrate:
1-a memory; 10-a silicon substrate; 20-a first conductive layer;
30-a semiconductor layer; 40-a second conductive layer; 50-a first trench;
60-semiconductor walls; 70-a second trench; 80-semiconductor pillars;
90-retaining wall; 91-groove; 92-sub-grooves;
93-heavily doped layer; 94-an adhesion layer; 95-barrier layer;
96-bit lines; 100-a first dielectric layer; 200-a second dielectric layer;
300-a third dielectric layer; 400-a fourth dielectric layer; 500-fifth dielectric layers;
600-sixth dielectric layers; 700-seventh dielectric layer.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in detail hereinafter with reference to the accompanying drawings. It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be arbitrarily combined with each other.
The embodiments herein may be embodied in a number of different forms. One of ordinary skill in the art will readily recognize the fact that the implementations and content may be transformed into a wide variety of forms without departing from the spirit and scope of the present application. Therefore, the present application should not be construed as being limited to the following description of the embodiments. Embodiments and features of embodiments in this application may be combined with each other arbitrarily without conflict.
The scale of the drawings in this application may be referred to in the actual process, but is not limited thereto. For example: the width-to-length ratio of the semiconductor layer, the thickness and the spacing of each film layer can be adjusted according to actual needs. The drawings described in the present application are only schematic in structure, and one mode of the present application is not limited to the shapes or the numerical values shown in the drawings, etc.
In the present specification, for convenience, words such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, which indicate an azimuth or a positional relationship, are used to describe positional relationships of constituent elements with reference to the drawings, only for convenience of description and simplification of the description, and do not indicate or imply that the apparatus or elements to be referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus should not be construed as limiting the present application. The positional relationship of the constituent elements is appropriately changed according to the direction in which the respective constituent elements are described. Therefore, the present invention is not limited to the words described in the specification, and may be appropriately replaced according to circumstances.
In this specification, the terms "disposed," "connected," and "connected" are to be construed broadly, unless explicitly stated or limited otherwise. For example, it may be a fixed connection, a removable connection, or an integral connection; may be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intermediate members, or may be in communication with the interior of two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.
In the description of the present application, ordinal numbers such as "first", "second", etc., are provided to avoid intermixing of constituent elements, and are not intended to be limiting in terms of number.
In this specification, "film" and "layer" may be exchanged with each other. For example, the "metal layer" may sometimes be replaced with a "metal film".
In the process of forming a Buried Bit Line (BBL), since a chemical substance forming the Bit Line is easily reacted with a silicon substrate, a barrier layer may be first provided in a groove to prevent the reaction from occurring, but the barrier layer has poor adhesiveness to the silicon substrate and is easily peeled off, so that an adhesive layer is provided between the silicon substrate and the barrier layer. The existing bit line generally adopts tungsten/cobalt/ruthenium/molybdenum as main conductive material, titanium, cobalt, nickel and tantalum as adhesion layer, taN (titanium nitride), tiN (titanium nitride) and the like as barrier layer for preventing tungsten from diffusing into silicon.
However, the inventor of the present application found that if the manufacturing method of disposing the adhesion layer and the barrier layer between the silicon substrate and the bit line is applied to the subsequent process at a temperature exceeding 400 ℃, titanium, cobalt, nickel or tantalum metal serving as the adhesion layer diffuses into the silicon substrate to react with silicon, and after the metal diffusion is completed, vacancies remain in the original places, so that TiN (titanium nitride) or TaN in the barrier layer diffuses into the vacancies to cause holes in the microstructure of the adhesion layer, and at this time, tungsten metal of the bit line can contain fluorine elements and the like, so that fluorine elements enter the holes to react with silicon to cause damage to the bit line structure, thereby not only increasing the resistance of the bit line itself, but also increasing the contact resistance between the bit line and the semiconductor pillar, and impairing the performance of the transistor.
Exemplary embodiments of the present application provide a memory including: a silicon substrate having an upper surface and a lower surface; a plurality of transistors on the silicon substrate and distributed in an array in a row direction and a column direction on the silicon substrate; each transistor comprises a semiconductor column extending on the upper surface of the silicon substrate along the direction perpendicular to the upper surface; adjacent two columns of semiconductor columns are separated by a first groove extending along the column direction, and adjacent two rows of semiconductor columns are separated by a second groove extending along the row direction; grooves extending in the column direction are arranged in the silicon substrate below a column of semiconductor columns; a plurality of bit lines extending along the column direction and arranged at intervals in the row direction, each bit line being located in one of the grooves and connected to the bottom end of the semiconductor pillar; and the heavily doped layer is positioned between the bit line and the inner wall of the groove and is contacted with at least part of the area of the bit line.
In an exemplary embodiment, each of the grooves includes a plurality of sub-grooves communicating with each other in a column direction, each of the sub-grooves being located in the silicon substrate under one of the second grooves and extending to under the semiconductor pillars on both sides of the second groove; and the inner wall of each sub-groove is distributed with one heavily doped layer.
In the description of the present application, the term "column direction" is defined as the extending direction of the bit lines of the memory; the term "row direction" is perpendicular to the column direction and the plane formed by the row direction and the column direction is parallel to the silicon substrate of the memory.
In the description of the present application, the term "heavily doped" is defined as a doping concentration of the substance to be doped of 1.0E19cm -3 -1.0E21cm -3 Within a range of (2).
Fig. 1 is a perspective schematic view of a memory provided in accordance with an exemplary embodiment of the present application. As shown in fig. 1, the memory 1 includes a silicon substrate 10 and a plurality of transistors arranged in an array in a row direction and a column direction on the silicon substrate 10, which are located on the silicon substrate 10. Each transistor includes a semiconductor pillar 80, the semiconductor pillar 80 extending on the upper surface of the silicon substrate 10 in a direction perpendicular to the upper surface. Adjacent two columns of semiconductor pillars 80 are spaced apart by the first trench 50 extending in the column direction, and adjacent two rows of semiconductor pillars are spaced apart by the second trench 70 extending in the row direction; a groove 91 extending in the column direction is provided in the silicon substrate 10 under a column of semiconductor pillars 80.
Each memory further includes a plurality of bit lines 96 extending in the column direction and arranged at intervals in the row direction, each bit line 96 being located in one of the recesses 91 and connected to the bottom end of the semiconductor pillar;
each memory device further includes a plurality of heavily doped layers 93 between the bit lines 96 and the inner walls of the recesses 91, in contact with at least a portion of the bit lines 96; the heavily doped layer 93 is formed of N-type heavily doped silicon.
Fig. 2 is a schematic partial enlarged view at M in fig. 1. As shown in fig. 2, the groove 91 includes a plurality of sub-grooves 92 communicating with each other in the column direction. Each sub-recess 92 is located in the silicon substrate 10 below one of the second trenches 70 and extends to below the semiconductor pillars on both sides of that second trench. A heavily doped layer 93 is distributed on the inner wall of each sub-groove 92.
Exemplary embodiments of the present application also provide a method of manufacturing a memory. The memory provided by the exemplary embodiments of the present application can be obtained by this method. The manufacturing method may include the steps of:
s10: providing a silicon substrate 10, wherein the silicon substrate 10 has an upper surface and a lower surface; sequentially depositing a first conductive layer 20, a semiconductor layer 30, and a second conductive layer 40 on an upper surface of the silicon substrate 10; for example, it is possible to deposit on a silicon substrateA thick N-type heavily doped silicon epitaxial layer as a first conductive layer 20 +.>A thick P-type lightly doped silicon epitaxial layer as semiconductor layer 30->A thick N-type heavily doped silicon epitaxial layer serves as the second conductive layer 40.
S20: a plurality of first trenches 50 (i.e., bit line trenches BL trench) extending in the column direction and spaced apart in the row direction are etched on the second conductive layer 40, and the first trenches 50 penetrate the second conductive layer 40, the semiconductor layer 30, the first conductive layer 20, and the inside of the silicon substrate 10, and a semiconductor wall 60 is formed between two adjacent first trenches 50, as shown in fig. 3A to 3C.
S30: the first trench 50 is filled with a first dielectric material to form a first dielectric layer 100, and a Chemical Mechanical Planarization (CMP) process is used to make the upper surface of the first dielectric layer 100 flush with the upper surface of the second conductive layer 40, i.e., two adjacent semiconductor walls 60 are separated by the first dielectric layer 100, as shown in fig. 4A and 4B.
S40: a second dielectric material is deposited over the plurality of semiconductor walls 60 and the first dielectric layer 100 to form a second dielectric layer 200 that covers the semiconductor walls 60 and the first dielectric layer 100, as shown in fig. 5A and 5B.
S50: a plurality of second trenches 70 (i.e., word line trenches WL trench) extending in the row direction and spaced apart in the column direction are etched on the second dielectric layer 200, and the second trenches 70 penetrate the semiconductor wall 60 and the first dielectric layer 100 and expose the upper surface of the silicon substrate 10. The plurality of second trenches 70 space each semiconductor wall 60 into a plurality of semiconductor pillars 80, each semiconductor pillar 80 comprising a first conductive layer 20, a semiconductor layer 30, and a second conductive layer 40. The semiconductor pillars 80 and the first dielectric layer 100 between two adjacent second trenches 70 constitute barrier walls 90 extending in the row direction, and the plurality of barrier walls 90 are separated by the second trenches 70 in the column direction, as shown in fig. 6A to 6C.
S60: a third dielectric material is deposited on the bottom surface of the second trench 70 and on the side walls of the barrier wall 90 to form a third dielectric layer 300, and a third dielectric material is also deposited on the top surface of the barrier wall 90 to form a third dielectric layer 300 (not shown), as shown in fig. 7A and 7B.
S70: the third dielectric layer 300 on the bottom surface of the second trench 70 is removed by etching to expose the upper surface of the silicon substrate 10 and the first dielectric layer 100 alternately arranged in the row direction, while the third dielectric layer 300 on the top surface of the barrier wall 90 is removed by etching, as shown in fig. 8A and 8B.
S80: the exposed silicon substrate 10 is etched such that grooves 91 extending in the column direction are formed under a column of the semiconductor pillars 80, each groove 91 may include a plurality of sub-grooves 92 communicating with each other in the column direction, the sub-grooves 90 being located in the silicon substrate 10 under one second trench 70 and extending under the semiconductor pillars 80 on both sides of the second trench 70, the shape of the sub-grooves 92 in a longitudinal section on a plane perpendicular to the second trench 70 may be bowl-shaped, oval-shaped, "sigma (sigma) shaped", diamond-shaped, or the like, as shown in fig. 9A and 9B.
S90: a heavily doped layer 93 is epitaxially grown on the inner wall of the silicon substrate 10 or the outermost layer of the silicon substrate 10 itself within each sub-recess 92 using the second dielectric layer 200 on the top surface of the barrier wall 90 and the third dielectric layer 300 on the side wall as a mask, as shown in fig. 10A and 10B.
Specifically, the method of forming the heavily doped layer 93 may include:
s910: a substance to be doped (for example, phosphorus) is doped into silicon by means of plasma doping, and then a heavily doped layer 93 formed of phosphorus-heavily doped silicon is epitaxially grown on the inner wall surface of the silicon substrate 10 within each sub-recess 92 by selective epitaxial growth.
Alternatively, the method of forming the heavily doped layer 93 may include:
s920: depositing a substance to be doped (for example, phosphorus) on the inner wall surface of the silicon substrate 10 in each sub-groove 92 by an atomic layer deposition (Atomic Layer Deposition, ALD) method, and then diffusing the substance to be doped into the silicon substrate 10 by a heat driving manner, thereby forming a heavily doped layer 93 formed of phosphorus-heavily doped silicon at the outermost layer of the silicon substrate 10 itself;
alternatively, the method of forming the heavily doped layer 93 may include:
s930: the substance to be doped (for example, phosphorus) is converted into a gas, and the vapor of the substance to be doped (for example, phosphorus vapor) is diffused into the outermost layer of the silicon substrate 10 itself by using nitrogen or other inert gas as a carrier gas, using a sub-atmospheric pressure chemical vapor deposition (SACVD) method, following the principle of the first law of fick, thereby forming a heavily doped layer 93 formed of phosphorus-heavily doped silicon at the outermost layer of the silicon substrate 10 itself.
During the formation of the heavily doped layer 93, the second dielectric layer 200 on the top surface of the barrier wall 90 and the third dielectric layer 300 on the sidewall may act as a hard mask to prevent the penetration of the species to be doped into the semiconductor pillar 80.
S100: filling the second trench 70 and the groove 91 with bit line material and bringing the heavily doped layer 93 into contact with a portion of the bit line material in the groove 91 as shown in fig. 11A and 11B;
illustratively, it may include: an adhesion layer material, a barrier layer material are sequentially deposited on the walls of the second trench 70 and the recess 91, and then a bit line material is filled in the second trench 70 and the recess 91, and the adhesion layer material, the barrier layer material and the bit line material are sequentially covered on the top surface of the barrier wall 90, and the heavily doped layer 93 is brought into contact with at least a partial region of at least one of the bit line material, the adhesion layer material and the barrier layer material in the recess 91.
S110: the material in the second trench 70 and the top surface of the barrier wall 90 is removed by etching back, and the material in the recess 91 is retained, so that an adhesion layer 94 is formed from the adhesion layer material, a barrier layer 95 is formed from the barrier layer material, and a bit line 96 is formed from the bit line material in the recess 91, as shown in fig. 12A and 12B.
S120: the third dielectric layer 300 on the sidewalls of both sides of the barrier wall 90 is removed by wet etching, which can eliminate the risk of metal contamination (the third dielectric layer is exposed to the adhesion layer material such as Ti/Co/Ni/ta+tin/tan+tungsten/cobalt/rubidium/molybdenum, the barrier layer material and the bit line material, and there may be metal residues in the third dielectric material of the third dielectric layer due to metal diffusion), as shown in fig. 13A and 13B.
S130: depositing a fourth dielectric material on the bottom surface of the second trench 70, the side walls of the barrier wall 90, and the top surface of the second dielectric layer 200 of the barrier wall 90 to form a fourth dielectric layer 400; and depositing a fifth dielectric material in the second trench 70, followed by CMP planarization, forming a fifth dielectric layer 500, as shown in fig. 14A and 14B.
S140: the fifth dielectric layer 500 in the second trench 70 is etched back to a certain height (the lower end of the gate can be determined by the height) as shown in fig. 15A and 15B.
S150: the fourth dielectric layer 400 on the top surface of the second dielectric layer 200 of the barrier wall 90 is etched and removed, and the fourth dielectric layer 400 on the sidewalls of the two sides of the barrier wall 90 is etched to be level with the height of the fifth dielectric layer 500, as shown in fig. 16.
S160: depositing a sixth dielectric material on the surface of the fifth dielectric layer 500, the top surface of the barrier wall 90 and the side walls on both sides in the second trench 70 to form a sixth dielectric layer 600, and removing the sixth dielectric layer 600 on the top surface of the barrier wall 90;
s170: the seventh dielectric material is filled in the second trench 70 to form a seventh dielectric layer 700, and the seventh dielectric layer 700 is made to cover the entire surface of the silicon substrate formed in step S160, followed by CMP planarization, as shown in fig. 17A and 17B.
S180: the second dielectric layer 200 on the top surface of the barrier wall 90 and the sixth dielectric layer 600 on the sidewalls of both sides of the barrier wall 90 are removed by etching, and the first dielectric layer 100 (not shown) between two adjacent semiconductor pillars 80 is etched back to a certain height, thereby freeing up space around the semiconductor pillars 80, as shown in fig. 18A and 18B.
S190: a gate insulating layer (e.g., tiN) and a gate material (e.g., a metal such as tungsten) are sequentially deposited on the sidewalls of the semiconductor pillars 80, and the gate insulating layer and the gate material are made to fill the space around the semiconductor pillars 80 and cover the entire surface of the silicon substrate obtained in step S180, as shown in fig. 1.
S200: etching the gate insulating layer and the gate material back to a certain height, wherein the remaining gate material forms a gate, and two ends of the gate can extend to the first conductive layer 20 and the second conductive layer 40 respectively; each semiconductor pillar 80 and the gate surrounding the semiconductor pillar 80 constitute a transistor.
The method for manufacturing the memory may further include:
s210: after forming the gate electrode, an interlayer dielectric layer ILD (inter-layer dielectric) covering the gate electrode and the first and second conductive layers 100 and 200 is deposited in the space between the respective film layers, and is prepared for the subsequent fabrication of a Contact hole (Node Contact).
In the process of forming the embedded bit line, the heavily doped layer formed by N-type heavily doped silicon is formed on the inner wall of the silicon substrate or the outermost layer in the silicon substrate, so that the diffusion of metal in the adhesion layer into the silicon is inhibited, and then the reaction of fluorine and other elements in the bit line and the silicon is inhibited, the structure of the bit line is kept intact, and meanwhile, ohmic contact is formed between the heavily doped layer and the metal bit line, so that the contact resistance between the bottom of the semiconductor column and the bit line is reduced, and the performance of the transistor is enhanced.
In an exemplary embodiment of the present application, either one or both of the first trench and the second trench may be formed using a Self-aligned dual imaging (Self-aligned Double Patterning, SADP) process.
In an exemplary embodiment of the present application, the groove may be formed by performing side etching on the first trench through wet etching.
In an exemplary embodiment of the present application, the first to seventh dielectric layers may each be independently formed using an Atomic Layer Deposition (ALD) or a chemical vapor deposition (Chemical Vapor Deposition, CVD) process.
In an exemplary embodiment of the present application, the methods of depositing the first dielectric material to the seventh dielectric material may each be independently selected from any one of ALD and CVD.
In an exemplary embodiment of the present application, the first to seventh dielectric materials may be selected from silicon nitride, silicon oxide, and the like.
In an embodiment of the present application, after any one of the first dielectric material to the seventh dielectric material is deposited, the formed dielectric layer may be planarized using a CMP process, for example, after the second dielectric material is filled in the second trench in step S200, the dielectric layer formed on the surface of the device may be planarized using a CMP process.
The embodiment of the application provides a memory, which can be obtained by the manufacturing method of the memory provided by the embodiment of the application.
In the embodiment of the present application, the material of the gate may be selected from any one or more of conductor materials formed by group IVA elements, for example, the material of the gate may be selected from any one or more of polysilicon, polysilicon germanium, and the like.
In embodiments of the present application, the material of the gate insulating layer may be selected from silicon oxide (e.g., siO 2 ) Hafnium oxide (e.g., hfO) 2 ) Zirconium oxide (e.g., zrO) and aluminum oxide (e.g., al) 2 O 3 ) Any one or more of the following. The gate insulating layer may have a single-layer structure or a multi-layer structure, and may include, for example, a two-layer structure formed of silicon oxide and hafnium oxide, wherein the silicon oxide layer is in contact with the channel region, and the hafnium oxide layerIs in contact with the gate. The thickness of the gate insulating layer may be set according to practical electrical requirements, for example, may be 2nm to 5nm.
In embodiments of the present application, the memory may be a transistor-containing device, such as a dynamic random access memory (Dynamic Random Access Memory, DRAM), a magnetic random access memory (Magnetic Random Access Memory, MRAM), or the like.
The embodiment of the application also provides electronic equipment, which comprises the memory provided by the embodiment of the application.
In an embodiment of the present application, the electronic device may include a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.
Although the embodiments disclosed in the present application are described above, the embodiments are only used for facilitating understanding of the present application, and are not intended to limit the present application. Any person skilled in the art to which this application pertains will be able to make any modifications and variations in form and detail of implementation without departing from the spirit and scope of the disclosure, but the scope of the application is still subject to the scope of the claims that follow.

Claims (9)

1. A method of manufacturing a memory, comprising:
providing a silicon substrate having an upper surface and a lower surface;
sequentially depositing a first conductive layer, a semiconductor layer and a second conductive layer on the upper surface of the silicon substrate;
etching a plurality of first grooves extending along the column direction and spaced along the row direction on the second conductive layer, and enabling the first grooves to penetrate through the second conductive layer, the semiconductor layer, the first conductive layer and the silicon substrate to be exposed, wherein a semiconductor wall is formed between two adjacent first grooves;
filling the first trench with a first dielectric material to form a first dielectric layer;
depositing a second dielectric material over a plurality of the semiconductor walls and the first dielectric layer, forming a second dielectric layer overlying the semiconductor walls and the first dielectric layer;
etching a plurality of second trenches extending in the row direction and spaced in the column direction on the second dielectric layer, enabling the second trenches to penetrate through the semiconductor walls and the first dielectric layer and expose the upper surface of the silicon substrate, enabling each semiconductor wall to be spaced into a plurality of semiconductor columns by the plurality of second trenches, enabling the semiconductor columns and the first dielectric layer between two adjacent second trenches to form blocking walls extending in the row direction, and enabling the blocking walls to be spaced by the second trenches in the column direction;
depositing a third dielectric material on the bottom surface of the second groove and the side walls on two sides of the barrier wall to form a third dielectric layer;
removing the third dielectric layer on the bottom surface of the second trench by etching to expose the upper surface of the silicon substrate and the first dielectric layer alternately arranged along the row direction;
etching the exposed silicon substrate so that grooves extending in the column direction are formed in the silicon substrate below a column of the semiconductor pillars, each groove comprising a plurality of sub-grooves which are mutually communicated in the column direction, each sub-groove being located in the silicon substrate below one of the second trenches and extending to below the semiconductor pillars on both sides of the second trench;
providing a heavily doped layer on the inner wall surface of each sub-groove or forming the heavily doped layer by the outermost layer of the inner wall of the sub-groove by using masks on the top surface and the side wall of the semiconductor column;
filling bit line materials in the plurality of mutually communicated sub-grooves to form bit lines extending along the column direction, wherein the bit lines are connected with the bottom ends of the semiconductor columns, and the heavily doped layers are in contact with the bit lines;
and forming a grid electrode on the side wall of the semiconductor column.
2. The method of manufacturing of claim 1, wherein the material of the heavily doped layer comprises silicon heavily doped with phosphorus.
3. The manufacturing method according to claim 1, wherein an adhesion layer and a barrier layer are further provided between the bit line and the heavily doped layer, and the adhesion layer is provided between the heavily doped layer and the barrier layer; the bit line, the adhesion layer and the barrier layer all contain metal elements, and the metal elements are selected from any one or more of titanium, cobalt, nickel, tungsten, copper and aluminum.
4. The manufacturing method according to claim 1, wherein the etching the exposed silicon substrate so that a groove extending in a column direction is formed under a column of the semiconductor pillars, comprises: etching the exposed silicon substrate to form sub-grooves extending to the lower parts of the semiconductor columns at two sides of each second groove in the silicon substrate below each second groove, and forming a groove by mutually communicating a plurality of sub-grooves arranged along the column direction.
5. The manufacturing method according to claim 1, wherein the disposing a heavily doped layer on an inner wall surface of the recess of the silicon substrate or forming a heavily doped layer on an outermost layer of the recess itself of the silicon substrate using a mask on top surfaces and sidewalls of the semiconductor pillars comprises:
selectively epitaxially growing N-type heavily doped silicon on the inner wall of the groove by using the second dielectric layer on the top surface of the baffle wall and the third dielectric layer on the side wall as masks to form a heavily doped layer; the N-type heavily doped silicon is obtained by doping substances to be doped into the silicon in a plasma doping mode; or alternatively, the first and second heat exchangers may be,
depositing a substance to be doped on the inner wall of the groove in the silicon substrate by adopting an atomic layer deposition method, and diffusing the substance to be doped into the silicon substrate by adopting heating driving; or alternatively, the first and second heat exchangers may be,
and converting the dopant to be doped into vapor, and diffusing the vapor of the dopant to be doped onto the inner wall of the groove by adopting a sub-atmospheric pressure chemical vapor deposition method.
6. The method of manufacturing of claim 1, wherein the forming a gate on the sidewall of the semiconductor pillar comprises:
removing the third dielectric layers on the side walls at two sides of the barrier wall by etching;
depositing a fourth dielectric material on the bottom surface of the second groove, the side walls on the two sides and the top surface of the baffle wall to form a fourth dielectric layer;
depositing a fifth dielectric material in the second trench to form a fifth dielectric layer;
etching the fifth dielectric layer in the second groove back to a certain height, and removing the fourth dielectric layer at the upper parts of the side walls at the two sides of the barrier wall;
depositing a sixth dielectric material on the surface of the fifth dielectric layer in the second groove and on the side walls of the two sides of the barrier wall to form a sixth dielectric layer;
filling a seventh dielectric material in the second groove to form a seventh dielectric layer;
removing the second dielectric layer on the top surface of the barrier wall by etching, and etching the sixth dielectric layer on the side walls on two sides of the barrier wall and the first dielectric layer between two adjacent semiconductor columns back to a certain height, so that space is vacated around the semiconductor columns;
depositing a gate insulating layer on the side wall of the semiconductor column, and filling a gate material in the space around the semiconductor column;
and etching the gate insulating layer and the gate material back to a certain height, wherein the rest gate material forms a gate.
7. A memory, characterized in that the memory is manufactured by a method according to any of claims 1-6.
8. An electronic device comprising a memory according to claim 7.
9. The electronic device of claim 8, comprising a storage device, a smart phone, a computer, a tablet, an artificial intelligence device, a wearable device, or a mobile power source.
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