CN115835624A - Memory and manufacturing method thereof - Google Patents

Memory and manufacturing method thereof Download PDF

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CN115835624A
CN115835624A CN202211486602.3A CN202211486602A CN115835624A CN 115835624 A CN115835624 A CN 115835624A CN 202211486602 A CN202211486602 A CN 202211486602A CN 115835624 A CN115835624 A CN 115835624A
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layer
semiconductor
silicon substrate
groove
wall
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CN115835624B (en
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李永杰
赵超
王桂磊
毛淑娟
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Beijing Superstring Academy of Memory Technology
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Beijing Superstring Academy of Memory Technology
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Priority to PCT/CN2023/093542 priority patent/WO2024108920A1/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

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  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)

Abstract

A memory and its manufacturing method, the memory includes the silicon substrate; a plurality of transistors located on the silicon substrate and distributed in an array along the row direction and the column direction, the transistors including a semiconductor column; the semiconductor columns in two adjacent columns are separated by first trenches extending along the column direction, and the semiconductor columns in two adjacent rows are separated by second trenches extending along the row direction; grooves extending in the column direction are formed in the silicon substrate below the columns of semiconductor pillars; and a plurality of bit lines extending along the column direction and arranged at intervals in the row direction, each bit line being positioned in one of the grooves and connected to the bottom end of the semiconductor pillar, the heavily doped layer positioned between the bit line and the inner wall of the groove being in contact with at least a part of the regions of the bit lines. The memory is provided with the heavily doped layer, so that ohmic contact is formed between the heavily doped layer and the bit line, the contact resistance between the bottom of the semiconductor column and the bit line is reduced, and the performance of the memory is improved.

Description

Memory and manufacturing method thereof
Technical Field
The present application relates to, but is not limited to, the field of semiconductor devices, and more particularly, to a memory and a method of fabricating the same.
Background
Dynamic Random Access Memory (DRAM) is a common system Memory, and is widely used in personal computers, notebooks, and consumer electronics. The DRAM stores data in a memory cell having a capacitor and an array transistor. Vertical Gate-All-Around Field Effect transistors (VGAAFETs) have great advantages in 3D integration and wiring and are often used in DRAMs.
Disclosure of Invention
The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the present application.
In one aspect, an exemplary embodiment of the present application provides a memory including: a silicon substrate having an upper surface and a lower surface; the transistors are positioned on the silicon substrate and distributed in an array along the row direction and the column direction on the silicon substrate; each of the transistors includes a semiconductor pillar extending in a direction perpendicular to an upper surface of the silicon substrate at the upper surface; the semiconductor columns in two adjacent columns are separated by first trenches extending along the column direction, and the semiconductor columns in two adjacent rows are separated by second trenches extending along the row direction; grooves extending in the column direction are formed in the silicon substrate below a column of semiconductor pillars; a plurality of bit lines extending along the column direction and arranged at intervals in the row direction, each bit line being located in one of the recesses and connected to the bottom ends of the semiconductor pillars; the heavily doped layers are positioned between the bit lines and the inner walls of the grooves and are in contact with at least partial regions of the bit lines; the heavily doped layer is formed of N-type doped silicon.
In an exemplary embodiment, each of the recesses includes a plurality of sub-recesses interconnected in a column direction, each of the sub-recesses being located in the silicon substrate under one of the second trenches and extending to under the semiconductor pillars on both sides of the second trench; and the inner wall of each sub-groove is uniformly distributed with one heavily doped layer.
In an exemplary embodiment, each of the heavily doped layers extends between the semiconductor pillar and the silicon substrate.
In an exemplary embodiment, the heavily doped layer is disposed on the inner wall surface of the groove or is used as the heavily doped layer by the outermost layer of the inner wall itself of the groove.
In an exemplary embodiment, the material of the heavily doped layer comprises silicon heavily doped with phosphorus.
In an exemplary embodiment, an adhesion layer and a barrier layer are further disposed between the bit line and the heavily doped layer, and the adhesion layer is disposed between the heavily doped layer and the barrier layer; the bit line, the adhesion layer and the barrier layer contain metal elements, and the metal elements are selected from any one or more of titanium, cobalt, nickel, tungsten, copper and aluminum.
In another aspect, an exemplary embodiment of the present application provides a method of manufacturing a memory, including: providing a silicon substrate having an upper surface and a lower surface;
forming a semiconductor pillar on an upper surface of the silicon substrate, the semiconductor pillar extending in a direction perpendicular to the upper surface on the upper surface of the silicon substrate; the semiconductor columns in two adjacent columns are separated by first trenches extending along the column direction, and the semiconductor columns in two adjacent rows are separated by second trenches extending along the row direction;
forming a groove extending in a column direction in the silicon substrate under a column of the semiconductor pillars;
setting a heavily doped layer on the inner wall surface of the groove of the silicon substrate or forming a heavily doped layer on the outermost layer of the groove of the silicon substrate by using the masks on the top surface and the side wall of each semiconductor pillar;
filling bit line materials in the grooves to form bit lines extending along the column direction, enabling the heavily doped layers to be in contact with partial regions of the bit lines, and enabling each bit line to be connected with the bottom end of a corresponding column of semiconductor columns;
a gate is formed on sidewalls of the semiconductor pillar.
In an exemplary embodiment, forming a semiconductor pillar on an upper surface of the silicon substrate includes:
providing a silicon substrate, wherein the silicon substrate is provided with an upper surface and a lower surface, and a first conducting layer, a semiconductor layer and a second conducting layer are sequentially deposited on the upper surface of the silicon substrate;
etching a plurality of first grooves which extend along the column direction and are spaced along the row direction on the second conductive layer, enabling the first grooves to penetrate through the second conductive layer, the semiconductor layer, the first conductive layer and expose the interior of the silicon substrate, and forming a semiconductor wall between two adjacent first grooves;
filling the first groove with a first dielectric material to form a first dielectric layer;
depositing a second dielectric material on the plurality of semiconductor walls and the first dielectric layer to form a second dielectric layer covering the semiconductor walls and the first dielectric layer;
and etching a plurality of second grooves which extend along the row direction and are spaced along the column direction on the second dielectric layer, enabling the second grooves to penetrate through the semiconductor wall and the first dielectric layer and expose the upper surface of the silicon substrate, spacing each semiconductor wall into a plurality of semiconductor columns by the plurality of second grooves, forming blocking walls which extend along the row direction by the semiconductor columns and the first dielectric layer between every two adjacent second grooves, and spacing the blocking walls by the second grooves along the column direction.
In an exemplary embodiment, forming a groove extending in a column direction in the silicon substrate under a column of the semiconductor pillars specifically includes:
depositing a third dielectric material on the bottom surface of the second groove and the side walls on the two sides of the blocking wall to form a third dielectric layer;
removing the third dielectric layer on the bottom surface of the second groove by etching to expose the upper surface of the silicon substrate and the first dielectric layer which are alternately arranged along the row direction;
and etching the exposed silicon substrate to form a groove extending along the column direction under a column of the semiconductor columns.
In an exemplary embodiment, the etching the exposed silicon substrate such that a groove extending in a column direction is formed under a column of the semiconductor pillars includes: and etching the exposed silicon substrate, so that sub-grooves extending to the lower parts of the semiconductor columns on two sides of each second groove are formed in the silicon substrate below each second groove, and a plurality of sub-grooves arranged along the column direction are communicated with each other to form a groove.
In an exemplary embodiment, the disposing a heavily doped layer on an inner wall surface of the recess of the silicon substrate or forming a heavily doped layer on an outermost layer of the recess itself of the silicon substrate using a mask on a top surface and sidewalls of each semiconductor pillar specifically includes:
selectively and epitaxially growing N-type heavily doped silicon on the inner wall of the groove by using the second dielectric layer on the top surface of the retaining wall and the third dielectric layer on the side wall as masks to form a heavily doped layer; the N-type heavily doped silicon is obtained by doping substances to be doped into the silicon in a plasma doping mode; or the like, or, alternatively,
depositing a substance to be doped on the inner wall of the groove in the silicon substrate by adopting an atomic layer deposition method, and diffusing the substance to be doped into the silicon substrate by adopting heating drive; or the like, or, alternatively,
and converting the substance to be doped into steam, and diffusing the steam of the substance to be doped onto the inner wall of the groove by adopting a sub-atmospheric pressure chemical vapor deposition method.
In an exemplary embodiment, forming a gate on a sidewall of the semiconductor pillar specifically includes:
removing the third dielectric layers on the side walls on the two sides of the blocking wall by etching;
depositing a fourth dielectric material on the bottom surface of the second groove, the side walls on two sides of the blocking wall and the top surface to form a fourth dielectric layer;
depositing a fifth dielectric material in the second trench to form a fifth dielectric layer;
etching the fifth dielectric layer in the second groove back to a certain height, and removing the fourth dielectric layers on the upper parts of the side walls on the two sides of the blocking wall;
depositing a sixth dielectric material on the surface of the fifth dielectric layer in the second trench and the side walls on the two sides of the barrier wall to form a sixth dielectric layer;
filling a seventh dielectric material in the second trench to form a seventh dielectric layer;
removing the second dielectric layer on the top surface of the blocking wall by etching, and etching back the sixth dielectric layer on the side walls on two sides of the blocking wall and the first dielectric layer between two adjacent semiconductor columns to a certain height, thereby vacating a space around the semiconductor columns;
depositing a gate insulating layer on the side wall of the semiconductor column, and filling a gate material in the space around the semiconductor column;
and etching the gate insulating layer and the gate material back to a certain height, and forming a gate by using the residual gate material.
In another aspect, an exemplary embodiment of the present application provides an electronic device including the memory of any one of the above.
In an exemplary embodiment, the electronic device includes a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power source.
According to the memory, the groove is formed in the silicon substrate below the semiconductor column, the heavily doped layer grows on the surface of the inner wall of the groove or the heavily doped layer is formed on the outermost layer of the groove of the silicon substrate, ohmic contact is formed between the heavily doped layer and the bit line, contact resistance between the bottom of the semiconductor column and the bit line is reduced, and performance of a transistor is enhanced.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application. Other advantages of the present application may be realized and attained by the instrumentalities and combinations particularly pointed out in the specification and the drawings.
Drawings
The accompanying drawings are included to provide an understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the examples serve to explain the principles of the disclosure and not to limit the disclosure.
FIG. 1 is a perspective schematic view of a memory provided in accordance with an exemplary embodiment of the present application;
FIG. 2 is a schematic partial enlarged view at M in FIG. 1;
fig. 3A is a schematic perspective view of an intermediate product resulting from an intermediate step of a method of manufacturing a memory provided according to an exemplary embodiment of the present application;
FIG. 3B isbase:Sub>A schematic cross-sectional view taken along the direction A-A in FIG. 3A;
FIG. 3C is a schematic cross-sectional view taken along direction B-B in FIG. 3A;
fig. 4A is a schematic perspective view of an intermediate product resulting from an intermediate step of a method of manufacturing a memory provided according to an exemplary embodiment of the present application;
FIG. 4B isbase:Sub>A schematic cross-sectional view taken along the direction A-A in FIG. 4A;
fig. 5A is a schematic perspective view of an intermediate product resulting from an intermediate step of a method of manufacturing a memory provided according to an exemplary embodiment of the present application;
FIG. 5B isbase:Sub>A schematic cross-sectional view taken along the direction A-A in FIG. 5A;
fig. 6A is a schematic perspective view of an intermediate product resulting from an intermediate step of a method of manufacturing a memory provided according to an exemplary embodiment of the present application;
FIG. 6B isbase:Sub>A schematic cross-sectional view taken along the direction A-A in FIG. 6A;
FIG. 6C is a schematic cross-sectional view taken along direction B-B in FIG. 6A;
fig. 7A is a schematic perspective view of an intermediate product resulting from an intermediate step of a method of manufacturing a memory provided in accordance with an exemplary embodiment of the present application;
FIG. 7B is a schematic cross-sectional view taken along the direction B-B in FIG. 7A;
fig. 8A is a schematic perspective view of an intermediate product resulting from an intermediate step of a method of manufacturing a memory provided according to an exemplary embodiment of the present application;
FIG. 8B is a schematic cross-sectional view taken along the direction B-B in FIG. 8A;
fig. 9A is a schematic perspective view of an intermediate product resulting from an intermediate step of a method of manufacturing a memory provided in accordance with an exemplary embodiment of the present application;
FIG. 9B is a schematic cross-sectional view taken along the direction B-B in FIG. 9A;
fig. 10A is a schematic perspective view of an intermediate product resulting from an intermediate step of a method of manufacturing a memory provided in accordance with an exemplary embodiment of the present application;
FIG. 10B is a schematic partial enlarged view at N in FIG. 10A;
fig. 11A is a schematic perspective view of an intermediate product resulting from an intermediate step of a method of manufacturing a memory provided in accordance with an exemplary embodiment of the present application;
FIG. 11B is a schematic cross-sectional view taken along the direction B-B in FIG. 11A;
fig. 12A is a schematic perspective view of an intermediate product resulting from an intermediate step of a method of manufacturing a memory provided in accordance with an exemplary embodiment of the present application;
FIG. 12B is a schematic cross-sectional view taken along the direction B-B in FIG. 12A;
fig. 13A is a schematic perspective view of an intermediate product resulting from an intermediate step of a method of manufacturing a memory provided in accordance with an exemplary embodiment of the present application;
FIG. 13B is a schematic cross-sectional view taken along the direction B-B in FIG. 13A;
fig. 14A is a schematic perspective view of an intermediate product resulting from an intermediate step of a method of manufacturing a memory provided according to an exemplary embodiment of the present application;
FIG. 14B is a schematic cross-sectional view taken along the direction B-B in FIG. 14A;
fig. 15A is a schematic perspective view of an intermediate product resulting from an intermediate step of a method of manufacturing a memory provided in accordance with an exemplary embodiment of the present application;
FIG. 15B is a schematic cross-sectional view taken along the direction B-B in FIG. 15A;
fig. 16 is a schematic cross-sectional view of an intermediate product resulting from an intermediate step of a method of manufacturing a memory provided in accordance with an exemplary embodiment of the present application;
fig. 17A is a schematic perspective view of an intermediate product resulting from an intermediate step of a method of manufacturing a memory provided in accordance with an exemplary embodiment of the present application;
FIG. 17B is a schematic cross-sectional view taken along the direction B-B in FIG. 17A;
fig. 18A is a schematic perspective view of an intermediate product resulting from an intermediate step of a method of manufacturing a memory provided according to an exemplary embodiment of the present application; and
fig. 18B is a schematic cross-sectional view taken along the direction B-B in fig. 18A.
Description of reference numerals:
1-a memory; 10-a silicon substrate; 20-a first conductive layer;
30-a semiconductor layer; 40-a second conductive layer; 50-a first trench;
60-a semiconductor wall; 70-a second trench; 80-semiconductor columns;
90-a retaining wall; 91-a groove; 92-a sub-groove;
93-heavily doped layer; 94-an adhesive layer; 95-a barrier layer;
96-bit line; 100-a first dielectric layer; 200-a second dielectric layer;
300-a third dielectric layer; 400-a fourth dielectric layer; 500-a fifth dielectric layer;
600-a sixth dielectric layer; 700-seventh dielectric layer.
Detailed Description
To make the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.
The embodiments herein may be embodied in many different forms. Those skilled in the art can readily appreciate the fact that the present invention is susceptible to implementation and content variations without departing from the spirit and scope of the present application. Therefore, the present application should not be construed as being limited to the contents described in the following embodiments. In the present application, the embodiments and features of the embodiments may be arbitrarily combined with each other without conflict.
The drawing scale in this application may be referenced in the actual process, but is not limited thereto. For example: the width-length ratio of the semiconductor layer and the thickness and the distance of each film layer can be adjusted according to actual needs. The drawings described in the present application are only schematic structural views, and one aspect of the present application is not limited to the shapes, numerical values, or the like shown in the drawings.
In this specification, for convenience, terms indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to explain positional relationship of constituent elements with reference to the drawings, only for convenience of description and simplification of description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present application. The positional relationship of the components is changed as appropriate in accordance with the direction in which each component is described. Therefore, the words described in the specification are not limited to the words described in the specification, and may be replaced as appropriate.
In this specification, the terms "disposed" and "connected" are to be construed broadly unless otherwise explicitly stated or limited. For example, it may be a fixed connection, or a removable connection, or an integral connection; can be a mechanical connection, or an electrical connection; either directly or indirectly through intervening components, or both may be interconnected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In the description of the present application, ordinal numbers such as "first", "second", and the like are provided to avoid confusion of constituent elements, and are not limited in number.
In the present specification, "film" and "layer" may be interchanged with each other. For example, a "metal layer" may sometimes be replaced with a "metal film".
In the process of forming a Buried Bit Line (BBL), since a chemical substance forming the Bit Line is easily reacted with the silicon substrate, a barrier layer may be first disposed in the groove to prevent the reaction from occurring, but the adhesion of the barrier layer to the silicon substrate is not good and is easily detached, so that an adhesion layer is disposed between the silicon substrate and the barrier layer. The conventional bit line usually uses tungsten/cobalt/ruthenium/molybdenum metal as the main conductive material, titanium, cobalt, nickel, tantalum as the adhesion layer, taN (titanium nitride), tiN (titanium nitride) and so on as the barrier layer for preventing tungsten from diffusing into silicon.
However, the inventors of the present application found that if the manufacturing method of disposing the adhesion layer and the barrier layer between the silicon substrate and the bit line is applied to the subsequent process at a temperature exceeding 400 ℃, titanium, cobalt, nickel or tantalum metal as the adhesion layer will diffuse into the silicon substrate to react with silicon, and after the metal diffusion is completed, vacancies will be left in the original place, which will cause TiN (titanium nitride) or TaN in the barrier layer to diffuse into the vacancies to cause voids in the microstructure of the adhesion layer, and at this time, the tungsten metal of the bit line will contain fluorine element and the like, so that fluorine element will enter the voids to react with silicon to cause damage to the bit line structure, which not only increases the resistance of the bit line itself, but also increases the contact resistance between the bit line and the semiconductor pillar, and weakens the performance of the transistor.
An exemplary embodiment of the present application provides a memory including: a silicon substrate having an upper surface and a lower surface; the transistors are positioned on the silicon substrate and distributed in an array along the row direction and the column direction on the silicon substrate; each transistor comprises a semiconductor pillar extending on the upper surface of the silicon substrate along the direction vertical to the upper surface; the semiconductor columns in two adjacent columns are separated by first trenches extending along the column direction, and the semiconductor columns in two adjacent rows are separated by second trenches extending along the row direction; grooves extending in the column direction are arranged in the silicon substrate below a column of semiconductor columns; a plurality of bit lines extending along the column direction and arranged at intervals in the row direction, each bit line being located in one of the recesses and connected to the bottom end of the semiconductor pillar; and the heavily doped layer is positioned between the bit line and the inner wall of the groove and is in contact with at least partial region of the bit line.
In an exemplary embodiment, each of the recesses includes a plurality of sub-recesses interconnected in a column direction, each of the sub-recesses being located in the silicon substrate under one of the second trenches and extending to under the semiconductor pillars on both sides of the second trench; and the inner wall of each sub-groove is uniformly distributed with one heavily doped layer.
In the description of the present application, the term "column direction" is defined as the direction of extension of the bit lines of the memory; the term "row direction" is perpendicular to the column direction, and the plane formed by the row direction and the column direction is parallel to the silicon substrate of the memory.
In the description of the present application, the term "heavily doped" is defined as a doping concentration of a substance to be doped of 1.0E19cm -3 -1.0E21cm -3 Within the range of (1).
FIG. 1 is a perspective schematic view of a memory provided in accordance with an exemplary embodiment of the present application. As shown in fig. 1, the memory 1 includes a silicon substrate 10 and a plurality of transistors disposed on the silicon substrate 10 and arranged in an array along a row direction and a column direction on the silicon substrate 10. Each transistor includes a semiconductor pillar 80, and the semiconductor pillar 80 extends in a direction perpendicular to an upper surface of the silicon substrate 10 at the upper surface. Adjacent two columns of semiconductor pillars 80 are spaced apart by first trenches 50 extending in the column direction, and adjacent two rows of semiconductor pillars are spaced apart by second trenches 70 extending in the row direction; a groove 91 extending in the column direction is provided in the silicon substrate 10 under a column of the semiconductor pillars 80.
Each memory further comprises a plurality of bit lines 96, the bit lines 96 extend along the column direction and are arranged at intervals in the row direction, and each bit line 96 is positioned in one of the grooves 91 and is connected with the bottom end of the semiconductor pillar;
each memory further includes a plurality of heavily doped layers 93 located between the bit lines 96 and the inner walls of the grooves 91, in contact with at least partial regions of the bit lines 96; heavily doped layer 93 is formed of heavily N-doped silicon.
Fig. 2 is a schematic partial enlarged view at M in fig. 1. As shown in fig. 2, the groove 91 includes a plurality of sub-grooves 92 interconnected in the column direction. Each sub-recess 92 is located in the silicon substrate 10 below one of the second trenches 70 and extends below the semiconductor pillars on both sides of the second trench. A heavily doped layer 93 is distributed on the inner wall of each sub-groove 92.
Exemplary embodiments of the present application also provide a method of manufacturing a memory. The memory provided by the exemplary embodiments of the present application as described above may be obtained by this method. The manufacturing method may include the steps of:
s10: providing a silicon substrate 10, wherein the silicon substrate 10 is provided with an upper surface and a lower surface; depositing a first conductive layer 20, a semiconductor layer 30 and a second conductive layer 40 in sequence on the upper surface of the silicon substrate 10; for example, it can be deposited on a silicon substrate
Figure BDA0003962613290000111
A thick N-type heavily doped epitaxial layer of silicon serves as the first conductive layer 20,
Figure BDA0003962613290000112
thick P-type lightly doped silicon epitaxial layer as semiconductorThe thickness of the layer (30) is,
Figure BDA0003962613290000113
a thick, heavily N-doped epitaxial layer of silicon serves as the second conductive layer 40.
S20: a plurality of first trenches 50 (i.e., bit line trenches BL trench) extending in the column direction and spaced apart from each other in the row direction are etched in the second conductive layer 40, the first trenches 50 penetrate through the second conductive layer 40, the semiconductor layer 30, the first conductive layer 20 and expose the interior of the silicon substrate 10, and a semiconductor wall 60 is formed between two adjacent first trenches 50, as shown in fig. 3A to 3C.
S30: the first trench 50 is filled with a first dielectric material to form a first dielectric layer 100, and a Chemical Mechanical Planarization (CMP) method is used to level the upper surface of the first dielectric layer 100 with the upper surface of the second conductive layer 40, i.e., two adjacent semiconductor walls 60 are separated by the first dielectric layer 100, as shown in fig. 4A and 4B.
S40: a second dielectric material is deposited on the plurality of semiconductor walls 60 and the first dielectric layer 100 to form a second dielectric layer 200 covering the semiconductor walls 60 and the first dielectric layer 100, as shown in fig. 5A and 5B.
S50: a plurality of second trenches 70 (i.e., word line trenches WL trench) extending in the row direction and spaced apart in the column direction are etched in the second dielectric layer 200, such that the second trenches 70 penetrate the semiconductor wall 60 and the first dielectric layer 100 and expose the upper surface of the silicon substrate 10. A plurality of second trenches 70 space each semiconductor wall 60 into a plurality of semiconductor pillars 80, each semiconductor pillar 80 including a first conductive layer 20, a semiconductor layer 30, and a second conductive layer 40. The semiconductor pillars 80 and the first dielectric layer 100 between two adjacent second trenches 70 constitute the blocking walls 90 extending in the row direction, and the plurality of blocking walls 90 are spaced by the second trenches 70 in the column direction, as shown in fig. 6A to 6C.
S60: a third dielectric material is deposited on the bottom surface of the second trench 70 and the sidewalls of the blocking wall 90 to form a third dielectric layer 300, and a third dielectric material is also deposited on the top surface of the blocking wall 90 to form the third dielectric layer 300 (not shown), as shown in fig. 7A and 7B.
S70: the third dielectric layer 300 on the bottom surface of the second trench 70 is removed by etching to expose the upper surface of the silicon substrate 10 and the first dielectric layer 100 alternately arranged in the row direction, while the third dielectric layer 300 on the top surface of the blocking wall 90 is removed by etching, as shown in fig. 8A and 8B.
S80: the exposed silicon substrate 10 is etched such that recesses 91 extending in the column direction are formed below a column of the semiconductor pillars 80, each recess 91 may include a plurality of sub-recesses 92 communicating with each other in the column direction, the sub-recesses 90 are located in the silicon substrate 10 below one second trench 70 and extend below the semiconductor pillars 80 on both sides of the second trench 70, and the longitudinal cross-section of the sub-recesses 92 in a plane perpendicular to the second trench 70 may have a bowl shape, an oval shape, a sigma shape, a diamond shape, or the like, as shown in fig. 9A and 9B.
S90: a heavily doped layer 93 is epitaxially grown on the inner wall of the silicon substrate 10 in each sub-recess 92 or the outermost layer of the silicon substrate 10 itself, using the second dielectric layer 200 on the top surface of the barrier wall 90 and the third dielectric layer 300 on the side wall as masks, as shown in fig. 10A and 10B.
Specifically, the method of forming the heavily doped layer 93 may include:
s910: a substance to be doped (for example, phosphorus) is doped into silicon by means of plasma doping, and then a heavily doped layer 93 formed of silicon heavily doped with phosphorus is epitaxially grown on the inner wall surface of the silicon substrate 10 within each sub-groove 92 by a selective epitaxial growth method.
Alternatively, the method of forming the heavily doped layer 93 may include:
s920: depositing a substance to be doped (e.g., phosphorus) on the inner wall surface of the silicon substrate 10 in each sub-groove 92 by using an Atomic Layer Deposition (ALD) method, and then diffusing the substance to be doped into the silicon substrate 10 by using a heating driving method, thereby forming a heavily doped Layer 93 formed of silicon heavily doped with phosphorus at the outermost Layer of the silicon substrate 10 itself;
alternatively, the method of forming the heavily doped layer 93 may include:
s930: a substance to be doped (for example, phosphorus) is converted into a gas, and a vapor of the substance to be doped (for example, phosphorus vapor) is diffused into the outermost layer of the silicon substrate 10 itself by a sub-atmospheric chemical vapor deposition (SACVD) method using nitrogen or other inert gas as a carrier gas, following the principle of fick's first law, thereby forming a heavily doped layer 93 formed of silicon heavily doped with phosphorus at the outermost layer of the silicon substrate 10 itself.
During the formation of the heavily doped layer 93, the second dielectric layer 200 on the top surface of the blocking wall 90 and the third dielectric layer 300 on the sidewall can be used as a hard mask to prevent the penetration of the to-be-doped material into the semiconductor pillar 80.
S100: filling the second trench 70 and the groove 91 with bit line material and contacting the heavily doped layer 93 with a portion of the bit line material in the groove 91, as shown in fig. 11A and 11B;
illustratively, the method can comprise the following steps: an adhesion layer material and a barrier layer material are sequentially deposited on the walls of the second trench 70 and the recess 91, and then a bit line material is filled in the second trench 70 and the recess 91, and the adhesion layer material, the barrier layer material and the bit line material are sequentially made to cover the top surface of the barrier wall 90, and the heavily doped layer 93 is made to contact at least a partial region of at least one of the bit line material, the adhesion layer material and the barrier layer material in the recess 91.
S110: the material in the second trench 70 and the top surface of the blocking wall 90 is removed by etching back, leaving the material in the recess 91, thereby forming an adhesion layer 94 from the adhesion layer material, a barrier layer 95 from the barrier layer material, and a bit line 96 from the bit line material in the recess 91, as shown in fig. 12A and 12B.
S120: the third dielectric layer 300 on the sidewalls on both sides of the barrier wall 90 is removed by wet etching, which can eliminate the risk of metal contamination (the third dielectric layer is exposed to the adhesion layer material such as Ti/Co/Ni/Ta + TiN/TaN + tungsten/cobalt/rubidium/molybdenum, the barrier layer material, and the bit line material, and there may be metal residue in the third dielectric material of the third dielectric layer due to metal diffusion), as shown in fig. 13A and 13B.
S130: depositing a fourth dielectric material on the bottom surface of the second trench 70, the sidewalls of the blocking wall 90 and the top surface of the second dielectric layer 200 of the blocking wall 90 to form a fourth dielectric layer 400; and depositing a fifth dielectric material in the second trench 70 followed by CMP planarization to form a fifth dielectric layer 500, as shown in fig. 14A and 14B.
S140: the fifth dielectric layer 500 in the second trench 70 is etched back to a certain height (the lower end of the gate electrode can be determined by the height), as shown in fig. 15A and 15B.
S150: the fourth dielectric layer 400 on the top surface of the second dielectric layer 200 of the barrier wall 90 is removed by etching, and the fourth dielectric layer 400 on the sidewalls of both sides of the barrier wall 90 is etched to be flush with the height of the fifth dielectric layer 500, as shown in fig. 16.
S160: depositing a sixth dielectric material on the surface of the fifth dielectric layer 500 in the second trench 70, the top surface and the sidewalls of the barrier wall 90 to form a sixth dielectric layer 600, and removing the sixth dielectric layer 600 on the top surface of the barrier wall 90;
s170: a seventh dielectric layer 700 is formed by filling the seventh dielectric material in the second trench 70, and the seventh dielectric layer 700 covers the entire surface of the silicon substrate formed in step S160, followed by CMP planarization, as shown in fig. 17A and 17B.
S180: the second dielectric layer 200 on the top surface of the barrier wall 90 and the sixth dielectric layer 600 on the sidewalls of both sides of the barrier wall 90, as well as the first dielectric layer 100 between two adjacent semiconductor pillars 80 (not shown) are removed by etching back to a certain height, thereby making a space around the semiconductor pillars 80, as shown in fig. 18A and 18B.
S190: a gate insulating layer (e.g., tiN) and a gate material (e.g., a metal such as tungsten) are sequentially deposited on the sidewalls of the semiconductor pillar 80, and the gate insulating layer and the gate material are made to fill the space around the semiconductor pillar 80 and cover the entire surface of the silicon substrate obtained in step S180, as shown in fig. 1.
S200: etching the gate insulating layer and the gate material back to a certain height, forming a gate from the rest of the gate material, wherein two ends of the gate can respectively extend to the first conductive layer 20 and the second conductive layer 40; each semiconductor pillar 80 and the gate electrode surrounding the semiconductor pillar 80 constitute one transistor.
The method of manufacturing the memory may further include:
s210: after the gate is formed, an interlayer dielectric ILD (inter-layer dielectric) covering the gate and the first and second conductive layers 100 and 200 is deposited in the space between the respective layers, and is ready for the subsequent fabrication of a Contact hole (Node Contact).
In the process of forming the embedded bit line, a heavily doped layer formed by N-type heavily doped silicon is formed by epitaxial growth on the inner wall of the silicon substrate or the outermost layer in the silicon substrate, so that metal in the adhesion layer is inhibited from diffusing into the silicon, and then elements such as fluorine in the bit line are inhibited from reacting with the silicon, the structure of the bit line is kept intact, ohmic contact is formed between the heavily doped layer and the metal bit line, contact resistance between the bottom of the semiconductor column and the bit line is reduced, and the performance of a transistor is enhanced.
In an exemplary embodiment of the present application, either one or both of the first trench and the second trench may be formed using a Self-aligned Double Patterning (SADP) process.
In an exemplary embodiment of the present application, the recess may be formed by performing a side etching of the first trench by a wet etching.
In an exemplary embodiment of the present application, the first to seventh dielectric layers may be formed each independently using an Atomic Layer Deposition (ALD) or a Chemical Vapor Deposition (CVD) process.
In exemplary embodiments of the present application, the methods of depositing the first dielectric material to the seventh dielectric material may each be independently selected from any one of ALD and CVD.
In exemplary embodiments of the present application, the first to seventh dielectric materials may be selected from silicon nitride, silicon oxide, and the like.
In the embodiment of the present application, after depositing any one of the first to seventh dielectric materials, the formed dielectric layer may be planarized by using a CMP process, for example, after filling the second trench with the second dielectric material in step S200, the dielectric layer formed on the surface of the device may be planarized by using a CMP process.
The embodiment of the application provides a memory, and the memory can be obtained by the manufacturing method of the memory provided by the embodiment of the application.
In the embodiments of the present application, the material of the gate may be selected from any one or more of conductor materials formed from group IVA elements, for example, the material of the gate may be selected from any one or more of polysilicon, polycrystalline silicon germanium, and the like.
In embodiments of the present application, the material of the gate insulating layer may be selected from silicon oxide (e.g., siO) 2 ) Hafnium oxide (e.g., hfO) 2 ) Zirconium oxide (e.g., zrO) and aluminum oxide (e.g., al) 2 O 3 ) Any one or more of them. The gate insulating layer may have a single-layer structure or a multi-layer structure, and may include, for example, a two-layer structure formed of silicon oxide and hafnium oxide, in which the silicon oxide layer is in contact with the channel region and the hafnium oxide layer is in contact with the gate. The thickness of the gate insulating layer may be set according to actual electrical requirements, and may be, for example, 2nm to 5nm.
In an embodiment of the present application, the Memory may be a device including a transistor, for example, a Dynamic Random Access Memory (DRAM), a Magnetic Random Access Memory (MRAM), or the like.
An embodiment of the present application further provides an electronic device, which includes the memory provided in the embodiment of the present application.
In embodiments of the present application, the electronic device may include a storage device, a smartphone, a computer, a tablet, an artificial intelligence device, a wearable device, or a mobile power source.
Although the embodiments disclosed in the present application are described above, the descriptions are only for the convenience of understanding the present application, and are not intended to limit the present application. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure as defined by the appended claims.

Claims (14)

1. A memory, comprising:
a silicon substrate having an upper surface and a lower surface;
the transistors are positioned on the silicon substrate and distributed in an array along the row direction and the column direction on the silicon substrate; each transistor comprises a semiconductor pillar extending on the upper surface of the silicon substrate along the direction vertical to the upper surface; the semiconductor columns in two adjacent columns are separated by first trenches extending along the column direction, and the semiconductor columns in two adjacent rows are separated by second trenches extending along the row direction; grooves extending in the column direction are arranged in the silicon substrate below a column of semiconductor columns;
a plurality of bit lines extending along the column direction and arranged at intervals in the row direction, each bit line being located in one of the recesses and connected to the bottom end of the semiconductor pillar;
and the heavily doped layer is positioned between the bit line and the inner wall of the groove and is in contact with at least partial region of the bit line.
2. The memory according to claim 1, wherein each of the recesses includes a plurality of sub-recesses communicating with each other in the column direction, each of the sub-recesses being located in the silicon substrate below one of the second trenches and extending below the semiconductor pillars on both sides of the second trench;
and the inner wall of each sub-groove is uniformly distributed with one heavily doped layer.
3. The memory of claim 2, wherein each of the heavily doped layers extends between the semiconductor pillar and the silicon substrate.
4. The memory according to claim 1, wherein the heavily doped layer is provided on the inner wall surface of the groove or is used as the heavily doped layer by the outermost layer of the inner wall itself of the groove.
5. The memory of any one of claims 1 to 4, wherein the material of the heavily doped layer comprises silicon heavily doped by phosphorus.
6. The memory according to any one of claims 1 to 4, wherein an adhesion layer and a barrier layer are further disposed between the bit line and the heavily doped layer, and the adhesion layer is disposed between the heavily doped layer and the barrier layer;
the bit line, the adhesion layer and the barrier layer contain metal elements, and the metal elements are selected from any one or more of titanium, cobalt, nickel, tungsten, copper and aluminum.
7. A method of manufacturing a memory, comprising:
providing a silicon substrate having an upper surface and a lower surface;
forming a semiconductor pillar on an upper surface of the silicon substrate, the semiconductor pillar extending in a direction perpendicular to the upper surface on the upper surface of the silicon substrate; the semiconductor columns in two adjacent columns are separated by first trenches extending along the column direction, and the semiconductor columns in two adjacent rows are separated by second trenches extending along the row direction;
forming a groove extending in a column direction in the silicon substrate under a column of the semiconductor pillars;
setting a heavily doped layer on the inner wall surface of the groove of the silicon substrate or forming the heavily doped layer on the outermost layer of the groove of the silicon substrate by using masks on the top surface and the side wall of the semiconductor column;
filling bit line materials in the grooves to form bit lines extending along the column direction, enabling the heavily doped layers to be in contact with partial regions of the bit lines, and enabling each bit line to be connected with the bottom end of a corresponding column of semiconductor columns;
a gate is formed on sidewalls of the semiconductor pillar.
8. The manufacturing method according to claim 7, wherein the forming of the semiconductor pillar on the upper surface of the silicon substrate comprises:
depositing a first conductive layer, a semiconductor layer and a second conductive layer on the upper surface of the silicon substrate in sequence;
etching a plurality of first grooves which extend along the column direction and are spaced along the row direction on the second conductive layer, enabling the first grooves to penetrate through the second conductive layer, the semiconductor layer, the first conductive layer and expose the interior of the silicon substrate, and forming a semiconductor wall between two adjacent first grooves;
filling the first groove with a first dielectric material to form a first dielectric layer;
depositing a second dielectric material on the plurality of semiconductor walls and the first dielectric layer, forming a second dielectric layer overlying the semiconductor walls and the first dielectric layer;
and etching a plurality of second grooves which extend along the row direction and are spaced along the column direction on the second dielectric layer, enabling the second grooves to penetrate through the semiconductor wall and the first dielectric layer and expose the upper surface of the silicon substrate, spacing each semiconductor wall into a plurality of semiconductor columns by the plurality of second grooves, forming blocking walls which extend along the row direction by the semiconductor columns and the first dielectric layer between every two adjacent second grooves, and spacing the blocking walls by the second grooves along the column direction.
9. The manufacturing method according to claim 8, wherein the forming of the groove extending in the column direction in the silicon substrate under the column of the semiconductor pillars comprises:
depositing a third dielectric material on the bottom surface of the second groove and the side walls on the two sides of the blocking wall to form a third dielectric layer;
removing the third dielectric layer on the bottom surface of the second groove by etching to expose the upper surface of the silicon substrate and the first dielectric layer which are alternately arranged along the row direction;
and etching the exposed silicon substrate to form a groove extending along the column direction under a column of the semiconductor columns.
10. The manufacturing method according to claim 9, wherein the etching of the exposed silicon substrate so that a groove extending in a column direction is formed below a column of the semiconductor pillars comprises: and etching the exposed silicon substrate, so that sub-grooves extending to the lower parts of the semiconductor columns on two sides of each second groove are formed in the silicon substrate below each second groove, and a plurality of sub-grooves arranged along the column direction are communicated with each other to form a groove.
11. The manufacturing method according to claim 8, wherein said providing a heavily doped layer on an inner wall surface of the recess of the silicon substrate or forming a heavily doped layer on an outermost layer of the recess itself of the silicon substrate using a mask on top surfaces and sidewalls of the semiconductor pillars comprises:
selectively and epitaxially growing N-type heavily doped silicon on the inner wall of the groove by using the second dielectric layer on the top surface of the retaining wall and the third dielectric layer on the side wall as masks to form a heavily doped layer; the N-type heavily doped silicon is obtained by doping substances to be doped into the silicon in a plasma doping mode; or the like, or, alternatively,
depositing a substance to be doped on the inner wall of the groove in the silicon substrate by adopting an atomic layer deposition method, and diffusing the substance to be doped into the silicon substrate by adopting heating drive; or the like, or, alternatively,
and converting the substance to be doped into steam, and diffusing the steam of the substance to be doped onto the inner wall of the groove by adopting a sub-atmospheric pressure chemical vapor deposition method.
12. The method of manufacturing of claim 9, wherein the forming a gate on a sidewall of the semiconductor pillar comprises:
removing the third dielectric layers on the side walls on the two sides of the blocking wall by etching;
depositing a fourth dielectric material on the bottom surface of the second groove, the side walls on two sides of the blocking wall and the top surface to form a fourth dielectric layer;
depositing a fifth dielectric material in the second trench to form a fifth dielectric layer;
etching the fifth dielectric layer in the second groove back to a certain height, and removing the fourth dielectric layers on the upper parts of the side walls on the two sides of the blocking wall;
depositing a sixth dielectric material on the surface of the fifth dielectric layer in the second trench and the side walls on the two sides of the barrier wall to form a sixth dielectric layer;
filling a seventh dielectric material in the second trench to form a seventh dielectric layer;
removing the second dielectric layer on the top surface of the barrier wall by etching, and etching back the sixth dielectric layer on the side walls of the two sides of the barrier wall and the first dielectric layer between two adjacent semiconductor columns to a certain height, thereby vacating a space around the semiconductor columns;
depositing a gate insulating layer on the side wall of the semiconductor column, and filling a gate material in the space around the semiconductor column;
and etching the gate insulating layer and the gate material back to a certain height, and forming a gate by the rest gate material.
13. An electronic device, characterized in that it comprises a memory according to any one of claims 1 to 6.
14. The electronic device of claim 13, comprising a storage device, a smartphone, a computer, a tablet, an artificial intelligence device, a wearable device, or a mobile power source.
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