CN115831775A - Chip CSP packaging method and chip packaging piece - Google Patents
Chip CSP packaging method and chip packaging piece Download PDFInfo
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Abstract
The application provides a chip CSP packaging method and a chip packaging piece. The chip CSP packaging method is used for packaging the upper electrode chip and the lower electrode chip and comprises the following steps: placing a chip on the surface of a first carrier plate, wherein a first electrode faces the first carrier plate, and a first packaging adhesive layer is laid on the peripheral side of the chip; a through hole extending longitudinally is formed in the first packaging adhesive layer; extending the second electrode to the surface of the first carrier plate along the surface of the first packaging adhesive layer and the through hole in an additive manufacturing mode, and laying a second packaging adhesive layer on the surface of the first packaging adhesive layer; and turning the chip to the surface of the second carrier plate, and respectively extending the first electrode and the second electrode along the surface of the first packaging adhesive layer in an additive manufacturing mode to obtain the chip packaging piece. The second electrode extends to the same side as the first electrode, so that the chip is conveniently packaged by a CSP packaging method, the packaging size can be reduced, the packaging efficiency is improved, a packaging substrate is omitted, and the packaging cost can be reduced.
Description
Technical Field
The present disclosure relates to the field of chip packaging technologies, and in particular, to a chip CSP packaging method and a chip package.
Background
With the development of integrated circuit technology, the package size of electronic chips is more and more miniaturized. CSP (Chip Scale Package) packaging is a new generation of Chip packaging technology. The CSP package can make the ratio of the chip area to the package area exceed 1.14 (close to 1.
Need adopt flip chip in CSP encapsulation, the electrode setting of chip is on the same side of chip promptly, but most chips all belong to upper and lower electrode chip on the market, the electrode setting of chip is on two upper and lower different faces of chip promptly, and upper and lower electrode chip is difficult to adopt CSP packaging method to encapsulate, and the packaging size that causes this type of chip is great, and packaging efficiency is lower, and packaging cost is higher.
Disclosure of Invention
In view of the above, the present application is proposed to provide a chip CSP packaging method and a chip package that overcome or at least partially solve the above problems, including:
a chip CSP packaging method is used for packaging a chip, wherein the chip comprises a first electrode and a second electrode which are oppositely arranged; the method comprises the following steps:
placing the chip on the surface of a first carrier plate, wherein the first electrode faces the first carrier plate, and a first packaging adhesive layer is laid on the peripheral side of the chip; the first packaging adhesive layer is internally provided with a through hole extending longitudinally;
extending the second electrode to the surface of the first carrier plate along the surface of the first packaging adhesive layer and the through hole in an additive manufacturing mode, and laying a second packaging adhesive layer on the surface of the first packaging adhesive layer;
and turning the chip to the surface of a second carrier plate, and respectively extending the first electrode and the second electrode along the surface of the first packaging adhesive layer in an additive manufacturing mode to obtain a chip packaging piece.
Preferably, the step of laying the first encapsulating adhesive layer on the peripheral side of the chip includes:
laying an initial packaging adhesive layer on the peripheral side of the chip;
etching and removing the target part of the initial packaging adhesive layer to form a first packaging adhesive layer; the target part is a columnar structure which corresponds to the longitudinal extension of the side edge of the chip.
Preferably, the step of extending the second electrode to the surface of the first carrier along the surface of the first encapsulant layer and the through hole by an additive manufacturing method includes:
preparing a conductive post along the inside of the through hole in an additive manufacturing manner;
preparing a conductive path on the surface of the first packaging adhesive layer in an additive manufacturing mode; wherein the conductive via is connected to the second electrode and the conductive pillar, respectively.
Preferably, the step of preparing a conductive path on the surface of the first encapsulation adhesive layer by an additive manufacturing method includes:
coating a photosensitive material on the surface of the first packaging adhesive layer, and carrying out exposure and development to expose a first target area on the surface of the first packaging adhesive layer; wherein the first target region is connected to the second electrode and the conductive pillar, respectively;
preparing the conductive path on the surface of the first target area by an additive manufacturing mode;
and removing the photosensitive material.
Preferably, the step of extending the first electrode and the second electrode along the surface of the first encapsulant layer by additive manufacturing includes:
respectively preparing a first expanding passage and a second expanding passage on the surface of the first packaging adhesive layer in an additive manufacturing mode; wherein the first extended path is connected to the first electrode; the second expansion path is connected to the second electrode.
Preferably, the step of respectively preparing a first expanding passage and a second expanding passage on the surface of the first packaging adhesive layer through an additive manufacturing manner includes:
coating a photosensitive material on the surface of the first packaging adhesive layer, and carrying out exposure and development to expose a third target area and a fourth target area on the surface of the first packaging adhesive layer; wherein the third target region is connected to the first electrode; the fourth target region is connected to the second electrode.
Respectively preparing the first expansion passage on the surface of the third target area and the second expansion passage on the surface of the fourth target area in an additive manufacturing mode;
and removing the photosensitive material.
Preferably, the step of extending the first electrode and the second electrode along the surface of the first encapsulant layer by additive manufacturing further includes:
and grinding the first packaging adhesive layer to expose the first electrode and the second electrode.
Preferably, the additive manufacturing manner includes one or more of chemical vapor deposition, physical vapor deposition, atomic layer deposition, sputtering, evaporation, electroplating and chemical plating.
Preferably, the materials of the first packaging adhesive layer and the second packaging adhesive layer include one or more of epoxy resin, silica gel, PI resin, PE resin and PT resin.
A chip package prepared by the chip CSP packaging method comprises the following steps: the chip and the packaging adhesive layer; the packaging adhesive layer wraps the chip; the first electrode and the second electrode respectively extend to the surface of the packaging glue layer.
The application has the following advantages:
in the embodiment of the present application, for the problem that it is difficult to adopt the CSP packaging method to encapsulate to current upper and lower electrode chip, the present application provides a solution that adopts the additive manufacturing mode to extend the upper electrode of chip to the same side with the lower electrode, specifically is: the chip is placed on the surface of a first carrier plate, the first electrode faces the first carrier plate, and a first packaging adhesive layer is laid on the periphery of the chip; the first packaging adhesive layer is internally provided with a through hole extending longitudinally; extending the second electrode to the surface of the first carrier plate along the surface of the first packaging adhesive layer and the through hole in an additive manufacturing mode, and laying a second packaging adhesive layer on the surface of the first packaging adhesive layer; and turning the chip to the surface of a second carrier plate, and respectively extending the first electrode and the second electrode along the surface of the first packaging adhesive layer in an additive manufacturing mode to obtain a chip packaging piece ". The second electrode extends to the same side as the first electrode, so that the chip is conveniently packaged by a CSP packaging method, the packaging size can be reduced, the packaging efficiency is improved, a packaging substrate is omitted, and the packaging cost can be reduced.
Drawings
In order to more clearly illustrate the technical solutions of the present application, the drawings required to be used in the description of the present application will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art that other drawings may be obtained according to these drawings without creative efforts.
Fig. 1 is a flowchart illustrating steps of a CSP packaging method according to an embodiment of the present application;
fig. 2 is a schematic flowchart illustrating a CSP packaging method according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a chip package according to an embodiment of the present disclosure.
The reference numbers in the drawings of the specification are as follows:
100. a chip; 110. a first electrode; 111. a first expansion path; 120. a second electrode; 121. a conductive path; 122. a conductive post; 123. a second expansion path.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, the present application is described in further detail with reference to the accompanying drawings and detailed description. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that, in any embodiment of the present application, the chip CSP packaging method is used for packaging the chip 100, and the chip 100 is a top-bottom electrode chip, that is, includes a first electrode 110 and a second electrode 120 which are oppositely disposed. As an example, the first electrode 110 is a positive electrode (P-electrode), and the second electrode 120 is a negative electrode (N-electrode); as another example, the first electrode 110 is a negative electrode (N-electrode), and the second electrode 120 is a positive electrode (P-electrode).
Referring to fig. 1-2, a method for packaging a chip CSP provided by an embodiment of the present application is shown, including:
s110, placing the chip 100 on the surface of a first carrier plate, wherein the first electrode 110 faces the first carrier plate, and a first packaging adhesive layer is laid on the periphery of the chip 100; the first packaging adhesive layer is internally provided with a through hole extending longitudinally;
s120, extending the second electrode 120 to the surface of the first carrier plate along the surface of the first packaging adhesive layer and the through hole in an additive manufacturing mode, and laying a second packaging adhesive layer on the surface of the first packaging adhesive layer;
s130, turning the chip 100 over to the surface of the second carrier, and extending the first electrode 110 and the second electrode 120 along the surface of the first package adhesive layer respectively in an additive manufacturing manner, so as to obtain a chip package.
In the embodiment of the present application, for a problem that the existing upper and lower electrode chip is difficult to be packaged by the CSP packaging method, the present application provides a solution that the upper electrode of the chip 100 is extended to the same side as the lower electrode by an additive manufacturing method, specifically: "place the chip 100 on the surface of a first carrier, the first electrode 110 faces the first carrier, and a first encapsulation adhesive layer is laid on the periphery of the chip 100; the first packaging adhesive layer is internally provided with a through hole extending longitudinally; extending the second electrode 120 to the surface of the first carrier plate along the surface of the first encapsulation adhesive layer and the through hole by an additive manufacturing method, and laying a second encapsulation adhesive layer on the surface of the first encapsulation adhesive layer; the chip 100 is turned over to the surface of the second carrier, and the first electrode 110 and the second electrode 120 respectively extend along the surface of the first package adhesive layer by an additive manufacturing method, so as to obtain a chip package. By extending the second electrode 120 to the same side as the first electrode 110, the chip 100 is conveniently packaged by the CSP method, so that the package size can be reduced, the package efficiency can be improved, and the package cost can be reduced by eliminating the package substrate.
Next, a chip CSP packaging method in the present exemplary embodiment will be further described.
As the step S110, the chip 100 is placed on the surface of a first carrier, the first electrode 110 faces the first carrier, and a first encapsulant layer is disposed around the chip 100; and a longitudinally extending through hole is formed in the first packaging adhesive layer.
The chip 100 is horizontally placed on the surface of the first carrier plate, and the first packaging adhesive layer is poured on the surface of the first carrier plate, so that the first packaging adhesive layer wraps the periphery of the chip 100, the top of the first packaging adhesive layer extends to a position not higher than the top of the second electrode 120, and the through hole extending longitudinally is formed inside the first packaging adhesive layer.
The first encapsulating adhesive layer is made of an encapsulating adhesive, and specifically, the encapsulating adhesive includes one or more of epoxy resin, silica gel, PI (Polyimide) resin, PE (Polyethylene) resin, and PT (phenyl Triazine) resin. The first packaging adhesive layer formed after the packaging adhesive is cured has better insulation and sealing performance, can provide protection and prevents a product from being affected with damp.
In step S120, the second electrode 120 is extended to the surface of the first carrier along the surface of the first encapsulant layer and the through hole by an additive manufacturing method, and a second encapsulant layer is laid on the surface of the first encapsulant layer.
Respectively preparing extension circuits on the surface of the first encapsulating adhesive layer and inside the through hole in an Additive Manufacturing (AM) manner, so that the end of the second electrode 120 extends to the surface of the first carrier plate, and pouring the second encapsulating adhesive layer on the surface of the first encapsulating adhesive layer, and the top of the second encapsulating adhesive layer extends to a position higher than the top of the second electrode 120.
It should be noted that additive manufacturing is also called 3D printing, which is a manufacturing technology for manufacturing a solid object by stacking a special metal material, a non-metal material or a medical biomaterial layer by layer in a manner of extrusion, sintering, melting, photocuring, spraying, etc. by using software and a numerical control system based on a digital model file. Specifically, the additive manufacturing manner referred to in the present application may be one or more of chemical vapor deposition, physical vapor deposition, atomic layer deposition, sputtering, evaporation, electroplating, and electroless plating.
The extension line may be made of the same conductive material as the second electrode 120.
The second packaging adhesive layer is made of packaging adhesive. The second packaging adhesive layer formed after the packaging adhesive is cured has better insulation and sealing performance, can provide protection and prevents a product from being affected with damp.
As an example, a conductive pillar 122 extending longitudinally is prepared by additive manufacturing along the inside of the via such that the conductive pillar 122 extends from the via bottom to the via top; then, a horizontally extending conductive via 121 is prepared along the surface of the first encapsulant layer by additive manufacturing, such that one end of the conductive via 121 is connected to the second electrode 120, and the other end is connected to the top of the conductive pillar 122.
As another example, a horizontally extending conductive via 121 is prepared along the surface of the first encapsulant layer by additive manufacturing, such that one end of the conductive via 121 is connected to the second electrode 120, and the other end extends to the top side of the through hole; a longitudinally extending conductive post 122 is then prepared by additive manufacturing along the interior of the via such that the conductive post 122 extends from the bottom of the via to the top of the via and connects with the end of the conductive via 121 remote from the second electrode 120.
In step S130, the chip 100 is turned over to the surface of the second carrier, and the first electrode 110 and the second electrode 120 respectively extend along the surface of the first package adhesive layer by an additive manufacturing method, so as to obtain a chip package.
Horizontally placing the chip 100 on the surface of the second carrier, and preparing an expanded path on the surface of the first packaging adhesive layer in an additive manufacturing manner, so that the first electrode 110 and the second electrode 120 respectively extend along the surface of the first packaging adhesive layer, thereby obtaining the chip package.
The extended path may be made of a conductive material the same as that of the first electrode 110 or the second electrode 120.
In an embodiment of the present application, a specific process of "laying the first encapsulant layer on the peripheral side of the chip 100" may be further described in conjunction with the following description.
An initial packaging adhesive layer is laid on the periphery of the chip 100. Specifically, the initial encapsulating adhesive layer is poured on the surface of the first carrier plate, so that the initial encapsulating adhesive layer wraps around the chip 100, and the top of the initial encapsulating adhesive layer extends to a position not higher than the top of the second electrode 120.
Etching and removing the target part of the initial packaging adhesive layer to form a first packaging adhesive layer; wherein the target portion is a longitudinally extending pillar structure corresponding to a side of the chip 100. Specifically, an etching window is formed by coating a photosensitive material and exposing and developing, so that the target part can be conveniently etched and removed.
In an embodiment of the present application, a specific process of "etching away the target portion of the initial encapsulation adhesive layer to form the first encapsulation adhesive layer" may be further described in conjunction with the following description.
And coating a photosensitive material on the surface of the initial packaging adhesive layer, and exposing and developing to expose the target part of the initial packaging adhesive layer. Specifically, the photosensitive material is coated on the surface of the initial encapsulation adhesive layer, and is exposed and developed, so that the photosensitive material which is subjected to photopolymerization is cured to form a first photosensitive material layer, and the photosensitive material which is not subjected to photopolymerization (i.e., the photosensitive material on the surface of the target portion) is washed away. The photosensitive material comprises photoresist (including positive photoresist and negative photoresist), photosensitive polyimide resin, photosensitive sol-gel or a mixture or a composition thereof, and one or more of PhTES, N-methyl-2-pyrrolidone and polymethyl methacrylate mixed solution, and has better photosensitive characteristics.
And etching and removing the target part to form the first packaging adhesive layer. Specifically, the target site is etched away by rapid chemical etching. Different corrosion solutions can be respectively selected according to the material of the initial packaging adhesive layer, the product is immersed in the corrosion solutions, the corrosion condition is observed, the product is taken out immediately after the first target part is corroded, and the corrosion solutions are removed by washing with clear water.
And removing the photosensitive material. Specifically, the first photosensitive material layer is removed by a degumming agent.
In an embodiment of the present application, a specific process of extending the second electrode 120 to the surface of the first carrier along the surface of the first encapsulant layer and the through hole by an additive manufacturing manner may be further described with reference to the following description.
Preparing a conductive path 121 on the surface of the first packaging adhesive layer in an additive manufacturing manner; wherein the conductive vias 121 are respectively connected to the second electrode 120 and the conductive pillar 122. Specifically, the conductive via 121 extending horizontally is prepared on the surface of the first encapsulant layer by additive manufacturing, such that one end of the conductive via 121 is connected to the second electrode 120, and the other end is connected to the top of the conductive pillar 122.
In an embodiment of the present application, a specific process of "preparing the conductive pillar 122 along the inside of the through hole by an additive manufacturing manner" may be further described in conjunction with the following description.
Coating a photosensitive material on the surface of the first packaging adhesive layer, and carrying out exposure and development to expose a second target area on the surface of the first packaging adhesive layer; wherein the second target area corresponds to a position of the through hole. Specifically, the photosensitive material is coated on the surface of the first packaging adhesive layer, and is exposed and developed, so that the photosensitive material which is subjected to photopolymerization reaction is cured to form a second photosensitive material layer, and the photosensitive material which is not subjected to photopolymerization reaction (i.e. the photosensitive material on the surface of the second target region) is washed away.
The conductive posts 122 are prepared inside the vias by additive manufacturing. Specifically, the conductive pillars 122 extending longitudinally are prepared inside the through holes by an additive manufacturing method.
And removing the photosensitive material. Specifically, the second photosensitive material layer is removed by a degelling agent.
In an embodiment of the present application, a specific process of "preparing the conductive vias 121 on the surface of the first encapsulant layer by additive manufacturing" may be further described in conjunction with the following description.
Coating a photosensitive material on the surface of the first packaging adhesive layer, and carrying out exposure and development to expose a first target area on the surface of the first packaging adhesive layer; wherein the first target area is connected to the second electrode 120 and the conductive pillar 122, respectively. Specifically, the photosensitive material is coated on the surface of the first encapsulation adhesive layer, and is exposed and developed, so that the photosensitive material which has a photopolymerization reaction is cured to form a third photosensitive material layer, and the photosensitive material which has not a photopolymerization reaction (i.e., the photosensitive material on the surface of the first target region) is washed away.
The conductive path 121 is prepared on the surface of the first target area by additive manufacturing. Specifically, the conductive path 121 extending horizontally is prepared on the surface of the target area by an additive manufacturing method.
And removing the photosensitive material. Specifically, the third photosensitive material layer is removed by a degelling agent.
In an embodiment of the present application, a specific process of "extending the first electrode 110 and the second electrode 120 along the surface of the first encapsulant layer by an additive manufacturing manner" may be further described in conjunction with the following description.
Respectively preparing a first expanding passage 111 and a second expanding passage 123 on the surface of the first packaging adhesive layer in an additive manufacturing mode; wherein the first extension path 111 is connected to the first electrode 110; the second expansion path 123 is connected to the second electrode 120. Specifically, the first expanding path 111 and the second expanding path 123 extending horizontally are respectively prepared on the surface of the first packaging adhesive layer in an additive manufacturing manner. Therefore, the electrode of the chip 100 can be expanded, so that the size of the electrode is enlarged, and the welding requirement in application is met.
In an embodiment of the present application, a specific process of "preparing the first extended via 111 and the second extended via 123 on the surface of the first encapsulant layer by additive manufacturing" may be further described in conjunction with the following description.
Coating a photosensitive material on the surface of the first packaging adhesive layer, and carrying out exposure and development to expose a third target area and a fourth target area on the surface of the first packaging adhesive layer; wherein the third target region is connected to the first electrode 110; the fourth target area is connected to the second electrode 120. Specifically, the photosensitive material is coated on the surface of the first encapsulating adhesive layer, and is exposed and developed, so that the photosensitive material which has undergone photopolymerization is cured to form a fourth photosensitive material layer, and the photosensitive material which has not undergone photopolymerization (i.e., the photosensitive material on the surfaces of the third target area and the fourth target area) is washed away.
And respectively preparing the first expansion passage 111 on the surface of the third target area and the second expansion passage 123 on the surface of the fourth target area by an additive manufacturing mode. Specifically, the first expanding passage 111 extending horizontally is prepared on the surface of the three target regions, and the second expanding passage 123 extending horizontally is prepared on the surface of the four target regions, respectively, by an additive manufacturing method.
And removing the photosensitive material. And removing the fourth photosensitive material layer by using a degumming agent.
In an embodiment of the present application, a specific process of "extending the first electrode 110 and the second electrode 120 along the surface of the first encapsulant layer by an additive manufacturing manner" may be further described in conjunction with the following description.
And grinding the first packaging adhesive layer to expose the first electrode 110 and the second electrode 120. Specifically, before "coating a photosensitive material on the surface of the first encapsulation adhesive layer, performing exposure and development, and exposing a third target region and a fourth target region on the surface of the first encapsulation adhesive layer", a grinding device is used to grind the first encapsulation adhesive layer, so that the first electrode 110 and the second electrode 120 are exposed.
It should be noted that, in other embodiments, the number of the chips 100 may also be two or more. When two or more chips 100 are arranged, arranging a plurality of chips 100 on the surface of the first carrier at intervals, so that the first electrode 110 faces the first carrier, and laying the first encapsulant layer on the periphery of each chip 100; the through holes are formed in the first packaging adhesive layer corresponding to the side edges of the chips 100; extending the second electrode 120 of each chip 100 to the surface of the first carrier along the surface of the first encapsulant layer and the through hole respectively by an additive manufacturing method; turning all the chips 100 to the surface of a second carrier, respectively extending the first electrode 110 and the second electrode 120 of each chip 100 along the surface of the first packaging adhesive layer in an additive manufacturing manner, and performing glue filling packaging on all the chips 100 to obtain a chip packaging module; and cutting the chip packaging module to obtain a plurality of chip packaging parts.
In a specific implementation of the present application, the encapsulation method includes:
placing the chip 100 on the surface of a first carrier plate, wherein the first electrode 110 faces the first carrier plate, and a first packaging adhesive layer is laid on the periphery of the chip 100; the first packaging adhesive layer is internally provided with a through hole extending longitudinally;
preparing a longitudinally extending conductive pillar 122 along the inside of the via by additive manufacturing such that the conductive pillar 122 extends from the via bottom to the via top;
preparing a horizontally extending conductive via 121 along the surface of the first encapsulation adhesive layer by an additive manufacturing manner, so that one end of the conductive via 121 is connected to the second electrode 120, and the other end is connected to the top of the conductive pillar 122;
laying a second packaging adhesive layer on the surface of the first packaging adhesive layer;
the chip 100 is turned over to the surface of the second carrier, and the first electrode 110 and the second electrode 120 respectively extend along the surface of the first package adhesive layer in an additive manufacturing manner, so as to obtain a chip package.
In another specific implementation of the present application, the encapsulation method includes:
placing the chip 100 on the surface of a first carrier plate, wherein the first electrode 110 faces the first carrier plate, and a first packaging adhesive layer is laid on the periphery of the chip 100; the first packaging adhesive layer is internally provided with a through hole extending longitudinally;
preparing a horizontally extending conductive path 121 along the surface of the first packaging adhesive layer in an additive manufacturing manner, so that one end of the conductive path 121 is connected with the second electrode 120, and the other end of the conductive path extends to the top side edge of the through hole;
preparing a longitudinally extending conductive pillar 122 along the inside of the via by additive manufacturing, such that the conductive pillar 122 extends from the bottom of the via to the top of the via and connects with the end of the conductive via 121 away from the second electrode 120;
laying a second packaging adhesive layer on the surface of the first packaging adhesive layer;
the chip 100 is turned over to the surface of the second carrier, and the first electrode 110 and the second electrode 120 respectively extend along the surface of the first package adhesive layer in an additive manufacturing manner, so as to obtain a chip package.
Referring to fig. 3, a chip package prepared by the chip CSP packaging method according to any one of the above embodiments is shown, which includes: the chip 100 and the packaging adhesive layer; the packaging adhesive layer wraps the chip 100; the first electrode 110 and the second electrode 120 respectively extend to the surface of the encapsulation adhesive layer. The electrodes of the chip packaging part are arranged on the same surface, so that the chip packaging part is convenient to package by adopting a CSP packaging method, the packaging size is small, the packaging efficiency is high, a packaging substrate is omitted, and the packaging cost is low.
While preferred embodiments of the present application have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the true scope of the embodiments of the application.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrases "comprising one of 8230; \8230;" 8230; "does not exclude the presence of additional like elements in a process, method, article, or terminal device that comprises the element.
The above detailed description is made on the chip CSP packaging method and the chip package provided by the present application, and the principle and the implementation of the present application are explained by applying specific examples, and the description of the above examples is only used to help understanding the method and the core idea of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. A chip CSP packaging method is used for packaging a chip, wherein the chip comprises a first electrode and a second electrode which are oppositely arranged; it is characterized by comprising:
placing the chip on the surface of a first carrier plate, wherein the first electrode faces the first carrier plate, and a first packaging adhesive layer is laid on the peripheral side of the chip; the first packaging adhesive layer is internally provided with a through hole extending longitudinally;
extending the second electrode to the surface of the first carrier plate along the surface of the first packaging adhesive layer and the through hole in an additive manufacturing mode, and laying a second packaging adhesive layer on the surface of the first packaging adhesive layer;
and turning the chip to the surface of a second carrier plate, and respectively extending the first electrode and the second electrode along the surface of the first packaging adhesive layer in an additive manufacturing mode to obtain a chip packaging piece.
2. The CSP packaging method as recited in claim 1 wherein said step of laying a first adhesive packaging layer on the periphery of said chip comprises:
laying an initial packaging adhesive layer on the peripheral side of the chip;
etching and removing the target part of the initial packaging adhesive layer to form a first packaging adhesive layer; the target part is a columnar structure which corresponds to the longitudinal extension of the side edge of the chip.
3. The CSP packaging method of claim 1, wherein the step of extending the second electrode to the surface of the first carrier plate along the surface of the first packaging adhesive layer and the through holes by additive manufacturing comprises:
preparing a conductive column along the inside of the through hole in an additive manufacturing mode;
preparing a conductive path on the surface of the first packaging adhesive layer in an additive manufacturing mode; wherein the conductive via is connected to the second electrode and the conductive pillar, respectively.
4. The chip CSP packaging method according to claim 3, wherein the step of preparing the conductive path on the surface of the first packaging adhesive layer by additive manufacturing comprises:
coating a photosensitive material on the surface of the first packaging adhesive layer, and carrying out exposure and development to expose a first target area on the surface of the first packaging adhesive layer; wherein the first target region is connected to the second electrode and the conductive pillar, respectively;
preparing the conductive path on the surface of the first target area by additive manufacturing;
and removing the photosensitive material.
5. The chip CSP packaging method as recited in claim 1 wherein said step of extending said first and second electrodes along respective surfaces of said first encapsulant layer by additive manufacturing includes:
respectively preparing a first expanding passage and a second expanding passage on the surface of the first packaging adhesive layer in an additive manufacturing mode; wherein the first extended path is connected to the first electrode; the second extended path is connected to the second electrode.
6. The chip CSP packaging method according to claim 5, wherein the step of respectively preparing the first expanding path and the second expanding path on the surface of the first packaging adhesive layer by additive manufacturing comprises:
coating a photosensitive material on the surface of the first packaging adhesive layer, and carrying out exposure and development to expose a third target area and a fourth target area on the surface of the first packaging adhesive layer; wherein the third target region is connected to the first electrode; the fourth target region is connected to the second electrode.
Respectively preparing the first expansion passage on the surface of the third target area and the second expansion passage on the surface of the fourth target area in an additive manufacturing mode;
and removing the photosensitive material.
7. The chip CSP packaging method as recited in claim 5 wherein said step of extending said first and second electrodes along respective surfaces of said first encapsulant layer by additive manufacturing further comprises:
and grinding the first packaging adhesive layer to expose the first electrode and the second electrode.
8. The chip CSP packaging method according to claim 1, wherein the additive manufacturing manner comprises one or more of chemical vapor deposition, physical vapor deposition, atomic layer deposition, sputtering, evaporation, electroplating and electroless plating.
9. The chip CSP packaging method according to claim 1, wherein the material of the first and second packaging adhesive layers comprises one or more of epoxy resin, silica gel, PI resin, PE resin and PT resin.
10. A chip package prepared by the chip CSP packaging method according to any one of claims 1 to 9, comprising: the chip and the packaging adhesive layer; the packaging adhesive layer wraps the chip; the first electrode and the second electrode respectively extend to the surface of the packaging glue layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211594753.0A CN115831775A (en) | 2022-12-13 | 2022-12-13 | Chip CSP packaging method and chip packaging piece |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211594753.0A CN115831775A (en) | 2022-12-13 | 2022-12-13 | Chip CSP packaging method and chip packaging piece |
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| CN115831775A true CN115831775A (en) | 2023-03-21 |
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| CN202211594753.0A Pending CN115831775A (en) | 2022-12-13 | 2022-12-13 | Chip CSP packaging method and chip packaging piece |
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| CN (1) | CN115831775A (en) |
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2022
- 2022-12-13 CN CN202211594753.0A patent/CN115831775A/en active Pending
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