CN115801025B

CN115801025B - Up-conversion mixing method and digital transmitter

Info

Publication number: CN115801025B
Application number: CN202210781076.7A
Authority: CN
Inventors: 戎亮
Original assignee: Shanghai Xingsi Semiconductor Co ltd
Current assignee: Shanghai Xingsi Semiconductor Co ltd
Priority date: 2022-07-04
Filing date: 2022-07-04
Publication date: 2023-07-11
Anticipated expiration: 2042-07-04
Also published as: WO2024007454A1; CN115801025A

Abstract

The application provides an up-conversion mixing method and a digital transmitter architecture, wherein the method comprises the following steps: collectingWith 2 ⁿ Each phase in the phase local oscillation IQ digital signal respectively carries out up-conversion and mixing processing on the in-phase baseband digital signal and the quadrature baseband digital signal which are received simultaneously to obtain 2 ⁿ And (3) carrying out phase up-conversion on the mixed signals, wherein n is an integer, n is more than or equal to 2, and the phases of any two-phase local oscillation IQ digital signals are different. The method and the device can effectively relieve the problem of serious modulation harmonic waves.

Description

Up-conversion mixing method and digital transmitter

Technical Field

The present application relates to the field of digital transmitters, and in particular, to an up-conversion mixing method, a computer program, a computer readable storage medium, an FPGA, and a digital transmitter.

Background

The digital transmitter is based on a digital algorithm, takes a transmitter implementation mode of taking a full digital logic operation unit (Standard Cell) as a main internal module (or basic unit) of the transmitter, and is matched with a proper output power matching module to realize a circuit framework form with the same working principle (radio frequency signal transmission) as an analog transmitter.

Compared with the analog transmitter architecture, the digital transmitter architecture has simpler and alternative module functions in implementation to realize corresponding functional modules of the analog transmitter. And by taking advantage of the high density nature of digital modules, a more compact transmitter architecture (area advantage) and more efficient power transmission (switching power amplifier nature transmitter) are achieved.

Research in digital transmitters has been carried out in the industry for many years, where power output modules are divided into two broad categories, the voltage-power mode, i.e. the SCPA (Switch Capacitor Power Amplifier, switched capacitor power amplifier) form, and the current mode, i.e. the CEPA (Current Envelop Power Amplifier, current envelope power amplifier) form. The existing digital transmitter architecture schemes currently include:

1) Digital transmitter circuitry employing a phase-contrast architecture of LINC (Linear Amplification with Nonlinear Components, linear with nonlinear components) and its modified form of M-LINC form digital transmitter circuitry;

2) An In-Phase Quadrature (In-Phase Quadrature) Sharing SCPA digital circuit is directly adopted, the modulation frequency bandwidth is large, but modulation harmonic wave which is difficult to eliminate is usually generated because radio frequency modulation cannot be used In a high-frequency band, and the switching Phase of radio frequency is required to be dynamically switched by an IQ Sharing scheme, so that the control frequency of the SCPA digital circuit is difficult to control;

3) The SCPA circuit adopting the digital POLAR (POLAR) modulation scheme has a difficult signal processing bandwidth at present, because the bandwidth of the phase component often needs more than 3 times of the baseband signal to cover the phase change signal with characteristic meaning, and therefore, the design control difficulty of the PLL (Phase Locked Loop, phase-locked loop) is higher. At present, INTEL adopts a POLAR framework with a high frequency multiplication asymmetric mode, and can solve the existing harmonic problems. But falls into the category of radio frequency modulation (my non-radio frequency modulation frequency) due to the sampling frequency being too high.

The digital transmitter circuit adopting the LINC mode or the digital transmitter circuit adopting the MLINC (Multiple LINC) framework has overlarge area, the requirement of vector signal Combination of radio frequency on phase noise amplitude is far higher than that of a digital IQ coding (Combination) scheme used in the current patent, the baseband computing capability requirement is very high, the digital computing power consumption is high, and vector decomposition is needed. Because each SCPA driver needs to perform initial switching phase adjustment according to the combination value of IQ, the digital transmitting mechanism frame adopting the IQ-Sharing mode has the effect that the modulation harmonic wave occurs at the modulation frequency position (usually Fc/N, N is a positive integer) as a result of the frequency-reducing operation because the actual dynamic combination working frequency (the modulation frequency can not reach the frequency point above the 3GH up-conversion frequency mixing). The phase extraction of the digital POLAR framework requires that by controlling the phase of the PLL, a very large bandwidth requirement is created in the process of combining the radio frequency phase signal with the amplitude envelope signal. Therefore, the working frequency of the system cannot reach the radio frequency, so that higher modulation harmonic exists on two sides of a modulation frequency interval from a carrier center frequency point, and meanwhile, the system needs to use square root calculation and trigonometric function calculation to carry out CORDIC (Coordinate Rotation Digital Computer, coordinate rotation digital calculation method) decomposition from a general baseband IQ signal, so that the actual baseband calculation power consumption is also high.

Disclosure of Invention

The main objective of the present application is to provide an up-conversion mixing method, a computer program, a computer readable storage medium, an FPGA and a digital transmitter, so as to solve the problem of serious harmonic of the digital modulation transmitter in the prior art.

According to one aspect of an embodiment of the present invention, there is providedAn up-conversion mixing method is provided, comprising: by 2 ⁿ Each phase in the phase local oscillation IQ digital signal respectively carries out up-conversion and mixing processing on the in-phase baseband digital signal and the quadrature baseband digital signal which are received simultaneously to obtain 2 ⁿ And carrying out phase up-conversion on the mixed signals, wherein n is an integer, n is more than or equal to 2, and the phases of the IQ digital signals of any two phases are different.

Optionally, each phase of the local oscillation IQ digital signal includes a local oscillation i+ template signal, a local oscillation I-template signal, a local oscillation q+ template signal, and a local oscillation Q-template signal, and 2 is adopted ⁿ Each phase in the phase local oscillation IQ digital signal respectively carries out up-conversion and mixing processing on the in-phase baseband digital signal and the quadrature baseband digital signal which are received simultaneously to obtain 2 ⁿ Phase up-converting the mixed signal, comprising: performing bit AND operation on the local oscillator I+ template signal and the in-phase baseband digital signal to obtain a first radio frequency signal; performing bit AND operation on the local oscillator I-template signal and the in-phase baseband digital signal to obtain a second radio frequency signal; performing bit AND operation by adopting the local oscillator Q+ template signal and the quadrature baseband digital signal to obtain a third radio frequency signal; performing bit AND operation by adopting the local oscillator Q-template signal and the quadrature baseband digital signal to obtain a fourth radio frequency signal; and carrying out frequency mixing processing on the first radio frequency signal, the second radio frequency signal, the third radio frequency signal and the fourth radio frequency signal to obtain a positive frequency up-conversion frequency mixed signal and a negative frequency up-conversion frequency mixed signal.

Optionally, performing mixing processing on the first radio frequency signal, the second radio frequency signal, the third radio frequency signal and the fourth radio frequency signal to obtain a positive up-conversion mixed signal and a negative up-conversion mixed signal, including: when the in-phase baseband digital signal has positive attribute and the quadrature baseband digital signal has positive attribute, performing bit OR operation on the first radio frequency signal and the third radio frequency signal to obtain the positive up-conversion mixed signal, and performing bit OR operation on the second radio frequency signal and the fourth radio frequency signal to obtain the negative up-conversion mixed signal; when the in-phase baseband digital signal has positive attribute and the quadrature baseband digital signal has negative attribute, performing bit OR operation on the first radio frequency signal and the fourth radio frequency signal to obtain the positive up-conversion mixed signal, and performing bit OR operation on the second radio frequency signal and the third radio frequency signal to obtain the negative up-conversion mixed signal; when the in-phase baseband digital signal has negative attribute and the quadrature baseband digital signal has positive attribute, performing bit OR operation on the second radio frequency signal and the third radio frequency signal to obtain the positive up-conversion mixed signal, and performing bit OR operation on the first radio frequency signal and the fourth radio frequency signal to obtain the negative up-conversion mixed signal; and when the in-phase baseband digital signal has negative attribute and the quadrature baseband digital signal has negative attribute, performing bit OR operation on the second radio frequency signal and the fourth radio frequency signal to obtain the positive up-conversion mixed signal, and performing bit OR operation on the first radio frequency signal and the third radio frequency signal to obtain the negative up-conversion mixed signal.

According to another aspect of an embodiment of the present invention, there is provided a computer program for performing any of the methods.

According to another aspect of an embodiment of the present invention, there is provided a computer-readable storage medium including a stored program, wherein the program performs any one of the methods.

According to yet another aspect of an embodiment of the present invention, there is also provided an FPGA (Field Programmable Gate Array ) for running a program, wherein the program when run performs any of the methods described herein.

According to yet another aspect of an embodiment of the present invention, there is also provided a digital transmitter including an up-conversion mixing module and a plurality of first filters, wherein the up-conversion mixing module is configured to perform any of the methods; the plurality of first filters are respectively used for carrying out filtering processing on one up-conversion mixed signal output by the up-conversion mixing module so as to obtain a power amplification signal with an out-of-band signal suppression effect, wherein the filtering processing comprises shifting processing, power amplification processing and power combining processing.

Optionally, the first filter is a parallel FIR (Finite Impulse Response, finite length unit impulse response) filter, and the parallel FIR filter includes a plurality of parallel shift registers, a plurality of serializers, and a plurality of power amplifiers, where the parallel shift registers are configured to perform parallel shift processing on the same received up-converted mixed signal to obtain a plurality of parallel shift signals; the serializers are respectively used for converting one received parallel shift signal into a serial digital signal; the power amplifiers are respectively used for carrying out power amplification on a received serial digital signal so as to obtain power amplified signals; and the switch capacitors are used for combining the power amplification signals output by the power amplifiers.

Optionally, the shift frequency of the parallel shift processing is the modulation frequency or the carrier frequency of the up-conversion mixed signal; and/or the parallel FIR filter further comprises at least one input selection module for selecting an input timing corresponding to the parallel shift register so that the same parallel FIR filter comprises a plurality of parallel shift registers having M input timings; and the output of the parallel shift register with the largest number corresponding to the (j-1) th input time sequence is the input of the parallel shift register with the smallest number corresponding to the j-th input time sequence, and the number of the parallel shift registers with the numbers corresponding to the M=N is greater than the number of the parallel shift registers corresponding to the (j-1) th input time sequence, wherein the number of the parallel shift registers corresponding to the j-th input time sequence is greater than the number of the parallel shift registers corresponding to the (j-1) th input time sequence, and the number of the parallel shift registers with the numbers corresponding to the M=N is greater than or equal to 1.

Optionally, the digital transmitter further includes a second filter and a transmitting antenna, where the second filter is configured to filter the power amplified signal output by the first filter; the transmitting antenna is used for receiving the filtered power amplification signal output by the second filter and sending the power amplification signal; and/or the digital transmitter further comprises an in-phase modulator, a quadrature modulator and a decoder, wherein the in-phase modulator comprises a plurality of in-phase modulation modules which are sequentially connected in series, the in-phase modulation modules are used for receiving in-phase input signals and/or signal errors, generating in-phase modulation signals according to the in-phase input signals and/or the signal errors and outputting the in-phase modulation signals, the signal errors are error values which are acquired by the in-phase modulation modules and sent to the next in-phase modulation module, and the error values are errors between the in-phase input signals and the in-phase modulation signals generated by the in-phase modulation modules; the quadrature modulator comprises a plurality of quadrature modulation modules which are sequentially connected in series, wherein the quadrature modulation modules are used for receiving quadrature input signals and/or signal errors, generating quadrature modulation signals according to the quadrature input signals and/or the error values and outputting the quadrature modulation signals, wherein the signal errors are error values obtained by the quadrature modulation modules and sent to the next quadrature modulation module, and the error values are errors between the quadrature input signals and the quadrature modulation signals generated by the quadrature modulation modules; the decoder is respectively connected with the in-phase modulator, the quadrature modulator and the up-conversion mixing module, and is used for receiving a plurality of in-phase modulation signals and a plurality of quadrature modulation signals, decoding the in-phase modulation signals according to a decoder truth table, generating in-phase baseband digital signals and outputting the in-phase baseband digital signals to the up-conversion mixing module, decoding the quadrature modulation signals according to the decoder truth table, generating quadrature baseband digital signals and outputting the quadrature baseband digital signals to the up-conversion mixing module.

By adopting the technical scheme, in the up-conversion mixing method, 2 is adopted ⁿ Each phase in (n is more than or equal to 2) phase local oscillation IQ digital signals carries out up-conversion and mixing treatment on the in-phase baseband digital signals and the quadrature baseband digital signals respectively to obtain 2 ⁿ Phase up-conversion of mixed signals, i.e. local oscillation IQ digital signals with 4, 8 and 16 equal phases are adopted to count the in-phase basebandAnd carrying out up-conversion mixing treatment on the digital signals and the quadrature baseband digital signals to obtain up-conversion mixed signals with corresponding numbers. Compared with the prior art, the digital modulation transmitter has the serious problem of harmonic wave, and the application adopts the equal 2 of 4 phases and 8 phases ⁿ The local oscillation IQ digital signals with different phase phases are subjected to up-conversion and mixing treatment on the digital baseband signals, so that the problem of near-field noise degradation caused by folding back the local oscillation frequency in the frequency domain after the harmonic waves are convolved by the local oscillation signals in the up-conversion and mixing process can be well restrained, and the problem of serious modulation harmonic waves can be effectively relieved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:

FIG. 1 shows a flow diagram of an upconversion mixing method according to an embodiment of the present application;

FIG. 2 is a schematic diagram illustrating a truth table for 4 sets of local oscillation IQ digital signals according to an embodiment of the present application;

fig. 3 shows a schematic diagram of a digital transmitter according to an embodiment of the present application;

FIG. 4 shows a schematic diagram of the structure of a parallel FIR filter according to an embodiment of the present application;

fig. 5 and 6 are diagrams illustrating decoder truth tables of different bits, respectively, according to embodiments of the present application.

Wherein the above figures include the following reference numerals:

100. an up-conversion mixing module; 200. a first filter; 201. a parallel shift register and a serializer; 300. a power amplifier; 400. a second filter; 500. a modulator; 600. a decoder; 700. a DSP module; 800. a processing module; 900. a transmitting antenna; 101. an input selection module; 102. a parallel shift register.

Detailed Description

It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

In order to make the present application solution better understood by those skilled in the art, the following description will be made in detail and with reference to the accompanying drawings in the embodiments of the present application, it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, shall fall within the scope of the present application.

It should be noted that the terms "first," "second," and the like in the description and claims of this application and the accompanying drawings are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the present application described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Furthermore, in the description and in the claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.

As described in the background, the harmonics of the digital modulation transmitter in the prior art are serious, and in order to solve the above problem, in an exemplary embodiment of the present application, an up-conversion mixing method, a computer program, a computer readable storage medium, an FPGA, and a digital transmitter are provided.

According to an embodiment of the present application, an up-conversion mixing method is provided.

Fig. 1 is a flow chart of an up-conversion mixing method according to an embodiment of the present application. As shown in fig. 1, the method comprises the steps of:

step S101, adopt 2 ⁿ Each phase in the phase local oscillation IQ digital signal respectively carries out up-conversion and mixing processing on the in-phase baseband digital signal and the quadrature baseband digital signal which are received simultaneously to obtain 2 ⁿ And carrying out phase up-conversion on the mixed signals, wherein n is an integer, n is more than or equal to 2, and the phases of any two phases of local oscillation IQ digital signals are different.

In the up-conversion mixing method, 2 is adopted ⁿ Each phase in (n is more than or equal to 2) phase local oscillation IQ digital signals carries out up-conversion and mixing treatment on the in-phase baseband digital signals and the quadrature baseband digital signals respectively to obtain 2 ⁿ And carrying out up-conversion mixing treatment on the in-phase baseband digital signals and the quadrature baseband digital signals by adopting local oscillation IQ digital signals with 4 phases, 8 phases and 16 equal phases to obtain corresponding numbers of up-conversion mixing signals. Compared with the prior art, the digital modulation transmitter has the serious problem of harmonic wave, and the application adopts the equal 2 of 4 phases and 8 phases ⁿ The local oscillation IQ digital signals with different phase phases are subjected to up-conversion and mixing treatment on the digital baseband signals, so that the problem of near-field noise degradation caused by folding back the local oscillation frequency in the frequency domain after the harmonic waves are convolved by the local oscillation signals in the up-conversion and mixing process can be well restrained, and the problem of serious modulation harmonic waves can be effectively relieved.

According to a specific embodiment of the present application, each phase of the local oscillation IQ digital signal includes a local oscillation i+ template signal, a local oscillation I-template signal, a local oscillation q+ template signal, and a local oscillation Q-template signal, and 2 is adopted ⁿ Each phase in the phase local oscillation IQ digital signal respectively carries out up-conversion and mixing processing on the in-phase baseband digital signal and the quadrature baseband digital signal which are received simultaneously to obtain 2 ⁿ Phase up-converting the mixed signal, comprising: performing bit AND operation by using the local oscillator I+ template signal and the in-phase baseband digital signal to obtainA first radio frequency signal; performing bit and operation on the local oscillator I-template signal and the in-phase baseband digital signal to obtain a second radio frequency signal; performing bit and operation on the local oscillator Q+ template signal and the quadrature baseband digital signal to obtain a third radio frequency signal; performing bit and operation on the local oscillator Q-template signal and the quadrature baseband digital signal to obtain a fourth radio frequency signal; and carrying out frequency mixing processing on the first radio frequency signal, the second radio frequency signal, the third radio frequency signal and the fourth radio frequency signal to obtain a positive frequency up-conversion frequency mixed signal and a negative frequency up-conversion frequency mixed signal. In this embodiment, taking the local oscillation IQ digital signals with different 4 phases as an example, since the local oscillation IQ digital signals are in differential form, there is no modulated harmonic at the positions Fc (main carrier signal frequency) and 3Fc (third order carrier signal frequency), so for the 4 th order carrier harmonic existing in the 4Fc (fourth order carrier signal frequency), there is no mixing between the 3Fc and the 4Fc, and thus noise overlapping of the final carrier position is reduced, and further effects of suppressing modulated harmonic in the signals are achieved.

In order to further suppress modulation harmonics of the upconverted mixed signal, in another specific embodiment of the present application, the mixing processing is performed on the first radio frequency signal, the second radio frequency signal, the third radio frequency signal, and the fourth radio frequency signal to obtain a positive upconverted mixed signal and a negative upconverted mixed signal, which includes: when the in-phase baseband digital signal has positive attribute and the quadrature baseband digital signal has positive attribute, performing bit OR operation on the first radio frequency signal and the third radio frequency signal to obtain the positive up-conversion mixed signal, and performing bit OR operation on the second radio frequency signal and the fourth radio frequency signal to obtain the negative up-conversion mixed signal; when the in-phase baseband digital signal has positive attribute and the quadrature baseband digital signal has negative attribute, performing bit OR operation on the first radio frequency signal and the fourth radio frequency signal to obtain the positive up-conversion mixed signal, and performing bit OR operation on the second radio frequency signal and the third radio frequency signal to obtain the negative up-conversion mixed signal; when the in-phase baseband digital signal has a negative attribute and the quadrature baseband digital signal has a positive attribute, performing bit OR operation on the second radio frequency signal and the third radio frequency signal to obtain the positive up-conversion mixed signal, and performing bit OR operation on the first radio frequency signal and the fourth radio frequency signal to obtain the negative up-conversion mixed signal; and when the in-phase baseband digital signal has negative attribute and the quadrature baseband digital signal has negative attribute, performing bit OR operation on the second radio frequency signal and the fourth radio frequency signal to obtain the positive up-conversion mixed signal, and performing bit OR operation on the first radio frequency signal and the third radio frequency signal to obtain the negative up-conversion mixed signal.

According to a further specific embodiment of the present application, the in-phase baseband digital signal and the quadrature baseband digital signal respectively comprise sign bits and a first data set located on one side of the sign bits, where 2 is adopted ⁿ Before each phase in the phase local oscillation IQ digital signal performs up-conversion mixing processing on the in-phase baseband digital signal and the quadrature baseband digital signal which are received simultaneously, the method further includes: demodulating each first data set respectively to determine a corresponding second data set, wherein the second data set is in mirror symmetry with the corresponding first data set; and placing the second data set on one side of the first data set far away from the sign bit to obtain a demodulated in-phase signal and a demodulated quadrature signal. The in-phase baseband digital signal and the quadrature baseband digital signal with mirror symmetry rules are demodulated to obtain complete in-phase signals and quadrature signals, so that the data occupation amount of the in-phase baseband digital signal and the quadrature baseband digital signal is ensured to be small, and meanwhile, the transmission of the in-phase baseband digital signal and the quadrature baseband digital signal is ensured to be convenient.

In a specific embodiment, n=2, that is, the method of the present application processes the digital baseband signal including the in-phase baseband digital signal and the quadrature baseband digital signal with 4-phase data, so that compared with the method of using 2-phase data, the 2-phase local oscillation IQ digital signal added in the present application can suppress the harmonic wave at the position of 2Fc (carrier signal frequency of the second phase) from being convolved by the local oscillation (basically equivalent to carrier signal frequency Fc) and then fold back to Fc in the frequency domain, thereby causing the problem of near-field noise degradation and alleviating the problem of serious modulation harmonic wave. The truth table of the above-mentioned local oscillation IQ digital signal of 4 phases is shown in fig. 2. P1-P4 respectively represent phase 1-phase 4 four-phase IQ local oscillation signal template data. After the local oscillation digital signals with 4 different configurations used in the embodiment and the PWM decoding signals are subjected to bit and operation, a digital I/Q dual-channel radio frequency mixing signal is obtained, and a subsequent digital IQ mixing module can directly perform 'bit or' combination on the 4-phase I/Q radio frequency signals after up-conversion.

The specific up-conversion mixing implementation process is as follows:

when the in-phase baseband digital signal and the quadrature baseband digital signal after PWM decoding are 9 bits (1 bit sign bit+8 bit digital bit), for example, when the input of PWM decoding is-3/2, the decoder truth table shown in fig. 5 may be obtained, where the in-phase baseband digital signal after PWM decoding is 1.0111.1110 and the quadrature baseband digital signal is 0.0011.1100, where the first bits of the in-phase baseband digital signal and the quadrature baseband digital signal both represent sign bits, 0 represents positive, and 1 represents negative. The in-phase baseband digital signal and the quadrature baseband digital signal need to be subjected to I/Q mixing with a 4-phase IQ local oscillation digital signal template, so that pulse digital stream data represented by each phase is obtained respectively.

Mixing the in-phase baseband digital signal with a local oscillator I+ template signal of a first phase to obtain a first radio frequency signal Iap, mixing the quadrature baseband digital signal with a local oscillator Q+ template signal of the first phase to obtain a third radio frequency signal Qap, mixing the in-phase baseband digital signal with a local oscillator I-template signal of the first phase to obtain a second radio frequency signal Ian, and mixing the quadrature baseband digital signal with the local oscillator Q-template signal of the first phase to obtain a fourth radio frequency signal Qan with the values of:

first radio frequency signal iap= (1000.1000 & 0111.1110) = 0000.1000;

second radio frequency signal ian= (0010.0010 & 0111.1110) = 0010.0010;

third radio frequency signal qap= (0100.0100 & 0011.1100) = 0000.0100;

fourth radio frequency signal Qan = (0001.0001 & 0011.1100) = 0001.0000;

then, a mixing operation is performed, i.e., the generated 4 sets of signals are bit-or-combined, wherein the quadrature baseband digital signal has a positive property due to the in-phase baseband digital signal having a negative property, so that:

and combining Ian and Qap to obtain an up-conversion mixed forward up-conversion mixed signal IQap= 0010.0110;

iap is combined with Qan to obtain an upconverted, mixed negative upconverted mixed signal iqan= 0001.1000.

Equivalent to outputting 3 pulse widths in the positive PA, 2 pulse width data in the negative PA.

Similarly, the in-phase baseband digital signal and the second phase mix to obtain a first radio frequency signal Ibp and a second radio frequency signal Ibn respectively, and the quadrature baseband digital signal and the second phase mix to obtain a third radio frequency signal Qbp and a fourth radio frequency signal Qbn respectively have the values:

first radio frequency signal ibp= (0001.0001 & 0111.1110) = 0001.0000;

second radio frequency signal ibn= (0100.0100 & 0111.1110) = 0100.0100;

third radio frequency signal qbp= (1000.1000 & 0011.1100) = 0000.1000;

fourth radio frequency signal Qbn = (0010.0010 & 0011.1100) = 0010.0000;

then, since the in-phase baseband digital signal has a negative property, the quadrature baseband digital signal has a positive property, a mixing operation is performed to obtain an up-converted mixed forward digital signal iqbp= 0100.1100, and an up-converted mixed forward digital signal iqbn= 0011.0000.

Similarly, the in-phase baseband digital signal is mixed with the third phase to obtain the first radio frequency signal Icp and the second radio frequency signal Icn, and the quadrature baseband digital signal is mixed with the third phase to obtain the third radio frequency signal Qcp and the fourth radio frequency signal Qcn with the values of:

first radio frequency signal icp= (0010.0010 & 0111.1110) = 0010.0010;

second radio frequency signal icn= (1000.1000 & 0111.1110) = 0000.1000;

Third radio frequency signal qcp= (0001.0001 & 0011.1100) = 0001.0000;

fourth radio frequency signal Qcn = (0100.0100 & 0011.1100) = 0000.0100.

Then, since the in-phase baseband digital signal has a negative attribute, the quadrature baseband digital signal has a positive attribute, and a mixing operation is performed, so as to obtain a forward digital signal after up-conversion mixing and a forward digital signal after up-conversion mixing, where iqcp=0001.1000 and iqcn= 0010.0110, respectively.

Similarly, the in-phase baseband digital signal is mixed with the fourth phase to obtain the first radio frequency signal Idp and the second radio frequency signal Idn, and the quadrature baseband digital signal is mixed with the fourth phase to obtain the third radio frequency signal Qdp and the fourth radio frequency signal Qdn respectively with the values:

first radio frequency signal idp= (0100.0100 & 0111.1110) = 0100.0100;

second radio frequency signal idn= (0001.0001 & 0111.1110) = 0001.0000;

third radio frequency signal qdp= (0010.0010 & 0011.1100) = 0010.0000;

fourth radio frequency signal Qdn = (1000.1000 & 0011.1100) = 0000.1000;

then, since the in-phase baseband digital signal has a negative attribute, the quadrature baseband digital signal has a positive attribute, and a mixing operation is performed, so as to obtain an up-converted and mixed forward digital signal and an up-converted and mixed forward digital signal, which are respectively iqdp= 0011.0000 and iqdn= 0100.1100.

It should be noted that the steps illustrated in the flowcharts of the figures may be performed in a computer system such as a set of computer executable instructions, and that although a logical order is illustrated in the flowcharts, in some cases the steps illustrated or described may be performed in an order other than that illustrated herein.

The embodiment of the application also provides an up-conversion mixing device, and it should be noted that the up-conversion mixing device of the embodiment of the application can be used for executing the up-conversion mixing method provided by the embodiment of the application. The following describes an up-conversion mixing device provided in an embodiment of the present application.

The up-conversion mixing device of the embodiment of the application comprises a processing unit, wherein the processing unit is used for adopting 2 ⁿ Each phase in the phase local oscillation IQ digital signal respectively carries out up-conversion and mixing processing on the in-phase baseband digital signal and the quadrature baseband digital signal which are received simultaneously to obtain 2 ⁿ And carrying out phase up-conversion on the mixed signals, wherein n is an integer, n is more than or equal to 2, and the phases of any two phases of local oscillation IQ digital signals are different.

In the up-conversion mixer, the processing means uses 2 ⁿ Each phase in (n is more than or equal to 2) phase local oscillation IQ digital signals carries out up-conversion and mixing treatment on the in-phase baseband digital signals and the quadrature baseband digital signals respectively to obtain 2 ⁿ And carrying out up-conversion mixing treatment on the in-phase baseband digital signals and the quadrature baseband digital signals by adopting local oscillation IQ digital signals with 4 phases, 8 phases and 16 equal phases to obtain corresponding numbers of up-conversion mixing signals. Compared with the prior art, the digital modulation transmitter has the serious problem of harmonic wave, and the application adopts the equal 2 of 4 phases and 8 phases ⁿ The local oscillation IQ digital signals with different phase phases are subjected to up-conversion and mixing treatment on the digital baseband signals, so that the problem of near-field noise degradation caused by folding back the local oscillation frequency in the frequency domain after the harmonic waves are convolved by the local oscillation signals in the up-conversion and mixing process can be well restrained, and the problem of serious modulation harmonic waves can be effectively relieved.

According to a specific embodiment of the present application, each phase of the local oscillator IQ digital signal includes a local oscillator i+ template signal, a local oscillator I-template signal, a local oscillator q+ template signal, and a local oscillator Q-template signal, where the processing unit includes a first operation module, a second operation module, a third operation module, a fourth operation module, and a processing module, where the first operation module is configured to perform a bit and operation with the local oscillator i+ template signal and the in-phase baseband digital signal, so as to obtain a first radio frequency signal; the second operation module is used for performing bit and operation on the local oscillator I-template signal and the in-phase baseband digital signal to obtain a second radio frequency signal; the third operation module is used for performing bit and operation on the local oscillator Q+ template signal and the quadrature baseband digital signal to obtain a third radio frequency signal; the fourth operation module is used for performing bit and operation on the local oscillator Q-template signal and the quadrature baseband digital signal to obtain a fourth radio frequency signal; and the processing module carries out frequency mixing processing on the first radio frequency signal, the second radio frequency signal, the third radio frequency signal and the fourth radio frequency signal by using English to obtain a positive up-conversion frequency-mixed signal and a negative up-conversion frequency-mixed signal. In this embodiment, taking the local oscillation IQ digital signals with different 4 phases as an example, since the local oscillation IQ digital signals are in differential form, there is no modulated harmonic at the positions Fc (main carrier signal frequency) and 3Fc (third order carrier signal frequency), so for the 4 th order carrier harmonic existing in the 4Fc (fourth order carrier signal frequency), there is no mixing between the 3Fc and the 4Fc, and thus noise overlapping of the final carrier position is reduced, and further effects of suppressing modulated harmonic in the signals are achieved.

In order to further suppress modulation harmonics of the upconverted mixed signal, in another specific embodiment of the present application, the processing module includes a first operator module, a second operator module, a third operator module, and a fourth operator module, where the first operator module is configured to perform a bit or operation on the first radio frequency signal and the third radio frequency signal to obtain the positive upconverted mixed signal, and perform a bit or operation on the second radio frequency signal and the fourth radio frequency signal to obtain the negative upconverted mixed signal when the in-phase baseband digital signal has a positive attribute and the quadrature baseband digital signal has a positive attribute; the second operation submodule is configured to perform a bit or operation on the first radio frequency signal and the fourth radio frequency signal to obtain the positive up-conversion mixed signal when the in-phase baseband digital signal has a positive attribute and the quadrature baseband digital signal has a negative attribute, and perform a bit or operation on the second radio frequency signal and the third radio frequency signal to obtain the negative up-conversion mixed signal; the third operation submodule is configured to perform a bit or operation on the second radio frequency signal and the third radio frequency signal to obtain the positive up-conversion mixed signal when the in-phase baseband digital signal has a negative attribute and the quadrature baseband digital signal has a positive attribute, and perform a bit or operation on the first radio frequency signal and the fourth radio frequency signal to obtain the negative up-conversion mixed signal; the fourth operation submodule is configured to perform a bit or operation on the second radio frequency signal and the fourth radio frequency signal to obtain the positive up-conversion mixed signal when the in-phase baseband digital signal has a negative attribute and the quadrature baseband digital signal has a negative attribute, and perform a bit or operation on the first radio frequency signal and the third radio frequency signal to obtain the negative up-conversion mixed signal.

According to a further specific embodiment of the present application, the in-phase baseband digital signal and the quadrature baseband digital signal respectively include a sign bit and a first data set located at one side of the sign bit, and the apparatus further includes a demodulation module and a placement module, where the demodulation module is configured to, when using 2 ⁿ Before each phase in the phase local oscillation IQ digital signals respectively carries out up-conversion mixing processing on the in-phase baseband digital signals and the quadrature baseband digital signals which are received simultaneously, demodulating each first data set respectively to determine a corresponding second data set, wherein the second data set is in mirror symmetry with the corresponding first data set; the placement module is configured to place the second data set on a side of the first data set away from the sign bit, so as to obtain a demodulated in-phase signal and a demodulated quadrature signal. The in-phase baseband digital signal and the quadrature baseband digital signal with mirror symmetry rules are demodulated to obtain complete in-phase signals and quadrature signals, so that the data occupation amount of the in-phase baseband digital signal and the quadrature baseband digital signal is ensured to be small, and meanwhile, the transmission of the in-phase baseband digital signal and the quadrature baseband digital signal is ensured to be convenient.

In a specific embodiment, n=2, that is, the apparatus of the present application processes a digital baseband signal including an in-phase baseband digital signal and the quadrature baseband digital signal with 4-phase data, so that compared with using 2-phase data, the 2-phase local oscillation IQ digital signal added in the present application can suppress the harmonic wave at the position of 2Fc (carrier signal frequency of the second phase) from being convolved by the local oscillation (substantially equivalent to carrier signal frequency Fc) signal, and fold back to Fc in the frequency domain, thereby causing the problem of near-field noise degradation and alleviating the problem of serious modulation harmonic wave. The truth table of the above-mentioned local oscillation IQ digital signal of 4 phases is shown in fig. 2. P1-P4 respectively represent phase 1-phase 4 four-phase IQ local oscillation signal template data. After the local oscillation digital signals with 4 different configurations used in the embodiment and the PWM decoding signals are subjected to bit and operation, a digital I/Q dual-channel radio frequency mixing signal is obtained, and a subsequent digital IQ mixing module can directly perform 'bit or' combination on the 4-phase I/Q radio frequency signals after up-conversion.

The specific up-conversion mixing implementation process is as follows:

first radio frequency signal iap= (1000.1000 & 0111.1110) = 0000.1000;

second radio frequency signal ian= (0010.0010 & 0111.1110) = 0010.0010;

third radio frequency signal qap= (0100.0100 & 0011.1100) = 0000.0100;

fourth radio frequency signal Qan = (0001.0001 & 0011.1100) = 0001.0000;

first radio frequency signal ibp= (0001.0001 & 0111.1110) = 0001.0000;

second radio frequency signal ibn= (0100.0100 & 0111.1110) = 0100.0100;

third radio frequency signal qbp= (1000.1000 & 0011.1100) = 0000.1000;

fourth radio frequency signal Qbn = (0010.0010 & 0011.1100) = 0010.0000;

first radio frequency signal icp= (0010.0010 & 0111.1110) = 0010.0010;

second radio frequency signal icn= (1000.1000 & 0111.1110) = 0000.1000;

Third radio frequency signal qcp= (0001.0001 & 0011.1100) = 0001.0000;

fourth radio frequency signal Qcn = (0100.0100 & 0011.1100) = 0000.0100.

first radio frequency signal idp= (0100.0100 & 0111.1110) = 0100.0100;

second radio frequency signal idn= (0001.0001 & 0111.1110) = 0001.0000;

third radio frequency signal qdp= (0010.0010 & 0011.1100) = 0010.0000;

fourth radio frequency signal Qdn = (1000.1000 & 00111100) = 0000.1000;

The up-conversion mixing device comprises a processor and a memory, wherein the processing unit and the like are stored in the memory as program units, and the processor executes the program units stored in the memory to realize corresponding functions.

The processor includes a kernel, and the kernel fetches the corresponding program unit from the memory. The kernel can be provided with one or more than one kernel, and the problem that the harmonic wave of the digital modulation transmitter in the prior art is serious is solved by adjusting the kernel parameters.

The memory may include volatile memory, random Access Memory (RAM), and/or nonvolatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM), among other forms in computer readable media, the memory including at least one memory chip.

The embodiment of the invention provides a computer program which is used for executing the up-conversion mixing method.

An embodiment of the present invention provides a computer-readable storage medium having stored thereon a program which, when executed by a processor, implements the above-described up-conversion mixing method.

Specifically, the computer program and the computer readable storage medium are all software with a hardware implementation platform.

The embodiment of the invention provides a processor, which is used for running a program, wherein the up-conversion mixing method is executed when the program runs.

The embodiment of the invention provides equipment, which comprises a processor, a memory and a program stored in the memory and capable of running on the processor, wherein the processor realizes at least the following steps when executing the program:

The device herein may be a server, PC, PAD, cell phone, etc.

The present application also provides a computer program product adapted to perform a program initialized with at least the following method steps when executed on a data processing device:

According to another exemplary embodiment of the present application, there is also provided an FPGA for running a program, where the program runs on any one of the methods described above.

The FPGA is configured to perform any of the methods described above using 2 ⁿ Each phase in (n is more than or equal to 2) phase local oscillation IQ digital signals carries out up-conversion and mixing treatment on the in-phase baseband digital signals and the quadrature baseband digital signals respectively to obtain 2 ⁿ And carrying out up-conversion mixing treatment on the in-phase baseband digital signals and the quadrature baseband digital signals by adopting local oscillation IQ digital signals with 4 phases, 8 phases and 16 equal phases to obtain corresponding numbers of up-conversion mixing signals. Compared with the prior art, the digital modulation transmitter has the serious problem of harmonic wave, and the application adopts the equal 2 of 4 phases and 8 phases ⁿ The local oscillation IQ digital signals with different phase positions are subjected to up-conversion and frequency mixing treatment on the digital baseband signals, so that the problem of near-field noise degradation caused by folding back the local oscillation frequency in the frequency domain after harmonic waves are convolved by the local oscillation signals in the up-conversion frequency mixing process can be well restrained, the problem of serious modulation harmonic waves can be effectively relieved, and the signal effect of the up-conversion frequency mixing signals obtained by the FPGA is guaranteed to be good.

According to yet another exemplary embodiment of the present application, there is also provided a digital transmitter as shown in fig. 3, the digital transmitter including an up-conversion mixing module 100 and a plurality of first filters 200, wherein the up-conversion mixing module 100 is configured to perform any of the above methods; the plurality of first filters 200 are respectively configured to perform filtering processing on one of the upconverted signals output by the upconverting and mixing module 100 to obtain a power amplified signal with an out-of-band signal suppression effect, where the filtering processing includes a shift processing, a power amplifying processing, and a power combining processing.

In the digital transmitter, any one of the methods is executed through the up-conversion mixing module, and up-conversion mixing processing is carried out on the input in-phase baseband digital signal and the quadrature baseband digital signal, so that the harmonic wave in the input signal is effectively restrained; the up-conversion mixed signal is subjected to preset processing such as shifting, power amplification and power combination through a first filter, and a power amplification signal with required power is obtained and sent out. Compared with the prior art, the digital modulation transmitter architecture has the serious problem of harmonic wave of the digital modulation transmitter, and adopts the digital modulation transmitter architecture with 4 phases and 8 equal 2 phases ⁿ The local oscillation IQ digital signals with different phase positions are subjected to up-conversion and frequency mixing treatment on the digital baseband signals, so that the problem of near-field noise degradation caused by folding back the local oscillation frequency in the frequency domain after harmonic waves are convolved by the local oscillation signals in the up-conversion frequency mixing process can be well restrained, the problem of serious harmonic wave modulation can be effectively relieved, and the signal quality sent by a digital modulation transmitter architecture is guaranteed to be good.

In order to further ensure better signal quality sent by the digital modulation transmitter, according to another specific embodiment of the present application, as shown in fig. 3, the first filter 200 is a parallel FIR filter, where the parallel FIR filter includes a plurality of parallel shift registers and a serializer 201, and a plurality of power amplifiers 300, where the parallel shift registers are configured to perform parallel shift processing on the same received up-converted mixed signal to obtain a plurality of parallel shift signals; the serializers are respectively used for converting one received parallel shift signal into a serial digital signal; the power amplifiers 300 are respectively configured to power amplify a received serial digital signal to obtain power amplified signals; and the switch capacitors are used for combining the power amplification signals output by the power amplifiers. The parallel shift register is used for carrying out parallel shift processing on the signals after up-conversion and frequency mixing, so that the functions of suppressing and noise filtering of signals in other frequency bands outside the main frequency band of the radio frequency signals are realized, and meanwhile, the phase consistency of baseband signals is also maintained, and the function of radio frequency digital filtering is further realized; and the parallel shift signal is converted into a serial digital signal which can be directly accepted by the switch type power amplifier through the serializer, so that the parallel-serial conversion of the parallel shift signal is realized, and the power amplification of the serial digital signal is realized through the power amplifier.

Since digital signal processing is a signal expansion method considering the time domain, it is not a conventional frequency signal transmission principle. The principle of the digital transmitter is that the high-speed digital flow control power amplification is used for switching at the radio frequency switching frequency to realize the transmission of the baseband signal envelope. The function of the serializer is therefore to achieve the purpose of driving the final power amplifier with parallel processed digital data.

The frequency signal transmission principle refers to that a baseband signal is in a limited frequency domain range, and generally refers to that Fb is the total bandwidth of the baseband signal within 0 Hz-Fb/2. The process of moving the signal from the baseband frequency band to the carrier frequency band is realized through carrier frequency mixing.

In the practical application process, the power amplifier is a switched capacitor power amplifier, and the output power weight of the digital transmitter is matched with the switched capacitor module with corresponding size through different power amplifiers to realize weight matching.

In yet another specific embodiment of the present application, the shift frequency of the parallel shift process is the modulation frequency or the carrier frequency of the up-converted mixed signal. The serial shift frequency of the serializer is matched with the shift frequency of the parallel shift, and it is necessary to ensure that the data flow rate value is the same.

According to still another specific embodiment of the present application, as shown in fig. 4, the parallel FIR filter further includes at least one input selecting module 101, where the input selecting module 101 is configured to select an input timing corresponding to the parallel shift register 102, so that a plurality of parallel shift registers included in a same parallel FIR filter have M input timings; wherein M is greater than or equal to 1 and less than or equal to N, N is the number of the parallel shift registers included in the parallel FIR filter, the number of the parallel shift register corresponding to the j-th input time sequence is greater than the number of the parallel shift register corresponding to the (j-1) -th input time sequence, the output of the parallel shift register with the largest number corresponding to the (j-1) -th input time sequence is the input of the parallel shift register with the smallest number corresponding to the j-th input time sequence, and j is greater than or equal to 1 and less than or equal to M, and N parallel shift registers are numbered according to the sequence of the input time sequences corresponding to M=N. The input selection module is a module capable of enhancing the configurable function of the parallel FIR filter, and the output of the power amplifier completely belongs to fixed output power because the subsequent serializer does not have the configurable function, so that the frequency response attribute of the parallel FIR filter can be configured by using the input selection module. In addition, the serial number of the parallel shift register corresponding to the j-th input time sequence is larger than the serial number of the parallel shift register corresponding to the (j-1) -th input time sequence, so that the consistency and the singleness of data in each parallel shift register can be ensured.

The parallel FIR filter has various configurable and adjustable capabilities, and can realize different weight configurations and delay configurations, so that the transmitting mechanism frame has adjustable characteristics and can be expanded or reduced.

Each of the parallel shift registers described above can be regarded as a data channel, and typically each data channel can select as input the data in the data channel whose input data is from the last data channel or other data channel whose sequence number is more preceding, and the number of selections is not limited, and typically 2 or 3 is used as the data channel. When this function is used, the mth data channel can receive the data used by the mth-1 (or M-2, M-3) data channel at the same point in time and output through the subsequent corresponding serializer.

Table 1 illustrates an input scheme obtained by selecting an input timing by the input selection module, as shown in Table 1, there are 16 data channels in total, wherein the parallel shift register with the data channel number 1 has no input selection module and the input selection scheme, and the data channel numbers 2-15 respectively correspond to one input selection module.

Specifically, for the input selection scheme 1, the input of the data channel 2 is the output of the data channel 1, the input of the data channel 3 is the output of the data channel 2, … …, and the input of the data channel 16 is the output of the data channel 15, so that there are 16 input timings, each corresponding to 1 power amplifier.

For the input selection scheme 2, the input of the

data channels

2 and 3 is the output of the data channel 1, the input of the

data channels

4 and 5 is the output of the data channel 3, … …, the input of the data channels 14 and 15 is the output of the data channel 13, and the input of the data channel 16 is the output of the data channel 15, so that 9 input time sequences are provided, wherein the first input time sequence and the last input time sequence respectively correspond to 1 power amplifier, the other 7 input time sequences respectively correspond to 2 power amplifiers, and the weight corresponding to each power amplifier is fixed, and compared with the input selection scheme 1, the number of the power amplifiers corresponding to each of the middle 7 input time sequences is changed, which is equivalent to adjusting the weight corresponding to each power amplifier of the middle 7 input time sequences.

For example, for the input timing 3, in the input selection scheme 1, there is a weight a of the power amplifier corresponding to the data channel 3, in the input selection scheme 2, there is a weight b of the power amplifier corresponding to the data channel 4 and a weight c of the power amplifier corresponding to the data channel 5, which corresponds to a weight (b+c) of the power amplifier, that is, which corresponds to adjustment of the weights of the power amplifiers corresponding to the input timing 3 from a to (b+c) is achieved.

For input selection scheme 3, the inputs of

data channels

2 and 3 are the output of data channel 1, the inputs of data channels 4-6 are the output of data channel 3, … …, the inputs of data channels 14 and 15 are the output of data channel 13, and the input of data channel 16 is the output of data channel 15, for a total of 7 input timings, wherein the first input timing and the last input timing respectively correspond to 1 power amplifier, the other 5 input timings respectively correspond to 2, 3, 4, 3, 2 power amplifiers, and because the weight corresponding to each power amplifier is fixed, the number of power amplifiers corresponding to each of the middle 5 input timings is changed compared with that of input selection scheme 1, which is equivalent to adjusting the weight of the power amplifier corresponding to each of the middle 5 input timings.

For example, for the input timing 3, in the input selection scheme 1, there is a weight a of the power amplifier corresponding to the data channel 3, in the input selection scheme 3, there is a weight b of the power amplifier corresponding to the data channel 4, a weight c of the power amplifier corresponding to the data channel 5, and a weight d of the power amplifier corresponding to the data channel 6, which correspond to the weight (b+c+d) of the power amplifier, that is, which correspond to the adjustment of the weights from a to (b+c+d) of the power amplifier corresponding to the input timing 3.

In the present application, different weight configurations and delay configurations may be implemented based on the input selection of the input selection module, and further, the setting of the input selection module may be customized according to the actual application, for example, in table 1, the data channel 1 does not correspondingly set the input selection module, and the data channels 2-16 respectively correspondingly set the input selection module; for another example, data lanes 1-15 may each correspond to a setup input selection module, while data lane 16 does not correspond to a setup input selection module; for another example, the input selection modules may be set to correspond to even numbered data channels, respectively, and the input selection modules may not be set to correspond to odd numbered data channels.

TABLE 1

Of course, in a specific embodiment, the parallel FIR filter may not include the input selection module, and each of the parallel shift registers may be regarded as a data channel, and each data channel selects the source of its input data as the data in its last data channel.

The power amplifier behind the serializer is actually a D-class power amplifier directly driving the switch capacitor, and the power amplifier connected with each data channel is set to have different driving capacities, so that the weight adjusting function of different digital shift FIR filters is realized. This function is similar to the structure of the finite impulse response FIR filter used in the baseband signal, shifted to the radio frequency domain by means of 4-phase quadrature modulation.

In order to further implement the signal transmitting function of the digital transmitter, in another specific embodiment, as shown in fig. 3, the digital transmitter further includes a second filter 400 and a transmitting antenna 900, where the second filter 400 is used to filter the power amplified signal output by the first filter 200; the transmitting antenna 900 is configured to receive and transmit the filtered power amplified signal output from the second filter 400. The second filter with the transformer as a core realizes power output under low voltage by converting the external standard impedance into the impedance seen by the internal power amplifier.

In a specific embodiment, the second filter is a band-pass filter, and the second filter realizes a 50Ω output function of an external standard through impedance matching conversion. Of course, the second filter is not limited to the band-pass filter, and may be any other suitable filter.

According to yet another specific embodiment of the present application, as shown in fig. 3, the digital transmitter further includes an in-phase modulator, a quadrature modulator, and a decoder 600, where the in-phase modulator and the quadrature modulator form a modulator 500 as shown in fig. 3, where the in-phase modulator includes a plurality of in-phase modulation modules sequentially connected in series, where the in-phase modulation module is configured to receive an in-phase input signal and/or a signal error, and generate an in-phase modulation signal according to the in-phase input signal and/or the signal error and output the in-phase modulation signal, where the signal error is an error value acquired by the in-phase modulation module and sent to a next in-phase modulation module, and the error value is an error between the in-phase input signal and the in-phase modulation signal generated by the in-phase modulation module; the quadrature modulator comprises a plurality of quadrature modulation modules which are sequentially connected in series, wherein the quadrature modulation modules are used for receiving quadrature input signals and/or signal errors, generating quadrature modulation signals according to the quadrature input signals and/or the error values and outputting the quadrature modulation signals, wherein the signal errors are error values obtained by the quadrature modulation modules and sent to the next quadrature modulation module, and the error values are errors between the quadrature input signals and the quadrature modulation signals generated by the quadrature modulation modules; the decoder 600 is connected to the in-phase modulator, the quadrature modulator, and the up-conversion mixing module 100, and the decoder 600 is configured to receive a plurality of in-phase modulated signals and a plurality of quadrature modulated signals, decode the plurality of in-phase modulated signals according to a decoder truth table, generate an in-phase baseband digital signal, output the in-phase baseband digital signal to the up-conversion mixing module 100, decode the plurality of quadrature modulated signals according to the decoder truth table, generate a quadrature baseband digital signal, and output the quadrature baseband digital signal to the up-conversion mixing module 100. Through the in-phase modulator and the quadrature modulator, a laminated modulation function is realized, in-phase input signals and quadrature input signals can be decomposed into a plurality of sections of bit number numerical sections with different weights, so that subsequent demodulation is facilitated, a reusable segmentation algorithm can realize unified delay and hardware architecture, binary values obtained through the laminated modulation function are directly converted into corresponding multi-bit parallel data through a mapping table through a decoder, and up-conversion mixing processing is respectively carried out.

Specifically, when the in-phase modulation module is an in-phase modulation module of a serial header, the in-phase modulation module is configured to receive an in-phase input signal, generate an in-phase modulation signal according to the in-phase input signal, and output the in-phase modulation signal, and the in-phase modulation module is further configured to determine an error between the in-phase input signal and the in-phase modulation signal generated by itself, obtain the signal error, and send the signal error to the next in-phase modulation module connected in series; when the in-phase modulation module is an in-phase modulation module connected in series with the tail part, the in-phase modulation module is used for receiving the in-phase input signal and the signal error, generating an in-phase modulation signal according to the in-phase input signal and the signal error and outputting the in-phase modulation signal; when the in-phase modulation module is other in-phase modulation modules except for the in-phase modulation module of the serial head and the serial tail, the in-phase modulation module is used for receiving an in-phase input signal and a signal error, generating an in-phase modulation signal according to the in-phase input signal and the signal error and outputting the in-phase modulation signal, and determining an error between the in-phase input signal and the in-phase modulation signal generated by the in-phase modulation module, obtaining a signal error and sending the signal error to the next in-phase modulation module of the serial.

In addition, 2-segment modulation schemes are adopted to modulate in-phase input signals and quadrature input signals in the prior art, and the specific process is as follows: assuming that the total input signal word width is 12 bits (1 bit sign bit +11bit amplitude), 2-segment modulation can decompose the 11bit amplitude into 5+6 form, or 6+5 form or 7+4 form. Taking the 5+6 format as an example, the binary data of 5 bits is decoded into 31 control bits by thermometer codes (to control 31 PAs with weight of 2), while the rest 6 bits keep binary weights, and the power amplifier driving mode with weight of 1,0.5,0.25 … … is controlled, which causes the precision of the power amplifier to be more difficult to control and causes the signal noise to be larger. Compared with the mode, the in-phase modulator and the quadrature modulator do not need to split the plurality of power amplifiers, so that the accuracy of the power amplifiers can be controlled easily, and the signal noise is low.

Because the modulation schemes of the in-phase modulator and the quadrature modulator are adopted, the demodulation mode of the subsequent decoder does not adopt the mixed modulation scheme of the thermometer code and the binary code, but adopts the width modulation scheme of the decoder directly, so that the same demodulation period can be ensured.

In one embodiment, the 8-bit decoder truth table is shown in FIG. 5 and the 16-bit decoder truth table is shown in FIG. 6. As can be seen from the examples shown in fig. 5 and fig. 6, when the decoder receives a plurality of in-phase modulation signals and a plurality of quadrature modulation signals, if the decoder decodes 8bit data, the input quantized value with an input data range of-4 to +4 is translated to obtain 9bit (1 bit is a sign bit, the remaining 8 bits are PWM width and decode absolute values of the corresponding input values), the width of the PWM is spread to two sides by using a center point, in order to ensure that the data occupies a small amount of memory, the data output by the decoder is 1bit sign bit +4 bit data bit (i.e., the first data set), if the input in-phase modulation signal or quadrature modulation signal is +4, the corresponding decoder data is 01111111, and the in-phase modulation signal or quadrature modulation signal output by the decoder is 01111; when the input in-phase modulation signal or quadrature modulation signal is-2, the decoder data is 100111100, and the in-phase modulation signal or quadrature modulation signal output from the decoder is 10011. If 16 bits are decoded, the range of the input data value is within the range of-8- +8, the obtained decoded data is 17 bits of data, the width data of 1bit sign bit and the expansion of the 16bit central point are contained, and the data output by the decoder is 9 bits, and comprises 1bit sign bit and 8bit data bits.

Of course, in an actual application process, the decoder may directly output the decoded data without compressing the decoded data, for example, when the input in-phase modulation signal or quadrature modulation signal is +4, the corresponding decoder data is 01111111, and the in-phase modulation signal or quadrature modulation signal output by the decoder is 01111111.

Of course, the number of bits of the in-phase modulation signal and the quadrature modulation signal is not limited to the 8bit and the 16bit, and may be other number of bits, which is specifically determined by the application scenario of the signal, for example, the number of bits is generally 8bit when the signal is applied to a mobile phone, and the number of bits is generally 16bit or more when the signal is applied to a base station.

In order to further ensure a better noise suppression effect, in an actual application process, as shown in fig. 3, the digital transmitter further includes a DSP module 700 and a processing module 800, where the DSP module 700 is configured to receive a digital baseband signal and process the digital baseband signal; an input of the processing module 800 is connected to the DSP module 700, an output of the processing module is connected to the in-phase modulator and the quadrature modulator, and the processing module is configured to decompose the processed digital baseband signal into an initial in-phase signal and an initial quadrature signal, and perform predetermined processing on the initial in-phase signal and the initial quadrature signal, respectively, to obtain the corresponding in-phase input signal and quadrature input signal, where the predetermined processing includes at least one of signal synchronization, frequency up-conversion, over-sampling, and baseband filtering. Through the DSP module and the processing module, the input digital baseband signals are subjected to digital processing, signal decomposition, signal synchronization, frequency up-conversion, over-sampling, baseband filtering and other processing, and the signal quality of the signals reaching the in-phase modulator and the quadrature modulator is further ensured to be better.

As shown in fig. 3, the digital transmitter of the present application is a wireless digital transmitter, and further includes a transmitting antenna 900, which is connected to the second filter 400, and is configured to receive and transmit the power synthesized and filtered signal sent by the second filter 400.

According to another specific embodiment of the present application, the DSP module receives the digital baseband signal through a digital baseband signal interface, where the digital baseband signal interface is the same digital interface as that of the analog transmitter, and after the digital baseband signal interface is decomposed by signals corresponding to the analog to digital, multiple times of signal synchronization and over-sampling are used to achieve a higher sampling rate, so as to obtain a certain level of noise suppression gain. In order to match the carrier frequency change, a follow-up change or a fixed interpolation frequency 2 method may be adopted. The following sampling frequency change means that the sampling frequency of the interface portion and the carrier frequency are in a frequency multiplication relationship, that is, the carrier frequency fc=n× Fbb, where Fbb is the data receiving frequency of the interface portion and N is a fixed integer multiple. The fixed interpolation frequency is Fbb, which is a fixed frequency point and does not change with the change of the center frequency position Fc of the transmitted signal.

The digital transmitter is not divided according to the stages of DA, filtering, frequency conversion, frequency mixing and the like, and the functional modules are replaced by the all-digital modules, so that the area of the digital transmitter can be greatly saved compared with the analog scheme. In addition, each digital module in the digital transmitter can be switched to the process node very rapidly, and can be iterated in other processes rapidly. In addition, since the final load of the digital logic output drive is a switch-mode power amplifier, the efficiency of the power amplifier is higher than that of other linear PAs. Due to the adoption of a uniquely developed 4-phase digital filtering scheme, the filter has the inhibition effect on modulation harmonic waves and high-frequency carrier harmonic waves, and can meet the requirements on reducing off-chip filter devices or filtering performance while realizing output signals meeting radio frequency output frequency specifications by matching with a unique passband power synthesis filter structure.

In addition, all modules from the leftmost pure digital baseband signal (not including a DSP module) to the rightmost impedance matching filter network output taking a transformer coil as a core of the digital transmitter can be realized by adopting a pure digital logic unit, so that a general-purpose platform (such as an FPGA (field programmable gate array), a programmable device, a computing core module with a high-speed interface such as ARM/RISC (reduced instruction set computer) and the like) can be used as a hardware realization carrier, and the framework scheme of the realization can be realized in a compilable manner by using an algorithm in a hardware description language manner. Thus, implementation may be accomplished in a conventional manner such as CMOS circuit design, or in a manner using a hardware description language.

In the foregoing embodiments of the present invention, the descriptions of the embodiments are emphasized, and for a portion of this disclosure that is not described in detail in this embodiment, reference is made to the related descriptions of other embodiments.

In the several embodiments provided in the present application, it should be understood that the disclosed technology content may be implemented in other manners. The above-described embodiments of the apparatus are merely exemplary, and the division of the units may be a logic function division, and there may be another division manner when actually implemented, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some interfaces, units or modules, or may be in electrical or other forms.

The units described above as separate components may or may not be physically separate, and components shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated units described above, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in essence or a part contributing to the prior art or all or part of the technical solution in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the above-mentioned method of the various embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing program codes.

From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

1) In the up-conversion mixing method described in the present application, 2 is adopted ⁿ Each phase in (n is more than or equal to 2) phase local oscillation IQ digital signals carries out up-conversion and mixing treatment on the in-phase baseband digital signals and the quadrature baseband digital signals respectively to obtain 2 ⁿ Phase up-conversion of mixed signals, i.e. local oscillation IQ digital signals with 4, 8 and 16 equal phases are adopted for the in-phase baseband digital signals and the quadrature baseband digital signalsAnd performing up-conversion mixing processing to obtain up-conversion mixed signals with corresponding numbers. Compared with the prior art, the digital modulation transmitter has the serious problem of harmonic wave, and the application adopts the equal 2 of 4 phases and 8 phases ⁿ The local oscillation IQ digital signals with different phase phases are subjected to up-conversion and mixing treatment on the digital baseband signals, so that the problem of near-field noise degradation caused by folding back the local oscillation frequency in the frequency domain after the harmonic waves are convolved by the local oscillation signals in the up-conversion and mixing process can be well restrained, and the problem of serious modulation harmonic waves can be effectively relieved.

2) In the up-conversion mixer described above, the processing means uses 2 ⁿ Each phase in (n is more than or equal to 2) phase local oscillation IQ digital signals carries out up-conversion and mixing treatment on the in-phase baseband digital signals and the quadrature baseband digital signals respectively to obtain 2 ⁿ And carrying out up-conversion mixing treatment on the in-phase baseband digital signals and the quadrature baseband digital signals by adopting local oscillation IQ digital signals with 4 phases, 8 phases and 16 equal phases to obtain corresponding numbers of up-conversion mixing signals. Compared with the prior art, the digital modulation transmitter has the serious problem of harmonic wave, and the application adopts the equal 2 of 4 phases and 8 phases ⁿ The local oscillation IQ digital signals with different phase phases are subjected to up-conversion and mixing treatment on the digital baseband signals, so that the problem of near-field noise degradation caused by folding back the local oscillation frequency in the frequency domain after the harmonic waves are convolved by the local oscillation signals in the up-conversion and mixing process can be well restrained, and the problem of serious modulation harmonic waves can be effectively relieved.

3) The FPGA is used for executing any one of the methods, and the method adopts 2 ⁿ Each phase in (n is more than or equal to 2) phase local oscillation IQ digital signals carries out up-conversion and mixing treatment on the in-phase baseband digital signals and the quadrature baseband digital signals respectively to obtain 2 ⁿ And carrying out up-conversion mixing treatment on the in-phase baseband digital signals and the quadrature baseband digital signals by adopting local oscillation IQ digital signals with 4 phases, 8 phases and 16 equal phases to obtain corresponding numbers of up-conversion mixing signals. Compared with the prior art, the digital modulation transmitter has serious harmonic wave problem, adopts 4 phases, 8 are equal to 2 ⁿ The local oscillation IQ digital signals with different phase positions are subjected to up-conversion and frequency mixing treatment on the digital baseband signals, so that the problem of near-field noise degradation caused by folding back the local oscillation frequency in the frequency domain after harmonic waves are convolved by the local oscillation signals in the up-conversion frequency mixing process can be well restrained, the problem of serious modulation harmonic waves can be effectively relieved, and the signal effect of the up-conversion frequency mixing signals obtained by the FPGA is guaranteed to be good.

4) In the digital transmitter, any one of the methods is executed through the up-conversion mixing module, and up-conversion mixing processing is carried out on the input in-phase baseband digital signal and the quadrature baseband digital signal, so that the harmonic wave in the input signal is effectively restrained; the up-conversion mixed signal is subjected to preset processing such as filtering, shifting and power amplification through a first filter, and a power amplification signal with required power is obtained and sent out. Compared with the prior art, the digital modulation transmitter architecture has the serious problem of harmonic wave of the digital modulation transmitter, and adopts the digital modulation transmitter architecture with 4 phases and 8 equal 2 phases ⁿ The local oscillation IQ digital signals with different phase positions are subjected to up-conversion and frequency mixing treatment on the digital baseband signals, so that the problem of near-field noise degradation caused by folding back the local oscillation frequency in the frequency domain after harmonic waves are convolved by the local oscillation signals in the up-conversion frequency mixing process can be well restrained, the problem of serious harmonic wave modulation can be effectively relieved, and the signal quality sent by a digital modulation transmitter architecture is guaranteed to be good.

The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. An up-conversion mixing method, comprising:

by 2 ⁿ Each phase in the phase local oscillation IQ digital signal respectively carries out up-conversion and mixing processing on the in-phase baseband digital signal and the quadrature baseband digital signal which are received simultaneously to obtain 2 ⁿ Phase up-conversion frequency mixing, wherein n is an integer, n is more than or equal to 2, the phases of the local oscillation IQ digital signals of any two phases are different,

each phase of the local oscillator IQ digital signal comprises a local oscillator I+ template signal, a local oscillator I-template signal, a local oscillator Q+ template signal and a local oscillator Q-template signal, and 2 is adopted ⁿ Each phase in the phase local oscillation IQ digital signal respectively carries out up-conversion and mixing processing on the in-phase baseband digital signal and the quadrature baseband digital signal which are received simultaneously to obtain 2 ⁿ Phase up-converting the mixed signal, comprising:

performing bit AND operation on the local oscillator I+ template signal and the in-phase baseband digital signal to obtain a first radio frequency signal;

Performing bit AND operation on the local oscillator I-template signal and the in-phase baseband digital signal to obtain a second radio frequency signal;

performing bit AND operation by adopting the local oscillator Q+ template signal and the quadrature baseband digital signal to obtain a third radio frequency signal;

performing bit AND operation by adopting the local oscillator Q-template signal and the quadrature baseband digital signal to obtain a fourth radio frequency signal;

mixing the first radio frequency signal, the second radio frequency signal, the third radio frequency signal and the fourth radio frequency signal to obtain a positive up-conversion mixed signal and a negative up-conversion mixed signal,

carrying out frequency mixing processing on the first radio frequency signal, the second radio frequency signal, the third radio frequency signal and the fourth radio frequency signal to obtain a positive up-conversion frequency-mixed signal and a negative up-conversion frequency-mixed signal, wherein the frequency mixing processing comprises the following steps:

when the in-phase baseband digital signal has positive attribute and the quadrature baseband digital signal has positive attribute, performing bit OR operation on the first radio frequency signal and the third radio frequency signal to obtain the positive up-conversion mixed signal, and performing bit OR operation on the second radio frequency signal and the fourth radio frequency signal to obtain the negative up-conversion mixed signal;

When the in-phase baseband digital signal has positive attribute and the quadrature baseband digital signal has negative attribute, performing bit OR operation on the first radio frequency signal and the fourth radio frequency signal to obtain the positive up-conversion mixed signal, and performing bit OR operation on the second radio frequency signal and the third radio frequency signal to obtain the negative up-conversion mixed signal;

when the in-phase baseband digital signal has negative attribute and the quadrature baseband digital signal has positive attribute, performing bit OR operation on the second radio frequency signal and the third radio frequency signal to obtain the positive up-conversion mixed signal, and performing bit OR operation on the first radio frequency signal and the fourth radio frequency signal to obtain the negative up-conversion mixed signal;

and when the in-phase baseband digital signal has negative attribute and the quadrature baseband digital signal has negative attribute, performing bit OR operation on the second radio frequency signal and the fourth radio frequency signal to obtain the positive up-conversion mixed signal, and performing bit OR operation on the first radio frequency signal and the third radio frequency signal to obtain the negative up-conversion mixed signal.

2. A computer readable storage medium, characterized in that the computer readable storage medium comprises a stored program, wherein the program when executed by a processor implements the method of claim 1.

3. An FPGA for running a program, wherein the program runs on execution of the method of claim 1.

4. A digital transmitter, comprising:

an up-conversion mixing module for performing the method of claim 1;

and the plurality of first filters are respectively used for carrying out filtering processing on one up-conversion mixed signal output by the up-conversion mixing module so as to obtain a power amplification signal with an out-of-band signal suppression effect, wherein the filtering processing comprises shift processing, power amplification processing and power combination processing.

5. The digital transmitter of claim 4 wherein the first filter is a parallel FIR filter, the parallel FIR filter comprising:

the plurality of parallel shift registers are used for carrying out parallel shift processing on the received same up-conversion mixed signal to obtain a plurality of parallel shift signals;

a plurality of serializers for converting one of the received parallel shift signals into a serial digital signal, respectively;

The power amplifiers are respectively used for carrying out power amplification on a received serial digital signal so as to obtain power amplified signals;

and the switch capacitors are used for combining the power amplification signals output by the power amplifiers.

6. The digital transmitter of claim 5, wherein the shift frequency of the parallel shift process is a modulation frequency or a carrier frequency of the upconverted mixed signal;

and/or the number of the groups of groups,

the parallel FIR filter further comprises at least one input selection module, wherein the input selection module is used for selecting input time sequences corresponding to the parallel shift registers so that a plurality of parallel shift registers included in the same parallel FIR filter have M input time sequences;

and the output of the parallel shift register with the largest number corresponding to the (j-1) th input time sequence is the input of the parallel shift register with the smallest number corresponding to the j-th input time sequence, and the number of the parallel shift registers with the numbers corresponding to the M=N is greater than the number of the parallel shift registers corresponding to the (j-1) th input time sequence, wherein the number of the parallel shift registers corresponding to the j-th input time sequence is greater than the number of the parallel shift registers corresponding to the (j-1) th input time sequence, and the number of the parallel shift registers with the numbers corresponding to the M=N is greater than or equal to 1.

7. The digital transmitter of claim 4, wherein the digital transmitter further comprises:

the second filter is used for filtering the power amplification signal output by the first filter;

the transmitting antenna is used for receiving the filtered power amplification signal output by the second filter and sending the power amplification signal;

and/or the number of the groups of groups,

the digital transmitter further includes:

the in-phase modulator comprises a plurality of in-phase modulation modules which are sequentially connected in series, wherein the in-phase modulation modules are used for receiving in-phase input signals and/or first signal errors, generating in-phase modulation signals according to the in-phase input signals and/or the first signal errors and outputting the in-phase modulation signals, the first signal errors are first error values which are acquired by the in-phase modulation modules and sent to the next in-phase modulation module, and the first error values are errors between the in-phase input signals and the in-phase modulation signals generated by the in-phase modulation modules;

the quadrature modulator comprises a plurality of quadrature modulation modules which are sequentially connected in series, wherein the quadrature modulation modules are used for receiving quadrature input signals and/or second signal errors, generating quadrature modulation signals according to the quadrature input signals and/or the second signal errors and outputting the quadrature modulation signals, the second signal errors are second error values which are acquired by the quadrature modulation modules and sent to the next quadrature modulation module, and the second error values are errors between the quadrature input signals and the quadrature modulation signals generated by the quadrature modulation modules;

The decoder is respectively connected with the in-phase modulator, the quadrature modulator and the up-conversion mixing module, and is used for receiving a plurality of in-phase modulation signals and a plurality of quadrature modulation signals, decoding the in-phase modulation signals according to a decoder truth table, generating in-phase baseband digital signals and outputting the in-phase baseband digital signals to the up-conversion mixing module, decoding the quadrature modulation signals according to the decoder truth table, generating quadrature baseband digital signals and outputting the quadrature baseband digital signals to the up-conversion mixing module.