CN115801025A

CN115801025A - Up-conversion mixing method and digital transmitter architecture

Info

Publication number: CN115801025A
Application number: CN202210781076.7A
Authority: CN
Inventors: 戎亮
Original assignee: Shanghai Xingsi Semiconductor Co ltd
Current assignee: Shanghai Xingsi Semiconductor Co ltd
Priority date: 2022-07-04
Filing date: 2022-07-04
Publication date: 2023-03-14
Anticipated expiration: 2042-07-04
Also published as: CN115801025B; WO2024007454A1

Abstract

The application provides an up-conversion mixing method and a digital transmitter architecture, wherein the method comprises the following steps: by means of 2 ⁿ Each phase in the phase local oscillator IQ digital signal respectively carries out up-conversion frequency mixing processing on an in-phase baseband digital signal and a quadrature baseband digital signal which are received simultaneously to obtain 2 ⁿ And phase up-conversion frequency mixing signals, wherein n is an integer and is more than or equal to 2, and the phases of any two-phase local oscillator IQ digital signals are different. The method and the device can effectively relieve the problem of serious modulation harmonic waves.

Description

Up-conversion mixing method and digital transmitter architecture

Technical Field

The present application relates to the field of digital transmitters, and in particular, to an up-conversion mixing method, a computer program, a computer readable storage medium, an FPGA, and a digital transmitter architecture.

Background

The digital transmitter is realized by taking a digital algorithm as a basis, taking a full digital logic operation unit (Standard Cell) as a transmitter implementation mode of a main internal module (or a basic unit) of the transmitter, and matching with a proper output power matching module to realize a circuit framework form of the same working principle (radio frequency signal transmission) as an analog transmitter.

Compared with an analog transmitter framework, the digital transmitter framework has a simpler function capable of replacing a module to realize a corresponding functional module of the analog transmitter in an implementation mode. And by taking advantage of the high density nature of digital modules, a more compact transmitter architecture (area advantage) and more efficient power transmission (switched power amplifier nature transmitter) are achieved.

Currently, research on digital transmitters has been conducted in the industry for many years, wherein Power output modules are divided into two broad categories, i.e., a voltage Power Amplifier (SCPA) format and a Current Power Amplifier (CEPA) format. The existing digital transmitter architecture schemes include:

1) A digital transmitter circuit structured in a phase difference manner of LINC (Linear Amplification with Nonlinear Components, linearity with Nonlinear Components) and an M-LINC type digital transmitter circuit of an improved form thereof;

2) An IQ (In-Phase Quadrature) ringing (shared) SCPA digital circuit is directly adopted, the modulation frequency bandwidth is large, but generally radio frequency modulation cannot be used In a high-frequency band, so that modulation harmonics which are difficult to eliminate are generated, and the IQ ringing scheme also needs to dynamically switch the switching Phase of radio frequency, so that the control frequency of the SCPA digital circuit is difficult to control;

3) The SCPA circuit using the digital POLAR modulation scheme has a difficulty in increasing the signal processing bandwidth, because the bandwidth of the Phase component is usually 3 times that of the baseband signal to cover the Phase change signal with a characteristic meaning, and thus the design and control difficulty of the PLL (Phase Locked Loop) is high. At present, INTEL adopts a high frequency multiplication asymmetric mode POLAR framework, and can solve some existing harmonic problems. But belongs to the category of radio frequency modulation (i.e. non-radio frequency modulation frequency) due to the too high sampling frequency.

The digital transmitter circuit adopting the LINC method or the digital transmitter circuit adopting the MLINC (Multiple LINC, multilayer LINC) framework has an excessively large area, the requirement of the vector signal Combination of radio frequency for the phase noise amplitude is far higher than that of the digital IQ Combination scheme used in the current patent, the baseband computing capability requirement is very high, the digital computing power consumption is high, and the vector decomposition is required. In the digital transmission mechanism frame adopting the IQ Sharing mode, each SCPA drive needs to perform initial switch phase adjustment according to the combined value of IQ, so that the actual working frequency of dynamic combination (the modulation frequency cannot reach the frequency point above 3GH up-conversion mixing) is reduced, and the modulation harmonic wave appears at the modulation frequency position (usually Fc/N, N is a positive integer) as a result of the frequency reduction operation. Phase extraction in a digital POLAR architecture requires control of the phase of the PLL, which can create significant bandwidth requirements in the process of combining the rf phase signal with the amplitude envelope signal. Therefore, the working frequency of the baseband signal cannot reach the radio frequency, so that higher modulation harmonics exist at two sides of the modulation frequency interval from the center frequency point of the carrier, and meanwhile, the CORDIC (Coordinate Rotation Digital Computer) decomposition from the general baseband IQ signal needs to use square root calculation and trigonometric function calculation, so that the actual baseband calculation power consumption is also high.

Disclosure of Invention

The present application mainly aims to provide an up-conversion frequency mixing method, a computer program, a computer readable storage medium, an FPGA, and a digital transmitter architecture, so as to solve the problem of serious harmonic of a digital modulation transmitter in the prior art.

According to an aspect of the embodiments of the present invention, there is provided an up-conversion mixing method, including: by means of 2 ⁿ Each phase in the phase local oscillator IQ digital signals respectively carries out up-conversion frequency mixing processing on in-phase baseband digital signals and quadrature baseband digital signals which are received simultaneously to obtain 2 ⁿ And performing phase up-conversion and frequency mixing on the signals, wherein n is an integer and is more than or equal to 2, and the phases of the local oscillator IQ digital signals of any two phases are different.

Optionally, each phase of local oscillator IQ digital signal comprises a local oscillator I + template signal, a local oscillator I-template signal, a local oscillator Q + template signal and a local oscillator Q-template signal, and 2 is adopted ⁿ Each phase in the phase local oscillator IQ digital signal respectively carries out up-conversion frequency mixing processing on an in-phase baseband digital signal and a quadrature baseband digital signal which are received simultaneously to obtain 2 ⁿ A phase up-converted mixed signal comprising: performing bit AND operation by using the local oscillator I + template signal and the in-phase baseband digital signal to obtain a first radio frequency signal; performing bit AND operation by using the local oscillator I-template signal and the in-phase baseband digital signal to obtain a second radio frequency signal; using the local oscillator Q + template signal andperforming bit AND operation on the orthogonal baseband digital signal to obtain a third radio frequency signal; performing bit AND operation by using the local oscillator Q-template signal and the orthogonal baseband digital signal to obtain a fourth radio frequency signal; and performing frequency mixing processing on the first radio-frequency signal, the second radio-frequency signal, the third radio-frequency signal and the fourth radio-frequency signal to obtain a positive up-conversion frequency-mixed signal and a negative up-conversion frequency-mixed signal.

Optionally, the frequency mixing processing is performed on the first radio frequency signal, the second radio frequency signal, the third radio frequency signal, and the fourth radio frequency signal to obtain a positive up-conversion frequency-mixed signal and a negative up-conversion frequency-mixed signal, and the method includes: when the in-phase baseband digital signal has a positive attribute and the quadrature baseband digital signal has a positive attribute, performing bit-or operation on the first radio frequency signal and the third radio frequency signal to obtain the positive up-conversion mixed signal, and performing bit-or operation on the second radio frequency signal and the fourth radio frequency signal to obtain the negative up-conversion mixed signal; when the in-phase baseband digital signal has a positive attribute and the quadrature baseband digital signal has a negative attribute, performing bit-or operation on the first radio-frequency signal and the fourth radio-frequency signal to obtain the positive up-conversion mixed signal, and performing bit-or operation on the second radio-frequency signal and the third radio-frequency signal to obtain the negative up-conversion mixed signal; when the in-phase baseband digital signal has a negative attribute and the quadrature baseband digital signal has a positive attribute, performing a bit or operation on the second radio frequency signal and the third radio frequency signal to obtain the positive up-conversion mixed signal, and performing a bit or operation on the first radio frequency signal and the fourth radio frequency signal to obtain the negative up-conversion mixed signal; and when the in-phase baseband digital signal has a negative attribute and the quadrature baseband digital signal has a negative attribute, performing bit-or operation on the second radio-frequency signal and the fourth radio-frequency signal to obtain the positive up-conversion mixed signal, and performing bit-or operation on the first radio-frequency signal and the third radio-frequency signal to obtain the negative up-conversion mixed signal.

According to another aspect of embodiments of the present invention, there is provided a computer program for performing any one of the methods.

According to another aspect of embodiments of the present invention, there is provided a computer-readable storage medium including a stored program, wherein the program performs any one of the methods.

According to still another aspect of the embodiments of the present invention, there is provided an FPGA (Field Programmable Gate Array) configured to run a program, where the program is configured to execute any one of the methods when running.

There is also provided, in accordance with yet another aspect of embodiments of the present invention, a digital transmitter architecture, including an up-conversion mixing module and a plurality of first filters, wherein the up-conversion mixing module is configured to perform any one of the methods; the plurality of first filters are respectively used for filtering one up-conversion frequency-mixed signal output by the up-conversion frequency-mixing module to obtain a power amplification signal with an out-of-band signal suppression effect, wherein the filtering process comprises a shifting process, a power amplification process and a power combination process.

Optionally, the first filter is a parallel FIR (Finite Impulse Response) filter, and the parallel FIR filter includes a plurality of parallel shift registers, a plurality of serializers, and a plurality of power amplifiers, where the parallel shift registers are configured to perform parallel shift processing on the same received up-converted and mixed signal to obtain a plurality of parallel shift signals; the plurality of serializers are respectively used for converting the received parallel shift signal into a serial digital signal; the power amplifiers are respectively used for carrying out power amplification on the received serial digital signal to obtain a power amplification signal; and the plurality of switched capacitors are used for combining the power amplification signals output by the plurality of power amplifiers.

Optionally, the shift frequency of the parallel shift processing is a modulation frequency or a carrier frequency of the up-converted and mixed signal; and/or the parallel FIR filter further comprises at least one input selection module, wherein the input selection module is used for selecting the input timing sequence corresponding to the parallel shift register, so that a plurality of parallel shift registers included in the same parallel FIR filter have M input timing sequences; m is more than or equal to 1 and less than or equal to N, N is the number of the parallel shift registers included by the parallel FIR filter, the number of the parallel shift register corresponding to the jth input time sequence is greater than that of the parallel shift register corresponding to the (j-1) th input time sequence, the output of the parallel shift register with the largest number corresponding to the (j-1) th input time sequence is the input of the parallel shift register with the smallest number corresponding to the jth input time sequence, j is more than or equal to 1 and less than or equal to M, and the N parallel shift registers are numbered according to the sequence of the corresponding input time sequences when M = N.

Optionally, the digital transmitter architecture further includes a second filter and a transmitting antenna, wherein the second filter is configured to filter the power amplified signal output by the first filter; the transmitting antenna is used for receiving the filtered power amplification signal output by the second filter and transmitting the filtered power amplification signal; and/or the digital transmitter architecture further comprises an in-phase modulator, a quadrature modulator and a decoder, wherein the in-phase modulator comprises a plurality of in-phase modulation modules which are sequentially connected in series, the in-phase modulation module is used for receiving an in-phase input signal and/or a signal error, generating an in-phase modulation signal according to the in-phase input signal and/or the signal error, and outputting the in-phase modulation signal, wherein the signal error is an error value which is acquired by the in-phase modulation module and sent to a next in-phase modulation module, and the error value is an error between the in-phase input signal and the in-phase modulation signal generated by the in-phase modulation module; the quadrature modulator comprises a plurality of quadrature modulation modules which are sequentially connected in series, wherein the quadrature modulation modules are used for receiving quadrature input signals and/or signal errors, generating quadrature modulation signals according to the quadrature input signals and/or the error values and outputting the quadrature modulation signals, the signal errors are error values which are acquired by the quadrature modulation modules and sent to the next quadrature modulation module, and the error values are errors between the quadrature input signals and the quadrature modulation signals generated by the quadrature modulation modules; the decoder is connected with the in-phase modulator, the quadrature modulator and the up-conversion mixing module respectively, and is configured to receive the plurality of in-phase modulation signals and the plurality of quadrature modulation signals, decode the plurality of in-phase modulation signals according to a decoder truth table, generate an in-phase baseband digital signal and output the in-phase baseband digital signal to the up-conversion mixing module, and decode the plurality of quadrature modulation signals according to the decoder truth table, generate an orthogonal baseband digital signal and output the orthogonal baseband digital signal to the up-conversion mixing module.

By adopting the technical scheme of the application, the up-conversion frequency mixing method adopts 2 ⁿ (n is more than or equal to 2) each phase in the phase local oscillator IQ digital signal respectively carries out up-conversion frequency mixing processing on the in-phase baseband digital signal and the quadrature baseband digital signal to obtain 2 ⁿ And performing up-conversion frequency mixing on the in-phase baseband digital signals and the quadrature baseband digital signals by using local oscillator IQ digital signals with 4-phase, 8-phase and 16-phase equalities and different phases to obtain up-conversion frequency-mixed signals with corresponding numbers. Compared with the problem of serious harmonic wave of the digital modulation transmitter in the prior art, 4-phase, 8-phase and 2-phase digital modulation transmitters are adopted in the method ⁿ The local oscillator IQ digital signals with different phase phases carry out up-conversion and frequency mixing processing on the digital baseband signals, so that the problem of near-field noise deterioration caused by folding back the local oscillation frequency in a frequency domain after the harmonic waves are convoluted by the local oscillator signals in the up-conversion frequency mixing process can be well inhibited, and the problem of serious modulation harmonic waves can be effectively alleviated.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this application, are included to provide a further understanding of the application, and the description of the exemplary embodiments and illustrations of the application are intended to explain the application and are not intended to limit the application. In the drawings:

fig. 1 shows a flow diagram of an up-conversion mixing method according to an embodiment of the application;

fig. 2 shows a schematic diagram of a truth table of 4 sets of local oscillator IQ digital signals according to an embodiment of the present application;

fig. 3 shows a schematic structural diagram of a digital transmitter architecture according to an embodiment of the present application;

FIG. 4 shows a schematic structural diagram of a parallel FIR filter according to an embodiment of the present application;

fig. 5 and 6 respectively show schematic diagrams of decoder truth tables of different bit numbers according to an embodiment of the application.

Wherein the figures include the following reference numerals:

100. an up-conversion frequency mixing module; 200. a first filter; 201. a parallel shift register and a serializer; 300. a power amplifier; 400. a second filter; 500. a modulator; 600. a decoder; 700. a DSP module; 800. a processing module; 900. a transmitting antenna; 101. an input selection module; 102. a parallel shift register.

Detailed Description

It should be noted that, in the present application, the embodiments and features of the embodiments may be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

In order to make the technical solutions of the present application better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances in order to facilitate the description of the embodiments of the application herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.

As mentioned in the background, the harmonics of the prior art digital modulation transmitters are severe, and in order to solve the above problems, in an exemplary embodiment of the present application, an up-conversion mixing method, a computer program, a computer readable storage medium, an FPGA and a digital transmitter architecture are provided.

According to an embodiment of the application, an up-conversion mixing method is provided.

Fig. 1 is a flowchart of an up-conversion mixing method according to an embodiment of the present application. As shown in fig. 1, the method comprises the steps of:

step S101, adopt 2 ⁿ Each phase in the phase local oscillator IQ digital signal respectively carries out up-conversion frequency mixing processing on an in-phase baseband digital signal and a quadrature baseband digital signal which are received simultaneously to obtain 2 ⁿ And performing phase up-conversion and frequency mixing on the signals, wherein n is an integer and is more than or equal to 2, and the phases of the local oscillator IQ digital signals of any two phases are different.

In the above up-conversion mixing method, 2 is adopted ⁿ (n is more than or equal to 2) each phase in the phase local oscillator IQ digital signal respectively carries out up-conversion frequency mixing processing on the in-phase baseband digital signal and the orthogonal baseband digital signal to obtain 2 ⁿ The signals after the phase up-conversion and frequency mixing adopt local oscillator IQ digital signals with 4-phase, 8-phase and 16-phase equality and different phases to the in-phase baseband digital signalsAnd carrying out up-conversion frequency mixing processing on the signals and the orthogonal baseband digital signals to obtain up-conversion frequency-mixed signals with corresponding numbers. Compared with the problem of serious harmonic wave of the digital modulation transmitter in the prior art, 4-phase, 8-phase and 2-phase digital modulation transmitters are adopted in the method ⁿ The local oscillator IQ digital signals with different phase phases carry out up-conversion and frequency mixing processing on the digital baseband signals, so that the problem of near-field noise deterioration caused by folding back the local oscillation frequency in a frequency domain after the harmonic waves are convoluted by the local oscillator signals in the up-conversion frequency mixing process can be well inhibited, and the problem of serious modulation harmonic waves can be effectively alleviated.

According to a specific embodiment of the present application, each of the local oscillator IQ digital signals includes a local oscillator I + template signal, a local oscillator I-template signal, a local oscillator Q + template signal, and a local oscillator Q-template signal, and 2 is adopted ⁿ Each phase in the phase local oscillator IQ digital signal respectively carries out up-conversion frequency mixing processing on an in-phase baseband digital signal and a quadrature baseband digital signal which are received simultaneously to obtain 2 ⁿ A phase up-converted mixed signal comprising: performing bit AND operation by using the local oscillator I + template signal and the in-phase baseband digital signal to obtain a first radio frequency signal; performing bit AND operation on the local oscillator I-template signal and the in-phase baseband digital signal to obtain a second radio frequency signal; performing bit AND operation by using the local oscillator Q + template signal and the orthogonal baseband digital signal to obtain a third radio frequency signal; performing bit AND operation by using the local oscillator Q-template signal and the orthogonal baseband digital signal to obtain a fourth radio frequency signal; and performing frequency mixing processing on the first radio frequency signal, the second radio frequency signal, the third radio frequency signal and the fourth radio frequency signal to obtain a positive up-conversion frequency-mixed signal and a negative up-conversion frequency-mixed signal. In this embodiment, taking local IQ digital signals with different phases of 4 phases as an example, since the local IQ digital signals are in a differential form and there is no modulation harmonic at Fc (main carrier signal frequency) and 3Fc (third carrier signal frequency), there is no mixing between 3Fc and 4Fc for 4-order carrier harmonics existing in 4Fc (fourth carrier signal frequency), and noise aliasing at the final carrier position is reduced, thereby further reducing noise aliasingThe effect of suppressing the modulated harmonics in the signal is achieved.

In order to further suppress the modulation harmonic of the up-converted mixed signal, in another specific embodiment of the present application, the mixing processing is performed on the first rf signal, the second rf signal, the third rf signal, and the fourth rf signal to obtain a positive up-converted mixed signal and a negative up-converted mixed signal, and the method includes: performing a bit-or operation on the first rf signal and the third rf signal to obtain the positive up-converted and mixed signal, and performing a bit-or operation on the second rf signal and the fourth rf signal to obtain the negative up-converted and mixed signal, when the in-phase baseband digital signal has a positive attribute and the quadrature baseband digital signal has a positive attribute; performing a bit-or operation on the first rf signal and the fourth rf signal to obtain the positive up-converted and mixed signal, and performing a bit-or operation on the second rf signal and the third rf signal to obtain the negative up-converted and mixed signal, when the in-phase baseband digital signal has a positive attribute and the quadrature baseband digital signal has a negative attribute; performing a bit-or operation on the second rf signal and the third rf signal to obtain the positive up-converted and mixed signal, and performing a bit-or operation on the first rf signal and the fourth rf signal to obtain the negative up-converted and mixed signal, when the in-phase baseband digital signal has a negative attribute and the quadrature baseband digital signal has a positive attribute; when the in-phase baseband digital signal has a negative attribute and the quadrature baseband digital signal has a negative attribute, performing a bit-or operation on the second rf signal and the fourth rf signal to obtain the positive up-converted and mixed signal, and performing a bit-or operation on the first rf signal and the third rf signal to obtain the negative up-converted and mixed signal.

According to another specific embodiment of the present application, the in-phase baseband digital signal and the quadrature baseband digital signal respectively include a sign bit and a first data group located at one side of the sign bit, and 2 is adopted ⁿ Phase local oscillator IQ digital signalBefore each phase in the signal respectively performs up-conversion mixing processing on an in-phase baseband digital signal and a quadrature baseband digital signal which are received simultaneously, the method further comprises the following steps: demodulating each first data set respectively to determine a corresponding second data set, wherein the second data set is in mirror symmetry with the corresponding first data set; and placing the second data group on one side of the first data group far away from the sign bit to obtain a demodulated in-phase signal and a demodulated quadrature signal. The in-phase baseband digital signal and the quadrature baseband digital signal with mirror symmetry rules are demodulated to obtain a complete in-phase signal and a complete quadrature signal, so that the data occupation of the in-phase baseband digital signal and the quadrature baseband digital signal is less, and the transmission of the in-phase baseband digital signal and the quadrature baseband digital signal is more convenient.

In a specific embodiment, n =2, that is, the method of the present application uses 4-phase data to process a digital baseband signal including an in-phase baseband digital signal and a quadrature baseband digital signal, so that compared with using 2-phase data, the present application adds 2-phase local oscillator IQ digital signals to suppress a problem that a harmonic at a 2Fc (carrier signal frequency of a second phase) position is folded back to Fc in a frequency domain after being convolved by a local oscillator (substantially equal to the carrier signal frequency Fc) signal, thereby causing near-field noise degradation and alleviating a problem of serious modulation harmonic. The truth table of the 4-phase local oscillator IQ digital signal is shown in fig. 2. P1-P4 represent phase 1-phase 4 four-phase IQ local oscillator signal template data respectively. The 4 local oscillation digital signals with different configurations used in this embodiment are subjected to bit and operation with the PWM decoded signal to obtain a digitized I/Q dual-channel rf mixing signal, and then the digital IQ mixing module may directly perform bit or' combining on the 4-phase I/Q rf signal that has been up-converted.

The specific up-conversion mixing execution process is as follows:

when the PWM-decoded in-phase baseband digital signal and the quadrature baseband digital signal are 9 bits (1 bit sign bit +8bit digital bits), for example, when the input of the PWM decoding is-3/2, the decoder truth table shown in fig. 5 can be obtained, where the PWM-decoded in-phase baseband digital signal is 1.0111.1110 and the quadrature baseband digital signal is 0.0011.1100, where the first bits of the in-phase baseband digital signal and the quadrature baseband digital signal both represent sign bits, 0 represents positive and 1 represents negative. The in-phase baseband digital signal and the quadrature baseband digital signal need to be subjected to I/Q frequency mixing with a 4-phase IQ local oscillator digital signal template to respectively obtain pulse digital stream data represented by each phase.

The in-phase baseband digital signal and the local oscillator I + template signal of the first phase are mixed to obtain a first radio frequency signal Iap, the quadrature baseband digital signal and the local oscillator Q + template signal of the first phase are mixed to obtain a third radio frequency signal Qap, the in-phase baseband digital signal and the local oscillator I-template signal of the first phase are mixed to obtain a second radio frequency signal Ian, and the quadrature baseband digital signal and the local oscillator Q-template signal of the first phase are mixed to obtain a fourth radio frequency signal Qan, wherein the values of the fourth radio frequency signal Qan are respectively as follows:

the first radio frequency signal Iap = (1000.1000 and 0111.1110) =0000.1000;

the second radio frequency signal Ian = (0010.0010 &0111.1110) =0010.0010;

the third radio frequency signal Qap = (0100.0100 &0011.1100) =0000.0100;

the fourth radio frequency signal Qan = (0001.0001 and 0011.1100) =0001.0000;

then, a mixing operation is performed, i.e. the resulting 4 sets of signals are bit or combined, wherein, since the in-phase baseband digital signal has a negative property and the quadrature baseband digital signal has a positive property, there is:

the Ian and the Qap are combined to obtain a forward up-conversion frequency-mixing signal IQap =0010.0110 after up-conversion frequency mixing;

and the Iap and the Qan are combined to obtain a negative up-conversion mixing signal IQan =0001.1000 after up-conversion mixing.

Equivalent to 3 pulse widths output by the positive PA and 2 pulse width data output by the negative PA.

Similarly, the in-phase baseband digital signal and the second phase are mixed to obtain a first radio frequency signal Ibp and a second radio frequency signal Ibn, and the quadrature baseband digital signal and the second phase are mixed to obtain a third radio frequency signal Qbp and a fourth radio frequency signal Qbn, which have the following values:

the first radio frequency signal Ibp = (0001.0001 &0111.1110) =0001.0000;

the second radio frequency signal Ibn = (0100.0100 &0111.1110) =0100.0100;

the third radio frequency signal Qbp = (1000.1000 and 0011.1100) =0000.1000;

the fourth radio frequency signal Qbn = (0010.0010 &0011.1100) =0010.0000;

then, since the in-phase baseband digital signal has a negative property and the quadrature baseband digital signal has a positive property, a mixing operation is performed, resulting in an up-conversion mixed forward digital signal IQbp =0100.1100, and in an up-conversion mixed forward digital signal IQbn =0011.0000.

Similarly, the in-phase baseband digital signal is mixed with the third phase to obtain the first rf signal Icp and the second rf signal Icn, and the quadrature baseband digital signal is mixed with the third phase to obtain the third rf signal Qcp and the fourth rf signal Qcn, respectively:

the first radio frequency signal Icp = (0010.0010 &0111.1110) =0010.0010;

a second radio frequency signal Icn = (1000.1000 &0111.1110) =0000.1000;

the third radio frequency signal Qcp = (0001.0001 and 0011.1100) =0001.0000;

the fourth radio frequency signal Qcn = (0100.0100 &0011.1100) =0000.0100.

Then, since the in-phase baseband digital signal has a negative attribute and the quadrature baseband digital signal has a positive attribute, a mixing operation is performed to obtain an up-conversion mixed forward digital signal and an up-conversion mixed forward digital signal, which are IQcp =0001.1000, iqcn =0010.0110, respectively.

Similarly, the in-phase baseband digital signal and the fourth phase are mixed to obtain a first rf signal Idp and a second rf signal Idn, and the quadrature baseband digital signal and the fourth phase are mixed to obtain a third rf signal Qdp and a fourth rf signal Qdn, respectively:

the first radio frequency signal Idp = (0100.0100 &0111.1110) =0100.0100;

the second radio frequency signal Idn = (0001.0001 and 0111.1110) =0001.0000;

the third radio frequency signal Qdp = (0010.0010 &0011.1100) =0010.0000;

a fourth radio frequency signal Qdn = (1000.1000 and 0011.1100) =0000.1000;

then, since the in-phase baseband digital signal has a negative property and the quadrature baseband digital signal has a positive property, a mixing operation is performed to obtain an up-conversion mixed forward digital signal and an up-conversion mixed forward digital signal, which are IQdp =0011.0000 and IQdn =0100.1100, respectively.

It should be noted that the steps illustrated in the flowcharts of the figures may be performed in a computer system such as a set of computer-executable instructions and that, although a logical order is illustrated in the flowcharts, in some cases, the steps illustrated or described may be performed in an order different than presented herein.

The embodiments of the present application further provide an up-conversion frequency mixing device, and it should be noted that the up-conversion frequency mixing device according to the embodiments of the present application may be used to execute the method for up-conversion frequency mixing provided in the embodiments of the present application. The following describes an up-conversion mixing apparatus provided in an embodiment of the present application.

The up-conversion mixing device of the embodiment of the application comprises a processing unit, wherein the processing unit is used for adopting 2 ⁿ Each phase in the phase local oscillator IQ digital signal respectively carries out up-conversion frequency mixing processing on an in-phase baseband digital signal and a quadrature baseband digital signal which are received simultaneously to obtain 2 ⁿ And performing phase up-conversion and frequency mixing on the signals, wherein n is an integer and is more than or equal to 2, and the phases of the local oscillator IQ digital signals of any two phases are different.

In the up-conversion mixing device, the processing unit adopts 2 ⁿ (n is more than or equal to 2) each phase in the phase local oscillator IQ digital signal respectively carries out up-conversion frequency mixing processing on the in-phase baseband digital signal and the quadrature baseband digital signal to obtain 2 ⁿ The signals after the frequency mixing are up-converted in phase, i.e. 4-phase, 8-phase and 16-phase local oscillator IQ digital signals with different phases are adoptedAnd carrying out up-conversion frequency mixing processing on the in-phase baseband digital signals and the quadrature baseband digital signals to obtain up-conversion frequency-mixed signals with corresponding numbers. Compared with the serious harmonic problem of the digital modulation transmitter in the prior art, 4-phase, 8-phase and 2-phase digital modulation transmitters are adopted in the method ⁿ The local oscillator IQ digital signals with different phase positions carry out up-conversion and frequency mixing processing on the digital baseband signals, so that the problem of near field noise deterioration caused by folding back the local oscillator frequency in the frequency domain after the harmonic waves are convoluted by the local oscillator signals in the up-conversion frequency mixing process can be well solved, and the problem of serious modulation harmonic waves can be effectively relieved.

According to a specific embodiment of the present application, each phase of the local oscillator IQ digital signal includes a local oscillator I + template signal, a local oscillator I-template signal, a local oscillator Q + template signal, and a local oscillator Q-template signal, and the processing unit includes a first operation module, a second operation module, a third operation module, a fourth operation module, and a processing module, where the first operation module is configured to perform a bit and operation on the local oscillator I + template signal and the in-phase baseband digital signal to obtain a first radio frequency signal; the second operation module is used for performing bit AND operation by adopting the local oscillator I-template signal and the in-phase baseband digital signal to obtain a second radio frequency signal; the third operation module is used for performing bit AND operation on the local oscillator Q + template signal and the orthogonal baseband digital signal to obtain a third radio frequency signal; the fourth operation module is configured to perform a bit and operation on the local oscillator Q-template signal and the quadrature baseband digital signal to obtain a fourth radio frequency signal; the processing module performs frequency mixing processing on the first radio frequency signal, the second radio frequency signal, the third radio frequency signal and the fourth radio frequency signal by using English to obtain a positive up-conversion frequency-mixed signal and a negative up-conversion frequency-mixed signal. In this embodiment, taking local IQ digital signals with different 4-phase phases as an example, because the local IQ digital signals are in a differential form and there is no modulation harmonic at positions Fc (main carrier signal frequency) and 3Fc (third carrier signal frequency), there is no mixing of 3Fc and 4Fc for the 4 th order carrier harmonic existing at 4Fc (fourth carrier signal frequency), and thus noise aliasing at the final carrier position is reduced, and the effect of suppressing the modulation harmonic in the signals is further achieved.

In order to further suppress the modulation harmonic of the up-converted mixed signal, in another specific embodiment of the present application, the processing module includes a first operation sub-module, a second operation sub-module, a third operation sub-module, and a fourth operation sub-module, where the first operation sub-module is configured to perform a bit or operation on the first radio frequency signal and the third radio frequency signal to obtain the positive up-converted mixed signal, and perform a bit or operation on the second radio frequency signal and the fourth radio frequency signal to obtain the negative up-converted mixed signal, when the in-phase baseband digital signal has a positive attribute and the quadrature baseband digital signal has a positive attribute; the second operation sub-module is configured to perform a bit or operation on the first rf signal and the fourth rf signal to obtain the positive up-conversion mixed signal, and perform a bit or operation on the second rf signal and the third rf signal to obtain the negative up-conversion mixed signal, when the in-phase baseband digital signal has a positive attribute and the quadrature baseband digital signal has a negative attribute; the third operation sub-module is configured to perform a bit or operation on the second rf signal and the third rf signal to obtain the positive up-conversion mixed signal, and perform a bit or operation on the first rf signal and the fourth rf signal to obtain the negative up-conversion mixed signal, when the in-phase baseband digital signal has a negative attribute and the quadrature baseband digital signal has a positive attribute; the fourth operation sub-module is configured to perform a bit or operation on the second rf signal and the fourth rf signal to obtain the positive up-conversion mixed signal, and perform a bit or operation on the first rf signal and the third rf signal to obtain the negative up-conversion mixed signal, when the in-phase baseband digital signal has a negative attribute and the quadrature baseband digital signal has a negative attribute.

According to another specific embodiment of the present application, the in-phase baseband digital signal and the quadrature baseband digital signalThe word signal comprises a sign bit and a first data group positioned at one side of the sign bit, and the device also comprises a demodulation module and a placement module, wherein the demodulation module is used for adopting 2 ⁿ Before each phase in the phase local oscillator IQ digital signals respectively carry out up-conversion frequency mixing processing on in-phase baseband digital signals and orthogonal baseband digital signals which are received simultaneously, demodulating each first data group respectively to determine a corresponding second data group, wherein the second data group is in mirror symmetry with the corresponding first data group; the placing module is used for placing the second data group on one side of the first data group far away from the sign bit to obtain a demodulated in-phase signal and a demodulated quadrature signal. The in-phase baseband digital signal and the quadrature baseband digital signal with mirror symmetry rules are demodulated to obtain a complete in-phase signal and a complete quadrature signal, so that the data occupation of the in-phase baseband digital signal and the quadrature baseband digital signal is less, and the transmission of the in-phase baseband digital signal and the quadrature baseband digital signal is more convenient.

In a specific embodiment, n =2, that is, the apparatus of the present application uses 4-phase data to process a digital baseband signal including an in-phase baseband digital signal and the quadrature baseband digital signal, so that compared with using 2-phase data, the added 2-phase local oscillator IQ digital signal of the present application can suppress a problem that a harmonic at a 2Fc (carrier signal frequency of the second phase) position is folded back to Fc in a frequency domain after being convolved by a local oscillator (substantially equal to the carrier signal frequency Fc) signal, thereby causing deterioration of near field noise and alleviating a problem of serious modulation harmonics. The truth table of the 4-phase local oscillator IQ digital signals is shown in fig. 2. P1-P4 represent phase 1-phase 4 four-phase IQ local oscillator signal template data respectively. The 4 local oscillation digital signals with different configurations used in this embodiment are subjected to bit and operation with the PWM decoded signal to obtain a digitized I/Q dual-channel rf mixing signal, and then the digital IQ mixing module may directly perform bit or' combining on the up-converted 4-phase I/Q rf signal.

The specific up-conversion mixing execution process is as follows:

when the PWM-decoded in-phase baseband digital signal and quadrature baseband digital signal are 9 bits (1 bit sign bit +8bit digital bits), for example, when the input of the PWM decoding is-3/2, the decoder truth table shown in fig. 5 can be used to obtain that the PWM-decoded in-phase baseband digital signal is 1.0111.1110 and the quadrature baseband digital signal is 0.0011.1100, where the first bits of the in-phase baseband digital signal and the quadrature baseband digital signal both represent sign bits, 0 represents positive and 1 represents negative. The in-phase baseband digital signal and the quadrature baseband digital signal need to be subjected to I/Q frequency mixing with a 4-phase IQ local oscillator digital signal template to respectively obtain pulse digital stream data represented by each phase.

the first radio frequency signal Iap = (1000.1000 and 0111.1110) =0000.1000;

the second radio frequency signal Ian = (0010.0010 &0111.1110) =0010.0010;

the third radio frequency signal Qap = (0100.0100 &0011.1100) =0000.0100;

the fourth radio frequency signal Qan = (0001.0001 &0011.1100) =0001.0000;

then, a mixing operation is performed, i.e., the resulting 4 sets of signals are bit or combined, wherein, since the in-phase baseband digital signal has a negative property and the quadrature baseband digital signal has a positive property, there are:

Similarly, the in-phase baseband digital signal and the second phase are mixed to obtain a first rf signal Ibp and a second rf signal Ibn, respectively, and the quadrature baseband digital signal and the second phase are mixed to obtain a third rf signal Qbp and a fourth rf signal Qbn, respectively:

the first radio frequency signal Ibp = (0001.0001 &0111.1110) =0001.0000;

the second radio frequency signal Ibn = (0100.0100 &0111.1110) =0100.0100;

the third radio frequency signal Qbp = (1000.1000 &0011.1100) =0000.1000;

the fourth radio frequency signal Qbn = (0010.0010 &0011.1100) =0010.0000;

Similarly, the in-phase baseband digital signal and the third phase are mixed to obtain the first rf signal Icp and the second rf signal Icn, and the quadrature baseband digital signal and the third phase are mixed to obtain the third rf signal Qcp and the fourth rf signal Qcn, respectively:

the first radio frequency signal Icp = (0010.0010 &0111.1110) =0010.0010;

a second radio frequency signal Icn = (1000.1000 and 0111.1110) =0000.1000;

the third radio frequency signal Qcp = (0001.0001 &0011.1100) =0001.0000;

the fourth radio frequency signal Qcn = (0100.0100 &0011.1100) =0000.0100.

Then, since the in-phase baseband digital signal has a negative attribute and the quadrature baseband digital signal has a positive attribute, a mixing operation is performed to obtain an up-converted mixed forward digital signal and an up-converted mixed forward digital signal, which are IQcp =0001.1000, iqcn =0010.0110, respectively.

the first radio frequency signal Idp = (0100.0100 &0111.1110) =0100.0100;

the second radio frequency signal Idn = (0001.0001 and 0111.1110) =0001.0000;

the third radio frequency signal Qdp = (0010.0010 &0011.1100) =0010.0000;

the fourth radio frequency signal Qdn = (1000.1000 &00111100) =0000.1000;

The up-conversion mixing device comprises a processor and a memory, wherein the processing unit and the like are stored in the memory as program units, and the processor executes the program units stored in the memory to realize corresponding functions.

The processor comprises a kernel, and the kernel calls the corresponding program unit from the memory. One or more than one kernel can be set, and the problem of serious harmonic waves of the digital modulation transmitter in the prior art is solved by adjusting the kernel parameters.

The memory may include volatile memory in a computer readable medium, random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM), including at least one memory chip.

An embodiment of the present invention provides a computer program, where the computer program is configured to execute the above up-conversion mixing method.

An embodiment of the present invention provides a computer-readable storage medium, on which a program is stored, and the program, when executed by a processor, implements the above up-conversion mixing method.

Specifically, the computer program and the computer-readable storage medium are both software with a hardware implementation platform.

The embodiment of the invention provides a processor, which is used for running a program, wherein the up-conversion mixing method is executed when the program runs.

The embodiment of the invention provides equipment, which comprises a processor, a memory and a program which is stored on the memory and can run on the processor, wherein when the processor executes the program, at least the following steps are realized:

The device herein may be a server, a PC, a PAD, a mobile phone, etc.

The present application further provides a computer program product adapted to perform a program initialized with at least the following method steps when executed on a data processing device:

step S101, adopt 2 ⁿ Each phase in the phase local oscillator IQ digital signals respectively carries out up-conversion frequency mixing processing on in-phase baseband digital signals and quadrature baseband digital signals which are received simultaneously to obtain 2 ⁿ And phase up-conversion frequency mixing signals, wherein n is an integer and is more than or equal to 2, and the phases of the local oscillator IQ digital signals of any two phases are different.

According to another exemplary embodiment of the present application, there is also provided an FPGA configured to run a program, where the program when running performs any one of the above methods.

Said FPGA being adapted to perform any of the above methods, said method employing 2 ⁿ (n is more than or equal to 2) each phase in the phase local oscillator IQ digital signal respectively carries out up-conversion frequency mixing processing on the in-phase baseband digital signal and the quadrature baseband digital signal to obtain 2 ⁿ The signals after the phase up-conversion and frequency mixing are the same as the number of the in-phase baseband by adopting local oscillator IQ digital signals with 4-phase, 8-phase and 16-phase equality and different phasesAnd performing up-conversion frequency mixing processing on the word signals and the quadrature baseband digital signals to obtain up-conversion frequency-mixed signals with corresponding number. Compared with the problem of serious harmonic wave of the digital modulation transmitter in the prior art, 4-phase, 8-phase and 2-phase digital modulation transmitters are adopted in the method ⁿ The local oscillator IQ digital signals with different phase positions carry out up-conversion and frequency mixing processing on the digital baseband signals, so that the problem of near field noise deterioration caused by folding the local oscillator frequency back in the frequency domain after harmonic waves are convoluted by the local oscillator signals in the up-conversion frequency mixing process can be well inhibited, the problem of serious modulation harmonic waves can be effectively relieved, and the signal effect of the signals obtained by the FPGA after up-conversion frequency mixing is better.

According to yet another exemplary embodiment of the present application, there is also provided a digital transmitter architecture as shown in fig. 3, the digital transmitter architecture comprising an up-conversion mixing module 100 and a plurality of first filters 200, wherein the up-conversion mixing module 100 is configured to perform any one of the above methods; the plurality of first filters 200 are respectively configured to perform filtering processing on one up-conversion mixed signal output by the up-conversion mixing module 100 to obtain a power amplified signal with out-of-band signal suppression effect, where the filtering processing includes shifting processing, power amplifying processing, and power combining processing.

In the digital transmitter architecture, any one of the methods is executed by the up-conversion mixing module, and the up-conversion mixing processing is performed on the input in-phase baseband digital signal and quadrature baseband digital signal, so as to effectively suppress harmonic waves in the input signal; the signals after the up-conversion and frequency mixing are subjected to predetermined processing such as shifting, power amplification, power combination and the like through a first filter, and power amplification signals with required power are obtained and sent out. Compared with the problem of serious harmonic wave of the digital modulation transmitter in the prior art, the digital modulation transmitter architecture of the application adopts 4-phase, 8-phase and 2-phase ⁿ The local oscillator IQ digital signals with different phase phases carry out up-conversion and frequency mixing processing on the digital baseband signals, so that the problem of near-field noise deterioration caused by folding the local oscillator frequency back in the frequency domain after the harmonic waves are convoluted by the local oscillator signals in the up-conversion frequency mixing process can be well solved, and the problem of modulation and frequency mixing can be effectively relievedThe problem of serious harmonic suppression ensures that the quality of signals sent by a digital modulation transmitter framework is better.

In order to further ensure that the quality of the signal transmitted by the digital modulation transmitter is good, according to another specific embodiment of the present application, as shown in fig. 3, the first filter 200 is a parallel FIR filter, and the parallel FIR filter includes a plurality of parallel shift registers, a serializer 201, and a plurality of power amplifiers 300, where the parallel shift registers are configured to perform parallel shift processing on the received same up-converted and mixed signal to obtain a plurality of parallel shift signals; the plurality of serializers are respectively used for converting the received one parallel shift signal into a serial digital signal; the plurality of power amplifiers 300 are respectively configured to perform power amplification on a received serial digital signal to obtain a power amplified signal; and the plurality of switched capacitors are used for combining the power amplification signals output by the plurality of power amplifiers. The parallel shift register is used for carrying out parallel shift processing on the signals after the up-conversion frequency mixing, so that the functions of inhibiting signals of other frequency bands outside a main frequency band of the radio-frequency signals and filtering noise are realized, and the phase consistency of baseband signals is kept, thereby further realizing the function of radio-frequency digital filtering; and the parallel shift signal is converted into a serial digital signal which can be directly received by the switch type power amplifier through the serializer, so that the parallel-serial conversion of the parallel shifted signal is realized, and the power amplification of the serial digital signal is realized through the power amplifier.

Since the digital signal processing is a signal spreading method considering a time domain, it is not a conventional frequency signal transmission principle. The digital transmitter architecture is based on the principle that the envelope of baseband signals is transmitted by controlling power amplification through a high-speed digital code stream and switching the frequency of a radio frequency switch. The function of the serializer described above is therefore to implement the digital data processed in parallel for the purpose of driving the final power amplifier.

By frequency signal transmission principle is meant that the baseband signal is within a limited frequency domain, typically within 0Hz to Fb/2, fb being the total bandwidth of the baseband signal. The process of moving the signal from the baseband frequency band to the carrier frequency band is realized through carrier frequency mixing.

In an actual application process, the power amplifier is a switched capacitor power amplifier, and the output power weight of the digital transmitter architecture is matched with the switched capacitor modules with corresponding sizes through different power amplifiers to realize weight matching.

In another specific embodiment of the present application, the shift frequency of the parallel shift processing is a modulation frequency or a carrier frequency of the up-converted and mixed signal. In addition, the serial shift frequency of the serializer is matched with the shift frequency of the parallel shift, and the data flow value needs to be ensured to be the same.

According to another specific embodiment of the present application, as shown in fig. 4, the parallel FIR filter further includes at least one input selecting block 101, where the input selecting block 101 is configured to select an input timing corresponding to the parallel shift register 102, so that a plurality of the parallel shift registers included in the same parallel FIR filter have M input timings; and N is the number of the parallel shift registers included by the parallel FIR filter, the number of the parallel shift register corresponding to the jth input time sequence is greater than that of the parallel shift register corresponding to the (j-1) th input time sequence, the output of the parallel shift register corresponding to the (j-1) th input time sequence and having the largest number is the input of the parallel shift register corresponding to the jth input time sequence and having the smallest number, j is greater than or equal to 1 and less than or equal to M, and the N parallel shift registers are numbered according to the sequence of the corresponding input time sequences when M = N. The input selection module is a module capable of enhancing the configurable function of the parallel FIR filter, and because the subsequent serializer does not have the configurable function and the output of the power amplifier completely belongs to the fixed output power, the frequency response property of the parallel FIR filter can be configured by using the input selection module. In addition, the number of the parallel shift register corresponding to the jth input timing sequence is greater than that of the parallel shift register corresponding to the (j-1) th input timing sequence, so that the consistency and the unicity of data in each parallel shift register can be guaranteed.

The order of the parallel FIR filter has various configurable and adjustable capabilities, and different weight configurations and delay configurations can be realized, so that the transmitter architecture has adjustable characteristics and can be expanded or reduced.

Each parallel shift register can be regarded as a data channel, generally, each data channel can select data in the data channel with the source of input data being the last data channel or other data channels with more front serial numbers as input, the number of the selection is not limited, and generally 2 or 3 is a reasonable selection for the data channel. When using this function, the Mth data channel can receive the data used by the M-1 (or M-2, M-3) data channel at the same time point and output the data through the corresponding subsequent serializer.

Table 1 exemplifies an input scheme obtained by selecting an input timing sequence by the input selection module, and as shown in table 1, there are 16 data channels in total, where the parallel shift register with data channel number 1 has no input selection module and an input selection scheme, and data channel numbers 2 to 15 correspond to one input selection module respectively.

Specifically, for input selection scheme 1, the input to data channel 2 is the output of data channel 1, the input to data channel 3 is the output of data channel 2, \8230; \ 8230;, the input to data channel 16 is the output of data channel 15, so that there are 16 input timings, each corresponding to 1 power amplifier.

For the input selection scheme 2, the inputs of the

data channels

2 and 3 are the output of the data channel 1, the inputs of the

data channels

4 and 5 are the output of the data channel 3, \8230 \ 8230;, the inputs of the data channels 14 and 15 are the output of the data channel 13, and the input of the data channel 16 is the output of the data channel 15, so that there are 9 input timings, wherein the first input timing and the last input timing respectively correspond to 1 power amplifier, and the other 7 input timings respectively correspond to 2 power amplifiers, and since the weight corresponding to each power amplifier is fixed, the number of power amplifiers corresponding to each of the middle 7 input timings is changed in the input selection scheme 2 compared with the input selection scheme 1, which is equivalent to the adjustment of the weight of the power amplifier corresponding to each of the middle 7 input timings.

For example, for the input timing sequence 3, in the input selection scheme 1, there is a weight a of the power amplifier corresponding to the data channel 3, and in the input selection scheme 2, there are a weight b of the power amplifier corresponding to the data channel 4 and a weight c of the power amplifier corresponding to the data channel 5, which correspond to the weight (b + c) of the corresponding power amplifier, that is, which corresponds to the adjustment of the weight of the power amplifier corresponding to the input timing sequence 3 from a to (b + c).

For the input option scheme 3, the inputs of the

data channels

2 and 3 are the output of the data channel 1, the inputs of the data channels 4 to 6 are the output of the data channel 3, \8230;, the inputs of the data channels 14 and 15 are the output of the data channel 13, and the input of the data channel 16 is the output of the data channel 15, so that there are 7 input timings, wherein the first input timing and the last input timing respectively correspond to 1 power amplifier, and the other 5 input timings respectively correspond to 2, 3, 4, 3, and 2 power amplifiers, and since the weight corresponding to each power amplifier is fixed, the number of power amplifiers corresponding to each of the middle 5 input timings is changed in the input option scheme 3 compared with the input option scheme 1, which is equivalent to adjusting the weight of the power amplifier corresponding to each of the middle 5 input timings.

For example, for the input timing sequence 3, in the input selection scheme 1, there is a weight a of the power amplifier corresponding to the data channel 3, and in the input selection scheme 3, there are a weight b of the power amplifier corresponding to the data channel 4, a weight c of the power amplifier corresponding to the data channel 5, and a weight d of the power amplifier corresponding to the data channel 6, which are equivalent to a weight (b + c + d) corresponding to the power amplifier, that is, equivalent to the adjustment of the weight of the power amplifier corresponding to the input timing sequence 3 from a to (b + c + d).

In the present application, different weight configurations and delay configurations can be implemented based on the input selection of the input selection module, and further, the setting of the input selection module can be customized according to the actual application, for example, in table 1, the input selection module is not correspondingly set in data channel 1, and the input selection modules are correspondingly set in data channels 2 to 16, respectively; for another example, data channels 1-15 may each correspond to a setup input selection module, while data channel 16 does not correspond to a setup input selection module; for another example, input selection modules may be respectively disposed corresponding to even data channels, and input selection modules may not be disposed corresponding to odd data channels.

TABLE 1

Of course, in a specific embodiment, the parallel FIR filter may not include the input selection module, each of the parallel shift registers may be regarded as a data channel, and each data channel selects a source of the input data as the data in the previous data channel as the input.

The power amplifier behind the serializer is actually a class-D power amplifier directly driving a switched capacitor, and the power amplifier connected with each data channel is set to have different driving capacities, so that the weight adjusting function of different digital shift FIR filters is realized. The function is similar to the structure of a finite impulse response FIR filter used in baseband signals, and the finite impulse response FIR filter is moved to the radio frequency field by a 4-phase quadrature modulation mode.

In order to further implement the signal transmitting function of the digital transmitter architecture, in another specific embodiment, as shown in fig. 3, the digital transmitter architecture further includes a second filter 400 and a transmitting antenna 900, where the second filter 400 is used for filtering the power amplified signal output by the first filter 200; the transmitting antenna 900 is configured to receive the filtered power amplified signal output by the second filter 400 and transmit the filtered power amplified signal. The second filter with the transformer as the core converts the impedance of the external standard into the impedance correspondingly seen by the internal power amplifier, thereby realizing the power output under the condition of low voltage.

In a specific embodiment, the second filter is a band-pass filter, and the second filter implements a 50 Ω output function of an external standard through impedance matching conversion. Of course, the second filter is not limited to the band pass filter, but may be any other suitable filter.

According to another specific embodiment of the present application, as shown in fig. 3, the digital transmitter architecture further includes an in-phase modulator, a quadrature modulator, and a decoder 600, where the in-phase modulator and the quadrature modulator constitute the modulator 500 shown in fig. 3, where the in-phase modulator includes a plurality of in-phase modulation modules connected in series in sequence, where the in-phase modulation module is configured to receive an in-phase input signal and/or a signal error, and generate an in-phase modulation signal according to the in-phase input signal and/or the signal error, and output the in-phase modulation signal, where the signal error is an error value obtained by the in-phase modulation module and sent to a next in-phase modulation module, and the error value is an error between the in-phase input signal and the in-phase modulation signal generated by the in-phase modulation module; the quadrature modulator comprises a plurality of quadrature modulation modules which are sequentially connected in series, wherein the quadrature modulation modules are used for receiving quadrature input signals and/or signal errors, generating quadrature modulation signals according to the quadrature input signals and/or the error values and outputting the quadrature modulation signals, the signal errors are error values which are acquired by the quadrature modulation modules and sent to the next quadrature modulation module, and the error values are errors between the quadrature input signals and the quadrature modulation signals generated by the quadrature modulation modules; the decoder 600 is connected to the in-phase modulator, the quadrature modulator, and the up-conversion mixing module 100, and the decoder 600 is configured to receive a plurality of the in-phase modulation signals and a plurality of the quadrature modulation signals, decode the plurality of the in-phase modulation signals according to a decoder truth table to generate in-phase baseband digital signals and output the in-phase baseband digital signals to the up-conversion mixing module 100, and decode the plurality of the quadrature modulation signals according to the decoder truth table to generate quadrature baseband digital signals and output the quadrature baseband digital signals to the up-conversion mixing module 100. The in-phase modulator and the quadrature modulator realize the function of laminated modulation, can decompose an in-phase input signal and a quadrature input signal into a plurality of numerical value sections with equal bit quantity but different weights so as to facilitate subsequent demodulation, can realize more uniform delay and hardware framework by a repeatedly used section algorithm, directly converts binary numerical values obtained by the function of laminated modulation into corresponding multi-bit parallel data through a mapping table by a decoder, and respectively carries out up-conversion frequency mixing processing.

Specifically, when the in-phase modulation module is an in-phase modulation module with a head connected in series, the in-phase modulation module is configured to receive an in-phase input signal, generate an in-phase modulation signal according to the in-phase input signal, and output the in-phase modulation signal, and determine an error between the in-phase input signal and the in-phase modulation signal generated by the in-phase modulation module, to obtain the signal error, and send the signal error to the next in-phase modulation module connected in series; when the in-phase modulation module is an in-phase modulation module with a series tail, the in-phase modulation module is used for receiving the in-phase input signal and the signal error, generating an in-phase modulation signal according to the in-phase input signal and the signal error and outputting the in-phase modulation signal; when the in-phase modulation module is an in-phase modulation module other than the in-phase modulation modules of the serial head and the serial tail, the in-phase modulation module is used for receiving an in-phase input signal and a signal error, generating an in-phase modulation signal according to the in-phase input signal and the signal error, outputting the in-phase modulation signal, determining an error between the in-phase input signal and the in-phase modulation signal generated by the in-phase modulation module, obtaining a signal error, and sending the signal error to the next in-phase modulation module connected in series.

In addition, a 2-segment modulation scheme is usually adopted to modulate an in-phase input signal and an orthogonal input signal, and the specific process is as follows: assuming that the word width of the total input signal is 12 bits (1 bit sign bit +11bit amplitude), the 2-segment modulation can decompose 11 bits of the amplitude into a form of 5+6, or a form of 6+5, or a form of 7+ 4. For example, in the form of 5+6, 5 bits of binary data are decoded into 31 control bits (to control 31 PAs with weight of 2) by thermometer code, and the remaining 6 bits retain binary weights, and the binary weights are controlled to be 1,0.5,0.25 \8230 \ 8230;, such power amplifier driving manner will result in more and more difficult control of the accuracy of the power amplifier and more signal noise. Compared with the mode, the in-phase modulator and the quadrature modulator do not need to be split into a plurality of power amplifiers, the accuracy of the power amplifiers can be easily controlled, and the signal noise is small.

Because of the modulation schemes of the in-phase modulator and the quadrature modulator, the demodulation mode of the subsequent decoder does not adopt a thermometer code and binary code mixed modulation scheme, but directly adopts the decoder to carry out a width modulation scheme, so that the same demodulation period can be ensured.

In one embodiment, the decoder truth table for 8 bits is shown in FIG. 5 below and the decoder truth table for 16 bits is shown in FIG. 6 below. As can be seen from the examples shown in fig. 5 and fig. 6, when the decoder receives a plurality of in-phase modulation signals and a plurality of quadrature modulation signals, if 8-bit data is decoded, input quantization values with a data range of-4 to +4 are input, and 9-bit (1 bit is a sign bit, and the remaining 8 bits are absolute values of PWM width corresponding to the input values) data are obtained after translation, where the PWM width is expanded to both sides by expanding a central point, and in order to ensure that the memory occupied by the data is small, the data output by the decoder is 1-bit sign bit + 4-bit data bits (i.e. the first data set), and if the input in-phase modulation signal or quadrature modulation signal is +4, the corresponding decoder data is 01111111, and the in-phase modulation signal or quadrature modulation signal output by the decoder is 01111; when the input in-phase modulation signal or quadrature modulation signal is-2, the decoder data is 100111100, and the in-phase modulation signal or quadrature modulation signal output from the decoder is 10011. If 16 bits are decoded, the range of the input data value is in the range of minus 8 to plus 8, the obtained decoded data is 17 bits of data and comprises 1bit of sign bit and width data expanded by a 16bit central point, and the data output by the decoder is 9 bits and comprises 1bit of sign bit and 8bit of data.

Certainly, in an actual application process, the decoder may also directly output the decoded data without compressing the decoded data, for example, when the input in-phase modulation signal or quadrature modulation signal is +4, the corresponding decoder data is 01111111, and the in-phase modulation signal or quadrature modulation signal output by the decoder is 01111111.

Of course, the number of bits of the in-phase modulation signal and the quadrature modulation signal is not limited to the 8bit and the 16bit, but may be other number of bits, which is determined by the application scenario of the signal, where the number of bits is generally 8 bits when the signal is applied to a mobile phone, and the number of bits is generally 16 bits or more when the signal is applied to a base station.

In order to further ensure a good noise suppression effect, in an actual application process, as shown in fig. 3, the digital transmitter architecture further includes a DSP module 700 and a processing module 800, where the DSP module 700 is configured to receive a digital baseband signal and process the digital baseband signal; the input of the processing module 800 is connected to the DSP module 700, the output of the processing module is connected to the in-phase modulator and the quadrature modulator, respectively, and the processing module is configured to decompose the processed digital baseband signal into an initial in-phase signal and an initial quadrature signal, and perform predetermined processing on the initial in-phase signal and the initial quadrature signal, respectively, to obtain the corresponding in-phase input signal and the corresponding quadrature input signal, where the predetermined processing includes at least one of signal synchronization, frequency boosting, oversampling, and baseband filtering. Through the DSP module and the processing module, the digital baseband signals are subjected to digital processing, signal decomposition, signal synchronization, frequency raising, oversampling, baseband filtering and the like, and the signal quality of the signals reaching the in-phase modulator and the quadrature modulator is further ensured to be good.

As shown in fig. 3, the digital transmitter architecture of the present application is a wireless digital transmitter architecture, and further includes a transmitting antenna 900, which is connected to the second filter 400 and is configured to receive and transmit the power synthesis and filtered signal sent by the second filter 400.

According to another specific embodiment of the present application, the DSP module receives the digital baseband signal through a digital baseband signal interface, the digital baseband signal interface is a digital interface that is the same as the analog transmitter, and after signal decomposition corresponding to the analog-to-digital, multiple signal synchronization and oversampling are used to achieve a higher sampling rate, so as to obtain a certain degree of gain for suppressing the noise floor. In order to match the carrier frequency change, 2 ways of changing or fixing the interpolation frequency in a follow-up manner can be adopted. The follow-up sampling frequency change means that the sampling frequency of the interface part and the carrier frequency have a frequency multiplication relation, that is, the carrier frequency Fc = N × Fbb, wherein Fbb is the data receiving frequency of the interface part, and N is a fixed integer multiple. The fixed interpolation frequency means that Fbb is a fixed frequency point and does not change along with the change of the central frequency position Fc of the transmission signal.

The digital transmitter framework is not divided according to the DA, filtering, frequency conversion, frequency mixing and other stages any more, and the functional modules are replaced by the all-digital modules, so that the digital transmitter framework can be greatly saved in the area of only one individual compared with the analog scheme. Moreover, each digital module in the digital transmitter architecture can rapidly switch the process node, and can rapidly iterate in other processes. In addition, since the digital logic output drive ultimately carries the object of a switched-mode operating power amplifier, its operating power amplifier efficiency may be higher relative to other linear PAs. Due to the adoption of the uniquely developed 4-phase digital filtering scheme, the filter has the effect of inhibiting modulation harmonic waves and high-frequency carrier harmonic waves, and can meet the requirements of reducing off-chip filter devices or filtering performance while realizing output signals meeting radio frequency output frequency specifications by matching with a unique passband power synthesis filter structure.

In addition, all modules from the pure digital baseband signal (without a DSP module) at the leftmost side to the impedance matching filter network output with the transformer coil as the core at the rightmost side of the basic signal of the digital transmitter architecture can be realized by adopting a pure digital logic unit, so that a general platform (such as an FPGA, a programmable device, a calculation core module with a high-speed interface, such as an ARM/RISC (advanced RISC machine/RISC)) can be used as a hardware realization carrier, and the architecture scheme of the realization can be realized in a manner of using an algorithm in a hardware description language and adopting a compiling manner. Therefore, the implementation mode can be realized in a traditional mode of CMOS circuit design, and can also be realized in a mode of using hardware description language.

In the above embodiments of the present invention, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

In the embodiments provided in the present application, it should be understood that the disclosed technology can be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the above-described division of the units may be a logical division, and in actual implementation, there may be another division, for example, multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed coupling or direct coupling or communication connection between each other may be an indirect coupling or communication connection through some interfaces, units or modules, and may be electrical or in other forms.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit may be implemented in the form of hardware, or may also be implemented in the form of a software functional unit.

The integrated unit may be stored in a computer-readable storage medium if it is implemented in the form of a software functional unit and sold or used as a separate product. Based on such understanding, the technical solution of the present invention, which is substantially or partly contributed by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.

From the above description, it can be seen that the above-mentioned embodiments of the present application achieve the following technical effects:

1) In the above up-conversion mixing method of the present application, 2 is adopted ⁿ (n is more than or equal to 2) each phase in the phase local oscillator IQ digital signal respectively carries out up-conversion frequency mixing processing on the in-phase baseband digital signal and the quadrature baseband digital signal to obtain 2 ⁿ And performing up-conversion frequency mixing on the in-phase baseband digital signal and the quadrature baseband digital signal by using local oscillator IQ digital signals with equal 4-phase, 8-phase and 16-phase phases and different phases to obtain up-conversion frequency-mixed signals with corresponding numbers. Compared with the problem of serious harmonic wave of the digital modulation transmitter in the prior art, 4-phase, 8-phase and 2-phase digital modulation transmitters are adopted in the method ⁿ The local oscillator IQ digital signals with different phase phases carry out up-conversion and frequency mixing processing on the digital baseband signals, so that the problem of near-field noise deterioration caused by folding back the local oscillation frequency in a frequency domain after the harmonic waves are convoluted by the local oscillator signals in the up-conversion frequency mixing process can be well inhibited, and the problem of serious modulation harmonic waves can be effectively alleviated.

2) In the up-conversion mixing device of the present application, the processing means employs 2 ⁿ (n is more than or equal to 2) each phase in the phase local oscillator IQ digital signal respectively carries out up-conversion frequency mixing processing on the in-phase baseband digital signal and the quadrature baseband digital signal to obtain 2 ⁿ The signals after the phase up-conversion and frequency mixing adopt local oscillator IQ digital signals with 4-phase, 8-phase and 16-phase equality and different phases to the in-phase baseband digital signalsAnd carrying out up-conversion frequency mixing processing on the signals and the orthogonal baseband digital signals to obtain up-conversion frequency-mixed signals with corresponding numbers. Compared with the serious harmonic problem of the digital modulation transmitter in the prior art, 4-phase, 8-phase and 2-phase digital modulation transmitters are adopted in the method ⁿ The local oscillator IQ digital signals with different phase positions carry out up-conversion and frequency mixing processing on the digital baseband signals, so that the problem of near field noise deterioration caused by folding back the local oscillator frequency in the frequency domain after the harmonic waves are convoluted by the local oscillator signals in the up-conversion frequency mixing process can be well solved, and the problem of serious modulation harmonic waves can be effectively relieved.

3) The FPGA of the present application is configured to perform any of the methods described above, which methods employ 2 ⁿ (n is more than or equal to 2) each phase in the phase local oscillator IQ digital signal respectively carries out up-conversion frequency mixing processing on the in-phase baseband digital signal and the quadrature baseband digital signal to obtain 2 ⁿ And performing up-conversion frequency mixing on the in-phase baseband digital signal and the quadrature baseband digital signal by using local oscillator IQ digital signals with equal 4-phase, 8-phase and 16-phase phases and different phases to obtain up-conversion frequency-mixed signals with corresponding numbers. Compared with the serious harmonic problem of the digital modulation transmitter in the prior art, 4-phase, 8-phase and 2-phase digital modulation transmitters are adopted in the method ⁿ The local oscillator IQ digital signals with different phase positions carry out up-conversion and frequency mixing processing on the digital baseband signals, so that the problem of near field noise deterioration caused by folding the local oscillator frequency back in the frequency domain after harmonic waves are convoluted by the local oscillator signals in the up-conversion frequency mixing process can be well inhibited, the problem of serious modulation harmonic waves can be effectively relieved, and the signal effect of the signals obtained by the FPGA after up-conversion frequency mixing is better.

4) In the digital transmitter architecture of the present application, any of the above methods is executed by the up-conversion mixing module, and the up-conversion mixing processing is performed on the input in-phase baseband digital signal and quadrature baseband digital signal, so as to effectively suppress harmonics in the input signal; the signals after the up-conversion and frequency mixing are subjected to predetermined processing such as filtering, shifting, power amplification and the like through a first filter, and power amplification signals with required power are obtained and sent out. Harmonic harmonics in comparison to prior art digitally modulated transmittersThe digital modulation transmitter architecture of the present application employs 4-phase, 8-phase, and 2-phase ⁿ The local oscillator IQ digital signals with different phase positions carry out up-conversion and frequency mixing processing on the digital baseband signals, so that the problem of near-field noise deterioration caused by folding the local oscillator frequency back in the frequency domain after the harmonic waves are convoluted by the local oscillator signals in the up-conversion frequency mixing process can be well inhibited, the problem of serious modulation harmonic waves can be effectively relieved, and the signal quality sent by a digital modulation transmitter framework is better.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An up-conversion mixing method, comprising:

by using 2 ⁿ Each phase in the phase local oscillator IQ digital signal respectively carries out up-conversion frequency mixing processing on an in-phase baseband digital signal and a quadrature baseband digital signal which are received simultaneously to obtain 2 ⁿ And performing phase up-conversion and frequency mixing on the signals, wherein n is an integer and is more than or equal to 2, and the phases of the local oscillator IQ digital signals of any two phases are different.

2. The method of claim 1, wherein each of the local oscillator IQ digital signals comprises a local oscillator I + template signal, a local oscillator I-template signal, a local oscillator Q + template signal, and a local oscillator Q-template signal, using 2 ⁿ Each phase in the phase local oscillator IQ digital signal respectively carries out up-conversion frequency mixing processing on an in-phase baseband digital signal and a quadrature baseband digital signal which are received simultaneously to obtain 2 ⁿ A phase up-converted mixed signal comprising:

performing bit AND operation by using the local oscillator I + template signal and the in-phase baseband digital signal to obtain a first radio frequency signal;

performing bit AND operation by using the local oscillator I-template signal and the in-phase baseband digital signal to obtain a second radio frequency signal;

performing bit AND operation by using the local oscillator Q + template signal and the orthogonal baseband digital signal to obtain a third radio frequency signal;

performing bit AND operation on the local oscillator Q-template signal and the orthogonal baseband digital signal to obtain a fourth radio frequency signal;

and performing frequency mixing processing on the first radio frequency signal, the second radio frequency signal, the third radio frequency signal and the fourth radio frequency signal to obtain a positive up-conversion frequency-mixed signal and a negative up-conversion frequency-mixed signal.

3. The method of claim 2, wherein mixing the first rf signal, the second rf signal, the third rf signal, and the fourth rf signal to obtain a positive up-converted mixed signal and a negative up-converted mixed signal comprises:

when the in-phase baseband digital signal has a positive attribute and the quadrature baseband digital signal has a positive attribute, performing bit-or operation on the first radio frequency signal and the third radio frequency signal to obtain the positive up-conversion mixed signal, and performing bit-or operation on the second radio frequency signal and the fourth radio frequency signal to obtain the negative up-conversion mixed signal;

when the in-phase baseband digital signal has a positive attribute and the quadrature baseband digital signal has a negative attribute, performing a bit or operation on the first radio frequency signal and the fourth radio frequency signal to obtain the positive up-conversion mixed signal, and performing a bit or operation on the second radio frequency signal and the third radio frequency signal to obtain the negative up-conversion mixed signal;

when the in-phase baseband digital signal has a negative attribute and the quadrature baseband digital signal has a positive attribute, performing bit-or operation on the second radio frequency signal and the third radio frequency signal to obtain the positive up-conversion mixed signal, and performing bit-or operation on the first radio frequency signal and the fourth radio frequency signal to obtain the negative up-conversion mixed signal;

and when the in-phase baseband digital signal has a negative attribute and the quadrature baseband digital signal has a negative attribute, performing bit OR operation on the second radio-frequency signal and the fourth radio-frequency signal to obtain the positive up-conversion mixed signal, and performing bit OR operation on the first radio-frequency signal and the third radio-frequency signal to obtain the negative up-conversion mixed signal.

4. A computer program for performing the method of any one of claims 1 to 3.

5. A computer-readable storage medium, characterized in that the computer-readable storage medium comprises a stored program, wherein the program performs the method of any one of claims 1 to 3.

6. An FPGA configured to execute a program, wherein the program when executed performs the method of any one of claims 1 to 3.

7. A digital transmitter architecture, comprising:

an up-conversion mixing module for performing the method of any one of claims 1 to 3;

and the plurality of first filters are respectively used for filtering one up-conversion mixed signal output by the up-conversion mixing module to obtain a power amplification signal with an out-of-band signal suppression effect, wherein the filtering process comprises a shifting process, a power amplification process and a power combination process.

8. The digital transmitter architecture of claim 7, wherein the first filter is a parallel FIR filter comprising:

the parallel shift registers are used for carrying out parallel shift processing on the same received up-conversion frequency-mixing signal to obtain a plurality of parallel shift signals;

a plurality of serializers each for converting a received one of the parallel shifted signals into a serial digital signal;

the power amplifiers are respectively used for carrying out power amplification on the received serial digital signal to obtain a power amplification signal;

and the plurality of switched capacitors are used for combining the power amplification signals output by the plurality of power amplifiers.

9. The digital transmitter architecture of claim 8, wherein the shift frequency of the parallel shift process is a modulation frequency or a carrier frequency of the up-converted mixed signal;

and/or the presence of a gas in the atmosphere,

the parallel FIR filter also comprises at least one input selection module, wherein the input selection module is used for selecting the input timing sequence corresponding to the parallel shift register, so that a plurality of parallel shift registers included in the same parallel FIR filter have M input timing sequences;

m is more than or equal to 1 and less than or equal to N, N is the number of the parallel shift registers included by the parallel FIR filter, the number of the parallel shift register corresponding to the jth input time sequence is greater than that of the parallel shift register corresponding to the (j-1) th input time sequence, the output of the parallel shift register with the largest number corresponding to the (j-1) th input time sequence is the input of the parallel shift register with the smallest number corresponding to the jth input time sequence, j is more than or equal to 1 and less than or equal to M, and the N parallel shift registers are numbered according to the sequence of the corresponding input time sequences when M = N.

10. The digital transmitter architecture of claim 7, further comprising:

a second filter for filtering the power amplified signal output by the first filter;

the transmitting antenna is used for receiving the filtered power amplification signal output by the second filter and transmitting the power amplification signal;

and/or the presence of a gas in the gas,

the digital transmitter architecture further comprises:

the in-phase modulator comprises a plurality of in-phase modulation modules which are sequentially connected in series, wherein the in-phase modulation module is used for receiving an in-phase input signal and/or a signal error, generating an in-phase modulation signal according to the in-phase input signal and/or the signal error and outputting the in-phase modulation signal, the signal error is an error value which is acquired by the in-phase modulation module and is sent to the next in-phase modulation module, and the error value is an error between the in-phase input signal and the in-phase modulation signal generated by the in-phase modulation module;

the quadrature modulator comprises a plurality of quadrature modulation modules which are sequentially connected in series, wherein the quadrature modulation modules are used for receiving quadrature input signals and/or signal errors, generating quadrature modulation signals according to the quadrature input signals and/or the error values and outputting the quadrature modulation signals, the signal errors are the error values which are obtained by the quadrature modulation modules and sent to the next quadrature modulation module, and the error values are errors between the quadrature input signals and the quadrature modulation signals generated by the quadrature modulation modules;

the decoder is connected with the in-phase modulator, the quadrature modulator and the up-conversion frequency mixing module respectively, and is used for receiving the in-phase modulation signals and the quadrature modulation signals, decoding the in-phase modulation signals according to a decoder truth table, generating in-phase baseband digital signals and outputting the in-phase baseband digital signals to the up-conversion frequency mixing module, decoding the quadrature modulation signals according to the decoder truth table, generating quadrature baseband digital signals and outputting the quadrature baseband digital signals to the up-conversion frequency mixing module.