CN115800934B - Power amplifier matching optimization method based on inscribed polygon and reflection coefficient constraint - Google Patents
Power amplifier matching optimization method based on inscribed polygon and reflection coefficient constraint Download PDFInfo
- Publication number
- CN115800934B CN115800934B CN202211487636.4A CN202211487636A CN115800934B CN 115800934 B CN115800934 B CN 115800934B CN 202211487636 A CN202211487636 A CN 202211487636A CN 115800934 B CN115800934 B CN 115800934B
- Authority
- CN
- China
- Prior art keywords
- fund
- harmonic
- impedance
- fundamental wave
- reflection coefficient
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Landscapes
- Microwave Amplifiers (AREA)
Abstract
The invention belongs to the technical field of wireless communication, and particularly relates to a power amplifier matching optimization method based on inscribed polygon and reflection coefficient constraint. When the broadband matching network is optimized, each frequency point in the frequency band corresponds to one solution space. According to the invention, the fundamental wave and harmonic impedance of each frequency point are optimized to the corresponding solution space region, so that the optimization design can be completed, the optimization efficiency and success rate can be effectively improved, and the design difficulty of the broadband matching network is reduced.
Description
Technical Field
The invention belongs to the technical field of wireless communication, and particularly relates to a power amplifier matching optimization method based on inscribed polygons and reflection coefficient constraint.
Background
With the advent of 5G communications, some applications requiring high data transmission rates may require up to hundreds of megahertz of wireless channel bandwidth, and further expansion of the bandwidth of the communication system is required to cover multiple frequency bands of 4G,5G simultaneously. Therefore, bandwidth expansion technology related to a power amplifier (hereinafter referred to as power amplifier) has been a hotspot in the field of power amplifier research. Fig. 1 is a schematic diagram of a broadband power amplifier. The proper broadband matching network design method can efficiently design the matching network meeting the requirements, thereby widening the working bandwidth of the power amplifier. Currently, broadband matching design methods used in industry and academia include smith chart matching, low Q matching networks, load pull technology (Load pull), etc. However, most of these design methods depend on design experience, and cannot simply and efficiently design a matching network required by a broadband high-efficiency power amplifier. Therefore, further research on the broadband matching design method is of great importance.
In the design process of broadband high-efficiency power amplifier, load traction simulation or test is usually adopted to obtain the optimal load impedance required by the power amplifier tube, namely, the same output power P is obtained by analyzing the power and efficiency corresponding to a series of load impedance on the complex impedance plane out And marking all corresponding load impedance to form a closed curve, namely an equal power load impedance curve (equal power circle). Similarly, the load impedances corresponding to the same drain efficiency DE are sequentially connected to form a series of equivalent efficiency load impedance curves (equivalent rate circles). Assuming that the required output power is P required Drain efficiency DE required Fig. 2 shows corresponding fundamental equal power circles, fundamental equal efficiency circles, second harmonic equal power circles, second harmonic equal efficiency circles, and it is to be noted that the shapes and centers of the equal power circles and the equivalent ratio circles are not identical due to the influence of parasitic parameters of the power amplifier tubes. The intersection part of the equal power circle and the equivalent ratio circle can meet the condition that the output power is larger than P required Efficiency is higher than DE required Is provided for the target load impedance region of (a).
The existing 2014 IEEE search article A linear 2-3.5GHz Highly Efficient Harmonic-Tuned Power Amplifier Exploiting Stepped-Impedance Filtering Matching Network provides a design method of a broadband power amplifier. Considering that the target load impedance area on the complex impedance plane obtained by load traction is generally irregularly shaped, it is difficult to represent the target load impedance area by an accurate mathematical expression, and the thought adopted by the above article is that: selecting the central position of the fundamental wave and harmonic wave target load impedance area as a target impedance value Z opt ＝R opt +j*X opt Wherein R is opt Is Z opt Real part of impedance, X opt Is Z opt After the allowable resistance and reactance error values are selected, the impedance imaginary part is used for constraining the optimized impedance value by adopting an objective function shown in the following formula.
Wherein R is L And X L Impedance Z of the design circuit respectively L ρ is an error value set according to the load traction impedance range. It should be emphasized that, unlike the rectangular coordinate system, the Smith chart uses equal-resistance circles and equal-reactance circles to represent impedance values, and therefore, the above-described objective function-constrained impedance region is not an ideal rectangle, but an approximately trapezoidal shape with four sides overlapping the equal-resistance circles and the equal-reactance circles, as shown in fig. 3.
However, it can also be found from fig. 3 that the area constrained by the optimization objective function is only a trapezoid intersecting with the target load impedance area, and the area is generally far smaller than the target load impedance area, so that the impedance area obtained by load traction cannot be fully utilized when the output matching network is optimized (the area shown by the shading in the figure is an area which cannot be utilized by the objective function), that is, an impedance value which does not meet the optimization objective convergence condition but meets the requirements of load traction power and efficiency may occur. Thus, the above method causes a decrease in the optimization efficiency and success rate in the actual power amplifier design, particularly in the broadband design.
Disclosure of Invention
Aiming at the problems, the invention provides a power amplifier matching optimization method based on inscribed polygon and reflection coefficient constraint, which improves a broadband power amplifier matching network optimization design method. Firstly, fundamental wave equal power circle, fundamental wave equal efficiency circle, second harmonic equal power circle and second harmonic equal efficiency circle data of a transistor are obtained through load traction; secondly, selecting proper power and efficiency to obtain an irregular area meeting design requirements, and determining an inscribed polygon target area T for fundamental wave load impedance optimization by using inscribed polygons _fund Determining a reflectance constraint target area T for second harmonic impedance optimization using reflectance constraints _2nd The method comprises the steps of carrying out a first treatment on the surface of the Finally, T is _fund And T is _2nd And carrying out optimization design of the matching network as an optimization target area. The invention restrains the harmonic wave while greatly expanding the fundamental wave impedance optimization target area, can more effectively utilize the result obtained by load traction, and is easier for the design of the broadband high-efficiency matching network.
In order to achieve the above object, the present invention provides a power amplifier matching optimization method based on inscribed polygon and reflection coefficient constraint, comprising the following steps:
s1, obtaining fundamental wave equal power circle, fundamental wave equal efficiency circle, second harmonic equal power circle, second harmonic equal efficiency circle and fundamental wave target power P of each design frequency point of a power amplification tube in a broadband by using load traction simulation _fund Fundamental wave target efficiency DE _fund Second harmonic target power P _2nd Second harmonic target efficiency DE _2nd ；
S2, according to the obtained overlapping area A of the second harmonic equal power circle and the second harmonic equal efficiency circle of each design frequency point _2nd Determining a reflection coefficient constraint target area T for second harmonic impedance optimization _2nd The region has a corresponding modulus of |Γ _2nd I, corresponding phase angle is theta _2nd ；
S3, judging whether the second harmonic frequency of each design frequency point is equal to the frequencies of other design frequency points of the power amplifier tube in the bandwidth; if not, executing the step S4; if yes, jumping to the step S5;
s4, according to the obtained overlapping area A of fundamental wave equal power circles and fundamental wave equal efficiency circles of all the design frequency points _fund Determining an inscribed polygonal target region T for fundamental load impedance optimization _fund The corresponding area of the polygon is S _fund ；
S5, adopting a correction scheme to the overlapped area A/u in the step S4 fund Correcting;
s6, designing a broadband output matching network, and simulating the output matching network to obtain fundamental wave load impedance Z L_fund Second harmonic load impedanceZ L_2nd ；
S7, judging fundamental wave load impedance Z of each design frequency point of the power amplification tube in the broadband L_fund Whether or not to be within the corresponding inscribed polygon target region T _fund An inner part; if yes, executing step S8; otherwise, jumping to the step S6;
s8, judging the second harmonic load impedance Z of each design frequency point of the power amplification tube in the broadband L_2nd Whether or not the target area T is constrained by the corresponding reflection coefficient _2nd An inner part; if yes, executing step S9; otherwise, jumping to the step S6;
s9, obtaining the optimal broadband power amplifier output matching network.
Further, the step S2 includes the following steps:
s2.1, selecting that the output power of the transistor is larger than the second harmonic target power P at the second harmonic frequency of each design frequency point according to the obtained second harmonic equal power circle and the second harmonic equal efficiency circle _2nd Efficiency higher than second harmonic target efficiency DE _2nd Is a overlapping area A of (2) _2nd ；
S2.2 calculating an overlap region A by the following formula _2nd Reflection coefficient modulus value |Γ corresponding to medium second harmonic impedance _2nd I and phase angle θ _2nd Wherein Z is _2nd For second harmonic impedance, Z 0 Is the reference impedance;
s2.3 the obtained reflection coefficient modulus value |Γ _2nd I and phase angle θ _2nd Limiting to obtain required reflection coefficient constraint target area T _2nd The lower and upper limits of the constraint are |Γ, respectively min |、θ min And |Γ max I and theta max 。
Further, the step S4 includes the following steps:
s4.1, selecting a transistor with output power larger than fundamental wave target power P at fundamental wave frequency points of all design frequency points _fund Efficiency higher than fundamental wave target efficiency DE _fund Is not equal to the overlap area of (1)Domain a _fund ；
S4.2 in the overlap region A _fund Inside sequentially selecting n points to form an inscribed polygon target area T _fund The n points are a 1 (x 1 ,y 1 )，a 2 (x 2 ,y 2 )，……，a n-1 (x n-1 ,y n-1 )，a n (x n ,y n )；
S4.3 calculating the area of the selected polygon by using the shoelace theorem, namely the following formula, and marking as S _fund ，
Wherein x is n+1 ＝x 1 ，y n+1 ＝y 1 。
Further, the step S7 includes the steps of:
s7.1 marking the fundamental wave load impedance of the design frequency point as Z L_fund The Z is L_fund ＝R L_fund +j*X L_fund Wherein R is L_fund As the real part of fundamental wave impedance, X L_fund J represents the imaginary part in the complex number for the imaginary part of the fundamental impedance;
s7.2 from the overlap region A _fund Interior a 1 ，a 2 ，……，a n-1 ，a n Two points and fundamental wave load impedance Z are sequentially selected L_fund Corresponding point (R L_fund ,X L_fund ) Forming n triangles, calculating n triangle areas by using the following formula, and accumulating to obtain Z L Corresponding point and selected a 1 ，a 2 ，……，a n-1 ，a n N triangular areas of dot composition and S L_fund ，
Wherein S is Δ (i) Is the area of the ith triangle in the n triangles, S L_fund Is the sum of the areas of n triangles;
s7.3 determining triangle area and S L_fund Whether or not to correspond to the polygon in step S4 _fund Equal; if so, designing fundamental wave impedance Z of frequency point L_fund In the corresponding inscribed polygon target region T _fund An inner part; if not, designing fundamental wave impedance Z of frequency point L_fund Not in the corresponding inscribed polygonal target region T _fund An inner part;
s7.4, selecting other design frequency points in the broadband, and repeating the steps S7.1-S7.3;
s7.5 if the fundamental wave impedance Z of all the design frequency points L_fund In the corresponding inscribed polygon target region T _fund In, executing step S8; otherwise, go to step S6.
Further, the step S8 includes the steps of:
s8.1 second harmonic impedance Z of each design frequency point obtained in the step S6 L_2nd The corresponding reflection coefficient modulus |Γ is calculated by the following formula L_2nd I and phase angle θ L_2nd ；
S8.2 if the reflectance modulus value |Γ L_2nd I and phase angle θ L_2nd The second harmonic impedance Z satisfies the following formula L_2nd Reflection coefficient constraint target area T located in second harmonic impedance optimization _2nd The method comprises the steps of carrying out a first treatment on the surface of the Otherwise, the second harmonic impedance Z L_2nd Reflection coefficient constraint target region T not optimized in second harmonic impedance _2nd An inner part;
wherein |Γ min |、θ min And |Γ max |、θ max The lower limit and the upper limit of the constraint in the step S2 are respectively;
s8.3, selecting other design frequency points in the broadband, and repeating the steps S8.1-S8.3;
s8.4 if the secondary fundamental wave impedance Z of all the design frequency points L_2nd Constraining the target region T at the respective corresponding reflection coefficient _2nd In, executing step S9; otherwise, go to step S6.
Further, when the frequency of each design frequency point is equal to the second harmonic frequency of other design frequency points in the bandwidth, namely a high frequency point f exists H Fundamental wave and low frequency point f of (2) L In the case of second harmonic impedance conflict (i.e. 2f L ＝f H ) For the overlapping area A/u fund And performing correction, wherein the correction method S5 comprises the following steps:
s5.1 obtaining the low frequency point f according to the step S2 L Second harmonic 2f of (2) L Is to constrain the target area A 'by the reflection coefficient of (C)' _2nd ；
S5.2 obtaining the high frequency point f according to the steps S1 and S4 H Overlapping area A 'of fundamental wave equal power and fundamental wave equal efficiency circle' _fund And the low frequency point f obtained in the step S5.1 L Second harmonic 2f L Is to constrain the target area A 'by the reflection coefficient of (C)' _2nd Comparing, selecting A/u in the overlapping area correction step S4 fund 。
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
(1) The invention can improve the probability of successful optimization of the output matching network and realize the optimal impedance matching of the broadband high-efficiency power amplifier. The optimal load impedance required by the power amplifier tube is usually obtained by adopting load traction simulation, the target impedance area is approximately trapezoidal, and the impedance area obtained by load traction is difficult to fully utilize.
(2) The invention can realize the design of the broadband high-efficiency power amplifier which spans multiple octaves. If the bandwidth of the traditional broadband power amplifier exceeds one octave, the matching network needs to be matched at the same time under certain high-frequency pointsTwo different impedance points (high frequency point fundamental impedance and low frequency point second harmonic impedance) are allocated. This is not possible in conventional matching networks. The invention reasonably expresses the fundamental wave impedance area at the high frequency point and the second harmonic impedance overlapping area at the low frequency point by using the inscribed polygon, and takes the fundamental wave impedance area and the second harmonic impedance overlapping area as the fundamental wave optimization area A/u of the high frequency point fund A power amplifier design across multiple octaves is achieved.
Drawings
Fig. 1 is a schematic diagram of a broadband power amplifier.
Fig. 2 illustrates fundamental equal power circles, fundamental equal efficiency circles, second harmonic equal power circles, second harmonic equal efficiency circles, and target load impedance regions determined by the same.
Fig. 3 is a graph of a conventional impedance optimization objective region based on an impedance error absolute value optimization objective function.
FIG. 4 is a flow chart of a power amplifier matching optimization method based on inscribed polygon and reflection coefficient constraint.
FIG. 5 second harmonic impedance optimization target region T using reflection coefficient constraints of the present invention _2nd A drawing.
FIG. 6 endo-polygonal target region T for fundamental load impedance optimization of the present invention _fund A drawing.
Fig. 7 is a diagram of a method for discriminating fundamental wave impedance of a matching network according to the present invention.
Fig. 8 is a diagram of a method for discriminating the second harmonic impedance of the matching network according to the present invention.
FIG. 9 shows a high-frequency point fundamental wave load impedance optimization target area T based on inscribed polygon and reflection coefficient constraint _fund A drawing.
Fig. 10 shows a matching network structure used in the example of the present invention.
Fig. 11 shows the saturated power and efficiency results of a 0.4-4.5GHz power amplifier designed in accordance with the present invention.
Detailed Description
The invention will be further described with reference to the drawings and the specific embodiments, it being noted that the technical solution and the design principle of the invention will be described in detail with only one preferred technical solution, but the scope of the invention is not limited thereto.
The examples are preferred embodiments of the present invention, but the present invention is not limited to the above-described embodiments, and any obvious modifications, substitutions or variations that can be made by one skilled in the art without departing from the spirit of the present invention are within the scope of the present invention.
Fig. 4 is a flowchart of an optimization design of a power amplifier matching network based on inscribed polygon and reflection coefficient constraint, including:
s1, obtaining fundamental wave equal power circle, fundamental wave equal efficiency circle, second harmonic equal power circle, second harmonic equal efficiency circle and fundamental wave target power P of each design frequency point of a power amplification tube in a broadband by using load traction simulation _fund Fundamental wave target efficiency DE _fund Second harmonic target power P _2nd Second harmonic target efficiency DE _2nd ；
S2, according to the obtained overlapping area A of the second harmonic equal power circle and the second harmonic equal efficiency circle of each design frequency point _2nd Determining a reflection coefficient constraint target area T for second harmonic impedance optimization _2nd The region has a corresponding modulus of |Γ _2nd I, corresponding phase angle is theta _2nd ；
S3, judging whether the second harmonic frequency of each design frequency point is equal to the frequencies of other design frequency points of the power amplifier tube in the bandwidth; if not, executing the step S4; if yes, jumping to the step S5;
in a specific embodiment, if the design frequency band of the broadband power amplifier is 1GHz-3GHz, each design frequency point is selected from 1GHz and 3 GHz. For example, when the design frequency point is 1GHz, the second harmonic frequency is 2GHz, when the design frequency point is 1.5GHz, the second harmonic frequency is 3GHz, when the design frequency point is 2GHz, the second harmonic frequency is 4GHz, and so on.
At this time, two situations may occur, one is that the second harmonic frequency of the design frequency point is equal to the frequencies of other design frequency points, for example, the second harmonic frequency of the design frequency point of 1GHz is 2GHz, and the frequencies of the design frequency point of other design frequency points of 2GHz are equal. The other case is that the second harmonic frequency of the design frequency point is not equal to the frequencies of other design frequency points, for example, the second harmonic frequency of the design frequency point of 2GHz is 4GHz and is different from other design frequency points in the frequency range of 1GHz-3 GHz. The purpose of our judgment is to make special treatment with step S5 for the first case. For the second case, the process proceeds to step S4.
S4, according to the obtained overlapping area A of fundamental wave equal power circles and fundamental wave equal efficiency circles of all the design frequency points _fund Determining an inscribed polygonal target region T for fundamental load impedance optimization _fund The corresponding area of the polygon is S _fund ；
S5, adopting a correction scheme to the overlapped area A/u in the step S4 fund Correcting;
s6, designing a broadband output matching network, and simulating the output matching network to obtain fundamental wave load impedance Z L_fund Second harmonic load impedance Z L_2nd ；
S7, judging fundamental wave load impedance Z of each design frequency point of the power amplification tube in the broadband L_fund Whether or not to be within the corresponding inscribed polygon target region T _fund An inner part; if yes, executing step S8; otherwise, jumping to the step S6;
s8, judging the second harmonic load impedance Z of each design frequency point of the power amplification tube in the broadband L_2nd Whether or not the target area T is constrained by the corresponding reflection coefficient _2nd An inner part; if yes, executing step S9; otherwise, jumping to the step S6;
s9, obtaining the optimal broadband power amplifier output matching network.
As a preferred embodiment of the present invention, as shown in fig. 5, step S2 includes the following specific matters:
s2.1, selecting that the output power of the transistor is larger than the second harmonic target power P at the second harmonic frequency of each design frequency point according to the obtained second harmonic equal power circle and the second harmonic equal efficiency circle _2nd Efficiency higher than second harmonic target efficiency DE _2nd Is a overlapping area A of (2) _2nd ；
S2.2 calculating an overlap region A by the following formula _2nd Reflection coefficient modulus value |Γ corresponding to medium second harmonic impedance _2nd I and phase angle θ _2nd Wherein Z is _2nd For second harmonic impedance, Z 0 Is the reference impedance;
s2.3 the obtained reflection coefficient modulus value |Γ _2nd I and phase angle θ _2nd Limiting to obtain required reflection coefficient constraint target area T _2nd The lower and upper limits of the constraint are |Γ, respectively min |、θ min And |Γ max I and theta max 。
As a preferred embodiment of the present invention, as shown in fig. 6, step S4 includes the steps of:
s4.1, selecting a transistor with output power larger than fundamental wave target power P at fundamental wave frequency points of all design frequency points _fund Efficiency higher than fundamental wave target efficiency DE _fund Is a overlapping area A of (2) _fund ；
S4.2 in the overlap region A _fund Inside sequentially selecting n points to form an inscribed polygon target area T _fund The n points are a 1 (x 1 ,y 1 )，a 2 (x 2 ,y 2 )，……，a n-1 (x n-1 ,y n-1 )，a n (x n ,y n )；
S4.3 calculating the area of the selected polygon by using the shoelace theorem, namely the following formula, and marking as S _fund ，
Wherein x is n+1 ＝x 1 ，y n+1 ＝y 1 。
As a preferred embodiment of the present invention, as shown in fig. 7, step S7 includes the steps of:
s7.1 marking the fundamental wave load impedance of the design frequency point as Z L_fund The Z is L_fund ＝R L_fund +j*X L_fund Wherein R is L_fund As the real part of fundamental wave impedance, X L_fund J represents the imaginary part in the complex number for the imaginary part of the fundamental impedance;
s7.2 from the overlap region A _fund Interior a 1 ，a 2 ，……，a n-1 ，a n Two points and fundamental wave load impedance Z are sequentially selected L_fund Corresponding point (R L_fund ,X L_fund ) Forming n triangles, calculating n triangle areas by using the following formula, and accumulating to obtain Z L Corresponding point and selected a 1 ，a 2 ，……，a n-1 ，a n N triangular areas of dot composition and S L_fund ，
Wherein S is Δ (i) Is the area of the ith triangle in the n triangles, S L_fund Is the sum of the areas of n triangles;
s7.3 determining triangle area and S L_fund Whether or not to correspond to the polygon in step S4 _fund Equal; if so, designing fundamental wave impedance Z of frequency point L_fund In the corresponding inscribed polygon target region T _fund An inner part; if not, designing fundamental wave impedance Z of frequency point L_fund Not in the corresponding inscribed polygonal target region T _fund An inner part;
s7.4, selecting other design frequency points in the broadband, and repeating the steps S7.1-S7.3;
s7.5 if the fundamental wave impedance Z of all the design frequency points L_fund In the corresponding inscribed polygon target region T _fund In, executing step S8; otherwise, go to step S6.
As shown in FIG. 7, S _fund Is not equal to S L_fund The fundamental impedance is outside the defined polygon and does not meet the design requirements. On the contrary, S _fund Equal to S L_fund The fundamental impedance lies within the defined polygon; finally, selecting other design frequency points in the broadband, and repeating the steps; if it isFundamental wave impedance Z of all design frequency points L_fund In the corresponding inscribed polygon target region T _fund In, executing step S8; otherwise, go to step S6.
As a preferred embodiment of the present invention, as shown in fig. 8, step S8 includes the steps of:
s8.1 second harmonic impedance Z of each design frequency point obtained in the step S6 L_2nd The corresponding reflection coefficient modulus |Γ is calculated by the following formula L_2nd I and phase angle θ L_2nd ；
S8.2 if the reflectance modulus value |Γ L_2nd I and phase angle θ L_2nd The second harmonic impedance Z satisfies the following formula L_2nd Reflection coefficient constraint target area T located in second harmonic impedance optimization _2nd The method comprises the steps of carrying out a first treatment on the surface of the Otherwise, the second harmonic impedance Z L_2nd Reflection coefficient constraint target region T not optimized in second harmonic impedance _2nd An inner part;
wherein |Γ min |、θ min And |Γ max |、θ max The lower limit and the upper limit of the constraint in the step S2 are respectively;
s8.3, selecting other design frequency points in the broadband, and repeating the steps S8.1-S8.3;
s8.4 if the secondary fundamental wave impedance Z of all the design frequency points L_2nd Constraining the target region T at the respective corresponding reflection coefficient _2nd In, executing step S9; otherwise, go to step S6.
As a preferred embodiment of the present invention, as shown in FIG. 9, when the frequency of each design frequency point is equal to the second harmonic frequencies of other design frequency points in the bandwidth, i.e. there is a high frequency point f H Fundamental wave and low frequency point f of (2) L In the case of second harmonic impedance conflict (i.e. 2f L ＝f H ) For the overlapping area A/u fund And performing correction, wherein the correction method S5 comprises the following steps:
s5.1 obtaining the low frequency point f according to the step S2 L Second harmonic 2f of (2) L Is to constrain the target area A 'by the reflection coefficient of (C)' _2nd ；
S5.2 obtaining the high frequency point f according to the steps S1 and S4 H Overlapping area A 'of fundamental wave equal power and fundamental wave equal efficiency circle' _fund And the low frequency point f obtained in the step S5.1 L Second harmonic 2f L Is to constrain the target area A 'by the reflection coefficient of (C)' _2nd Comparing, selecting A/u in the overlapping area correction step S4 fund 。
The invention is further illustrated by the following specific examples.
In the embodiment, a Wolfsspeed CGH40010F GaN HEMT power amplifier tube is adopted to design a 0.4-4.5GHz broadband high-efficiency power amplifier, and a dielectric substrate is a Rogers 4350B plate with epsilon r=3.66 and h=30 mil.
Firstly, obtaining fundamental wave equal power circles, fundamental wave equal efficiency circles, second harmonic equal power circles and second harmonic equal efficiency circles of 10 frequency points of 0.4, 0.5, 1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5GHz and the like according to the simulation in the step S1, and simultaneously selecting power and efficiency meeting design requirements as shown in a table 1; next, as shown in step S2, the overlapping area A of the second harmonic equal power circle and the second harmonic equal efficiency circle according to the above design frequency points _2nd Determining a reflection coefficient constraint target area T for second harmonic impedance optimization _2nd The region has a corresponding modulus of |Γ _2nd I, corresponding phase angle is theta _2nd As shown in table 2; thirdly, judging whether the frequencies of the frequency points are equal to the second harmonic frequencies of other design frequency points in the bandwidth or not as in the step S3, if so, correcting the next step by referring to the method of FIG. 9; next, as shown in step S4, the overlapping area a of the fundamental wave equal power circle and the fundamental wave equal efficiency circle according to the above design frequency points _fund Determining an inscribed polygonal target region T for fundamental load impedance optimization _fund The corresponding area of the polygon is S _fund As shown in table 3;and finally, utilizing the fundamental wave and harmonic wave optimization target area, and carrying out the optimization design of the broadband high-efficiency power amplifier output matching network according to the steps S6 to S9. For the broadband output matching network in step S6, the embodiment of the present invention adopts a step impedance matching network structure commonly used in the art for design.
TABLE 1 fundamental and second harmonic target power and target efficiency for each frequency bin
| Frequency (GHz) | 0.4 | 0.5 | 1 | 1.5 | 2 |
| P _fund (dBm) | 40 | 40 | 40 | 40 | 40 |
| DE _fund (％) | 60 | 62 | 60 | 60 | 64 |
| P _2nd (dBm) | 40 | 40 | 40 | 40 | 40 |
| DE _2nd (％) | 60 | 60 | 60 | 60 | 60 |
| Frequency (GHz) | 2.5 | 3 | 3.5 | 4 | 4.5 |
| P _fund (dBm) | 40 | 40 | 40 | 40 | 40 |
| DE _fund (％) | 61 | 62 | 60 | 60 | 60 |
| P _2nd (dBm) | 40 | 40 | 40 | 40 | 40 |
| DE _2nd (％) | 62 | 62 | 60 | 60 | 60 |
Table 2 second harmonic reflection coefficient for each frequency point
TABLE 3 area of optimized region for fundamental wave at each frequency point
| Frequency (GHz) | 0.4 | 0.5 | 1 | 1.5 | 2 |
| S _fund | 1133.5737 | 937.6558 | 633.0546 | 515.4673 | 276.1482 |
| Frequency (GHz) | 2.5 | 3 | 3.5 | 4 | 4.5 |
| S _fund | 185.2755 | 99.8515 | 150.6400 | 51.3387 | 42.3192 |
Fig. 10 shows an output matching structure obtained by the above-described method optimization design. The 1 port is connected to the drain of the transistor and has the same impedance as the load-pull reference impedance; port 2 is a termination load impedance typically 50Ohm.
The input matching network design requirement can be obtained by traction of source impedance by adopting a similar method, and the input matching network is optimized and designed. Fig. 11 is a saturated power and efficiency diagram of a 0.4-4.5GHz broadband power amplifier designed using the proposed broadband high-efficiency matching design approach. The result shows that the saturated output power is between 40.1 and 41.6dBm, the efficiency is between 62.1 and 68.5 percent, and the design of the broadband high-efficiency amplifier is realized.
Claims (6)
1. The power amplifier matching optimization method based on the restriction of the inscribed polygon and the reflection coefficient is characterized by comprising the following steps:
s1, obtaining fundamental wave equal power circle, fundamental wave equal efficiency circle, second harmonic equal power circle, second harmonic equal efficiency circle and fundamental wave target power P of each design frequency point of a power amplification tube in a broadband by using load traction simulation _fund Fundamental wave target efficiency DE _fund Second harmonic target power P _2nd Second harmonic target efficiency DE _2nd ；
S2, according to the obtained overlapping area A of the second harmonic equal power circle and the second harmonic equal efficiency circle of each design frequency point _2nd Determining a reflection coefficient constraint target area T for second harmonic impedance optimization _2nd The region has a corresponding modulus of |Γ _2nd I, corresponding phase angle is theta _2nd ；
S3, judging whether the second harmonic frequency of each design frequency point is equal to the frequencies of other design frequency points of the power amplifier tube in the bandwidth; if not, executing the step S4; if yes, jumping to the step S5;
s4, according to the obtained overlapping area A of fundamental wave equal power circles and fundamental wave equal efficiency circles of all the design frequency points _fund Determining an inscribed polygonal target region T for fundamental load impedance optimization _fund The corresponding area of the polygon is S _fund ；
S5, adopting a correction scheme to the overlapped area A/u in the step S4 fund Correcting;
s6, designing a broadband output matching network, and simulating the output matching network to obtain fundamental wave load impedance Z L_fund Second harmonic load impedance Z L_2nd ；
S7, judging fundamental wave load impedance Z of each design frequency point of the power amplification tube in the broadband L_fund Whether or not to be within the corresponding inscribed polygon target region T _fund An inner part; if yes, executing step S8; otherwise, jumping to the step S6;
s8, judging the second harmonic load impedance Z of each design frequency point of the power amplification tube in the broadband L_2nd Whether or not the target area T is constrained by the corresponding reflection coefficient _2nd An inner part; if yes, executing step S9; otherwise, jumping to the step S6;
s9, obtaining the optimal broadband power amplifier output matching network.
2. The power amplifier matching optimization method based on the inscribed polygon and the reflection coefficient constraint according to claim 1, wherein the step S2 includes the steps of:
s2.1, selecting that the output power of the transistor is larger than the second harmonic target power P at the second harmonic frequency of each design frequency point according to the obtained second harmonic equal power circle and the second harmonic equal efficiency circle _2nd Efficiency higher than second harmonic target efficiency DE _2nd Is a overlapping area A of (2) _2nd ；
S2.2 calculating an overlap region A by the following formula _2nd Reflection coefficient modulus value |Γ corresponding to medium second harmonic impedance _2nd I and phase angle θ _2nd Wherein Z is _2nd For second harmonic impedance, Z 0 Is the reference impedance;
s2.3 the obtained reflection coefficient modulus value |Γ _2nd I and phase angle θ _2nd Limiting to obtain required reflection coefficient constraint target area T _2nd The lower and upper limits of the constraint are |Γ, respectively min |、θ min And |Γ max I and theta max 。
3. The power amplifier matching optimization method based on the inscribed polygon and the reflection coefficient constraint according to claim 1, wherein the step S4 includes the steps of:
s4.1, selecting a transistor with output power larger than fundamental wave target power P at fundamental wave frequency points of all design frequency points _fund Efficiency higher than fundamental wave target efficiency DE _fund Is a overlapping area A of (2) _fund ；
S4.2 in the overlap region A _fund Inside sequentially selecting n points to form an inscribed polygon target area T _fund The n points are a 1 (x 1 ,y 1 )，a 2 (x 2 ,y 2 )，……，a n-1 (x n-1 ,y n-1 )，a n (x n ,y n )；
S4.3 calculating the area of the selected polygon by using the shoelace theorem, namely the following formula, and marking as S _fund ，
Wherein x is n+1 ＝x 1 ，y n+1 ＝y 1 。
4. The power amplifier matching optimization method based on the inscribed polygon and the reflection coefficient constraint according to claim 1, wherein the step S7 includes the steps of:
s7.1 marking the fundamental wave load impedance of the design frequency point as Z L_fund The Z is L_fund ＝R L_fund +j*X L_fund Wherein R is L_fund As the real part of fundamental wave impedance, X L_fund J represents the imaginary part in the complex number for the imaginary part of the fundamental impedance;
s7.2 from the overlap region A _fund Interior a 1 ，a 2 ，……，a n-1 ，a n Two points and fundamental wave load impedance Z are sequentially selected L_fund Corresponding point (R L_fund ,X L_fund ) Forming n triangles, calculating n triangle areas by using the following formula, and accumulating to obtain Z L Corresponding point and selected a 1 ，a 2 ，……，a n-1 ，a n N triangular areas of dot composition and S L_fund ，
Wherein S is Δ (i) Is the area of the ith triangle in the n triangles, S L_fund Is the sum of the areas of n triangles;
s7.3 determining triangle area and S L_fund Whether or not to correspond to the polygon in step S4 _fund Equal;if so, designing fundamental wave impedance Z of frequency point L_fund In the corresponding inscribed polygon target region T _fund An inner part; if not, designing fundamental wave impedance Z of frequency point L_fund Not in the corresponding inscribed polygonal target region T _fund An inner part;
s7.4, selecting other design frequency points in the broadband, and repeating the steps S7.1-S7.3;
s7.5 if the fundamental wave impedance Z of all the design frequency points L_fund In the corresponding inscribed polygon target region T _fund In, executing step S8; otherwise, go to step S6.
5. The power amplifier matching optimization method based on the inscribed polygon and the reflection coefficient constraint according to claim 1, wherein the step S8 includes the steps of:
s8.1 second harmonic impedance Z of each design frequency point obtained in the step S6 L_2nd The corresponding reflection coefficient modulus |Γ is calculated by the following formula L_2nd I and phase angle θ L_2nd ；
S8.2 if the reflectance modulus value |Γ L_2nd I and phase angle θ L_2nd The second harmonic impedance Z satisfies the following formula L_2nd Reflection coefficient constraint target area T located in second harmonic impedance optimization _2nd The method comprises the steps of carrying out a first treatment on the surface of the Otherwise, the second harmonic impedance Z L_2nd Reflection coefficient constraint target region T not optimized in second harmonic impedance _2nd An inner part;
wherein |Γ min |、θ min And |Γ max |、θ max The lower limit and the upper limit of the constraint in the step S2 are respectively;
s8.3, selecting other design frequency points in the broadband, and repeating the steps S8.1-S8.3;
s8.4 if the secondary fundamental wave impedance Z of all the design frequency points L_2nd Constraining the target region T at the respective corresponding reflection coefficient _2nd In, executing step S9; otherwise, go to step S6.
6. The power amplifier matching optimization method based on inscribed polygon and reflection coefficient constraint of claim 1, wherein when the frequency of each design frequency point is equal to the second harmonic frequencies of other design frequency points in the bandwidth, a high frequency point f exists H Fundamental wave and low frequency point f of (2) L In case of conflict of second harmonic impedance, for the overlapping region A\u fund And (5) performing correction, wherein the step (S5) comprises the following steps:
s5.1 obtaining the low frequency point f according to the step S2 L Second harmonic 2f of (2) L Is to constrain the target area A 'by the reflection coefficient of (C)' _2nd ；
S5.2 obtaining the high frequency point f according to the steps S1 and S4 H Overlapping area A 'of fundamental wave equal power and fundamental wave equal efficiency circle' _fund And the low frequency point f obtained in the step S5.1 L Second harmonic 2f L Is to constrain the target area A 'by the reflection coefficient of (C)' _2nd Comparing, selecting A/u in the overlapping area correction step S4 fund 。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211487636.4A CN115800934B (en) | 2022-11-25 | 2022-11-25 | Power amplifier matching optimization method based on inscribed polygon and reflection coefficient constraint |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211487636.4A CN115800934B (en) | 2022-11-25 | 2022-11-25 | Power amplifier matching optimization method based on inscribed polygon and reflection coefficient constraint |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115800934A CN115800934A (en) | 2023-03-14 |
| CN115800934B true CN115800934B (en) | 2023-06-09 |
Family
ID=85441341
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211487636.4A Active CN115800934B (en) | 2022-11-25 | 2022-11-25 | Power amplifier matching optimization method based on inscribed polygon and reflection coefficient constraint |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115800934B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016101627A1 (en) * | 2014-12-25 | 2016-06-30 | 中兴通讯股份有限公司 | Method and apparatus for increasing digital pre-distortion performance of radio frequency power amplifier |
| CN108009319A (en) * | 2017-11-13 | 2018-05-08 | 电子科技大学 | A kind of system using the impedance solution space limited design broadband matching network |
| CN114492277A (en) * | 2021-12-31 | 2022-05-13 | 厦门市三安集成电路有限公司 | Design method of radio frequency amplifier circuit and radio frequency amplifier circuit |
| CN114598279A (en) * | 2022-04-13 | 2022-06-07 | 江苏大学 | Doherty amplifier with optimized impedance-phase hybrid constraint matching |
-
2022
- 2022-11-25 CN CN202211487636.4A patent/CN115800934B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016101627A1 (en) * | 2014-12-25 | 2016-06-30 | 中兴通讯股份有限公司 | Method and apparatus for increasing digital pre-distortion performance of radio frequency power amplifier |
| CN108009319A (en) * | 2017-11-13 | 2018-05-08 | 电子科技大学 | A kind of system using the impedance solution space limited design broadband matching network |
| CN114492277A (en) * | 2021-12-31 | 2022-05-13 | 厦门市三安集成电路有限公司 | Design method of radio frequency amplifier circuit and radio frequency amplifier circuit |
| CN114598279A (en) * | 2022-04-13 | 2022-06-07 | 江苏大学 | Doherty amplifier with optimized impedance-phase hybrid constraint matching |
Non-Patent Citations (1)
| Title |
|---|
| 一种基于阻抗缓冲匹配技术的高效率Doherty放大器;孔娃等;《微电子学》;第47卷(第5期);第601-604页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115800934A (en) | 2023-03-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Chen et al. | Multiobjective Bayesian optimization for active load modulation in a broadband 20-W GaN Doherty power amplifier design | |
| US20140340278A1 (en) | Variable z0 antenna device design system and method | |
| CN102722613B (en) | Method for optimizing electronic component parameters in antenna broadband matching network by adopting genetic-simulated annealing combination | |
| CN106571781A (en) | Doherty power amplifier circuit | |
| CN107508565B (en) | Broadband power amplifier working in discontinuous frequency band | |
| WO2024078157A1 (en) | Method and system for optimizing lens in vivaldi antenna, and related device | |
| CN115186588A (en) | Power amplifier design method based on multi-objective particle swarm optimization | |
| CN110708701A (en) | Broadband radio frequency power amplifier design method and 5G low-frequency band radio frequency power amplifier | |
| CN115800934B (en) | Power amplifier matching optimization method based on inscribed polygon and reflection coefficient constraint | |
| CN114297922A (en) | Multi-octave power amplifier design method based on Bayesian optimization | |
| CN114598279A (en) | Doherty amplifier with optimized impedance-phase hybrid constraint matching | |
| US11265731B1 (en) | Small cell telecommunications network design | |
| CN108539416B (en) | Same-frequency dual-antenna system, decoupling method, antenna equipment and mobile terminal | |
| CN116341360A (en) | Antenna topology pixel optimization design method adopting machine learning auxiliary optimization | |
| Chen et al. | Support vector regression for harmonic optimization in continuous class-F power amplifier design | |
| CN211377989U (en) | class-J power amplifier with broadband mixed structure | |
| CN106898872A (en) | A kind of composite fractal ultra-wideband antenna | |
| CN209692710U (en) | A kind of broadband continuous type power amplifier based on multiple stage secondary harmonic controling | |
| CN114828174A (en) | Power distribution method and system based on series-parallel connection of power amplifiers | |
| Sun et al. | A wide-band power amplifier based on genetic algorithm and direct layout optimization | |
| CN112383282A (en) | Continuous inverse F-type power amplifier optimally designed by adopting fragment discrete structure matching network | |
| CN103457551B (en) | The method for designing of radio-frequency power amplifier broadband matching circuit | |
| CN108009319B (en) | System for designing broadband matching network by using limited impedance solution space | |
| CN115796101B (en) | Three-frequency Doherty power amplifier output matching network optimization method | |
| CN111463567A (en) | Low RCS ultra-wideband Vivaldi antenna based on differential evolution algorithm |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |