CN115800934A - Power amplifier matching optimization method based on inscribed polygon and reflection coefficient constraint - Google Patents
Power amplifier matching optimization method based on inscribed polygon and reflection coefficient constraint Download PDFInfo
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Abstract
The invention belongs to the technical field of wireless communication, and particularly relates to a power amplifier matching optimization method based on an inscribed polygon and reflection coefficient constraint. When the broadband matching network is optimized, each frequency point in the frequency band corresponds to a solution space. According to the invention, the optimization design can be completed only by optimizing the fundamental wave and harmonic impedance of each frequency point to the inside of the corresponding solution space region, so that the optimization efficiency and success rate can be effectively improved, and the design difficulty of the broadband matching network is reduced.
Description
Technical Field
The invention belongs to the technical field of wireless communication, and particularly relates to a power amplifier matching optimization method based on an inscribed polygon and reflection coefficient constraint.
Background
With the advent of 5G communication, some applications requiring high data transmission rate may require up to hundreds of megahertz wireless channel bandwidth, and the bandwidth of a communication system needs to be further expanded to cover multiple frequency bands of 4G,5G simultaneously. Therefore, bandwidth expanding technology of power amplifiers (hereinafter referred to as power amplifiers) has been a hot spot in the field of power amplifier research. Fig. 1 is a schematic structural diagram of a broadband power amplifier. The matching network meeting the requirement can be efficiently designed by a proper broadband matching network design method, and the working bandwidth of the power amplifier is further widened. Currently, the broadband matching design methods used in the industry and academia include smith chart matching, low Q matching network, load pull (Load pull), and the like. However, most of these design methods rely on design experience, and matching networks required by broadband high-efficiency power amplifiers cannot be designed simply and efficiently. Therefore, the method for further researching the broadband matching design is of great significance.
In the design process of a broadband high-efficiency power amplifier, in order to obtain the optimal load impedance required by a power amplifier tube, load pulling simulation or test is usually adopted, that is, the same output power P is obtained by analyzing the power and efficiency corresponding to a series of load impedances on a complex impedance plane out And marking all corresponding load impedances to form a closed curve, namely an equipower load impedance curve (equipower circle). Similarly, the load impedances corresponding to the same drain efficiency DE are connected in sequence to form a series of equal-efficiency load impedance curves (equivalent circle). Suppose the required output power is P required Drain efficiency of DE required Fig. 2 shows corresponding power circles such as a fundamental wave and the like, efficiency circles such as a fundamental wave and the like, power circles such as a second harmonic and the like, and it should be noted that the shapes and centers of the power circles and the equivalent ratio circle are not completely the same due to the influence of parasitic parameters of the power amplifier tube. The intersection part of the equipower circle and the equivalence ratio circle simultaneously satisfies that the output power is more than P required Efficiency higher than DE required The target load impedance region of (1).
In the IEEE search article A Linearized 2-3.5GHz high hly efficiency Harmonic-Tuned Power Amplifier expanding Stepped-Impedance Matching Network in 2014, a design method of a broadband Power Amplifier is provided. Considering that the target load impedance region on the complex impedance plane obtained by load pulling is usually irregular in shape and is difficult to be represented by an accurate mathematical expression, the above article takes the idea that: selecting the central positions of fundamental wave and harmonic target load impedance regions as target impedance values Z opt ＝R opt +j*X opt Wherein R is opt Is Z opt Real part of impedance, X opt Is Z opt The imaginary impedance component, after selecting the allowable resistance and reactance error values, is used to constrain the optimized impedance value using an objective function as shown in the following equation.
Wherein R is L And X L Respectively the impedance Z of the designed circuit L P is an error value set according to the load traction impedance range. It should be emphasized that, unlike the rectangular coordinate system, the Smith chart uses the isoresistance circle and the isoresistance circle to represent the impedance value, and therefore, the impedance region constrained by the above-mentioned objective function is not an ideal rectangle, but an approximate trapezoid shape with four sides coinciding with the isoresistance circle and the isoresistance circle, as shown in fig. 3.
However, it can also be found from fig. 3 that the region constrained by the optimization objective function is only a trapezoid intersecting with the target load impedance region, and the region is usually much smaller than the target load impedance region, so that the impedance region obtained by load pulling cannot be fully utilized when the output matching network is optimized (the region shown by hatching in the figure is a region that cannot be utilized by the above objective function), that is, an impedance value that does not satisfy the optimization target convergence condition but satisfies the load pulling power and efficiency requirements may occur. Therefore, the above method causes a reduction in optimization efficiency and success rate in practical power amplifier design, especially in broadband design.
Disclosure of Invention
Aiming at the existing problems, the invention provides a power amplifier matching optimization method based on an inscribed polygon and reflection coefficient constraint, and improves a broadband power amplifier matching network optimization design method. Firstly, acquiring efficiency circle data of a fundamental wave equipower circle, a second harmonic and the like of a transistor through load traction; secondly, selecting proper power and efficiency to obtain an irregular area meeting design requirements, and determining an inscribed polygon target area T for optimizing fundamental load impedance by using an inscribed polygon _fund Determining a reflection coefficient constrained target region T for second harmonic impedance optimization using reflection coefficient constraints _2nd (ii) a Finally, T is added _fund And T _2nd And performing optimization design of the matching network as an optimization target area. The invention greatly expands the fundamental wave impedance optimization target area and restrains the harmonic wave, can more effectively utilize the result obtained by load traction, and is easier to design a broadband high-efficiency matching network.
In order to achieve the above object, the present invention provides a power amplifier matching optimization method based on an inscribed polygon and reflection coefficient constraint, comprising the following steps:
s1, obtaining a fundamental wave equipower circle, a fundamental wave equipotency circle, a second harmonic equipotency circle and a fundamental wave target power P of each design frequency point of the broadband internal power amplifier tube by using load traction simulation _fund Fundamental target efficiency DE _fund Second harmonic target power P _2nd Second harmonic target efficiency DE _2nd ；
S2, according to the obtained overlapping area A of the second harmonic isopower circle and the second harmonic isoefficiency circle of each design frequency point _2nd Determining reflection coefficient constraints for second harmonic impedance optimizationTarget area T _2nd The corresponding modulus of the region is | Γ _2nd L corresponding to a phase angle of θ _2nd ；
S3, judging whether the second harmonic frequency of each design frequency point is equal to the frequencies of other design frequency points of the power amplifier tube in the bandwidth; if not, executing the step S4; if yes, jumping to the step S5;
s4, according to the obtained overlapped area A of the fundamental wave equipower circle and the fundamental wave equipotency circle of each design frequency point _fund Determining an inscribed polygonal target region T for fundamental load impedance optimization _fund The corresponding area of the polygon is S _fund ；
S5, adopting a correction scheme to the overlapped region A _inthe step S4 fund Correcting;
s6, designing a broadband output matching network, and simulating the output matching network to obtain fundamental load impedance Z L_fund Second harmonic load impedance Z L_2nd ；
S7, judging the fundamental wave load impedance Z of each design frequency point of the broadband internal power amplifier tube L_fund Whether in the corresponding inscribed polygon target area T _fund Inner; if yes, executing step S8; otherwise, jumping to the step S6;
s8, judging second harmonic load impedance Z of each design frequency point of power amplifier tube in broadband L_2nd Whether or not to constrain the target area T at the corresponding reflection coefficient _2nd Inner; if yes, executing step S9; otherwise, jumping to the step S6;
and S9, obtaining the optimal broadband power amplifier output matching network.
Further, the step S2 includes the steps of:
s2.1 according to the obtained second harmonic isopower circle and second harmonic isopower circle, selecting the transistor output power larger than the second harmonic target power P at the second harmonic frequency of each design frequency point _2nd Efficiency higher than second harmonic target efficiency DE _2nd Overlap region A of _2nd ；
S2.2 calculating the overlap area A by the following formula _2nd Reflection coefficient modulus gamma corresponding to middle and second harmonic impedance _2nd I and phase angle theta _2nd Wherein, Z _2nd Is the second harmonic impedance, Z 0 Is a reference impedance;
s2.3 pair of obtained reflection coefficient modulus gamma _2nd I and phase angle theta _2nd Limiting to obtain the required reflection coefficient constraint target area T _2nd The lower limit and the upper limit of the constraint are gamma min |、θ min And | Γ max I and theta max 。
Further, the step S4 includes the steps of:
s4.1 selecting the transistor output power larger than the fundamental wave target power P at the fundamental wave frequency point of each design frequency point _fund Efficiency higher than fundamental target efficiency DE _fund Overlap region A of _fund ；
S4.2 in the overlap region A _fund Sequentially selecting n points inside to form an inscribed polygon target area T _fund The n points are a 1 (x 1 ,y 1 )，a 2 (x 2 ,y 2 )，……，a n-1 (x n-1 ,y n-1 )，a n (x n ,y n )；
S4.3 the area of the selected polygon is calculated by using the shoelace theorem, namely the following formula and is marked as S _fund ，
Wherein x n+1 ＝x 1 ，y n+1 ＝y 1 。
Further, the step S7 includes the steps of:
s7.1 recording the fundamental load impedance of the designed frequency point as Z L_fund Z is the same as L_fund ＝R L_fund +j*X L_fund Wherein R is L_fund Is the real part of the fundamental impedance, X L_fund As the imaginary part of the fundamental impedance,j represents the imaginary part of the complex number;
s7.2 from overlap region A _fund Inner part a 1 ，a 2 ，……，a n-1 ，a n Two points are sequentially selected from the points and the fundamental load impedance Z L_fund Corresponding point (R) L_fund ,X L_fund ) Forming n triangles, calculating the area of n triangles by using the following formula, and accumulating to obtain a triangle with Z L Corresponding point and selected a 1 ，a 2 ，……，a n-1 ，a n N triangular areas of dots and S L_fund ，
Wherein S is Δ (i) Is the area of the ith triangle of the n triangles, S L_fund Is the sum of the areas of n triangles;
s7.3 judging triangular area and S L_fund Whether or not to correspond to the polygon in step S4 _fund Equal; if yes, designing fundamental wave impedance Z of frequency point L_fund In the corresponding inscribed polygon target region T _fund Inner; if not, designing fundamental wave impedance Z of frequency point L_fund Is not in the corresponding inscribed polygon target area T _fund Inner;
s7.4, selecting other design frequency points in the broadband, and repeating the steps S7.1-S7.3;
s7.5 if all fundamental wave impedance Z of design frequency point L_fund In the respectively corresponding inscribed polygon target areas T _fund If yes, executing step S8; otherwise, jump to step S6.
Further, the step S8 includes the steps of:
s8.1 according to the second harmonic impedance Z of each design frequency point obtained in the step S6 L_2nd The corresponding reflection coefficient modulus | Γ is calculated by the following formula L_2nd I and phase angle theta L_2nd ；
S8.2 if the reflection coefficient modulus value | Γ L_2nd I and phase angle theta L_2nd Satisfies the following formula, the second harmonic impedance Z L_2nd Reflection coefficient constraint target area T for second harmonic impedance optimization _2nd (ii) a Otherwise, the second harmonic impedance Z L_2nd Reflection coefficient constrained target region T not optimized for second harmonic impedance _2nd Internal;
wherein, | Γ min |、θ min And | Γ max |、θ max Respectively, the lower limit and the upper limit of the constraint in the step S2;
s8.3, selecting other designed frequency points in the broadband, and repeating the steps S8.1-S8.3;
s8.4 if all secondary fundamental wave impedance Z of design frequency point L_2nd Constraining the target region T at the respective reflection coefficients _2nd If yes, executing step S9; otherwise, jump to step S6.
Further, when the frequency of each design frequency point is equal to the second harmonic frequency of other design frequency points in the bandwidth, the high frequency point f exists H Fundamental wave and low frequency point f L In the case of second harmonic impedance conflicts (i.e., 2 f) L ＝f H ) Then for the overlap area A _ fund And correcting, wherein the correcting method S5 comprises the following steps:
s5.1 obtaining the low frequency point f according to the step S2 L Second harmonic 2f of L Is in the target region A' _2nd ；
S5.2 obtaining the high frequency point f according to the steps S1 and S4 H Of the fundamental wave equipower and the fundamental wave equipower circle of' _fund And the low frequency point f obtained in step S5.1 L Second harmonic 2f L Is in the target region A' _2nd Comparing, selecting the overlapped area of the two, and correcting A _instep S4 fund 。
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
(1) The invention can improve the successful optimization probability of the output matching network and realize the optimal impedance matching of the broadband high-efficiency power amplifier. The traditional broadband high-efficiency power amplifier usually adopts load traction simulation to obtain the optimal load impedance required by a power amplifier tube, the target impedance area of the traditional broadband high-efficiency power amplifier is similar to a trapezoid, and the impedance area obtained by load traction is difficult to be fully utilized.
(2) The invention can realize the design of high-efficiency power amplifier spanning multiple octaves and wide bands. If the bandwidth of the traditional broadband power amplifier exceeds one octave, the matching network needs to be matched with two different impedance points (high-frequency point fundamental wave impedance and low-frequency point second harmonic wave impedance) at certain high frequency points. This is not possible in conventional matching networks. The invention reasonably expresses the fundamental wave impedance area at the high frequency point and the second harmonic wave impedance overlapping area at the low frequency point by using an inscribed polygon, and takes the fundamental wave impedance overlapping area as the fundamental wave optimization area A _ofthe high frequency point fund And the design of the power amplifier spanning multiple octaves is realized.
Drawings
Fig. 1 is a schematic structural diagram of a broadband power amplifier.
Fig. 2 shows a fundamental equal power circle, a fundamental equal efficiency circle, a second harmonic equal power circle, a second harmonic equal efficiency circle, and a target load impedance region determined by the same.
FIG. 3 is a diagram of a conventional impedance-optimized target area based on an impedance error absolute value optimization objective function.
FIG. 4 is a flow chart of a power amplifier matching optimization method based on an inscribed polygon and reflection coefficient constraint.
FIG. 5 second harmonic impedance optimization target area T of the present invention using reflection coefficient constraints _2nd Drawing.
FIG. 6 internal to the invention for fundamental load impedance optimizationCutting polygon target area T _fund Figure (a).
Fig. 7 is a diagram of a matching network fundamental wave impedance discrimination method of the present invention.
FIG. 8 is a diagram of a method for determining second harmonic impedance of a matching network according to the present invention.
FIG. 9 shows an optimized target region T of high-frequency point fundamental load impedance based on inscribed polygon and reflection coefficient constraints _fund Drawing.
Fig. 10 shows a matching network structure used in the example of the present invention.
FIG. 11 shows the saturation power and efficiency results of a 0.4-4.5GHz power amplifier designed by the present invention.
Detailed Description
The present invention will be further described with reference to the accompanying drawings and specific embodiments, it should be noted that the technical solutions and design principles of the present invention are described in detail with reference to only one preferred technical solution, but the scope of the present invention is not limited thereto.
The examples are preferred embodiments of the present invention, but the present invention is not limited to the above embodiments, and any obvious modifications, substitutions or variations can be made by those skilled in the art without departing from the spirit of the present invention.
Fig. 4 is a flowchart of the power amplifier matching network optimization design based on the constraint of the internal tangent polygon and the reflection coefficient, which includes:
s1, obtaining fundamental wave equipower circle, fundamental wave equipotency circle, second harmonic equipotency circle and fundamental wave target power P of each design frequency point of the broadband inner power amplifier tube by using load traction simulation _fund Fundamental target efficiency DE _fund Second harmonic target power P _2nd Second harmonic target efficiency DE _2nd ；
S2, according to the obtained overlapping area A of the second harmonic isopower circle and the second harmonic isopower circle of each design frequency point _2nd Determining a reflection coefficient constrained target area T for second harmonic impedance optimization _2nd The corresponding modulus of the region is | Γ _2nd L corresponding to a phase angle of θ _2nd ；
S3, judging whether the second harmonic frequency of each designed frequency point is equal to the frequencies of other designed frequency points of the power amplifier tube in the bandwidth; if not, executing the step S4; if yes, jumping to the step S5;
in the specific embodiment, if the designed frequency band of the broadband power amplifier is 1GHz-3GHz, each designed frequency point is selected at 1GHz and 3 GHz. For example, when the design frequency point is 1GHz, the second harmonic frequency is 2GHz, when the design frequency point is 1.5GHz, the second harmonic frequency is 3GHz, when the design frequency point is 2GHz, the second harmonic frequency is 4GHz, and so on.
At this time, two situations may occur, one is a situation that the second harmonic frequency of the designed frequency point is equal to the frequencies of other designed frequency points, for example, the second harmonic frequency of the designed frequency point 1GHz is 2GHz, which is equal to the frequencies of 2GHz in other designed frequency points. The other situation is that the second harmonic frequency of the designed frequency point is not equal to the frequencies of other designed frequency points, for example, the second harmonic frequency of the designed frequency point 2GHz is 4GHz, which is different from other designed frequency points in the frequency band of 1GHz-3 GHz. The purpose of the judgment is to perform special processing by using the step S5 for the first case. For the second case, the process proceeds as in step S4.
S4, according to the obtained overlapped area A of the fundamental wave equipower circle and the fundamental wave equipotency circle of each design frequency point _fund Determining an inscribed polygonal target region T for fundamental load impedance optimization _fund The corresponding area of the polygon is S _fund ；
S5, adopting a correction scheme to the overlapped region A _inthe step S4 fund Correcting;
s6, designing a broadband output matching network, and simulating the output matching network to obtain fundamental load impedance Z L_fund Second harmonic load impedance Z L_2nd ；
S7, judging the fundamental wave load impedance Z of each design frequency point of the broadband inner power amplifier tube L_fund Whether in the corresponding inscribed polygon target area T _fund Internal; if yes, executing step S8; otherwise, jumping to the step S6;
s8 judgmentSecond harmonic load impedance Z of each design frequency point of power amplifier tube in broken broadband L_2nd Whether or not to constrain the target area T at the corresponding reflection coefficient _2nd Internal; if yes, executing step S9; otherwise, jumping to the step S6;
and S9, obtaining the optimal broadband power amplifier output matching network.
As a preferred embodiment of the present invention, as shown in fig. 5, step S2 includes the following details:
s2.1 according to the obtained second harmonic equipower circle and second harmonic equipower circle, selecting the transistor output power larger than the second harmonic target power P at the second harmonic frequency of each design frequency point _2nd Efficiency higher than second harmonic target efficiency DE _2nd Overlap region A of _2nd ；
S2.2 calculating the overlap area A by the following formula _2nd Reflection coefficient modulus gamma corresponding to middle and second harmonic impedance _2nd I and phase angle theta _2nd Wherein Z is _2nd Is the second harmonic impedance, Z 0 Is a reference impedance;
s2.3 pair the obtained reflection coefficient modulus gamma _2nd I and phase angle theta _2nd Limiting to obtain the required reflection coefficient to constrain the target region T _2nd The lower and upper limits of the constraint are | Γ min |、θ min And | Γ max I and theta max 。
As a preferred embodiment of the present invention, as shown in fig. 6, step S4 includes the steps of:
s4.1 selecting the transistor output power larger than the fundamental wave target power P at the fundamental wave frequency point of each design frequency point _fund Efficiency higher than fundamental target efficiency DE _fund Overlap region A of _fund ；
S4.2 in overlap region A _fund Sequentially selecting n points inside to form an inscribed polygon target area T _fund The n points are a 1 (x 1 ,y 1 )，a 2 (x 2 ,y 2 )，……，a n-1 (x n-1 ,y n-1 )，a n (x n ,y n )；
S4.3 the area of the selected polygon is calculated by using the shoelace theorem, namely the following formula and is marked as S _fund ，
Wherein x is n+1 ＝x 1 ，y n+1 ＝y 1 。
As a preferred embodiment of the present invention, as shown in fig. 7, step S7 includes the steps of:
s7.1 recording the fundamental load impedance of the design frequency point as Z L_fund Z is the same as L_fund ＝R L_fund +j*X L_fund Wherein R is L_fund Is the real part of the fundamental impedance, X L_fund Is the imaginary part of the fundamental impedance, j represents the imaginary part in the complex number;
s7.2 from overlap region A _fund Inner part a 1 ，a 2 ，……，a n-1 ，a n Two points are selected in sequence from the points and the fundamental load impedance Z L_fund Corresponding point (R) L_fund ,X L_fund ) Forming n triangles, calculating the area of n triangles by using the following formula, and accumulating to obtain a triangle with Z L Corresponding point and selected a 1 ，a 2 ，……，a n-1 ，a n N triangular areas of dots and S L_fund ，
Wherein S is Δ (i) Is the area of the ith triangle of the n triangles, S L_fund Is the sum of the areas of n triangles;
s7.3 judging triangular area and S L_fund Whether or not to correspond to the polygon in step S4 _fund Equal; if so, thenFundamental wave impedance Z of design frequency point L_fund In the corresponding inscribed polygon target region T _fund Internal; if not, designing fundamental wave impedance Z of frequency point L_fund Is not in the corresponding inscribed polygon target area T _fund Internal;
s7.4, selecting other designed frequency points in the broadband, and repeating the steps S7.1-S7.3;
s7.5 if all the fundamental wave impedance Z of the designed frequency point L_fund In the respective corresponding inscribed polygon target areas T _fund If yes, executing step S8; otherwise, jump to step S6.
As shown in FIG. 7, S _fund Is not equal to S L_fund And the fundamental wave impedance is positioned outside the defined polygon and does not meet the design requirement. Otherwise, S _fund Is equal to S L_fund The fundamental wave impedance is positioned in a defined polygon; finally, selecting other design frequency points in the broadband, and repeating the steps; fundamental wave impedance Z if all design frequency points L_fund In the respective corresponding inscribed polygon target areas T _fund If yes, executing step S8; otherwise, jump to step S6.
As a preferred embodiment of the present invention, as shown in fig. 8, step S8 includes the steps of:
s8.1 according to the second harmonic impedance Z of each design frequency point obtained in the step S6 L_2nd The corresponding reflection coefficient modulus gamma is calculated by the following formula L_2nd I and phase angle θ L_2nd ；
S8.2 if the reflection coefficient modulus value | Γ L_2nd I and phase angle theta L_2nd Satisfies the following formula, the second harmonic impedance Z L_2nd Reflection coefficient constraint target area T for second harmonic impedance optimization _2nd (ii) a Otherwise, the second harmonic impedance Z L_2nd Reflection coefficient constraint target area T not in second harmonic impedance optimization _2nd Inner;
wherein, | Γ min |、θ min And | Γ max |、θ max The lower limit and the upper limit of the constraint in the step S2 are respectively;
s8.3, selecting other design frequency points in the broadband, and repeating the steps S8.1-S8.3;
s8.4 if all the secondary fundamental wave impedance Z of the designed frequency point L_2nd Constraining the target region T at the respective reflection coefficients _2nd If yes, executing step S9; otherwise, jump to step S6.
As a preferred embodiment of the present invention, as shown in fig. 9, when the frequency of each design frequency point is equal to the second harmonic frequency of other design frequency points in the bandwidth, there is a high frequency point f H Fundamental wave and low frequency point f L In the case of second harmonic impedance conflicts (i.e., 2 f) L ＝f H ) Then for the overlap area A _ fund And correcting, wherein the correcting method S5 comprises the following steps:
s5.1 obtaining the low frequency point f according to the step S2 L Second harmonic 2f of L Is in the target region A' _2nd ；
S5.2 obtaining the high frequency point f according to the steps S1 and S4 H Of the fundamental wave equipower and the fundamental wave equipower circle of' _fund And the low frequency point f obtained in step S5.1 L Second harmonic 2f L Is in the target region A' _2nd Comparing, selecting the overlapped area of the two, and correcting A _instep S4 fund 。
The invention is further illustrated below by means of a specific example.
In this embodiment, a 0.4-4.5GHz broadband high-efficiency power amplifier is designed by using a wolffspeed CGH40010F GaN HEMT power amplifier tube, and the used dielectric substrate is a Rogers 4350B plate material with ∈ r =3.66, and h = 30mil.
Firstly, according to the simulation of the step S1, fundamental wave equipower circles, fundamental wave equipotent circles, second harmonic equipotent circles and the like of 10 frequency points such as 0.4, 0.5, 1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5GHz and the like are obtained,Selecting power and efficiency meeting design requirements at the same time according to the second harmonic equal efficiency circle, as shown in table 1; then, as stated in step S2, the overlap region A of the second harmonic equipower circle and the second harmonic equipower circle of each designed frequency point _2nd Determining a reflection coefficient constrained target region T for second harmonic impedance optimization _2nd The corresponding modulus of the region is | Γ _2nd | with a corresponding phase angle of θ _2nd As shown in table 2; thirdly, judging whether the frequency of each frequency point is equal to the second harmonic frequency of other designed frequency points in the bandwidth or not in the step S3, and if so, correcting the next step by referring to the method shown in the figure 9; next, as shown in step S4, the overlap area A of the circle of constant power and the circle of constant efficiency of the fundamental wave of each design frequency point _fund Determining an inscribed polygonal target region T for fundamental load impedance optimization _fund The corresponding area of the polygon is S _fund As shown in table 3; and finally, optimizing and designing the broadband high-efficiency power amplifier output matching network according to the steps S6 to S9 by utilizing the fundamental wave and harmonic wave optimization target area. For the broadband output matching network in step S6, the embodiment of the present invention is designed by using a commonly used step impedance matching network structure in the art.
TABLE 1 fundamental wave and second harmonic target power and target efficiency of each frequency point
| Frequency (GHz) | 0.4 | 0.5 | 1 | 1.5 | 2 |
| P _fund (dBm) | 40 | 40 | 40 | 40 | 40 |
| DE _fund (％) | 60 | 62 | 60 | 60 | 64 |
| P _2nd (dBm) | 40 | 40 | 40 | 40 | 40 |
| DE _2nd (％) | 60 | 60 | 60 | 60 | 60 |
| Frequency (GHz) | 2.5 | 3 | 3.5 | 4 | 4.5 |
| P _fund (dBm) | 40 | 40 | 40 | 40 | 40 |
| DE _fund (％) | 61 | 62 | 60 | 60 | 60 |
| P _2nd (dBm) | 40 | 40 | 40 | 40 | 40 |
| DE _2nd (％) | 62 | 62 | 60 | 60 | 60 |
TABLE 2 second harmonic reflection coefficient at each frequency point
TABLE 3 fundamental wave optimized area of each frequency point
| Frequency (GHz) | 0.4 | 0.5 | 1 | 1.5 | 2 |
| S _fund | 1133.5737 | 937.6558 | 633.0546 | 515.4673 | 276.1482 |
| Frequency (GHz) | 2.5 | 3 | 3.5 | 4 | 4.5 |
| S _fund | 185.2755 | 99.8515 | 150.6400 | 51.3387 | 42.3192 |
Fig. 10 shows an output matching structure optimally designed by the above method. The 1 port is connected to the drain of the transistor, and the impedance is the same as the reference impedance of load-pull; port 2 is terminated with a load impedance of typically 50Ohm.
By adopting a similar method, the design requirement of the input matching network can be obtained by source impedance traction, and the input matching network is optimally designed. FIG. 11 is a graph of saturation power and efficiency of a 0.4-4.5GHz broadband power amplifier designed using the broadband high efficiency matching design method proposed by the present invention. The results show that the saturated output power is between 40.1 and 41.6dBm, the efficiency is between 62.1 and 68.5 percent, and the design of a broadband high-efficiency amplifier is realized.
Claims (6)
1. A power amplifier matching optimization method based on an inscribed polygon and reflection coefficient constraint is characterized by comprising the following steps:
s1, obtaining fundamental wave equipower circle, fundamental wave equipotency circle, second harmonic equipotency circle and fundamental wave target power P of each design frequency point of the broadband inner power amplifier tube by using load traction simulation _fund Fundamental target efficiency DE _fund Second harmonic target power P _2nd Second harmonic target efficiency DE _2nd ；
S2, according to the obtained overlapping area A of the second harmonic isopower circle and the second harmonic isopower circle of each design frequency point _2nd Determining a reflection coefficient constrained target area T for second harmonic impedance optimization _2nd The corresponding modulus of the region is | Γ _2nd L corresponding to a phase angle of θ _2nd ；
S3, judging whether the second harmonic frequency of each design frequency point is equal to the frequencies of other design frequency points of the power amplifier tube in the bandwidth; if not, executing the step S4; if yes, jumping to the step S5;
s4, according to the obtained overlapped area A of the fundamental wave equipower circle and the fundamental wave equipotency circle of each design frequency point _fund Determining an inscribed polygonal target region T for fundamental load impedance optimization _fund The corresponding area of the polygon is S _fund ；
S5 adopting a correcting methodThe overlapping area A _instep S4 fund Correcting;
s6, designing a broadband output matching network, and simulating the output matching network to obtain fundamental load impedance Z L_fund Second harmonic load impedance Z L_2nd ；
S7, judging the fundamental wave load impedance Z of each design frequency point of the broadband internal power amplifier tube L_fund Whether in the corresponding inscribed polygon target area T _fund Inner; if yes, executing step S8; otherwise, jumping to the step S6;
s8, judging second harmonic load impedance Z of each design frequency point of power amplifier tube in broadband L_2nd Whether or not to constrain the target area T at the corresponding reflection coefficient _2nd Internal; if yes, executing step S9; otherwise, jumping to the step S6;
and S9, obtaining the optimal broadband power amplifier output matching network.
2. The power amplifier matching optimization method based on the inscribed polygon and reflection coefficient constraint according to claim 1, wherein the step S2 comprises the following steps:
s2.1 according to the obtained second harmonic equipower circle and second harmonic equipower circle, selecting the transistor output power larger than the second harmonic target power P at the second harmonic frequency of each design frequency point _2nd Efficiency higher than second harmonic target efficiency DE _2nd Overlap region A of _2nd ；
S2.2 calculating the overlap area A by the following formula _2nd Reflection coefficient modulus gamma corresponding to middle and second harmonic impedance _2nd I and phase angle theta _2nd Wherein Z is _2nd Is the second harmonic impedance, Z 0 Is a reference impedance;
s2.3 pair of obtained reflection coefficient modulus gamma _2nd I and phase angle theta _2nd Limiting to obtain the required reflection coefficient to constrain the target region T _2nd Lower limit of constraint andthe upper limit is gamma min |、θ min And | Γ max I and theta max 。
3. The power amplifier matching optimization method based on the inscribed polygon and the reflection coefficient constraint according to claim 1, wherein the step S4 comprises the following steps:
s4.1 selecting the transistor output power larger than the fundamental wave target power P at the fundamental wave frequency point of each design frequency point _fund Efficiency higher than fundamental target efficiency DE _fund Overlap region A of _fund ；
S4.2 in the overlap region A _fund Sequentially selecting n points inside to form an inscribed polygon target region T _fund The n points are a 1 (x 1 ,y 1 )，a 2 (x 2 ,y 2 )，……，a n-1 (x n-1 ,y n-1 )，a n (x n ,y n )；
S4.3 the area of the selected polygon is calculated by using the shoelace theorem, namely the following formula and is marked as S _fund ，
Wherein x is n+1 ＝x 1 ，y n+1 ＝y 1 。
4. The power amplifier matching optimization method based on the inscribed polygon and reflection coefficient constraint according to claim 1, wherein the step S7 comprises the following steps:
s7.1 recording the fundamental load impedance of the design frequency point as Z L_fund Z is said L_fund ＝R L_fund +j*X L_fund Wherein R is L_fund Is the real part of the fundamental impedance, X L_fund Is the imaginary part of the fundamental impedance, j represents the imaginary part in the complex number;
s7.2 from overlap region A _fund Inner part a 1 ，a 2 ，……，a n-1 ，a n Two points are selected in sequence from the points and the fundamental load impedance Z L_fund Corresponding point (R) L_fund ,X L_fund ) Forming n triangles, calculating the area of n triangles by using the following formula, and accumulating to obtain a triangle with Z L Corresponding point and selected a 1 ，a 2 ，……，a n-1 ，a n N triangular areas of dots and S L_fund ，
Wherein S is Δ (i) Is the area of the ith triangle of the n triangles, S L_fund Is the sum of the areas of n triangles;
s7.3 triangular area and S L_fund Whether or not to correspond to the polygon in step S4 _fund Equal; if so, designing the fundamental wave impedance Z of the frequency point L_fund In the corresponding inscribed polygon target region T _fund Internal; if not, designing fundamental wave impedance Z of frequency point L_fund Is not in the corresponding inscribed polygon target area T _fund Inner;
s7.4, selecting other designed frequency points in the broadband, and repeating the steps S7.1-S7.3;
s7.5 if all fundamental wave impedance Z of design frequency point L_fund In the respective corresponding inscribed polygon target areas T _fund If yes, executing step S8; otherwise, jump to step S6.
5. The power amplifier matching optimization method based on the inscribed polygon and reflection coefficient constraint according to claim 1, wherein the step S8 comprises the following steps:
s8.1 according to the second harmonic impedance Z of each design frequency point obtained in the step S6 L_2nd The corresponding reflection coefficient modulus | Γ is calculated by the following formula L_2nd I and phase angle theta L_2nd ；
S8.2 if the reflection coefficient modulus value is gamma L_2nd I and phase angle theta L_2nd Satisfies the following formula, the second harmonic impedance Z L_2nd Reflection coefficient constraint target area T for second harmonic impedance optimization _2nd (ii) a Otherwise, the second harmonic impedance Z L_2nd Reflection coefficient constrained target region T not optimized for second harmonic impedance _2nd Internal;
wherein, | Γ min |、θ min And | Γ max |、θ max The lower limit and the upper limit of the constraint in the step S2 are respectively;
s8.3, selecting other design frequency points in the broadband, and repeating the steps S8.1-S8.3;
s8.4 if all the secondary fundamental wave impedance Z of the designed frequency point L_2nd Constraining the target region T at the respective reflection coefficients _2nd If yes, executing step S9; otherwise, jump to step S6.
6. The power amplifier matching optimization method based on inscribed polygon and reflection coefficient constraint of claim 1, characterized in that when the frequency of each design frequency point is equal to the second harmonic frequency of other design frequency points in the bandwidth, the high frequency point f exists H Fundamental wave and low frequency point f L In the case of second harmonic impedance conflicts, then for the overlap area A_ fund And correcting, wherein the correcting method S5 comprises the following steps:
s5.1 obtaining the low frequency point f according to the step S2 L Second harmonic 2f of L Is in the target region A' _2nd ；
S5.2 obtaining the high frequency point f according to the steps S1 and S4 H Of the fundamental wave equipower and the fundamental wave equipower circle of' _fund And the low frequency point f obtained in step S5.1 L Second harmonic 2f L Is reflected byCoefficient constraint target region A' _2nd Comparing, selecting the overlapped area of the two, and correcting A _instep S4 fund 。
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