CN115799335A - Stacked nanosheet GAA-FET device and manufacturing method thereof - Google Patents

Abstract

The application provides a stacked nanosheet GAA-FET device and a manufacturing method thereof, wherein a stacked layer formed by alternately stacking a first semiconductor layer and a second semiconductor layer is formed on a substrate; etching the stacked layer to form a fin; etching partial areas at two ends of the first semiconductor layer from outside to inside, and forming second side walls at two ends of the first semiconductor layer; removing the first semiconductor layer release nanosheet channel, and taking the second semiconductor layer as a channel; transversely etching the overlapping area of the second side wall and the channel to form a gap; forming an interface oxide layer and a first high-k dielectric layer in the gap; and forming a second high-k dielectric layer between the first high-k dielectric layer and the second side wall and around the channel, and forming a metal gate surrounding the channel. An interface oxide layer, a first high-k dielectric layer and a second high-k dielectric layer are formed between the channel and the second side wall, so that an electric field generated by the metal gate is inhibited from being conducted to an overlapped region of the source drain region and the channel, the electric field intensity of the overlapped region is weakened, band-to-band tunneling leakage is inhibited, and off-state leakage of the device is avoided.

Description

Stacked nanosheet GAA-FET device and manufacturing method thereof

Technical Field

The application relates to the field of semiconductors, in particular to a stacked nanosheet GAA-FET device and a manufacturing method thereof.

Background

With the continuous shrinking of the feature size of integrated circuits, a traditional Fin-type Field Effect Transistor (FinFET) with three or two gates is limited to a node below 3nm, and a Gate-all-around Field-Effect Transistor (GAA-FET) compatible with a mainstream high-k metal Gate FinFET process is a next-generation key structure for realizing the shrinking of the size, and a channel of the GAA-FET is mainly of a Stacked Nanosheet (Stacked nano-Gate) structure. However, band-To-Band Tunneling (BTBT) leakage exists in the overlap region of the source and drain regions and the channel of the GAA-FET, resulting in a sharp increase in off-state leakage of the device.

Disclosure of Invention

In view of this, an object of the present application is to provide a stacked nanosheet GAA-FET device and a method for manufacturing the same, which suppress band-to-band tunneling leakage generated in an overlapping region of a source-drain region and a channel, avoid off-state leakage of the device, and improve device performance. The specific scheme is as follows:

in a first aspect, the present application provides a method for manufacturing a stacked nanosheet GAA-FET device, comprising:

forming a stacked layer in which a first semiconductor layer and a second semiconductor layer are alternately stacked on a substrate;

etching the stacked layer to form a fin, and forming a dummy gate and a first side wall on the fin;

etching partial areas at two ends of the first semiconductor layer from outside to inside, and forming second side walls at two ends of the first semiconductor layer;

removing the first semiconductor layer release nanosheet channel, wherein the second semiconductor layer serves as a channel;

transversely etching the overlapping area of the second side wall and the channel to form a gap;

forming an interface oxide layer and a first high-k dielectric layer in the gap;

and forming a second high-k dielectric layer between the first high-k dielectric layer and the second side wall and around the channel, and forming a metal gate surrounding the channel.

In a second aspect, embodiments of the present application further provide a stacked nanosheet GAA-FET device, comprising:

a substrate, a fin located on one side of the substrate; the fin includes a plurality of second semiconductor layers, the second semiconductor layers acting as channels;

the high-k metal gate structure comprises an interface oxide layer, a first high-k dielectric layer, a second high-k dielectric layer and a metal gate; the metal grid surrounds the second semiconductor layer, and two ends of the metal grid are provided with second side walls; the interface oxide layer and the first high-k dielectric layer are positioned between the channel and the second side wall; the second high-k dielectric layer is located between the channel and the second side wall and on the periphery of the channel.

The embodiment of the application provides a stacked nanosheet GAA-FET device and a manufacturing method thereof, wherein stacked layers formed by alternately stacking a first semiconductor layer and a second semiconductor layer are formed on a substrate; etching the stacked layer to form a fin, and forming a dummy gate and a first side wall on the fin; etching partial areas at two ends of the first semiconductor layer from outside to inside, and forming second side walls at two ends of the first semiconductor layer; removing the first semiconductor layer to release the nanosheet channel, and taking the second semiconductor layer as the channel; transversely etching the overlapping area of the second side wall and the channel to form a gap; forming an interface oxidation layer and a first high-k dielectric layer in the gap; and forming a second high-k dielectric layer between the first high-k dielectric layer and the second side wall and around the channel, and forming a metal gate surrounding the channel. Compared with the prior art, the band-to-band tunneling leakage is caused by the fact that an electric field generated by a metal gate is conducted to the overlapped region of the source region, the drain region and the channel, in the embodiment of the application, the interface oxide layer, the first high-k dielectric layer and the second high-k dielectric layer are formed between the channel and the second side wall, the conduction of the electric field to the overlapped region of the source region, the drain region and the channel can be inhibited, the electric field intensity of the overlapped region of the source region, the drain region and the channel is weakened, the electric field distribution of the overlapped region is changed, the band-to-band tunneling leakage generated in the overlapped region of the source region, the drain region and the channel is inhibited, the off-state leakage of a device is avoided, and the performance of the device is improved.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 shows a schematic flow chart of a method for manufacturing a stacked nanosheet GAA-FET device according to an embodiment of the present application;

fig. 2 to 21 show structural schematic diagrams of a stacked nanosheet GAA-FET device provided by an embodiment of the present application.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanying figures are described in detail below.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways than those described herein, and it will be apparent to those of ordinary skill in the art that the present application is not limited by the specific embodiments disclosed below.

Next, the present application will be described in detail with reference to the drawings, and in the detailed description of the embodiments of the present application, the cross-sectional views illustrating the device structures are not enlarged partially in general scale for the sake of illustration, and the drawings are only examples, which should not limit the scope of protection of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

As described in the background, band-To-Band Tunneling (BTBT) leakage exists in the overlap region of the source and drain regions and the channel of the GAA-FET, resulting in a sharp increase in device off-state leakage.

Based on the technical problem, the embodiment of the application provides a stacked nanosheet GAA-FET device and a manufacturing method thereof, wherein a stacked layer formed by alternately stacking a first semiconductor layer and a second semiconductor layer is formed on a substrate; etching the stacked layer to form a fin, and forming a dummy gate and a first side wall on the fin; etching partial areas at two ends of the first semiconductor layer from outside to inside, and forming second side walls at two ends of the first semiconductor layer; removing the first semiconductor layer release nanosheet channel, and taking the second semiconductor layer as a channel; transversely etching the overlapping area of the second side wall and the channel to form a gap; forming an interface oxidation layer and a first high-k dielectric layer in the gap; and forming a second high-k dielectric layer between the first high-k dielectric layer and the second side wall and around the channel, and forming a metal gate surrounding the channel. Therefore, compared with the prior art, an electric field generated by the metal gate is conducted to an overlapped region of the source-drain region and the channel to cause band-band tunneling leakage.

For the convenience of understanding, the stacked nanosheet GAA-FET device and the method for fabricating the same provided by the embodiments of the present application are described in detail below with reference to the accompanying drawings.

Referring to fig. 1, a schematic flow chart of a method for manufacturing a stacked nanosheet GAA-FET device provided by an embodiment of the present application may include the following steps.

S101, a stack layer in which a first semiconductor layer and a second semiconductor layer are alternately stacked is formed on a substrate.

In the embodiment of the present application, a substrate is provided, the substrate may be made of Si or SiGe, a bulk Si substrate may be used, and substrate doping is performed, specifically, a highly doped well region is formed in the bulk Si substrate by implanting, diffusing, and annealing, so as to reach a desired well depth. For the P-type FET, the high doped well region is an N well, and the injected impurities are N-type impurity ions, such as phosphorus (P) ions; in the case of an N-type FET, the highly doped well region is a p-well, and the implanted impurity is a p-type impurity ion, such as a boron (B) ion.

In the embodiment of the present application, stacked layers in which the first semiconductor layer 101 and the second semiconductor layer 102 are alternately stacked may be formed on a substrate, and specifically, referring to fig. 2, for a structural schematic diagram of a GAA-FET device provided in the embodiment of the present application, silicon dioxide (SiO) on the surface of a bulk silicon substrate may be removed ₂ ) And epitaxially growing a stack of alternately stacked first semiconductor layers 101 and second semiconductor layers 102 on the bulk silicon substrate 100.

The materials of the first semiconductor layer 101 and the second semiconductor layer 102 may be set according to actual requirements, the first semiconductor layer 101 may be a germanium-based film layer, the germanium-based film layer may include an epitaxial germanium layer, an epitaxial silicon-germanium layer, or a combination thereof, and the second semiconductor layer 102 may be an epitaxial silicon layer. For example, the first semiconductor layer/second semiconductor layer stack layer is SiGe/Si, and SiGe/Si periodic superlattice epitaxial growth is performed, and the epitaxial process may adopt reduced pressure epitaxy or molecular beam epitaxy, etc.

And S102, etching the stacked layer to form a fin, and forming a dummy gate and a first side wall on the fin.

In this embodiment, the stacked layer may be etched to form a fin, and a dummy gate and a first sidewall may be formed on the fin, specifically, referring to fig. 3, a self-aligned Sidewall Image Transfer (SIT) process may be used to form a nanoscale first sidewall 104 device array, where the first sidewall 104 may be a silicon nitride (SiN) first sidewall 104 _X ) Or silicon oxide. The specific forming process comprises the following steps: covering the stack with a sacrificial layer 103, which may be polysilicon (PolySi, p-si) or amorphous silicon (a-si), etching away part of the sacrificial layer, depositing a first sidewall 104, which may be silicon nitride (SiN) _x ) And etching the remaining sacrificial layer by adopting anisotropic etching to ensure that the sacrificial layer only remains on the plurality of periodic silicon nitride first side walls 104 on the stacked layer, wherein the first side walls 104 can play a role of a Hard Mask (Hard Mask) in photoetching.

And making the epitaxially grown stacked layers into a plurality of periodically distributed fins by an etching process. And etching by taking the first side wall 104 as a mask to form the fin with the stacked layer structure. The upper part of the fin is a conductive channel region formed by the stacked layers, and the lower part of the fin is a substrate, so that the fin shown in fig. 4 is formed. The fin includes not only the stacked layer structure 101/102 but also the single crystal silicon structure 100 deep into the substrate. The etching process is dry etching or wet etching, such as Reactive Ion Etching (RIE). The fins will be used to form one or more horizontal nanoplates of n-type and/or p-type field effect transistors.

A Shallow Trench Isolation (STI) region 105 may be formed between two adjacent fins to separate transistors on adjacent fins, as shown in fig. 5. First, a dielectric insulating material is deposited, followed by planarization, for example, by a CMP process, and then a selective etching back of the dielectric insulating material is performed to expose the three-dimensional fin structure, so as to form the shallow trench isolation 105. The upper surface of the shallow trench isolation 105 is generally level with the interface between the stacked layer structure in the fin and the single crystal silicon of the substrate, and may be higher or lower than the interface level line. The shallow trench isolation 105 may be formed of a suitable dielectric material, such as silicon dioxide (SiO) ₂ ) Silicon nitride (SiN) _x ) And the like.

Referring to fig. 6, the overall structure of the stacked nanosheet GAA-FET device is schematically illustrated, wherein two directions are defined, and two dotted lines X-X and Y-Y are set, the X-X line is a central line of the fin along the fin line direction, the Y-Y line is a central line of the fin perpendicular to the fin line direction, and the subsequent drawings are cross-sectional schematic views of the X-X line and the Y-Y line.

Next, a dummy gate 106 and a third sidewall 107 may be formed on the fin, as shown in fig. 7, which is a cross-sectional view of fig. 6 in the Y-Y direction, and the dummy gate 106 is formed on the exposed fin in a direction perpendicular to the fin line (i.e., the Y-Y direction), the dummy gate crossing the stacked layers on the fin, and fig. 8 is a cross-sectional view of fig. 6 in the X-X direction. The material used for the dummy gate 106 may be polysilicon (PolySi, p-si) or amorphous silicon (a-si).

Silicon nitride (SiN) is respectively arranged on two sides of the dummy gate along the fin line direction (X-X direction) _x ) The thickness of the third sidewall 107 may be the same for both sides of the third sidewall 107, as shown in fig. 9.

And S103, etching partial areas at two ends of the first semiconductor layer from outside to inside, and forming second side walls at two ends of the first semiconductor layer.

In the embodiment of the present application, the dummy gate 106 and the third sidewall 107 may be used as masks, and the source and drain etching is performed on the fin through an etching process, as shown in fig. 10, only the stacked layers below the dummy gate 106 and the third sidewall 107 are reserved.

Then, partial areas at both ends of the first semiconductor layer 101 are etched from the outside to the inside, and second sidewalls 108 are formed at both ends of the first semiconductor layer 101. Specifically, as shown in fig. 11, a pull-back etching is performed to etch away a portion of the first semiconductor layer 101 from the outside to the center of the first semiconductor layer 101, so as to form a second sidewall 108 in the etched region of the first semiconductor layer 101.

Then, silicon nitride (SiN) is deposited on the periphery of the fin _x ) Referring to fig. 12, the second sidewall 108 is etched until the second sidewall 108 is flush with the second semiconductor layer 102 in the vertical direction, that is, the second sidewalls 108 are formed at two ends of the first semiconductor layer 101, as shown in fig. 13.

And epitaxially forming a source/drain region and performing source/drain doping, as shown in fig. 14, wherein for PMOS, the source/drain region is boron (B) doped SiGe (SiGe: B), and for NMOS, the source/drain region is phosphorus (P) doped silicon (Si) (Si: P), and finally forming a source/drain region 110. And depositing an isolation layer 111 on the upper surfaces of the dummy gate 106 and the source and drain regions 110 to prevent interconnection short circuit between the dummy gate 106 and the source and drain regions 110 in the subsequent step, and performing chemical mechanical polishing on the isolation layer 111 to planarize the isolation layer 111.

Then, as shown in fig. 15, the dummy gate 106 formed of polysilicon (PolySi, p-si) or amorphous silicon (a-si) is etched or etched away by a selective etching or etching process, i.e., the dummy gate 106 is removed.

And S104, removing the first semiconductor layer release nanosheet channel, and taking the second semiconductor layer as a channel.

In the embodiment of the present application, the first semiconductor layer 101 may be removed to release the nanosheet channel, and the second semiconductor layer 102 is used as the channel, as shown in fig. 16. Specifically, the sacrificial layer in the stack layer, i.e., the first semiconductor layer 101, is selectively etched, and the second semiconductor layer 102 is released, i.e., nanosheet (nanosheet) channel release is performed. The nanoplates 202 may range in width from 1 to 100nm, in thickness from 1 to 30nm, and the spacing between each nanoplate 202 may range from 3 to 30nm.

And S105, transversely etching the overlapping area of the second side wall and the channel to form a gap.

In the embodiment of the present application, a gap 115 may be formed by laterally trimming (trimming) an overlapping region between the second sidewall 108 and the Nanosheet (NS) channel 102, as shown in fig. 17, so that a high-k dielectric layer is filled between the second sidewall 108 and the second semiconductor layer 102, thereby suppressing electric field from being conducted to the overlapping region between the source and drain regions and the channel, and suppressing electric leakage of the device in an off state.

And S106, forming an interface oxide layer and a first high-k dielectric layer in the gap.

In an embodiment of the present application, an interfacial oxide layer (IL) and a first high-k dielectric layer (HK 1) may be deposited in the void, the first high-k dielectric layer being a Hf-based high-k material, the material of the first high-k dielectric layer including at least one of: hfO ₂ 、HfSiO _x 、HfON、HfSiON、HfAlO _x 、HfLaO _x 。

In a possible implementation manner, when the interface oxide layer and the first high-k dielectric layer are formed in the gap, the interface oxide layer and the first high-k dielectric layer surrounding the channel may be formed, the first high-k dielectric layer between the channels is removed, and the interface oxide layer and the first high-k dielectric layer in the gap between the channel and the second sidewall are retained.

Specifically, referring to fig. 18, the interfacial oxide layer and the first high-k dielectric layer are shown as a film layer 112 for simplicity. An interface oxide layer and a first high-k dielectric layer 112 surrounding the channel may be formed in the deposition process, and the interface oxide layer and the first high-k dielectric layer between adjacent channels are not desirable, so that the first high-k dielectric layer between the channels may be selectively etched away to avoid affecting the device performance, and the interface oxide layer and the first high-k dielectric layer in the gap are retained, referring to fig. 19, which is a device structure diagram after the first high-k dielectric layer between the channels is removed.

And S107, forming a second high-k dielectric layer between the first high-k dielectric layer and the second side wall and around the channel, and forming a metal gate surrounding the channel.

In the embodiment of the present application, a second high-k dielectric layer (HK 2) 113 may be formed between the first high-k dielectric layer and the second sidewall, and around the channel, and a metal gate 114 may be formed to surround the channel, thereby forming a high-k metal gate structure, as shown with reference to fig. 20. Because an electric field generated by the metal gate is conducted to an overlapped region of the source-drain region and the channel to cause band-to-band tunneling leakage, the interface oxide layer, the first high-k dielectric layer and the second high-k dielectric layer are formed between the NS channel and the second side wall, so that the conduction of the electric field to the overlapped region of the source-drain region and the channel can be inhibited, the electric field intensity of the overlapped region of the source-drain region and the channel is weakened, the electric field distribution of the overlapped region is changed, the band-to-band tunneling leakage generated in the overlapped region of the source-drain region and the channel is inhibited, the off-state leakage of a device is avoided, and the performance of the device is improved.

In the embodiment of the present application, the overlapping region of the third sidewall 107 and the channel may also be laterally etched to form a gap 115, an interface oxide layer and the first high-k dielectric layer 112 are deposited in the gap, and the second high-k dielectric layer 113 is also formed around the channel, so as to further inhibit the electric field from being conducted to the overlapping region of the source-drain region and the channel, reduce the electric field intensity of the overlapping region of the source-drain region and the channel, inhibit the band-to-band tunneling leakage generated in the overlapping region of the source-drain region and the channel, and avoid the off-state leakage of the device.

It can be understood that HK2/HK1 double-layer structure can be formed in part of the NMOS region and the PMOS region of the GAA-FET device at the same time to inhibit band-to-band tunneling leakage in the source drain and channel overlapping region, HK2/HK1 double-layer structure can be formed only in the NMOS region or the PMOS region, and HK2/HK1 double-layer structure can be formed in all the NMOS region and the PMOS region of the GAA-FET device.

The material of the second high-k dielectric layer comprises at least one of the following materials: alO (aluminum oxide) _x 、MnO _x 、ZrO _x 、TiO _x 、MoO _x 、LaO _x 、MgO _x 、ScO _x 、YO _x 、NdO _x . The sum of the thicknesses of the first high-k dielectric layer and the second high-k dielectric layer can be greater than or equal to 0.1nm and less than or equal to 5nm.

The metal gate 114 may include a multi-layer structure of a capping layer TiN, a barrier layer TaN, a work function layer WFL, and a fill layer W, and a specific film structure thereof is not shown in fig. 20. Specifically, a covering layer TiN and a barrier layer TaN can be deposited to form TiN/TaN barrier-I, then PMOS WFL is deposited in an NMOS area and a PMOS area, the material of the PMOS WFL can be TiN or TiSiN, then the PMOS WFL is removed by selective corrosion of all the areas of the NMOS, the PMOS WFL in the PMOS area is reserved, then the barrier-I can be selectively corroded for part of the NMOS area according to actual requirements, the residual thickness of the TiN is controlled, then the PMOS WFL is selectively corroded for part of the PMOS area, the residual thickness of the PMOS WFL is controlled, then the NMOS WFL is deposited for the NMOS area and the PMOS area, and the material of the NMOS WFL can be TiAlC _x And finally, performing TiN/TaN barrier-II and filling layer W conductive filling metal deposition to form a high-k metal gate structure, and performing CMP planarization.

Then ILD dielectric deposition is carried out on the top, referring to FIG. 21, a dielectric CMP layer 116 is formed, contact hole photoetching and etching are carried out on the dielectric CMP layer 116, hole silicide 117 is deposited, a contact electrode is led out, and then the multilayer back-end interconnection and passivation protection process is completed, so that the preparation of the GAA-FET device is completed.

The embodiment of the application provides a method for manufacturing a stacked nanosheet GAA-FET device, wherein stacked layers formed by alternately stacking a first semiconductor layer and a second semiconductor layer are formed on a substrate; etching the stacked layer to form a fin, and forming a dummy gate and a first side wall on the fin; etching partial areas at two ends of the first semiconductor layer from outside to inside, and forming second side walls at two ends of the first semiconductor layer; removing the first semiconductor layer release nanosheet channel, and taking the second semiconductor layer as a channel; transversely etching the overlapping area of the second side wall and the channel to form a gap; forming an interface oxide layer and a first high-k dielectric layer in the gap; and forming a second high-k dielectric layer between the first high-k dielectric layer and the second side wall and around the channel, and forming a metal gate surrounding the channel. Therefore, compared with the prior art, an electric field generated by the metal gate is conducted to an overlapped region of the source-drain region and the channel to cause band-band tunneling leakage.

Based on the above method for manufacturing a stacked nanosheet GAA-FET device, an embodiment of the present application further provides a stacked nanosheet GAA-FET device, which is shown in reference to fig. 21 and includes:

a substrate 100, a fin on one side of the substrate; the fin includes a plurality of second semiconductor layers 102 that act as channels;

a high-k metal gate structure comprising an interface oxide layer and a first high-k dielectric layer 112, a second high-k dielectric layer 113 and a metal gate 114; the metal gate 114 surrounds the second semiconductor layer 102, and the second sidewall 108 is disposed on both ends of the metal gate 114; the interface oxide layer and the first high-k dielectric layer 112 are located between the channel and the second sidewall; the interfacial oxide layer and the second high-k dielectric layer 113 are located between the trench and the second sidewall and at the periphery of the trench.

Specifically, the material of the second high-k dielectric layer comprises at least one of the following materials: alO (aluminum oxide) _x 、MnO _x 、ZrO _x 、TiO _x 、MoO _x 、LaO _x 、MgO _x 、ScO _x 、YO _x 、NdO _x 。

Specifically, the first high-k dielectric layer is an Hf-based high-k material, and the material of the first high-k dielectric layer includes at least one of the following materials: hfO ₂ 、HfSiO _x 、HfON、HfSiON、HfAlO _x 、HfLaO _x 。

Specifically, the sum of the thicknesses of the first high-k dielectric layer and the second high-k dielectric layer is greater than or equal to 0.1nm and less than or equal to 5nm.

In the embodiment of the application, the interface oxide layer, the first high-k dielectric layer and the second high-k dielectric layer are formed between the channel and the second side wall, so that the conduction of an electric field to the overlapped region of the source-drain region and the channel can be inhibited, the electric field intensity of the overlapped region of the source-drain region and the channel is weakened, the electric field distribution of the overlapped region is changed, the band-to-band tunneling leakage generated in the overlapped region of the source-drain region and the channel is inhibited, the off-state leakage of a device is avoided, and the performance of the device is improved.

The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the apparatus embodiment, since it is substantially similar to the method embodiment, it is relatively simple to describe, and reference may be made to some descriptions of the method embodiment for relevant points.

The foregoing is merely a preferred embodiment of the present application and, although the present application discloses the foregoing preferred embodiments, the present application is not limited thereto. Those skilled in the art can now make numerous possible variations and modifications to the disclosed embodiments, or modify equivalent embodiments, using the methods and techniques disclosed above, without departing from the scope of the claimed embodiments. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application still fall within the protection scope of the technical solution of the present application without departing from the content of the technical solution of the present application.

Claims (10)

1. A method for manufacturing a stacked nanosheet GAA-FET device, comprising:

forming a stacked layer in which a first semiconductor layer and a second semiconductor layer are alternately stacked on a substrate;

etching the stacked layer to form a fin, and forming a dummy gate and a first side wall on the fin;

etching partial areas at two ends of the first semiconductor layer from outside to inside, and forming second side walls at two ends of the first semiconductor layer;

removing the first semiconductor layer release nanosheet channel, wherein the second semiconductor layer serves as a channel;

transversely etching the overlapping area of the second side wall and the channel to form a gap;

forming an interface oxidation layer and a first high-k dielectric layer in the gap;

and forming a second high-k dielectric layer between the first high-k dielectric layer and the second side wall and around the channel, and forming a metal gate surrounding the channel.

2. The method of claim 1, wherein the forming an interfacial oxide layer and a first high-k dielectric layer in the void comprises:

forming an interface oxide layer and a first high-k dielectric layer which surround the channel;

and removing the first high-k dielectric layer between the channels, and reserving the interface oxide layer and the first high-k dielectric layer in the gap between the channels and the second side wall.

3. The method of claim 1, wherein the material of the second high-k dielectric layer comprises at least one of the following materials: alO (aluminum oxide) _x 、MnO _x 、ZrO _x 、TiO _x 、MoO _x 、LaO _x 、MgO _x 、ScO _x 、YO _x 、NdO _x 。

4. The method of claim 1, wherein the first high-k dielectric layer is a Hf-based high-k material, and the material of the first high-k dielectric layer comprises at least one of the following materials: hfO ₂ 、HfSiO _x 、HfON、HfSiON、HfAlO _x 、HfLaO _x 。

5. The method of one of claims 1-4, wherein a sum of thicknesses of the first high-k dielectric layer and the second high-k dielectric layer is greater than or equal to 0.1nm and less than or equal to 5nm.

6. A method according to any one of claims 1 to 4, wherein said substrate is made of Si or SiGe.

7. A stacked nanosheet GAA-FET device, comprising:

a substrate, a fin located on one side of the substrate; the fin includes a plurality of second semiconductor layers that act as channels;

the high-k metal gate structure comprises an interface oxide layer, a first high-k dielectric layer, a second high-k dielectric layer and a metal gate; the metal grid surrounds the second semiconductor layer, and two ends of the metal grid are provided with second side walls; the interface oxide layer and the first high-k dielectric layer are positioned between the channel and the second side wall; the interface oxide layer and the second high-k dielectric layer are located between the channel and the second side wall and on the periphery of the channel.

8. The stacked nanoplate GAA-FET device of claim 7, wherein the material of the second high-k dielectric layer comprises at least one of: alO (aluminum oxide) _x 、MnO _x 、ZrO _x 、TiO _x 、MoO _x 、LaO _x 、MgO _x 、ScO _x 、YO _x 、NdO _x 。

9. The stacked nanoplate GAA-FET device of claim 7, wherein the first high-k dielectric layer is a Hf-based high-k material, the material of the first high-k dielectric layer comprising at least one of: hfO ₂ 、HfSiO _x 、HfON、HfSiON、HfAlO _x 、HfLaO _x 。

10. Stacked nanosheet GAA-FET device of any one of claims 7 to 9, wherein the sum of the thicknesses of the first high-k dielectric layer and the second high-k dielectric layer is greater than or equal to 0.1nm and less than or equal to 5nm.

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