CN115719706A - Stacked nanosheet GAA-FET device and manufacturing method thereof - Google Patents
Stacked nanosheet GAA-FET device and manufacturing method thereof Download PDFInfo
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Abstract
The application provides a stacked nanosheet GAA-FET device and a manufacturing method thereof, wherein a stacked layer formed by alternately stacking a first semiconductor layer and a second semiconductor layer is formed on a substrate; etching the stacked layer to form a fin; etching partial areas at two ends of the first semiconductor layer from outside to inside, and forming second side walls at two ends of the first semiconductor layer; removing the first semiconductor layer release nanosheet channel, and taking the second semiconductor layer as a channel; and sequentially forming an interface oxide layer, a first high-k dielectric layer, a second high-k dielectric layer, a third high-k dielectric layer and a metal gate, wherein the first high-k dielectric layer and/or the third high-k dielectric layer are made of Hf-based high-k materials. And a laminated structure formed by the first high-k dielectric layer, the second high-k dielectric layer and the third high-k dielectric layer is used as an oxygen absorption source to absorb oxygen in the interface oxide layer, so that the interface oxide layer of the GAA-FET device can be continuously reduced, the dielectric layer lamination formed among the stacked nanosheets is easier, the space limitation among the stacked nanosheets is avoided, and the performance of the GAA-FET device is improved.
Description
Technical Field
The application relates to the field of semiconductors, in particular to a stacked nanosheet GAA-FET device and a manufacturing method thereof.
Background
With the continuous shrinking of the feature size of integrated circuits, a traditional Fin-type Field Effect Transistor (FinFET) with three or two gates is limited to a node below 3nm, and a Gate-all-around Field-Effect Transistor (GAA-FET) compatible with a mainstream high-k metal Gate FinFET process is a next-generation key structure for realizing the shrinking of the size, and a channel of the GAA-FET is mainly of a Stacked Nanosheet (Stacked nano-Gate) structure.
In the prior art, an interface oxide layer (IL) and a metal gate are arranged around a channel, and a Work Function Layer (WFL) in the metal gate can be used as an oxygen absorption source to absorb oxygen in the interface oxide layer, however, in the process, due to the space limitation between stacked nanosheets, the phenomenon that the work function layer is difficult to fill or is not uniform in filling is easily caused, an effective metal gate oxygen absorption source is lacked, the oxygen absorption effect is poor, so that the interface oxide layer of the GAA-FET device is difficult to continuously reduce, and the device performance is affected.
Disclosure of Invention
In view of the above, an object of the present application is to provide a stacked nanosheet GAA-FET device and a method for fabricating the same, in which oxygen in an interface oxide layer is absorbed, so that the interface oxide layer of the GAA-FET device can be continuously reduced, and the device performance is improved. The specific scheme is as follows:
in a first aspect, the present application provides a method for fabricating a stacked nanosheet GAA-FET device, comprising:
forming a stacked layer in which a first semiconductor layer and a second semiconductor layer are alternately stacked on a substrate;
etching the stacked layer to form a fin, and forming a dummy gate and a first side wall on the fin;
etching partial areas at two ends of the first semiconductor layer from outside to inside, and forming second side walls at two ends of the first semiconductor layer;
removing the first semiconductor layer release nanosheet channel, wherein the second semiconductor layer serves as a channel;
forming an interface oxide layer, a first high-k dielectric layer, a second high-k dielectric layer, a third high-k dielectric layer and a metal gate which surround the channel in sequence; the first high-k dielectric layer and/or the third high-k dielectric layer are/is made of Hf-based high-k materials.
In a second aspect, embodiments of the present application further provide a stacked nanosheet GAA-FET device, comprising:
a substrate, a fin located on one side of the substrate; the fin includes a plurality of second semiconductor layers, the second semiconductor layers acting as channels;
and the high-k metal gate structure surrounds the channel and comprises an interface oxide layer, a first high-k dielectric layer, a second high-k dielectric layer, a third high-k dielectric layer and a metal gate.
The embodiment of the application provides a stacked nanosheet GAA-FET device and a manufacturing method thereof, wherein a stacked layer formed by alternately stacking a first semiconductor layer and a second semiconductor layer is formed on a substrate; etching the stacked layer to form a fin, and forming a dummy gate and a first side wall on the fin; etching partial areas at two ends of the first semiconductor layer from outside to inside, and forming second side walls at two ends of the first semiconductor layer; removing the first semiconductor layer release nanosheet channel, wherein the second semiconductor layer serves as a channel; and forming an interface oxide layer, a first high-k dielectric layer, a second high-k dielectric layer, a third high-k dielectric layer and a metal gate which surround the channel in sequence, wherein the first high-k dielectric layer and/or the third high-k dielectric layer are made of Hf-based high-k materials. Therefore, the laminated structure formed by the first high-k dielectric layer, the second high-k dielectric layer and the third high-k dielectric layer is used as an oxygen absorption source to absorb oxygen in the interface oxidation layer, so that the interface oxidation layer of the GAA-FET device can be continuously reduced, the first high-k dielectric layer, the second high-k dielectric layer and the third high-k dielectric layer are easily laminated among the stacked nanosheets, the laminated structure is not limited by the space among the stacked nanosheets, the stacked nanosheets can be uniformly filled, the oxygen absorption effect is good, and the performance of the GAA-FET device is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic flow chart illustrating a method for manufacturing a stacked nanosheet GAA-FET device according to an embodiment of the present application;
fig. 2 to 23 show structural schematic diagrams of a stacked nanosheet GAA-FET device provided by an embodiment of the present application.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanying figures are described in detail below.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways than those described herein, and it will be appreciated by those skilled in the art that the present application may be practiced without departing from the spirit and scope of the present application, and that the present application is not limited to the specific embodiments disclosed below.
Next, the present application will be described in detail with reference to the drawings, and in the detailed description of the embodiments of the present application, the cross-sectional views illustrating the device structures are not enlarged partially in general scale for the sake of illustration, and the drawings are only examples, which should not limit the scope of protection of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
As described in the background art, in the prior art, the interface oxide layer IL and the metal gate are provided around the trench, and the work function layer WFL in the metal gate can be used as an oxygen absorption source to absorb oxygen in the interface oxide layer, however, in the process, due to the space limitation between the stacked nanosheets, the work function layer is difficult to fill or is not uniformly filled, an effective metal gate oxygen absorption source is lacked, the oxygen absorption effect is poor, and the interface oxide layer of the GAA-FET device is difficult to continuously reduce, which affects the device performance.
Based on the technical problem, the embodiment of the application provides a stacked nanosheet GAA-FET device and a manufacturing method thereof, wherein a stacked layer formed by alternately stacking a first semiconductor layer and a second semiconductor layer is formed on a substrate; etching the stacked layer to form a fin, and forming a dummy gate and a first side wall on the fin; etching partial areas at two ends of the first semiconductor layer from outside to inside, and forming second side walls at two ends of the first semiconductor layer; removing the first semiconductor layer release nanosheet channel, wherein the second semiconductor layer serves as a channel; and forming an interface oxide layer, a first high-k dielectric layer, a second high-k dielectric layer, a third high-k dielectric layer and a metal gate which surround the channel in sequence, wherein the first high-k dielectric layer and/or the third high-k dielectric layer are made of Hf-based high-k materials. Therefore, the laminated structure formed by the first high-k dielectric layer, the second high-k dielectric layer and the third high-k dielectric layer is used as an oxygen absorption source to absorb oxygen in the interface oxide layer, so that the interface oxide layer of the GAA-FET device can be continuously reduced, the first high-k dielectric layer, the second high-k dielectric layer and the third high-k dielectric layer are easily laminated among the stacked nanosheets, the laminated structure is not limited by the space among the stacked nanosheets, the filling among the stacked nanosheets is uniform, the oxygen absorption effect is good, and the performance of the GAA-FET device is improved.
For the convenience of understanding, the stacked nanosheet GAA-FET device and the method for fabricating the same provided by the embodiments of the present application are described in detail below with reference to the accompanying drawings.
Referring to fig. 1, a schematic flow chart of a method for manufacturing a stacked nanosheet GAA-FET device provided in the embodiments of the present application may include the following steps.
S101, a stack layer in which a first semiconductor layer and a second semiconductor layer are alternately stacked is formed on a substrate.
In the embodiment of the present application, a substrate is provided, the substrate may be made of Si or SiGe, a bulk Si substrate may be used, and substrate doping is performed, specifically, a highly doped well region is formed in the bulk Si substrate by implanting, diffusing, and annealing, so as to reach a desired well depth. For the P-type FET, the high doped well region is an N well, and the implanted impurities are N-type impurity ions, such as phosphorus (P) ions; in the case of an N-type FET, the highly doped well region is a p-well, and the implanted impurity is a p-type impurity ion, such as a boron (B) ion.
In the embodiment of the present application, a stack layer in which the first semiconductor layer 101 and the second semiconductor layer 102 are alternately stacked may be formed on a substrate, and specifically, referring to fig. 2, for a structural schematic diagram of a GAA-FET device provided in the embodiment of the present application, silicon dioxide (SiO) on the surface of a bulk silicon substrate may be removed 2 ) And epitaxially growing a stack of alternately stacked first semiconductor layers 101 and second semiconductor layers 102 on the bulk silicon substrate 100.
The materials of the first semiconductor layer 101 and the second semiconductor layer 102 may be set according to actual requirements, the first semiconductor layer 101 may be a germanium-based film layer, the germanium-based film layer may include an epitaxial germanium layer, an epitaxial silicon-germanium layer, or a combination thereof, and the second semiconductor layer 102 may be an epitaxial silicon layer. For example, the first semiconductor layer/second semiconductor layer stack layer is SiGe/Si, and SiGe/Si periodic superlattice epitaxial growth is performed, and the epitaxial process may use reduced pressure epitaxy or molecular beam epitaxy.
And S102, etching the stacked layer to form a fin, and forming a dummy gate and a first side wall on the fin.
In this embodiment, the stacked layer may be etched to form a fin, and a dummy gate and a first sidewall may be formed on the fin, specifically, referring to fig. 3, a self-aligned Sidewall Image Transfer (SIT) process may be used to form a nanoscale first sidewall 104 device array, where the first sidewall 104 may be silicon nitride (SiN) X ) Or silicon oxide. The specific forming process comprises the following steps: covering the stack layer with a sacrificial layer 103, which may be polysilicon (PolySi, p-si) or amorphous silicon (a-si), etching away part of the sacrificial layer, depositing a first sidewall 104, which may be silicon nitride (SiN) x ) Etching the remaining sacrificial layer by anisotropic etching to leave only the plurality of periodic silicon nitride first sidewalls 104 on the stack, wherein the first sidewalls 104 can serve as a Hard Mask (Hard Mask) in photolithographyThe function of (1).
And making the epitaxially grown stacked layers into a plurality of periodically distributed fins by an etching process. And etching by taking the first side wall 104 as a mask to form the fin with the stacked layer structure. The upper part of the fin is a conductive channel region formed by the stacked layers, and the lower part of the fin is a substrate, so that the fin shown in fig. 4 is formed. The fin includes not only the stacked layer structure 101/102 but also the single crystal silicon structure 100 deep into the substrate. The etching process is dry etching or wet etching, such as Reactive Ion Etching (RIE). The fins will be used to form one or more horizontal nanoplates of n-type field effect transistors and/or p-type field effect transistors.
A Shallow Trench Isolation (STI) region 105 may be formed between two adjacent fins to separate transistors on adjacent fins, as shown in fig. 5. First, a dielectric insulating material is deposited, followed by planarization, for example, by a CMP process, and then a selective etching back of the dielectric insulating material is performed to expose the three-dimensional fin structure, so as to form the shallow trench isolation 105. The upper surface of the shallow trench isolation 105 is generally level with the interface between the stacked layer structure in the fin and the single crystal silicon of the substrate, and may be higher or lower than the interface level line. The shallow trench isolation 105 may be formed of a suitable dielectric material, such as silicon dioxide (SiO) 2 ) Silicon nitride (SiN) x ) And the like.
Referring to fig. 6, an overall structure diagram of the stacked nanosheet GAA-FET device is shown, wherein two directions are defined, and two dotted lines X-X and Y-Y are set, the X-X line is a central line of the fin along the fin line direction, and the Y-Y line is a central line of the fin perpendicular to the fin line direction, and the subsequent figures are cross-sectional diagrams of the X-X line and the Y-Y line.
Next, a dummy gate 106 and a third sidewall 107 may be formed on the fin, as shown in fig. 7, which is a cross-sectional view of fig. 6 in the Y-Y direction, and a dummy gate 106 may be formed on the exposed fin in a direction perpendicular to the fin line (i.e., the Y-Y direction), the dummy gate spanning the stacked layers on the upper portion of the fin, and fig. 8 is a cross-sectional view of fig. 6 in the X-X direction. The material used for the dummy gate 106 may be polysilicon (PolySi, p-si) or amorphous silicon (a-si).
On both sides of the dummy gate, along the fin lineTo (i.e., in the X-X direction) silicon nitride (SiN) x ) The thickness of the third sidewall 107 may be the same for both sides of the third sidewall 107, as shown in fig. 9.
And S103, etching partial areas at two ends of the first semiconductor layer from outside to inside, and forming second side walls at two ends of the first semiconductor layer.
In the embodiment of the present application, the dummy gate 106 and the third sidewall 107 may be used as masks, and the source and drain etching is performed on the fin through an etching process, as shown in fig. 10, only the stacked layers below the dummy gate 106 and the third sidewall 107 are reserved.
Then, partial regions at both ends of the first semiconductor layer 101 are etched from the outside to the inside, and second sidewalls 108 are formed at both ends of the first semiconductor layer 101. Specifically, as shown in fig. 11, a pull-back etching is performed to etch away a portion of the first semiconductor layer 101 from the outside to the center of the first semiconductor layer 101, so as to form a second sidewall 108 in the etched region of the first semiconductor layer 101.
Then, silicon nitride (SiN) is deposited on the periphery of the fin x ) Referring to fig. 12, the second sidewall 108 is etched until the second sidewall 108 is flush with the second semiconductor layer 102 in the vertical direction, that is, the second sidewalls 108 are formed at two ends of the first semiconductor layer 101, as shown in fig. 13.
And epitaxially forming a source/drain region and performing source/drain doping, as shown in fig. 14, wherein for PMOS, the source/drain region is boron (B) doped SiGe (SiGe: B), and for NMOS, the source/drain region is phosphorus (P) doped silicon (Si) (Si: P), and finally forming a source/drain region 110. And depositing an isolation layer 111 on the upper surfaces of the dummy gate 106 and the source and drain regions 110 to prevent interconnection short circuit between the dummy gate 106 and the source and drain regions 110 in the subsequent step, and performing chemical mechanical polishing on the isolation layer 111 to planarize the isolation layer 111.
Then, as shown in fig. 15, the dummy gate 106 formed of polysilicon (PolySi, p-si) or amorphous silicon (a-si) is etched or etched away by a selective etching or etching process, i.e., the dummy gate 106 is removed.
And S104, removing the first semiconductor layer release nanosheet channel, and taking the second semiconductor layer as a channel.
In the embodiment of the present application, the first semiconductor layer 101 may be removed to release the nanosheet channel, and the second semiconductor layer 102 is used as a channel, as shown in fig. 16. Specifically, the sacrificial layer in the stack layer, i.e., the first semiconductor layer 101, is selectively etched, and the second semiconductor layer 102 is released, i.e., nanosheet (nanosheet) channel release is performed. The nanoplates 202 may range in width from 1 to 100nm, in thickness from 1 to 30nm, and the spacing between each nanoplate 202 may range from 3 to 30nm.
And S105, forming an interface oxide layer, a first high-k dielectric layer, a second high-k dielectric layer, a third high-k dielectric layer and a metal gate which surround the channel in sequence.
In the embodiment of the present application, referring to fig. 17 to 21, an interface oxide layer 201, a first high-k dielectric layer 202, a second high-k dielectric layer 203, a third high-k dielectric layer 204 and a metal gate 205 may be sequentially formed to surround a channel, where the first high-k dielectric layer and/or the third high-k dielectric layer are Hf-based high-k materials. Wherein, the material of the interfacial oxide layer 201 may be SiO 2 Or SiON, etc., the interfacial oxide layer serves to improve the interfacial characteristics between the high-k dielectric layer and the channel.
Specifically, the material of the first high-k dielectric layer and/or the third high-k dielectric layer comprises at least one of the following materials: hfO 2 、HfSiO x 、HfON、HfSiON、HfAlO x 、HfLaO x The materials of the first high-k dielectric layer and the third high-k dielectric layer may be the same or different. The sum of the thicknesses of the first high-k dielectric layer, the second high-k dielectric layer and the third high-k dielectric layer is greater than or equal to 0.1nm and less than or equal to 5nm. And taking a laminated structure consisting of the first high-k dielectric layer, the second high-k dielectric layer and the third high-k dielectric layer as an oxygen absorption source to absorb oxygen in the interface oxidation layer, so that the interface oxidation layer of the GAA-FET device can be continuously reduced.
Referring to fig. 22, which is a schematic structural view in the Y-Y direction in fig. 6, it is easier to form a first high-k dielectric layer 202, a second high-k dielectric layer 203, and a third high-k dielectric layer 204 between stacked nanosheets, and the stacked nanosheets are not limited by space between the stacked nanosheets, so that the stacked nanosheets can be uniformly filled with oxygen, the oxygen absorption effect is good, and the performance of the GAA-FET device is improved.
The material of the second high-k dielectric layer 203 can be selected according to the type of the MOS transistor, so that the second high-k dielectric layer can be used as an oxygen absorption source to absorb oxygen in the interface oxide layer. In the PMOS region, the material of the second high-k dielectric layer comprises at least one of the following materials: alO (aluminum oxide) x 、MnO x 、ZrO x 、TiO x 、MoO x (ii) a In the NMOS region, the material of the second high-k dielectric layer comprises at least one of the following materials: laO x 、MgO x 、ScO x 、YO x 、NdO x 。
In a possible implementation manner, S105 may specifically be that an interface oxide layer, a first high-k dielectric layer, and a second high-k dielectric layer are sequentially formed to surround the channel, the second high-k dielectric layer is exposed and selectively etched in the first region, for example, the second high-k dielectric layer is selectively etched in a portion of the PMOS transistor without depositing the second high-k dielectric layer, then the second high-k dielectric layer surrounding the channel is formed again, the second high-k dielectric layer formed again is exposed and selectively etched in the second region, for example, the thickness of the second high-k dielectric layer needs to be controlled in a portion of the NMOS transistor, and then a third high-k dielectric layer and a metal gate surrounding the channel are formed.
The metal gate 114 may include a multi-layer structure of a capping layer TiN, a barrier layer TaN, a work function layer WFL, and a fill layer W, and a specific film structure thereof is not shown in fig. 21. Specifically, a covering layer TiN and a barrier layer TaN can be deposited to form TiN/TaN barrier-I, then PMOS WFL is deposited in an NMOS area and a PMOS area, the material of the PMOS WFL can be TiN or TiSiN, then the PMOS WFL is removed by selective corrosion of all the areas of the NMOS, the PMOS WFL in the PMOS area is reserved, then the barrier-I can be selectively corroded for part of the NMOS area according to actual requirements, the residual thickness of the TiN is controlled, then the PMOS WFL is selectively corroded for part of the PMOS area, the residual thickness of the PMOS WFL is controlled, then the NMOS WFL is deposited for the NMOS area and the PMOS area, and the material of the NMOS WFL can be TiAlC x And finally, performing TiN/TaN barrier-II and filling layer W conductive filling metal deposition to form a high-k metal gate structure, and performing CMP planarization.
Then ILD dielectric deposition is carried out on the top, referring to FIG. 23, a dielectric CMP layer 116 is formed, contact hole photoetching and etching are carried out on the dielectric CMP layer 116, hole silicide 117 is deposited, a contact electrode is led out, and then the multilayer back-end interconnection and passivation protection process is completed, so that the preparation of the GAA-FET device is completed.
The embodiment of the application provides a method for manufacturing a stacked nanosheet GAA-FET device, wherein stacked layers formed by alternately stacking a first semiconductor layer and a second semiconductor layer are formed on a substrate; etching the stacked layer to form a fin, and forming a dummy gate and a first side wall on the fin; etching partial areas at two ends of the first semiconductor layer from outside to inside, and forming second side walls at two ends of the first semiconductor layer; removing the first semiconductor layer release nanosheet channel, wherein the second semiconductor layer serves as a channel; and forming an interface oxide layer, a first high-k dielectric layer, a second high-k dielectric layer, a third high-k dielectric layer and a metal gate which surround the channel in sequence, wherein the first high-k dielectric layer and/or the third high-k dielectric layer are made of Hf-based high-k materials. Therefore, the laminated structure formed by the first high-k dielectric layer, the second high-k dielectric layer and the third high-k dielectric layer is used as an oxygen absorption source to absorb oxygen in the interface oxidation layer, so that the interface oxidation layer of the GAA-FET device can be continuously reduced, the first high-k dielectric layer, the second high-k dielectric layer and the third high-k dielectric layer are easily laminated among the stacked nanosheets, the laminated structure is not limited by the space among the stacked nanosheets, the stacked nanosheets can be uniformly filled, the oxygen absorption effect is good, and the performance of the GAA-FET device is improved.
Based on the above method for manufacturing a stacked nanosheet GAA-FET device, an embodiment of the present application further provides a stacked nanosheet GAA-FET device, as shown in fig. 23, including:
a substrate 100, a fin on one side of the substrate; the fin includes a plurality of second semiconductor layers 102 that act as channels;
and the high-k metal gate structure surrounds the channel and comprises an interface oxide layer 201, a first high-k dielectric layer 202, a second high-k dielectric layer 203, a third high-k dielectric layer 204 and a metal gate 205.
In particular toIn the PMOS region, the material of the second high-k dielectric layer comprises at least one of the following materials: alO (aluminum oxide) x 、MnO x 、ZrO x 、TiO x 、MoO x ；
In the NMOS region, the material of the second high-k dielectric layer comprises at least one of the following materials: laO x 、MgO x 、ScO x 、YO x 、NdO x 。
Specifically, the material of the first high-k dielectric layer and/or the third high-k dielectric layer comprises at least one of the following materials: hfO 2 、HfSiO x 、HfON、HfSiON、HfAlO x 、HfLaO x 。
Specifically, the sum of the thicknesses of the first high-k dielectric layer, the second high-k dielectric layer and the third high-k dielectric layer is greater than or equal to 0.1nm and less than or equal to 5nm.
In the embodiment of the application, the laminated structure formed by the first high-k dielectric layer, the second high-k dielectric layer and the third high-k dielectric layer is used as an oxygen absorption source to absorb oxygen in the interface oxide layer, so that the interface oxide layer of the GAA-FET device can be continuously reduced, the first high-k dielectric layer, the second high-k dielectric layer and the third high-k dielectric layer are easily laminated among the stacked nanosheets, the space limitation among the stacked nanosheets is avoided, the filling among the stacked nanosheets is uniform, the oxygen absorption effect is good, and the performance of the GAA-FET device is improved.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the apparatus embodiment, since it is substantially similar to the method embodiment, it is relatively simple to describe, and reference may be made to some descriptions of the method embodiment for relevant points.
The foregoing is merely a preferred embodiment of the present application and, although the present application has been described with reference to the preferred embodiments, it is not intended to limit the present application. Those skilled in the art can make numerous possible variations and modifications to the disclosed solution, or modify it to equivalent embodiments, using the methods and techniques disclosed above, without departing from the scope of the claimed solution. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application still fall within the protection scope of the technical solution of the present application without departing from the content of the technical solution of the present application.
Claims (10)
1. A method for manufacturing a stacked nanosheet GAA-FET device, comprising:
forming a stacked layer in which a first semiconductor layer and a second semiconductor layer are alternately stacked on a substrate;
etching the stacked layer to form a fin, and forming a dummy gate and a first side wall on the fin;
etching partial areas at two ends of the first semiconductor layer from outside to inside, and forming second side walls at two ends of the first semiconductor layer;
removing the first semiconductor layer release nanosheet channel, wherein the second semiconductor layer serves as a channel;
forming an interface oxide layer, a first high-k dielectric layer, a second high-k dielectric layer, a third high-k dielectric layer and a metal gate which surround the channel in sequence; the first high-k dielectric layer and/or the third high-k dielectric layer are made of Hf-based high-k materials.
2. The method of claim 1, wherein the sequentially forming an interface oxide layer, a first high-k dielectric layer, a second high-k dielectric layer, a third high-k dielectric layer, and a metal gate surrounding the channel comprises:
sequentially forming an interface oxidation layer, a first high-k dielectric layer and a second high-k dielectric layer which surround the channel;
exposing the first area and selectively corroding the second high-k dielectric layer;
forming a second high-k dielectric layer surrounding the channel again;
exposing the second area and selectively corroding the second high-k dielectric layer formed again;
and forming a third high-k dielectric layer and a metal gate which surround the channel.
3. The method of claim 1, wherein in the PMOS region, the material of the second high-k dielectric layer comprises at least one of the following materials: alO (aluminum oxide) x 、MnO x 、ZrO x 、TiO x 、MoO x ；
In the NMOS region, the material of the second high-k dielectric layer comprises at least one of the following materials: laO (LaO) x 、MgO x 、ScO x 、YO x 、NdO x 。
4. The method of claim 1, wherein a material of the first high-k dielectric layer and/or the third high-k dielectric layer comprises at least one of: hfO 2 、HfSiO x 、HfON、HfSiON、HfAlO x 、HfLaO x 。
5. The method of one of claims 1-4, wherein a sum of thicknesses of the first high-k dielectric layer, the second high-k dielectric layer, and the third high-k dielectric layer is greater than or equal to 0.1nm and less than or equal to 5nm.
6. A method according to any one of claims 1 to 4, wherein said substrate is made of Si or SiGe.
7. A stacked nanosheet GAA-FET device, comprising:
a substrate, a fin located on one side of the substrate; the fin includes a plurality of second semiconductor layers, the second semiconductor layers acting as channels;
and the high-k metal gate structure surrounds the channel and comprises an interface oxide layer, a first high-k dielectric layer, a second high-k dielectric layer, a third high-k dielectric layer and a metal gate.
8. Stacked nanoplatelet GAA-FETs according to claim 7The device is characterized in that in the PMOS region, the material of the second high-k dielectric layer comprises at least one of the following materials: alO (aluminum oxide) x 、MnO x 、ZrO x 、TiO x 、MoO x ；
In the NMOS region, the material of the second high-k dielectric layer comprises at least one of the following materials: laO x 、MgO x 、ScO x 、YO x 、NdO x 。
9. The stacked nanoplate GAA-FET device of claim 7, wherein the material of the first and/or third high-k dielectric layers comprises at least one of: hfO 2 、HfSiO x 、HfON、HfSiON、HfAlO x 、HfLaO x 。
10. Stacked nanosheet GAA-FET device of any one of claims 7 to 9, wherein the sum of the thicknesses of the first, second and third high-k dielectric layers is greater than or equal to 0.1nm and less than or equal to 5nm.
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