CN115799233A - Light-emitting chip array structure, preparation method and display structure - Google Patents
Light-emitting chip array structure, preparation method and display structure Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title abstract description 5
- 230000000903 blocking effect Effects 0.000 claims abstract description 113
- 239000004065 semiconductor Substances 0.000 claims abstract description 108
- 239000000758 substrate Substances 0.000 claims description 47
- 238000000034 method Methods 0.000 claims description 25
- 238000004519 manufacturing process Methods 0.000 claims description 16
- 239000010410 layer Substances 0.000 description 295
- 230000003287 optical effect Effects 0.000 description 16
- 239000011241 protective layer Substances 0.000 description 16
- 238000009792 diffusion process Methods 0.000 description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 238000010521 absorption reaction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 229910052738 indium Inorganic materials 0.000 description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 239000000428 dust Substances 0.000 description 2
- 238000005566 electron beam evaporation Methods 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- -1 moisture Substances 0.000 description 2
- 238000001579 optical reflectometry Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- 230000007480 spreading Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 230000001902 propagating effect Effects 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000002207 thermal evaporation Methods 0.000 description 1
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Abstract
The application discloses a light-emitting chip array structure, a preparation method and a display structure, and relates to the technical field of display. The light emitting chip array structure comprises a plurality of light emitting chips and a light blocking layer. The light emitting chip comprises a first semiconductor layer, an active layer and a second semiconductor layer which are sequentially stacked. The light blocking layer surrounds the circumferential edge of the light emitting chip to absorb and/or reflect light emitted by the active layer. The light emitting chip array structure provided by the application can improve the phenomenon of light crosstalk formed between adjacent light emitting chips, so that the screen image is clearer.
Description
Technical Field
The present application relates to the field of display technologies, and in particular, to a light emitting chip array structure, a manufacturing method thereof, and a display structure.
Background
The Micro-LED (Micro light emitting diode) technology, i.e. LED Micro-scaling and matrixing technology, refers to a high-density and Micro-sized LED array integrated on a chip, for example, each pixel of an LED display screen can be addressed and independently driven to light, and can be regarded as a Micro-scaled version of the LED display screen, and the distance between pixels is reduced from millimeter level to micron level.
However, micro-led shows that there is a light crosstalk phenomenon, which causes a screen image to be blurred. And the optical crosstalk phenomenon becomes more serious along with the reduction of the size of the Micro-LED chip and the distance between adjacent Micro-LED chips on the display panel, and the development of the Micro-LED technology is restricted.
Disclosure of Invention
The present application provides: a light emitting chip array structure comprising:
the light-emitting device comprises a plurality of light-emitting chips, a plurality of light-emitting chips and a plurality of light-emitting chips, wherein the light-emitting chips comprise a first semiconductor layer, an active layer and a second semiconductor layer which are sequentially stacked;
and the light blocking layer surrounds the circumferential edge of the light emitting chip to absorb and/or reflect light emitted by the active layer.
In one possible embodiment, the height of the light blocking layer is greater than or equal to the height of the active layer.
In a possible embodiment, the light emitting chip array structure further includes a protection layer covering the light emitting chips, and an absolute value of a height difference between a height of the light blocking layer and a height of the protection layer is less than or equal to a set threshold 。
In a possible embodiment, the plurality of light emitting chips are respectively disposed at intervals, and the light blocking layer is disposed around a circumferential edge of each of the light emitting chips.
In a possible implementation manner, the light emitting chip array structure further includes a substrate, the light emitting chip is disposed on the substrate, and the light blocking layer is disposed on the substrate and spaced apart from the light emitting chip.
In a possible embodiment, the light blocking layer surrounds a circumferential edge of the first semiconductor layer and is in contact with the first semiconductor layer.
In one possible embodiment, for a plurality of light emitting chips, the first semiconductor layer is continuously disposed, and the active layer and the second semiconductor layer are respectively disposed at intervals;
the light blocking layer is arranged on one surface, close to the active layers, of the first semiconductor layer and located between the adjacent active layers, and the light blocking layer and the active layers are arranged at intervals.
In one possible embodiment, the light-blocking layer is a diamond-like film.
The present application further provides: a method for preparing a light emitting chip array structure comprises the following steps:
arranging a plurality of light-emitting chips on a substrate, wherein each light-emitting chip comprises a first semiconductor layer, an active layer and a second semiconductor layer which are sequentially stacked;
the plurality of light-emitting chips are arranged at intervals respectively, and the light-blocking layer is arranged at the circumferential edge of each light-emitting chip so as to enable the light-blocking layer to absorb and/or reflect light emitted by the active layer.
In one possible embodiment, the plurality of light emitting chips are respectively disposed at intervals, and the light blocking layer is disposed at a circumferential edge of the light emitting chip, and includes:
and arranging a light-blocking layer on the substrate, wherein the light-blocking layer and the light-emitting chip are arranged at intervals.
In one possible embodiment, the plurality of light emitting chips are respectively disposed at intervals, and the light blocking layer is disposed at a circumferential edge of the light emitting chips, including:
and arranging the light-blocking layer, wherein the light-blocking layer surrounds the circumferential edge of the first semiconductor layer and is in contact with the first semiconductor layer.
In a possible embodiment, after the disposing the light blocking layer, the method further includes:
and stripping the substrate.
In one possible embodiment, for a plurality of light emitting chips, the first semiconductor layer is continuously disposed, and the active layer and the second semiconductor layer are respectively disposed at intervals;
set up the light blocking layer at the circumference border department of emitting chip, include:
and arranging a light blocking layer on the first semiconductor layer, wherein the light blocking layer is positioned between the adjacent active layers and is arranged at intervals with the active layers.
In one possible embodiment, after disposing the light blocking layer on the first semiconductor layer, the method further includes:
and stripping the substrate.
The present application further provides: a display structure, comprising the light emitting chip array structure provided in any of the above embodiments, or the light emitting chip array structure manufactured by the method for manufacturing the light emitting chip array structure provided in any of the above embodiments.
The application provides a light-emitting chip array structure, a light-emitting chip array structure preparation method and a display structure. The light blocking layer of the light emitting chip array structure is arranged on the circumferential edge of the light emitting chip in a surrounding mode, and when the light emitting chip is conducted, the light blocking layer can block light emitted by the light emitting chip from being possibly diffused to other light emitting chips in the light emitted by the light emitting chip in an absorbing and/or reflecting mode, so that the phenomenon of optical crosstalk formed between adjacent light emitting chips is improved, and further screen images are clearer.
Drawings
To more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.
Fig. 1 is a schematic cross-sectional manufacturing process diagram of a viewing angle when a first light-blocking layer is disposed in a light-emitting chip array structure according to an embodiment of the present invention;
fig. 2 is a schematic view illustrating a manufacturing process of another viewing angle when a first light-blocking layer is disposed in a light-emitting chip array structure according to an embodiment of the present invention;
fig. 3 is a schematic cross-sectional manufacturing flow diagram of a viewing angle when a second light-blocking layer is disposed in a light-emitting chip array structure according to an embodiment of the present invention;
fig. 4 is a schematic view illustrating a manufacturing process of another viewing angle when a second light-blocking layer is disposed on a light-emitting chip array structure according to an embodiment of the present invention;
fig. 5 is a schematic cross-sectional manufacturing flow diagram of a viewing angle when a third light-blocking layer is disposed in a light-emitting chip array structure according to an embodiment of the present invention;
fig. 6 is a schematic view illustrating a manufacturing process of another viewing angle when a third light-blocking layer is disposed in the light-emitting chip array structure according to an embodiment of the present invention.
Description of the main element symbols:
100-a substrate; 110-an intrinsic semiconductor layer; 200-a light emitting chip; 210-a first semiconductor layer; 220-an active layer; 230-a second semiconductor layer; 300-a light blocking layer; 400-a protective layer; 410-opening a hole; 500-a first electrode; 510-a second electrode; 600-a bonding layer; 700-current spreading layer.
Detailed Description
Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.
In the description of the present application, it is to be understood that the terms "central," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and to simplify the description, but are not intended to indicate or imply that the device or element so referred to must have a particular orientation, be constructed and operated in a particular orientation, and are not to be construed as limiting the present application.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In this application, unless expressly stated or limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly and encompass, for example, both fixed and removable connections or integral parts thereof; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In this application, unless expressly stated or limited otherwise, a first feature is "on" or "under" a second feature such that the first and second features are in direct contact, or the first and second features are in indirect contact via an intermediary. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
The inventor of the present application finds that the proportion of the side light emitted by the Micro-LED chip becomes larger along with the reduction of the chip size, and particularly, when the size of the Micro-LED chip is reduced to 10um × 10um or less, the side light emitted by the adjacent Micro-LED chips on the display panel interferes with each other, thereby forming a light crosstalk phenomenon, and the screen image becomes blurred.
Fig. 1, 3 and 5 respectively show a light emitting chip array structure provided by the present embodiment, which includes a plurality of light emitting chips 200 and a light blocking layer 300. The light emitting chip 200 includes a first semiconductor layer 210, an active layer 220, and a second semiconductor layer 230, which are sequentially stacked. The light blocking layer 300 surrounds the circumferential edge of the light emitting chip 200 to absorb and/or reflect light emitted from the active layer 220.
The light emitting chip array structure means that a plurality of light emitting chips 200 are arranged on the same plane at intervals, the plurality of light emitting chips 200 can be distributed in an array or other arrangement mode, and the plurality of light emitting chips 200 can be connected with each other or arranged independently.
The light blocking layer 300 of the light emitting chip array structure provided by the embodiment of the application is arranged around the circumferential edge of the light emitting chip 200, and when the light emitting chip 200 is conducted, the light blocking layer can block light which is possibly scattered to other light emitting chips 200 in the light emitted by the light emitting chip 200 in an absorption and/or reflection mode, so that the phenomenon of optical crosstalk formed between adjacent light emitting chips 200 is improved, and further, a screen image is clearer.
In the above embodiment, optionally, the light emitting chip 200 may be a Micro-led chip or a Mini-led chip; the first semiconductor layer 210 may be an N-type semiconductor layer, such as an N-GaN layer; the active layer 220 may be a multiple quantum well light emitting layer; the second semiconductor layer 230 may be a P-type semiconductor layer, for example, a P-GaN layer.
As shown in fig. 1, in the above embodiment, alternatively, the first electrode 500 may be disposed on the first semiconductor layer 210 by an e-beam evaporation method, and the second electrode 510 may be disposed on the second semiconductor layer 230 by an e-beam evaporation method. The light emitting chip 200 realizes that the first electrode 500 and the second electrode 510 are respectively electrically connected with an external driving chip in a flip-chip manner, so that the light emitting chip 200 is turned on and emits light. The first electrode 500 and/or the second electrode 510 may be made of Ti/Al/Ti/Au/Ni/Fe/Pt/Pd, respectively. In this embodiment, the first electrode 500 may be provided on the first semiconductor layer 210 and the second electrode 510 may be provided on the second semiconductor layer 230 at the same time by primary electron beam evaporation.
Further, a current diffusion layer 700 may be disposed on the second semiconductor layer 230, and then the second electrode 510 may be disposed on the current diffusion layer 700, where the area of the current diffusion layer 700 is larger than that of the second electrode 510, so that the current flowing through the second electrode 510 can be sufficiently and uniformly diffused to the second semiconductor layer 230 at each position through the current diffusion layer 700, thereby improving the performance of the light emitting chip 200. Specifically, the current diffusion layer 700 may be deposited on the second semiconductor layer 230 by magnetron sputtering, and then the second electrode 510 is deposited on the current diffusion layer 700, and after the deposition is completed, the current diffusion layer 700 and the surface of the second semiconductor layer 230 form an ohmic contact by using a Rapid Thermal Annealing (RTA) method. The current spreading layer 700 may be made of Indium Tin Oxide (ITO)/NI/AU conductive material.
Further, the light emitting chip array structure further includes a protective layer 400, and the protective layer 400 covers the light emitting chips 200.
In some embodiments, the protective layer 400 may be covered on the light emitting chip 200 by a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, so that the internal structure of the light emitting chip 200 is protected by the protective layer 400 and oxygen, moisture, dust, etc. are prevented from affecting the performance of the light emitting chip 200. In other embodiments, the protective layer 400 may also be coated on the light emitting chip 200, so that the protective layer 400 protects the internal structure of the light emitting chip 200 and prevents oxygen, moisture, dust, etc. from affecting the performance of the light emitting chip 200. The protection layer 400 may be an insulating photoresist, such as PFA photoresist.
In the embodiments of the present application, at least two arrangements of the height of the light blocking layer 300 are provided.
In some embodiments, as shown in fig. 5, in the light emitting chip array structure provided by the present embodiment, the height of the light blocking layer 300 is greater than or equal to the height of the active layer 220. Here, a horizontal plane on which the light emitting side of the light emitting chip array structure is located is taken as a reference plane, a distance between a side of the light blocking layer 300 away from the reference plane and the reference plane is taken as a height of the light blocking layer 300, and a distance between a side of the active layer 220 away from the reference plane and the reference plane is taken as a height of the active layer 220.
In this way, when the height of the light blocking layer 300 is greater than or equal to the height of the active layer 220, the light blocking layer 300 can block light emitted from the active layer 220, and particularly can block light parallel to the active layer 220, thereby improving the problem of optical crosstalk formed between adjacent light emitting chips 200.
In other embodiments, as shown in fig. 1 and 3, the absolute value of the height difference between the height of the light-blocking layer 300 and the height of the protection layer 400 is less than or equal to a predetermined valueThreshold value 。 Here, a horizontal plane on which the light emitting side of the light emitting chip array structure is located is taken as a reference plane, a distance between a side of the light blocking layer 300 away from the reference plane and the reference plane is taken as a height of the light blocking layer 300, and a distance between a side of the protection layer 400 away from the reference plane and the reference plane is taken as a height of the protection layer 400. Since the protective layer 400 covers the light emitting chip 200, the height of the protective layer 400 is greater than the height of the active layer 220 in the light emitting chip 200. Wherein, the set threshold value can be set according to the product requirement. Wherein, siO can be used for the protection layer 400 2 、SiN 4 。
In this way, by setting the absolute value of the height difference between the height of the light blocking layer 300 and the height of the protection layer 400 to be less than or equal to the set threshold, after the light emitting chip 200 is bonded to the driving chip, the light blocking layer 300 can be closer to the driving chip, so that the width of the gap between the light blocking layer 300 and the driving chip is reduced, light passing through the gap is reduced, and the phenomenon of optical crosstalk caused by light leakage is improved.
In the above embodiment, optionally, the opening 410 communicating with the first electrode 500 or communicating with the second electrode 510 may be respectively opened on the protection layer 400 by a dry etching method of ICP or RIE, and the bonding layer 600 may be respectively filled in the opening 410 by thermal evaporation or electron beam evaporation, so that when the light emitting chip 200 is bonded to the driving chip, the first electrode 500 and the second electrode 510 may be respectively conducted with the pad of the driving chip by the bonding layer 600. The bonding layer can adopt metal with a lower melting point, such as indium, and the indium metal is heated through reflow soldering, so that the indium metal is melted to be spherical, and the bonding layer is convenient to be soldered and bonded with the bonding pad of the driving chip.
In some embodiments, as shown in fig. 1 and 3, the present application provides a first and second arrangement of light blocking layer 300, respectively. The plurality of light emitting chips 200 are respectively disposed at intervals, and the light blocking layer 300 is disposed around a circumferential edge of each light emitting chip 200.
Specifically, since the plurality of light emitting chips 200 are respectively disposed at intervals, the plurality of light emitting chips 200 are independently disposed from each other without affecting each other, and thus the plurality of independent light emitting chips 200 can be respectively bonded to the driving chip in a mass transfer manner. Meanwhile, the light blocking layer 300 is arranged around the circumferential edge of each light emitting chip 200, so that light emitted from the active layer 220 can be blocked by the light blocking layer 300, thereby improving the phenomenon of optical crosstalk formed between adjacent light emitting chips 200 and further making the screen image clearer.
As shown in fig. 2 and 4, the active layer 220 and the second semiconductor layer 230 may be concave, and the first electrode 500 may be respectively located at inner sides of the concave active layer 220 and the concave second semiconductor layer 230, so that the light emitting chip 200 has a more compact structure, the space utilization rate is increased, the effective light emitting area of the light emitting chip 200 is increased, and the brightness of the light emitting chip 200 is increased.
As shown in fig. 1 and 2, the present embodiment provides a first arrangement of the light blocking layer 300. The light emitting chip array structure further includes a substrate 100, the light emitting chips 200 are disposed on the substrate 100, and the light blocking layer 300 is disposed on the substrate 100 and spaced apart from the light emitting chips 200. Among them, the substrate 100 may function to fix the relative positions of the light blocking layer 300 and the light emitting chip 200.
In this way, by disposing the light blocking layer 300 on the substrate 100, the light blocking layer 300 can block light emitted by the active layer 220 and lateral light emitted by the active layer 220 and propagating through the first semiconductor layer 210, the second semiconductor layer 230 and other layers by absorption or reflection, so as to improve the problem of optical crosstalk formed between the adjacent light emitting chips 200. Moreover, for the light-blocking layer 300 made of a conductive material, the light-blocking layer 300 and the light-emitting chip 200 are arranged at intervals, and the conductive light-blocking layer 300 is not in contact with at least two layers of materials of the light-emitting chip 200 at the same time, so that the problem of short circuit is avoided.
As shown in fig. 3 and 4, in the above embodiment, optionally, the present embodiment provides a second arrangement manner of the light blocking layer 300. The light blocking layer 300 surrounds the circumferential edge of the first semiconductor layer 210 and is in contact with the first semiconductor layer 210.
Specifically, the light blocking layer 300 surrounds the circumferential edge of the first semiconductor layer 210 and is in contact with the first semiconductor layer 210, so that the light blocking layer 300 and the light emitting chips 200 are not fixed through the substrate 100, and the substrate 100 can be peeled off, thereby preventing light from being transmitted between the adjacent light emitting chips 200 through the substrate 100, and further improving the optical crosstalk phenomenon.
In implementation, the light blocking layer 300 may be disposed separately from the active layer 220, the second semiconductor layer 230, and the second electrode 510, so as to prevent the light blocking layer 300 from contacting at least two layers of the light emitting chip 200, thereby preventing a short circuit from occurring.
As shown in fig. 3 and 4, when the light blocking layer 300 is disposed in the second manner, the protective layer 400 may be filled in the gaps between the light blocking layer 300 and the active layer 220, between the second semiconductor layer 230 and between the second electrode 510, so as to further improve the insulation property, avoid the short circuit phenomenon caused by excessive current, and further improve the stability of the light emitting chip 200.
In some embodiments, as shown in fig. 5 and 6, the present embodiment provides a third arrangement of the light blocking layer 300. For the plurality of light emitting chips 200, the first semiconductor layer 210 is continuously disposed, and the active layer 220 and the second semiconductor layer 230 are respectively disposed at intervals. The light blocking layer 300 is disposed on a surface of the first semiconductor layer 210 close to the active layers 220 and between adjacent active layers 220, and the light blocking layer 300 and the active layers 220 are disposed at an interval.
Specifically, since the first semiconductor layers 210 of the plurality of light emitting chips 200 are continuously disposed, the plurality of light emitting chips 200 can share one first semiconductor layer 210. The active layers 220 and the second semiconductor layers 230 of the light emitting chips 200 are respectively arranged at intervals, so that the active layers 220 and the second semiconductor layers 230 corresponding to each other in position can jointly constitute the light emitting chips 200 with the first semiconductor layers 210, and light emitting regions are formed in regions where the active layers 220 and the second semiconductor layers 230 are located, which is beneficial to improving the density of pixels and the brightness of the unit area of the light emitting regions. Meanwhile, the light blocking layer 300 is disposed on a surface of the first semiconductor layer 210 close to the active layers 220 and between adjacent active layers 220, so that the light blocking layer 300 in a square or grid shape can isolate and block light generated by adjacent light emitting chips 200, thereby improving the problem of optical crosstalk. In addition, the light blocking layer 300 is spaced apart from the active layer 220, so that the light blocking layer 300 is not simultaneously connected to at least two of the first semiconductor layer 210, the active layer 220, and the second semiconductor layer 230, thereby preventing a short circuit.
As shown in fig. 5, in the above embodiment, optionally, since the plurality of light emitting chips 200 can be fixed by the first semiconductor layer 210, the substrate 100 can be peeled off, so as to prevent light from being transmitted between the plurality of light emitting chips 200 through the substrate 100, thereby improving the optical crosstalk.
As shown in fig. 6, in the above embodiment, optionally, the first electrode 500 disposed on the first semiconductor layer 210 may be disposed around the plurality of light emitting chips 200, so that the plurality of light emitting chips 200 share one first electrode 500, thereby reducing an area occupied by the first electrode 500 and increasing a density of pixels and an area of a light emitting region. When the light emitting chips 200 are used, the corresponding light emitting chips 200 can be controlled to be turned on only by controlling the potentials of the second electrodes 510.
As shown in fig. 5 and 6, when the light blocking layer 300 adopts the third arrangement, the protective layer 400 may be filled in the gap between the light blocking layer 300 and the active layer 220 and the second semiconductor layer 230, thereby further improving the insulation property and the stability of the light emitting chip 200.
In the above embodiment, the light-blocking layer 300 is optionally a diamond-like film or a metal material with a certain light reflectivity.
Specifically, when the light blocking layer 300 is a diamond-like carbon film, the diamond-like carbon film (DLC) has advantages of high hardness, low friction coefficient, excellent film compactness, good chemical stability, and good optical properties. The diamond-like film can be deposited by a chemical vapor deposition method, and parameters such as power, gas pressure, chemical gas, flow, size and the like during the growth of the diamond-like film can be changed, so that the absorptivity of the diamond-like film to light is changed, and the optical crosstalk phenomenon is further adjusted. In addition, the light blocking layer 300 may also be a metal material with a certain light reflectivity, such as a metal material with a high reflectivity, such as gold, silver, copper, aluminum, molybdenum, etc.
In some embodiments, as shown in fig. 1, 3 and 5, another embodiment of the present application provides a method for preparing a light emitting chip array structure, including:
providing a plurality of light emitting chips 200 on a substrate 100, the light emitting chips 200 including a first semiconductor layer 210, an active layer 220, and a second semiconductor layer 230, which are sequentially stacked;
specifically, a plurality of light emitting chips 200 may be formed in a self-prepared manner by sequentially disposing the first semiconductor layer 210, the active layer 220, and the second semiconductor layer 230 on the substrate 100, thereby obtaining a light emitting chip array structure. The light emitting chip array structure may also be obtained by purchasing an epitaxial wafer including the substrate 100 and the light emitting chips 200, which has been prepared in advance. The intrinsic semiconductor layer 110 may be disposed on the substrate 100, and the first semiconductor layer 210 may be disposed on the intrinsic semiconductor layer 110, so that the intrinsic semiconductor layer 110 is a pure semiconductor completely free of impurities and lattice defects, thereby ensuring the fabrication quality of the light emitting chip 200.
The plurality of light emitting chips 200 are respectively disposed at intervals, and the light blocking layer 300 is disposed at a circumferential edge of the light emitting chips 200, so that the light blocking layer 300 absorbs and/or reflects light emitted from the active layer 220.
Specifically, the plurality of light emitting chips 200 may be respectively disposed at intervals, so that a gap with a certain width is formed between the plurality of light emitting chips 200, and then the light blocking layer 300 may be disposed on the substrate 100 or on the first semiconductor layer 210 at a circumferential edge of the light emitting chips 200 (i.e., in the gap), so that the light blocking layer 300 may surround the light emitting chips 200, and light emitted by the light emitting chips 200 may be blocked by the light blocking layer 300 in an absorption or reflection manner, thereby improving a phenomenon of optical crosstalk formed between adjacent light emitting chips 200, and further making a screen image clearer. Specifically, the epitaxial wafer may be etched by dry etching, wet etching, or dry-wet hybrid etching, so as to form a plurality of light emitting chips 200 spaced apart from each other. Wherein the dry etching can adopt ICP method and Cl 2 ，BCl 3 And gases such as Ar; the wet etching may use hydrofluoric acid (HF), buffered Oxide Etch (BOE, made by mixing hydrofluoric acid (49%) with water or ammonium fluoride with water).
In some embodiments, as shown in fig. 1 and 2, the present embodiment proposes a first arrangement of the light blocking layer 300. The plurality of light emitting chips 200 are respectively disposed at intervals, and the light blocking layer 300 is disposed at a circumferential edge of the light emitting chips 200, and includes:
the light blocking layer 300 is disposed on the substrate 100, and the light blocking layer 300 is disposed apart from the light emitting chip 200.
Specifically, the light blocking layer 300 may be deposited on the substrate 100 by chemical vapor deposition, and the light blocking layer 300 and the light emitting chip 200 are disposed at an interval by etching, so that the light blocking layer 300 is not connected to at least two layers of the light emitting chip 200 at the same time, and thus, for a scheme in which the light blocking layer 300 is made of a conductive material, the problem of short circuit between the conductive light blocking layer 300 and the light emitting chip 200 can be avoided.
In some embodiments, as shown in fig. 3 and 4, the present embodiment proposes a second arrangement of the light-blocking layer 300. The plurality of light emitting chips 200 are respectively disposed at intervals, and the light blocking layer 300 is disposed at a circumferential edge of the light emitting chips 200, and includes:
the light blocking layer 300 is disposed, and the light blocking layer 300 surrounds the circumferential edge of the first semiconductor layer 210 and is in contact with the first semiconductor layer 210.
Specifically, the light blocking layer 300 in contact with the first semiconductor layer 210 may be disposed on the substrate 100 by chemical vapor deposition, and at this time, the light blocking layer 300 does not simultaneously contact with the active layer 220 and the second semiconductor layer 230, so that the problem of short circuit can be avoided.
As shown in fig. 3, in the above embodiment, optionally, after the light blocking layer 300 is disposed, the method further includes:
the substrate 100 is peeled off.
Specifically, since the light blocking layer 300 is in direct contact with the first semiconductor layer 210, the light emitting chips 200 do not need to fix the relative position between the light blocking layer 300 and the first semiconductor layer 210 through the substrate 100, and therefore the substrate 100 can be peeled off, thereby preventing light from being transmitted between adjacent light emitting chips 200 through the substrate 100, and further improving the optical crosstalk phenomenon.
Further, when the intrinsic semiconductor layer 110 is disposed between the substrate 100 and the first semiconductor layer 210, the intrinsic semiconductor layer 110 may be removed after the substrate 100 is stripped.
As shown in fig. 1 and 3, in the above embodiment, optionally, when the light-blocking layer 300 adopts the first arrangement manner and the second arrangement manner, before the light-blocking layer 300 is arranged on the substrate 100, the protective layer 400 may be arranged on the light-emitting chip 200 by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, then the light-emitting chip 200 and the edge of the protective layer 400 are etched by an ICP method to expose the substrate 100, and finally the light-blocking layer 300 is arranged on the exposed substrate 100. The gas used in the ICP method may be Cl 2 ，BCl 3 And Ar. It should be noted that, the sequence of the above two steps of setting and etching is not limited, for example, the circumferential edge of the light emitting chip 200 may be etched first, and then the protective layer 400 is provided; the protective layer 400 may be disposed first, and then the circumferential edges of the protective layer 400 and the light emitting chip 200 may be etched, although the structures obtained by the two methods are different, the same or similar effects may be achieved.
In some embodiments, as shown in fig. 5 and 6, the present embodiment proposes a third arrangement of the light blocking layer 300. For the plurality of light emitting chips 200, the first semiconductor layer 210 is continuously disposed, and the active layer 220 and the second semiconductor layer 230 are respectively disposed at intervals;
the light blocking layer 300 is disposed at a circumferential edge of the light emitting chip 200, and includes:
the light blocking layer 300 is disposed on the first semiconductor layer 210, and the light blocking layer 300 is disposed between the adjacent active layers 220 and spaced apart from the active layers 220.
Specifically, the light blocking layer 300 may be disposed on the first semiconductor layer 210 by chemical vapor deposition, and the light blocking layer 300 is located between the adjacent active layers 220, so that the light blocking layer 300 in a shape of a square or a grid can surround the light emitting chip 200, thereby blocking light emitted by the active layers 220 and improving a crosstalk phenomenon between the adjacent light emitting chips 200. Moreover, for the light blocking layer 300 made of a conductive material, the light blocking layer 300 and the active layer 220 are arranged at intervals, and the light blocking layer 300 does not contact with at least two layers of materials of the light emitting chip 200 at the same time, so that the problem of short circuit can be avoided.
As shown in fig. 5 and 6, in the above embodiment, optionally, when the light-blocking layer 300 adopts the third setting manner, before the step of setting the light-blocking layer 300 on the first semiconductor layer 210, the active layer 220 and the second semiconductor layer 230 may be etched by Mesa in cooperation with ICP, so that the active layer 220 and the second semiconductor layer 230 of the plurality of light-emitting chips 200 are set at an interval while the first semiconductor layer 210 is exposed, and the light-blocking layer 300 is conveniently set on the first semiconductor layer 210.
As shown in fig. 5, in the above embodiment, optionally, after the light blocking layer 300 is disposed on the first semiconductor layer 210, the method further includes:
the substrate 100 is peeled off.
Specifically, since the light blocking layer 300 is disposed on the first semiconductor layer 210, the substrate 100 can be peeled off, thereby preventing light from being transmitted between the light emitting chips 200 through the substrate 100, and further improving the optical crosstalk.
Further, when the intrinsic semiconductor layer 110 is disposed between the substrate 100 and the first semiconductor layer 210, the intrinsic semiconductor layer 110 may be removed after the substrate 100 is peeled off, so as to prevent light from being transmitted between the plurality of light emitting chips 200 through the intrinsic semiconductor layer 110, thereby further improving the optical crosstalk.
In some embodiments, another embodiment of the present application provides a display structure, including the light emitting chip array structure provided in any one of the above embodiments, or the light emitting chip array structure manufactured by the method for manufacturing the light emitting chip array structure provided in any one of the above embodiments.
The display structure provided by the embodiment of the present application has the light emitting chip array structure provided by any one of the above embodiments, or the light emitting chip array structure manufactured by the method for manufacturing the light emitting chip array structure provided by any one of the above embodiments. Therefore, all the advantages of the light emitting chip array structure provided in any of the above embodiments and the light emitting chip array structure manufactured by the light emitting chip array structure manufacturing method are not repeated herein.
In some embodiments, the present invention further provides a display structure, which may be a display device or an electronic device having a display module, including but not limited to a mobile phone, a tablet, a notebook computer, a television, an AR/VR device, a vehicle instrument and central controller, an outdoor display, a head-up display (HUD), a home appliance with a display screen, and the like. The display structure may also be an electronic device having a light emitting module, including but not limited to a projector, a desk lamp, etc. The display structure comprises the light-emitting chip array structure or the light-emitting chip array structure prepared by the preparation method, and further comprises a driving chip used for being bonded with the light-emitting chip 200, a control module used for controlling the light-emitting chip 200 to display pictures, a power supply module and the like.
In the description of the present specification, reference to the description of "one embodiment," "some embodiments," "an example," "a specific example," or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application, and that variations, modifications, substitutions and alterations may be made to the above embodiments by those of ordinary skill in the art within the scope of the present application.
Claims (15)
1. A light emitting chip array structure, comprising:
the light-emitting device comprises a plurality of light-emitting chips, a plurality of light-emitting chips and a plurality of light-emitting chips, wherein each light-emitting chip comprises a first semiconductor layer, an active layer and a second semiconductor layer which are sequentially stacked;
and the light blocking layer surrounds the circumferential edge of the light emitting chip to absorb and/or reflect light emitted by the active layer.
2. The light emitting chip array structure of claim 1, wherein the height of the light blocking layer is greater than or equal to the height of the active layer.
3. The light emitting chip array structure of claim 2, further comprising a protection layer covering the light emitting chips, wherein an absolute value of a height difference between a height of the light blocking layer and a height of the protection layer is less than or equal to a predetermined threshold 。
4. The array structure of light emitting chips according to any one of claims 1 to 3, wherein the light emitting chips are disposed at intervals, and the light blocking layer surrounds a circumferential edge of each of the light emitting chips.
5. The array structure of claim 4, further comprising a substrate, wherein the light emitting chips are disposed on the substrate, and the light blocking layer is disposed on the substrate and spaced apart from the light emitting chips.
6. The light emitting chip array structure of claim 4, wherein the light blocking layer surrounds a circumferential edge of the first semiconductor layer and is in contact with the first semiconductor layer.
7. The light emitting chip array structure according to any one of claims 1 to 3, wherein for a plurality of light emitting chips, the first semiconductor layer is continuously disposed, and the active layer and the second semiconductor layer are respectively disposed at intervals;
the light blocking layer is arranged on one surface, close to the active layers, of the first semiconductor layer and located between the adjacent active layers, and the light blocking layer and the active layers are arranged at intervals.
8. The light-emitting chip array structure of claim 1, wherein the light-blocking layer is a diamond-like film.
9. A method for preparing a light-emitting chip array structure is characterized by comprising the following steps:
arranging a plurality of light-emitting chips on a substrate, wherein each light-emitting chip comprises a first semiconductor layer, an active layer and a second semiconductor layer which are sequentially stacked;
the plurality of light-emitting chips are arranged at intervals respectively, and the light-blocking layer is arranged at the circumferential edge of each light-emitting chip so as to enable the light-blocking layer to absorb and/or reflect light emitted by the active layer.
10. The method for manufacturing a light emitting chip array structure according to claim 9, wherein the plurality of light emitting chips are respectively disposed at intervals, and the disposing of the light blocking layer at the circumferential edge of the light emitting chip comprises:
and arranging a light-blocking layer on the substrate, wherein the light-blocking layer and the light-emitting chip are arranged at intervals.
11. The method for manufacturing a light emitting chip array structure according to claim 9, wherein the plurality of light emitting chips are respectively disposed at intervals, and the disposing of the light blocking layer at the circumferential edge of the light emitting chip comprises:
and arranging the light-blocking layer, wherein the light-blocking layer surrounds the circumferential edge of the first semiconductor layer and is in contact with the first semiconductor layer.
12. The method for preparing a light emitting chip array structure according to claim 11, wherein after the disposing of the light blocking layer, the method further comprises:
and stripping the substrate.
13. The method of manufacturing a light emitting chip array structure according to claim 9, wherein the first semiconductor layer is continuously provided, and the active layer and the second semiconductor layer are separately provided for a plurality of light emitting chips;
set up the light blocking layer at the circumference border department of emitting chip, include:
and arranging a light blocking layer on the first semiconductor layer, wherein the light blocking layer is positioned between the adjacent active layers and is arranged at intervals with the active layers.
14. The method for preparing the light emitting chip array structure according to claim 13, wherein after the light blocking layer is disposed on the first semiconductor layer, the method further comprises:
and stripping the substrate.
15. A display structure, comprising the light emitting chip array structure of any one of claims 1 to 8 or the light emitting chip array structure manufactured by the method of manufacturing the light emitting chip array structure of any one of claims 9 to 14.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117096171A (en) * | 2023-08-09 | 2023-11-21 | 深圳市思坦科技有限公司 | Micro display device, manufacturing method thereof and micro display device |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100201280A1 (en) * | 2007-09-12 | 2010-08-12 | Photonstar Led Limited | Electrically isolated vertical light emitting diode structure |
| CN104681576A (en) * | 2015-03-04 | 2015-06-03 | 扬州中科半导体照明有限公司 | Light emitting diode array with double insulating layers and production method of light emitting diode array |
| CN110600597A (en) * | 2019-08-21 | 2019-12-20 | 云谷（固安）科技有限公司 | Micro LED chip, display panel and preparation method of display panel |
| CN113161332A (en) * | 2021-05-19 | 2021-07-23 | 京东方晶芯科技有限公司 | Light-emitting substrate, preparation method thereof and display device |
| CN113380842A (en) * | 2020-03-10 | 2021-09-10 | 夏普福山半导体株式会社 | Image display element |
| CN113725248A (en) * | 2021-08-24 | 2021-11-30 | 上海天马微电子有限公司 | Display device and manufacturing method thereof |
| CN113745391A (en) * | 2021-08-26 | 2021-12-03 | 厦门天马微电子有限公司 | Display panel and display device |
| CN216054759U (en) * | 2021-09-08 | 2022-03-15 | 深圳市思坦科技有限公司 | Miniature LED chip, display device and light-emitting device |
| CN114256391A (en) * | 2021-12-22 | 2022-03-29 | 深圳市思坦科技有限公司 | Manufacturing method of display substrate, display substrate and display device |
| CN114628563A (en) * | 2022-05-12 | 2022-06-14 | 镭昱光电科技(苏州)有限公司 | Micro LED display chip and preparation method thereof |
| CN114975751A (en) * | 2022-05-25 | 2022-08-30 | 厦门天马显示科技有限公司 | Light-emitting panel, display device and backlight module |
| CN115188782A (en) * | 2021-04-02 | 2022-10-14 | 深圳市奥拓电子股份有限公司 | Micro-LED module, display screen and manufacturing method thereof |
-
2022
- 2022-11-30 CN CN202211526228.5A patent/CN115799233B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100201280A1 (en) * | 2007-09-12 | 2010-08-12 | Photonstar Led Limited | Electrically isolated vertical light emitting diode structure |
| CN104681576A (en) * | 2015-03-04 | 2015-06-03 | 扬州中科半导体照明有限公司 | Light emitting diode array with double insulating layers and production method of light emitting diode array |
| CN110600597A (en) * | 2019-08-21 | 2019-12-20 | 云谷（固安）科技有限公司 | Micro LED chip, display panel and preparation method of display panel |
| CN113380842A (en) * | 2020-03-10 | 2021-09-10 | 夏普福山半导体株式会社 | Image display element |
| CN115188782A (en) * | 2021-04-02 | 2022-10-14 | 深圳市奥拓电子股份有限公司 | Micro-LED module, display screen and manufacturing method thereof |
| CN113161332A (en) * | 2021-05-19 | 2021-07-23 | 京东方晶芯科技有限公司 | Light-emitting substrate, preparation method thereof and display device |
| CN113725248A (en) * | 2021-08-24 | 2021-11-30 | 上海天马微电子有限公司 | Display device and manufacturing method thereof |
| CN113745391A (en) * | 2021-08-26 | 2021-12-03 | 厦门天马微电子有限公司 | Display panel and display device |
| CN216054759U (en) * | 2021-09-08 | 2022-03-15 | 深圳市思坦科技有限公司 | Miniature LED chip, display device and light-emitting device |
| CN114256391A (en) * | 2021-12-22 | 2022-03-29 | 深圳市思坦科技有限公司 | Manufacturing method of display substrate, display substrate and display device |
| CN114628563A (en) * | 2022-05-12 | 2022-06-14 | 镭昱光电科技(苏州)有限公司 | Micro LED display chip and preparation method thereof |
| CN114975751A (en) * | 2022-05-25 | 2022-08-30 | 厦门天马显示科技有限公司 | Light-emitting panel, display device and backlight module |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117096171A (en) * | 2023-08-09 | 2023-11-21 | 深圳市思坦科技有限公司 | Micro display device, manufacturing method thereof and micro display device |
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| Publication number | Publication date |
|---|---|
| CN115799233B (en) | 2023-11-28 |
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