CN115799230A

CN115799230A - Stacked chip and electronic device

Info

Publication number: CN115799230A
Application number: CN202310081200.3A
Authority: CN
Inventors: 武晨希; 卡斯滕·尼尔森; 乔宁; 范健均; 柯政; 迪兰·理查德·缪尔; 图芭·代米尔吉
Original assignee: Shenzhen Shizhi Technology Co ltd
Current assignee: Shenzhen Shizhi Technology Co ltd
Priority date: 2023-02-08
Filing date: 2023-02-08
Publication date: 2023-03-14
Anticipated expiration: 2043-02-08
Also published as: CN115799230B

Abstract

The invention discloses a stacked chip and an electronic device. In order to solve the technical problems of large waste of expanded resources and high cost of the existing neural network, the invention designs a stacked chip which comprises a plurality of first type bare crystals; the first type bare chip comprises at least n bonding pads, wherein n is a positive integer; and realizing rotary coding mapping logic through at least one redistribution layer, and establishing an electrical connection relationship between the at least n pads of the two adjacent first type bare chips. The invention can realize simple vertical stacking of the same bare chips to expand the network scale to the required scale, reduce the development cost and the availability of chips, improve the reusability and avoid wasting resources. The invention is suitable for the field of brain-like computing.

Description

Stacked chip and electronic device

Technical Field

The present invention relates to a stacked chip and an electronic device, and more particularly, to a stacked chip and an electronic device for expanding hardware resources of a neural network in a three-dimensional stacking manner.

Background

Expansibility is one of the important indexes for evaluating the quality of chip design. Many chips often have various expandable resources, such as storage, neural networks, computational resources, etc., in themselves. In many scenarios, it is desirable that these resources be easily and inexpensively expandable.

A core particle or a small chip (chip) is a chip "modular" design scheme, and an integrated circuit where a plurality of non-functional modules (such as CPUs, GPUs, ISPs, etc.) are located is combined together by technologies such as 2D/2.5D/3D integrated packaging, etc. to construct a larger system on chip (SoC). The implementation of planar cascading is currently easier, as in prior art 1.

Prior art 1: US20220013504A1.

Neuromorphic chips (neuromorphic chips) have the characteristics of imitability and ultra-low power consumption, comprise a large number of silicon neurons and communicate through discrete impulse events, and are also called impulse neural network processor chips. In the prior art, in order to expand the scale of the impulse neural network, it is a conventional and convenient practice to put a plurality of neuromorphic chips in a Mesh grid on a Board (Board), and directly transmit impulse events through a chip-chip bus to realize connection, such as fig. 5 in prior art 2.

Prior art 2: CN114372568A.

However, different applications have different requirements, and the required network size is different, which results in different situations corresponding to different numbers of chips. Previous schemes to fix a specific number of chips (e.g., 4 x 4) on a board either exceed the actual chip number requirements, waste a lot of unnecessary chip resources and area, or scale up the network through complicated and difficult jumper schemes or with FPGA/PC.

Prior art 3: CN112257848A.

In general, for any scenario with resource scaling requirements (including but not limited to neural networks), a simple and resource-wasting solution is needed. For example, in implementing a 3D packaged chip or a 3D integrated circuit, if each layer of die is different, each layer of die needs to be designed and manufactured separately, which results in huge design, manufacturing and testing costs, and the overall yield is also affected by the yield, and different application requirements and corresponding scale requirements may further result in various cost increases.

It would be advantageous to solve the above problems if it were possible to extend the scale as desired, flexibly and conveniently (especially in the vertical direction) using the same hardware resources as "building blocks".

Disclosure of Invention

In order to solve or alleviate some or all of the technical problems, the invention is realized by the following technical scheme:

a stacked chip comprising a number of first type dies; the first type bare chip comprises at least n bonding pads, wherein n is a positive integer; and realizing rotary coding mapping logic through at least one redistribution layer, and establishing an electrical connection relation between the at least n pads of the two adjacent first type bare chips.

The first type bare chips comprise redistribution layers for realizing rotary coding mapping logic, and electrical connection relations are established between the at least n bonding pads of the two adjacent first type bare chips.

One or more shifted or dislocated electrical connection relationships exist between the at least n bonding pads of the two adjacent first type bare chips.

The n bonding pads form a bonding pad group together; the first type die includes m groups of pads to which rotational coding is applied within the groups, respectively, where m is a positive integer not less than 2.

The first type bare chip comprises n groups of bonding pads, and each group of bonding pads comprises a plurality of bonding pads; the rotation coding mapping logic is applied between groups and also between pads within a group.

The first type of die includes an independent pad for each first type of die and control die coupling.

The first type bare chip also comprises a grid pad or/and a shared pad; the grid bonding pad is used for realizing resource expansion among the first type bare chips, and the shared bonding pad is used for power supply or information sharing among all the first type bare chips.

And between the shared bonding pads of two adjacent first type bare chips, the rotary coding mapping logic is not applied.

And rotary coding mapping logic is applied between the independent bonding pads of two adjacent first type bare crystals.

The first type die also includes a local pad that is used to couple with an event driven sensor.

The stacked chip further includes a control die coupled to the at least n pads of the first type die.

The control die includes a microprocessor.

The individual pads include an identification pad for identifying a first type of die.

Output pads of the grid pads of two adjacent first type dies are coupled with corresponding input pads.

The oppositely positioned pads in the shared pads of the two adjacent first type bare chips are coupled.

The first type of die includes an independent pad for each first type of die and control die coupling;

the first type bare chips also comprise grid bonding pads for realizing the resource expansion among the first type bare chips; the first type of die further comprises a shared pad for power or information sharing among all the first type of dies; applying rotary coding mapping logic between the independent bonding pads of two adjacent first type bare crystals; output pads in the grid pads of two adjacent first type bare crystals are coupled with corresponding input pads; the oppositely positioned pads in the shared pads of the two adjacent first type bare chips are coupled.

A first electronic device comprising a stacked chip as claimed in any one of the preceding claims.

A three-dimensional stacking device comprises at least two first-class circuit boards, wherein the first-class circuit boards are provided with at least one resource expandable chip; the first type of circuit board comprises top bonding pads and bottom bonding pads, wherein at least n top bonding pads and n bottom bonding pads are symmetrically arranged relative to the plane of the first type of circuit board, and n is a positive integer; establishing an electrical connection between the n top pads and the n bottom pads using a rotation coding mapping logic.

From the symmetrical arrangement angle, one or two or more shifted or dislocated electrical connection relations exist between the n bottom bonding pads and the n top bonding pads.

The resource expandable chip is a neural network processor chip including a neural network processor.

The neural network processor chip is a pulsed neural network processor chip.

The pulse neural network processor chip comprises a grid pin; based on a grid bonding pad formed by a top bonding pad and a bottom bonding pad of the first type of circuit board, grid pins of the pulse neural network processor chips configured on the adjacent first type of circuit board are communicated with each other, so that the pulse neural network in the adjacent pulse neural network processor chips is expanded; and the top bonding pad and the bottom bonding pad belonging to the grid bonding pad are symmetrically arranged relative to the plane where the first type circuit board is located, and are respectively and independently coupled with the corresponding pins of the pulse neural network processor chip.

The pulse neural network processor chip comprises independent pins, the independent pins independently access pads on a motherboard through independent pads of a first type of circuit board, the independent pads comprise top pads and bottom pads which are symmetrically arranged about a plane where the first type of circuit board is located, and rotary coding mapping logic is applied.

For any independent pin of the pulse neural network processor chip, the first type circuit board is configured with N +1 top bonding pads and N +1 bottom bonding pads; the N +1 top pads and the N +1 bottom pads are symmetrically arranged about a plane where the first type of circuit board is located, and an electrical connection relation is established by using a rotary coding mapping logic, wherein N is a positive integer.

The three-dimensional stacked device supports a maximum of N first type circuit boards.

The n top bonding pads and the n bottom bonding pads form a bonding pad group together; the first type circuit board comprises m bonding pad groups which respectively apply rotation coding in the groups, wherein m is a positive integer not less than 2.

The first type circuit board comprises n groups of top bonding pads and n groups of bottom bonding pads, and the bonding pads are symmetrically arranged relative to the plane where the first type circuit board is located; the rotation encoding mapping logic is applied between groups and also between pads within a group.

One pin of the resource expandable chip is coupled with one of the n top bonding pads or/and the n bottom bonding pads; or, a pin related to the output signal after the output signal conversion of the resource expandable chip is coupled to one of the n top pads or/and the n bottom pads.

The n top pads are located in the same region and the n bottom pads are located in another same region.

The independent pads comprise identification pads for first type circuit board identification; and judging the number of the first type circuit boards stacked in the three-dimensional stacking device or/and the position of any first type circuit board in the three-dimensional stacking device based on the level of the identification bonding pad.

The impulse neural network processor chip includes: local pins that are not coupled to the first type of circuit board top pads or/and bottom pads.

The three-dimensional stacked device is coupled to the sensor through the local pin.

The impulse neural network processor chip includes: a shared pin coupled with a shared pad of the first type circuit board; and the top bonding pad and the bottom bonding pad which are included in the shared bonding pad and are symmetrically arranged are vertically coupled.

The three-dimensional stacking device further comprises a motherboard; at least a part of the pads in the motherboard are vertically coupled with the top pads or the bottom pads of the first type circuit board at the topmost side or the bottommost side in the three-dimensional stacking device.

The at least a portion of the pads in the motherboard include identification pads, the number of which is the same as the number of identification pads in the first type of circuit board.

The resource expandable chip at least comprises: grid pins, independent pins and shared pins; the first type of circuit board comprises grid pads, independent pads and shared pads which are correspondingly coupled with the grid pins, the independent pins and the shared pins, and the grid pads, the independent pads and the shared pads respectively correspondingly comprise top pads and bottom pads which are symmetrically arranged relative to a plane where the first type of circuit board is located; wherein electrical connections are established between top pads and bottom pads belonging to said independent pads using a rotary coded mapping logic.

The top bonding pad and the bottom bonding pad which belong to the shared bonding pad and are symmetrically arranged relative to the plane where the first type of circuit board is located are vertically coupled; and the top bonding pad and the bottom bonding pad belonging to the grid bonding pad are symmetrically arranged relative to the plane where the first type of circuit board is located, and are respectively and independently coupled with the corresponding pins of the resource expandable chip.

The resource expandable chip is a pulse neural network processor chip; the resource expandable chip also comprises local pins which are not coupled with the top bonding pads or/and the bottom bonding pads of the first type of circuit board.

Pads between adjacent first type circuit boards are coupled by board-to-board connectors.

A three-dimensional stacking method is at least applied to a plurality of first-class circuit boards, and the first-class circuit boards are provided with at least one resource expandable chip; arranging top bonding pads and bottom bonding pads on the first circuit board, wherein at least n top bonding pads and n bottom bonding pads are symmetrically arranged relative to the plane of the first circuit board, and n is a positive integer; establishing an electrical connection between the n top pads and the n bottom pads using a rotation coding mapping logic.

From the symmetrical arrangement angle, one or two shifted or staggered electrical connection relations exist between the n bottom bonding pads and the n top bonding pads.

The first type circuit board comprises another part of top welding pads and another part of bottom welding pads which are symmetrically arranged relative to the plane of the first type circuit board; between the other part of the top bonding pads and the other part of the bottom bonding pads: and vertically coupling or/and respectively coupling with pins corresponding to the resource extensible chips independently.

One pin of the resource expandable chip is coupled with one of the n top bonding pads or/and the n bottom bonding pads; or, a pin related to the output signal after the output signal conversion of the resource expandable chip is coupled with one of the n top pads or/and the n bottom pads.

The n bottom pads and the n top pads: is used to identify the number or location of the first type of circuit board or is used to transmit data.

The resource expandable chip is a pulse neural network processor chip;

the impulse neural network processor chip at least comprises: grid pins, independent pins and shared pins; the first type of circuit board comprises grid pads, independent pads and shared pads which are correspondingly coupled with the grid pins, the independent pins and the shared pins, and the grid pads, the independent pads and the shared pads respectively correspondingly comprise top pads and bottom pads which are symmetrically arranged relative to a plane where the first type of circuit board is located; wherein, the electrical connection relationship is established between the top bonding pad and the bottom bonding pad which belong to the independent bonding pad by using the rotary coding mapping logic; the top bonding pad and the bottom bonding pad which belong to the shared bonding pad and are symmetrically distributed relative to the plane of the first type circuit board are vertically coupled; and the top bonding pad and the bottom bonding pad which belong to the grid bonding pad are symmetrically arranged relative to the plane where the first type of circuit board is located, and are respectively and independently coupled with the corresponding pins of the pulse neural network processor chip.

One of the motherboard and the first type circuit board is coupled by a vertical coupling method at a side where a number of the first type circuit boards are stacked.

A circuit board comprises top bonding pads and bottom bonding pads, wherein at least n top bonding pads and n bottom bonding pads are symmetrically arranged relative to the plane of the circuit board, and n is a positive integer; establishing electrical connection relationships between the n top pads and the n bottom pads using a rotation coding mapping logic; the circuit board is provided with at least one resource expandable chip; one pin of the resource expandable chip is coupled with one of the n top bonding pads or/and the n bottom bonding pads; or, one pin related to the output signal after the conversion of the resource extensible chip output signal is coupled with one of the n top bonding pads or/and the n bottom bonding pads.

The resource expandable chip is a pulse neural network processor chip.

The n top bonding pads and the n bottom bonding pads jointly form a bonding pad group; the circuit board comprises m bonding pad groups which respectively apply rotation coding in the groups, wherein m is a positive integer not less than 2.

The circuit board comprises n groups of top bonding pads and n groups of bottom bonding pads, and the bonding pads are symmetrically arranged relative to the plane of the circuit board; the rotation coding mapping logic is applied between groups and also between pads within a group.

One pin of the resource-expandable chip or one pin related to the output signal after the output signal conversion of the resource-expandable chip can be pulled up or pulled down the top bonding pad or/and the bottom bonding pad coupled with the pin.

The resource expandable chip is a pulse neural network processor chip; the impulse neural network processor chip at least comprises: grid pins, independent pins and shared pins; the circuit board comprises grid pads, independent pads and shared pads which are correspondingly coupled with the grid pins, the independent pins and the shared pins, and the independent pads and the shared pads respectively comprise top pads and bottom pads which are symmetrically arranged relative to the plane where the circuit board is located; wherein electrical connections are established between top pads and bottom pads belonging to said independent pads using a rotary coded mapping logic.

The top bonding pad and the bottom bonding pad which belong to the shared bonding pad and are symmetrically arranged relative to the plane of the circuit board are vertically coupled; and the top bonding pad and the bottom bonding pad which belong to the grid bonding pad are symmetrically arranged relative to the plane of the circuit board and are respectively and independently coupled with the corresponding pins of the pulse neural network processor chip.

A second electronic device comprising a three-dimensional stacked apparatus as in any one of the preceding claims, or comprising a circuit board as in any one of the preceding claims.

Some or all embodiments of the invention have the following beneficial technical effects:

1) Expansibility: with Board-to-Board (Board-to-Board) connectors soldered on PCBs, the network scale can be expanded to a desired scale by simply vertically stacking circuit boards (constituting a three-dimensional stacked Board set) or chips.

2) By utilizing rotation/shift coding, the IO number is reduced, and the effect is more obvious when the number of stacks is more;

3) Modularization: all circuit boards or chips are the same regardless of the position of the circuit boards or chips; a single circuit board or chip design, which can be applied to any position;

4) Flexibility: control circuit boards, such as FPGAs or Microcontrollers (MCUs), can be added on either side of the three-dimensional stacked plate package and can be independently connected to either circuit board and either control pin/pad;

5) Compactness: 3D stacking, the volume of the whole system can be minimized.

Further advantages will be further described in the preferred embodiments.

The technical solutions/features disclosed above are intended to be summarized in the detailed description, and thus the ranges may not be exactly the same. The technical features disclosed in this section, together with technical features disclosed in the subsequent detailed description and parts of the drawings not explicitly described in the specification, disclose further aspects in a mutually rational combination.

The technical scheme combined by all the technical features disclosed at any position of the invention is used for supporting the generalization of the technical scheme, the modification of the patent document and the disclosure of the technical scheme.

Drawings

FIG. 1 is a schematic diagram of a top structure of a daughter board in one embodiment;

FIG. 2 is a schematic diagram of a bottom structure of a daughter board in an embodiment;

FIG. 3 is a diagram illustrating the stacking of daughter boards in an embodiment;

FIG. 4 is a diagram illustrating the expansion of neural networks in adjacent chips according to an embodiment;

FIG. 5 is a schematic diagram of adjacent daughter board communication;

FIG. 6 is a schematic diagram of rotational encoding;

FIG. 7 is a diagram of the layout of individual pins of a chip on a stacked daughter board;

FIG. 8 is a schematic side view of a vertical stack of multiple plates according to an embodiment of the present invention;

FIG. 9 is a diagram illustrating a distribution of identified pads on any daughter board in one embodiment;

FIG. 10 is a diagram illustrating a distribution of identified pads on a plurality of daughter boards when stacked in a preferred embodiment;

FIG. 11 is a schematic diagram of a plurality of daughter boards having identification signal rotary connections when stacked in accordance with a preferred embodiment;

FIG. 12 is a schematic diagram of the number of stacked daughter boards corresponding to the identification signal of each daughter board in the embodiment;

FIG. 13 is a schematic diagram of the rotary encoder electrical connection relationship and the signal logic transfer relationship;

FIG. 14 is a schematic diagram of a first order rotation encoding electrical connection;

FIG. 15 is a diagram of the electrical connection logic of the grid pins and grid pads of the chip;

FIG. 16 is a diagram of the logical relationship of the electrical connections of the individual pads of a die in a chip-like embodiment;

FIG. 17 is a diagram of the electrical connection logic of the grid pads of a die in a chip-like embodiment;

fig. 18 is a diagram of the logical relationship of the electrical connections of the shared pads of the die in a chip-like embodiment.

Detailed Description

Since various alternatives cannot be exhaustively described, the following will clearly and completely describe the gist of the technical solution in the embodiment of the present invention with reference to the drawings in the embodiment of the present invention. It is to be understood that the invention is not limited to the details disclosed herein, which may vary widely from one implementation to another.

In the present invention, "/" at any position indicates a logical "or" unless it is a division meaning. The ordinal numbers "first," "second," etc. in any position of the invention are used merely as distinguishing labels in description and do not imply an absolute sequence in time or space, nor that the terms in which such a number is prefaced must be read differently than the terms in which it is prefaced by the same term in another definite sentence.

The present invention may be described in terms of various elements combined into various embodiments, which may be combined into various methods, articles of manufacture. In the present invention, even if the points are described only when introducing the method/product scheme, it means that the corresponding product/method scheme explicitly includes the technical features.

When a step, a module or a feature is described as being present or included at any position in the invention, the existence of the step, the module or the feature is not implied to be exclusive and only exists, and other embodiments can be fully obtained by the technical scheme disclosed by the invention and other technical means assisted by the technical scheme disclosed by the invention by a person skilled in the art; based on the point described in the embodiments of the present invention, those skilled in the art can completely apply the means of substitution, deletion, addition, combination, and order change to some technical features to obtain a technical solution still following the concept of the present invention. Such solutions are also within the scope of protection of the present invention, without departing from the technical idea of the invention.

The noun explains:

a neuromorphic chip: the event-driven circuit has the characteristic of event driving, and the event is driven to be calculated or processed when the event occurs, so that the ultrahigh real-time performance and the ultralow power consumption are realized on a hardware circuit. The neural network processor chip is a special neural network processor chip with bionic property, and is also called a brain-like chip or a pulse neural network processor chip. Any chip based on Address Event Representation (AER) protocol or its variation protocol may be referred to as a neuromorphic chip, which is not limited in the present invention. Unless otherwise specified, the chips described in the embodiments of the present invention are referred to as neuromorphic chips.

Spiking Neural Network (SNN): one of the event-driven neuromorphic chips is a third-generation artificial neural network, and has the advantages of abundant space-time dynamics characteristics, various coding mechanisms, event-driven characteristics, low calculation cost and low power consumption. Compared with an Artificial Neural Network (ANN), the SNN is more bionic and advanced, and the SNN-based brain-isolated computing (brain-isolated computing) or neuromorphic computing (neuromorphic computing) has better performance and computing overhead than the traditional AI chip.

Address Event Representation (AER): the method is used for communication between neuromorphic chips or modules inside the chips, and comprises an event generation address (such as pixel coordinates which are triggered to generate an event) and an event generation time stamp. The AER protocol can establish virtual connections between neurons, and is beneficial to efficient hardware implementation of a neuromorphic chip. In some cases, the AER signal may be converted to SAER (Serial Address Event Representation) to improve transmission efficiency. Reference is made in particular to chinese patent CN 114372019B.

The invention is described below in the context of three-dimensional stacking of circuit boards, and the concept can also be moved to other application scenarios, such as chip-level/wafer-level three-dimensional stacking.

In one embodiment, the present invention realizes stacking of chips in a vertical direction based on a circuit board, and relates to stacking of a plurality of sub-boards (at least one or two or more), stacking of one or more sub-boards and a mother board, and the like, which is not limited by the present invention.

For the sake of clarity, a circuit board or the like (not shown) containing a controller (FPGA, MCU, etc.) is referred to as a motherboard in the present invention.

For circuit boards or the like containing resource-expandable chips (for example, but not limited to, neuromorphic chips, ANN chips), they are referred to as daughter boards (also referred to as first-class circuit boards in the circuit board group class embodiments) in the present invention. Each daughter board includes a top portion and a bottom portion, and the top portion is assumed to be a surface coupled to the chip (also referred to as a front surface) and the bottom portion is assumed to be a reverse surface of the top portion (also referred to as a back surface), and the bottom pads are usually coupled to pads on the motherboard, and the coupling between the pads on the bottom portion and the top portion can be realized, for example, by a board-to-board connector.

The front, back, top and bottom of the present invention are terms used for distinguishing between descriptions and are not to be construed as limiting, but in some cases are interchangeable. The invention does not limit whether the same type of neuromorphic chip is used on each daughter board.

The neuromorphic chip based on event communication has extremely low power consumption, can be as low as microwatts or milliwatts, and can effectively adapt to the difficult problem of heat dissipation when stacked in the vertical direction.

The top and bottom of each daughter board includes pads and typically may also include at least one securing hole. The pads are used for connecting with other daughter boards or mother boards, the pads comprise at least one pad used for connecting with corresponding pins or signal lines, at least one part of top pads and at least one part of bottom pads are symmetrically arranged about the plane of the daughter boards, namely the projection positions of the top pads and the bottom pads on the daughter boards are the same, so that the board-to-board connector can realize the coupling between different daughter boards (in practical application, pads for other use purposes may exist according to certain needs, and belong to another part except the at least one part of pads); the invention does not limit the arrangement mode of the top pads or the bottom pads, one or a pair of the top pads or more than two of the top pads can be arranged, the positions can be set according to actual requirements, and the correct logic can be realized when the top pads and the bottom pads are symmetrically arranged and vertically stacked.

Now, the technical contents of the product and the method related to the present invention are described by taking the circuit board type embodiment as an example, and the disclosed technical contents can be easily expanded to the chip type embodiment. As shown in fig. 1 and fig. 2, the top and the bottom of the circuit board each have a pair of pads, the top pads are respectively located at east and west sides of the daughter board (determined by the figure), and the top pads may also be respectively located at north and south sides of the daughter board, or the top pads include pads located at east, west, north and south sides, and the like.

Fig. 1 is a schematic diagram of a top structure of a daughter board in an embodiment, which includes a pair of pads and chip pads, where the chip pads are used for bonding chip pins to properly bond the chip to the daughter board. Optionally, the daughter board may further include a screen printing or the like as shown in the drawing. The chip may be a resource-expandable chip. Preferably, the resource expandable chip is a neuromorphic chip, and a larger neural network scale can be used by combining a plurality of neuromorphic chips.

In the preferred embodiment shown in fig. 1, the top includes at least two sets of pads: j1 and J2 are respectively positioned on the west side and the east side, the bonding pad J1 comprises two columns of bonding pads A and B, the bonding pad J2 also comprises two columns of bonding pads A and B, the number and the distribution of the bonding pads can be set according to actual conditions, and the invention is not limited.

Fig. 2 is a schematic diagram of a bottom structure of a daughter board in an embodiment, which at least includes two sets of pads: j3 and J4. The arrangement layout of the pads (J3 and J4) at the bottom of the daughter board corresponds to the arrangement layout of the pads (J1 and J2) at the top of the daughter board, and symmetric arrangement of planes where the daughter boards are located is achieved, so that a foundation is provided for easily achieving scale expansion by using the same hardware resources.

Illustratively, the daughter board bottom pads J3 include two columns a and B of pads, which are respectively connected to the two columns B and a of the adjacent daughter board top pads J1, and the daughter board bottom pads J4 include two columns a and B of pads, which are respectively connected to the two columns B and a of the adjacent daughter board top pads J2.

In the mother board, only one pair of pads may be included, and the pads are located on the bottom or top of the mother board, and their specific positions depend on the top or bottom of the three-dimensional stacked board group (i.e. three-dimensional stacked device, referred to as stacked board group; the three-dimensional stacked board group includes stacked daughter boards, but may or may not include mother boards). For example, including first daughter board and second daughter board, the third daughter board (all belong to first class circuit board) in the stacked plate group, if the mother board links to each other with two sets of pads (J3, J4) of first daughter board bottom, then two sets of pads (J1, J2) at first daughter board top correspond with two sets of pads (J3, J4) of second daughter board bottom respectively and are connected, two sets of pads (J1, J2) at second daughter board top correspond with two sets of pads (J3, J4) of third daughter board bottom respectively and are connected, analogize in proper order. If the mother board is connected with the two groups of bonding pads (J1, J2) at the top of the first daughter board, the two groups of bonding pads (J3, J4) at the bottom of the first daughter board are correspondingly connected with the two groups of bonding pads (J1, J2) at the top of the second daughter board respectively, and so on.

Fig. 3 is a schematic diagram of stacking a plurality of daughter boards according to a preferred embodiment of the present invention, in which the daughter boards Board _0 to Board _3 are respectively mounted with resource-expandable chips (such as neuromorphic chips) Chip _0 to Chip _3. Each daughter board can be regarded as realizing the two-dimensional expansion of resources along with the increase of the chip area, and the 4 daughter boards also realize the expansion in the vertical direction, thereby realizing the three-dimensional stacking of resources such as storage, calculation, neural networks and the like.

Fig. 4 is a schematic diagram of the expansion of the neural network in the adjacent chips in a certain embodiment, and the east event bus (pin) of one chip and the west event bus (pin) of the adjacent chip are correspondingly connected through the bonding pad, and are sequentially cascaded to realize the expansion of the neural network.

Fig. 5 is a schematic diagram of communication between adjacent daughter boards corresponding to fig. 4, where each daughter board has a pair of event buses on the top and bottom, for example, an east event input bus and an east event output bus are distributed on a pad on the top, and a west event input bus and a west event output bus are distributed on a pad on the bottom. Alternatively, the east event bus (including the input bus and the output bus) is located at the bottom pad, and the west event bus (including the input bus and the output bus) is located at the top pad, which is not limited by the invention. With the arrangement, the adjacent chips of the invention can be expanded in the vertical direction. East and west event buses are basic communication means for expanding the pulse neural network scale for the neuromorphic chip, and when the neuromorphic chip is implemented as other types of resource-expandable chips, the part of pads/pins can be used for basic transmission devices including data.

Through the vertical connection of the adjacent daughter board (for example, the vertical connection of the Borad _ i and the Borad _ i +1 in FIG. 5), the "east" event output bus (out _ E _ data and the corresponding handshake signals) at the top of the daughter board Borad _ i and the "west" event input bus (in _ W _ data and the corresponding handshake signals) at the bottom of the adjacent daughter board Borad _ i +1 communicate, so as to realize the neural network extension shown in FIG. 4.

Specifically, the east event output bus located in the group J1 at the top of the daughter Board _ i is complementarily connected to the west event input bus located in the group J3 at the bottom of the adjacent daughter Board _ i +1, and the east event input bus located in the group J1 at the bottom of the Board _ i is complementarily connected to the west event output bus located in the group J3 at the bottom of the adjacent daughter Board _ i +1, thereby implementing a vertically oriented 3D connection.

Alternatively, the neural network may be extended using a pair of "south" and "north" event buses between adjacent sub-boards, or extended using multiple pairs of event buses. The present invention is not limited to the names or specific locations of the event buses described above, whether they are located on the top or/and bottom pads of the daughter boards, so long as they achieve complementary connections between adjacent daughter boards.

In one embodiment, for example, the top of the daughter board includes a pair of "east" event buses, a pair of "south" event buses, and the bottom of the daughter board includes a pair of "west" event buses, a pair of "north" event buses, complementary to the corresponding event buses on the top of the daughter board, that complementarily communicate with the pins of the adjacent daughter boards to enable the expansion of the neural network.

In other embodiments, on the basis of the foregoing scheme, a data bus may be added to implement expansion in more dimensions, and correspondingly, the newly added data bus is connected to all chips. Preferably, the data bus is used to transmit AER events.

In some embodiments, the top of the daughter board includes at least one resource expansion chip, or other daughter boards may be cascaded in the vertical direction or/and in other directions than the vertical direction, so as to implement resource expansion, such as neural network, for example, but not limited thereto.

For certain types of embodiments of neuromorphic chips, the wires/pins (pins) that lead from the neuromorphic chip internal circuitry may be divided into four types/groups (correspondingly, the chip pads may be divided into four types/groups):

1) Local pin: refers to pins that need to be accessed externally but not by any daughter board or motherboard, such as sensor front ends, monitor pins for debugging, power-up pins.

2) Grid pins (also called complementary pins): pins that complementarily interact with adjacent daughter boards to enable cascading of chips. Broadly, such pins are used for resource expansion of a resource-extensible chip (in a neuromorphic chip, it is usually a neural network scale), which provides a data communication basis between a plurality of resource-extensible chips. This type of pin is described in fig. 4 or 5.

3) Sharing the pins: pins received from the motherboard but possibly shared (power or information) with all daughterboards, such as power supply, reset, configuration data bus.

4) Independent pin: refer to signal pins, such as configuration control signals, digital signal outputs, etc., also referred to as control pins, that require independent access to the motherboard.

In addition, the number and the name of each type of chip pins can be configured at will according to requirements, and the invention is not limited by the types of the chip pins configured on the top and the bottom bonding pads of the daughter board.

Therefore, the bonding pads (including but not limited to the aforementioned J1-J4 bonding pads) on the daughter board are distinguished for the four types of pins of the chip:

1) Local bonding pad: such pads are not coupled to similar aforementioned J1-J4 pads on the top and/or bottom of the daughter board, but are typically connected directly (wired out) to connectors (headers) at the edge of the circuit board.

2) Grid pad: complementary signals of the pads are respectively configured at the top of the matched daughter Board and the bottom of the daughter Board, for example, the top of the daughter Board is configured with an east event output bus, and the bottom of the daughter Board is configured with a west event input bus, so that when the top of the daughter Board _ i and the bottom of the adjacent daughter Board _ i +1 (or the bottom of the daughter Board _ i and the top of the adjacent daughter Board _ i + 1) are vertically plugged/connected, complementary/paired connection or communication of corresponding signals is realized, and a data communication basis is provided for a plurality of resource expandable chips. Data sent by the corresponding grid pad (unmated or non-complementary pad) is typically discarded when there is no further daughter board connection.

3) Sharing the bonding pad: is located at the same position of the top pad and the bottom pad. In other words, the symmetrical arrangement of the shared top pads and the shared bottom pads is coupled vertically (obviously perpendicular to the plane of the first type of circuit board) (direct coupling, without applying rotation coding).

4) Independent bonding pad: the individual pins from different chips are separated on pads on the top and/or bottom of the daughter board and are independently accessed or connected to the motherboard via the top and/or bottom pads of the daughter board. Thus, for a stacked board set that supports a maximum number N of daughter board stacks (N being a positive integer), either on top or at the bottom of any daughter board, each of this class of signals needs to be represented using at least N or N +1 (distinguishably identifiable) connection pads, which is an important challenge that the present invention faces before, since each of the at least N independent pins behaves the same in hardware on the chip, but is independent on the daughter board. To this end, the present invention uses a rotation coding strategy, which encodes each group in this class of signals on the daughter boards to correspond to different daughter boards.

The identification pad in the present invention can be regarded as one of the independent pads, which can be coupled with the identification pin (one of the independent pins) of the chip; in some cases, the chip may not have an identification pin, but the signal output from some pins of the chip is converted to obtain a pin with a function similar to the chip identification pin, and is coupled to the identification pad (for example, the ID _0 signal is pulled up), and is finally coupled to the motherboard.

In one embodiment, different daughter boards are provided to carry the same chip, and each chip has the same independent pin at the same position. For each independent pin, at least a maximum stacking number of N +1 (or N) pads (daughterboard single side) are arranged at certain areas (preferably adjacent areas) of the pads (such as J1-J4) at the top or bottom of each daughterboard, wherein N is a positive integer. When the number of pads is N +1, N is the number of daughter boards that can be stacked with maximum recognition of the entire system. Regarding the top and bottom bonding pads of the daughter board corresponding to any independent pin of the chip as a group; for any group of independent bonding pads, the independent bonding pads are symmetrically arranged on the top and the bottom of the daughter board and relative to the plane of the daughter board (obviously referring to the plane of the central section of the daughter board).

In a preferred embodiment, the present invention applies a rotation coding strategy to a group of independent pads corresponding to an independent pin of a resource-expandable chip on a daughter board, so as to realize independent access to a motherboard or other devices/modules when adjacent daughter boards are vertically plugged/connected/coupled.

Referring to fig. 6, a schematic diagram of a rotation coding strategy is shown by taking 8 code number information as an example. When the rotation coding is not applied (or before the rotation coding is applied), as shown in the upper left corner of the figure, the code number 0 before the coding corresponds to the code number 0, and the code number 1 before the coding corresponds to the code number 1, \8230 \ 8230;. When the 'one-time' rotary coding is applied, the code number 0 before coding corresponds to the code number 1, the code number 1 before coding corresponds to the code number 2, \8230;, the code number 7 before coding corresponds to the code number 0; by applying the 'secondary' rotary coding, the code number 0 before coding corresponds to the code number 2, the code number 1 before coding corresponds to the code number 3, \ 8230 \ 8230;, the code number 7 before coding corresponds to the code number 1; and so on. The rotation coding brings the ring arrangement effect similar to dislocation, and the application of the rotation coding for 'several times' can cause dislocation of several positions between the mapping relation before and after the coding. In the present invention, one (preferably) or two or more rotation codes can be applied.

Specifically, for any group of independent pins, the arrangement of the independent pins on the bottom pad of the daughter board and the arrangement of the independent pins on the top pad at the symmetrical positions realize rotation (also referred to as shift in the present invention) of one position. In addition, the rotation of two or other number of positions can be set according to actual needs, and the invention is not limited to this.

In a certain embodiment of the example in fig. 7, a schematic diagram of a layout of independent pins of a Chip on a stacked daughter Board is shown, where N is equal to 3, the daughter boards Board _0 to Board _3 are respectively mounted with the chips Chip _0 to Chip _3, and part or all of grid pins, shared pins, and independent pins in each Chip pin are coupled to top pads or/and bottom pads corresponding to the corresponding daughter Board, thereby implementing the scalable resource beyond 3D direction expansion.

The number of identification pads on the daughter board (N + 1) determines the maximum identifiable number of daughter boards (N) that can be supported stackable. Theoretically, the former has 1 more than the latter. However, in practical applications, it is preferable that the number of sub-boards in the stacked board group consisting of sub-boards is N-1 or less (redundant design).

In a preferred embodiment, the stacked daughter boards have the same hardware configuration, the chips mounted on the daughter boards are the same chip, and the control pin (independent pin) associated with each chip and the ADC, for example, is denoted as data _ i. Corresponding to the number N +1, each of the daughter boards is provided at the top and bottom with a set of independent pads data _0 to data _3 corresponding to the ADC control pins. As shown in fig. 7, assuming that the mother board is at the bottom of the stacked daughter boards (the top in fig. 7), the individual pins (examples) at the same positions of Chip _0 to Chip _3 are finally coupled to the pads data _0, data _1, data _2, and data _3 of the mother board, respectively (some coupling paths need to pass signals through the daughter boards).

In the daughter board bottom and top pads, there is a rotation (i.e., misalignment) of one (or more) positions between the top and bottom for the set of individual pads data _0 to data _3 associated with the aforementioned ADC. For example, from the perspective of signal logic transfer, data _0, data _1, data _2, and data _3 are arranged in sequence at the bottom, data _1, data _2, data _3, and data _0 are arranged in sequence at the top, and the misalignment relationships in such arrangements are the same in Board _0 to Board _3. Further logical and electrical connections to signal transfer can be found in fig. 13 and 14. It should be noted that the information transmission direction shown by the arrow in fig. 7 is only an example of a certain example, and the present invention is not limited thereto.

Therefore, independent pins of any chip are coupled with the corresponding bonding pads distributed on the top and the bottom of the daughter board at the same time, and then effective and logical stacking is realized by utilizing rotation/shift coding, the number of pins/IO (input/output) of the chip is reduced by multiplexing, and the more the number of the stacked daughter boards is, the more the effect is obvious. For example, one pin of Chip _0 (or its connected Chip pad) in fig. 7 is coupled to both the bottom pad data _0 and the top pad data _0 of the daughter board where the Chip is located.

In the preferred embodiment, the hardware resources of each chip and each daughter board are the same, which is beneficial to design, manufacture and test, and a user can flexibly set the number of vertically stacked daughter boards to realize different network scales, and the waste of chip resources is avoided, thereby reducing the cost. In other embodiments, the chips mounted on some daughter boards are different. The invention is not limited by the specification of the chip, and the complementary connection of the corresponding bonding pads can be realized only when the daughter boards are vertically connected.

Fig. 8 is a side view of a vertical stack of multiple circuit boards illustrating exemplary arrangements of bottom and top pads of a daughter board, including grid pads, individual pads, shared pads, etc., in accordance with an embodiment of the present invention. Similar to fig. 7, the motherboard is located at the bottom (left side in the figure) of the stacked daughter Board and is coupled to the bottom pad of daughter Board _0 (e.g., via a Board-to-Board connector), the top pad of Board _0 is coupled to the bottom pad of Board _1, and so on.

The individual pads have undergone rotation of one (or more) position between the bottom and top of the same daughterboard. The grid pads are complementarily coupled with the bottoms of the adjacent daughter boards at the top of a certain daughter Board, for example, complementary coupling is realized by a pair of east event buses which are included at the top of the daughter Board _0 and a pair of west event buses which are included at the bottom of the daughter Board _1, the grid pads are not subjected to rotary coding, dislocation/displacement electrical connection relation does not exist between pads which are symmetrically arranged on the same daughter Board, top pads and bottom pads which belong to the grid pads are symmetrically arranged relative to the plane where the first type of circuit Board is located, and the top pads and the bottom pads are respectively and independently coupled with pins corresponding to the resource expandable chip. It should be noted that pads may be disposed on the top and/or the bottom of the motherboard and coupled to the daughter Board, where the pad arrangement on the pad on the side of the motherboard close to the daughter Board _0 (e.g., the bottom of Board _0 in fig. 8) is the same as the pad arrangement on the bottom of Board _ 0.

In one embodiment, for example, the top of the daughter board includes a pair of "east" event buses, a pair of "south" event buses, and the bottom of the daughter board includes a pair of "west" event buses, a pair of "north" event buses, complementary to the respective event buses on the top of the daughter board, which complementarily communicate with pads of adjacent daughter boards to enable expansion of expandable resources (such as neural networks).

In a preferred embodiment, independent pins associated with the same control signal of a Chip (i.e., signals that each Chip is required to be independently coupled to the motherboard) are mapped onto the top or/and bottom pads of the daughter board, and the aforementioned rotated position corresponds to a signal length (also referred to as a bit number or bit), for example, the length of the control signal associated with the ADC control signal is 4, and when the independent pin data [0 [ 3] is mapped onto the top or/and bottom pads of the daughter board, the pad data _0_ [0 ], data _ 3], data _1_ [0 ], data _ 3], data _2_ [0 ], data _3_ [0 ] is arranged in sequence on the bottom pads of the daughter board, wherein Chip _0 to Chip _3 correspond to data _0_ [0 ], data _1_ [0 ], data _3_ [ 3], data _3_ [0 ] in sequence, and the following steps. One of the schemes that can be used here is the "first-order bus-type rotation encoding scheme" described later.

In addition to the aforementioned chip-sourced pins/pads, in some types of embodiments, the daughter boards may also include identification pads (also referred to as ID pads) for ID identification to identify whether the daughter board is at the bottom or top of the stack, the number of daughter boards stacked, the location of any daughter board in the stacked board set, and so forth. The layout and mapping relationships of the ID pads and the independent pads corresponding to the chip independent pins on the top and bottom pads of the daughter board are similar, as shown in fig. 8. By way of example, ID related information may be identified and processed by an FPGA on the motherboard via the ID pads.

Fig. 9 is a distribution diagram of identified pads on any daughter board in an embodiment. For the maximum identifiable number of daughter boards N (N is a positive integer) supported by the stacked board set, N +1 ID pads should be included on each daughter board. In a preferred embodiment, in order to reserve a safety space, when the stacked board set needs to be connected with the FPGA and the user board, each daughter board at least comprises N +2 ID pads.

The daughter board comprises a plurality of bottom bonding pads and a plurality of top bonding pads, and the bottom bonding pads and the top bonding pads are respectively symmetrical with respect to the plane where the daughter board is located. But uses a rotation encoded mapping in the electrical connection between pads, which provides a physical hardware implementable basis for the present invention.

Fig. 10 is a distribution diagram of the identification pads on a plurality of daughter boards when stacked in a preferred embodiment, the stacked Board group includes 6 daughter boards (Board _0 to Board _ 5) coupled in a vertical direction, the top pads and the bottom pads of any daughter Board are configured with the identification pads ID _0 to ID _7, and there is a rotation of one (or more) position from the top identification pad to the bottom identification pad.

The identification pad (also called ID pad) is used for identification of the daughter board, and may be regarded as a specific example of the individual pad. The identification pad may be directly coupled to a pin of the chip or coupled to a pin associated with the converted output signal of the chip.

Specifically, certain position identification pads in the bottom pads of each daughter board are sequentially arranged from ID _0 to ID _7, and position (vertical/directly below) identification pads corresponding to the positions in the top pads are sequentially arranged from ID _1 to ID _7and ID _0, so that rotation of one position is realized.

A plurality of daughter boards may be stacked as desired, with the bottom of a daughter board being vertically coupled to the top of an adjacent daughter board (e.g., a board-to-board connector), or/and the top of a daughter board being vertically coupled to the bottom of an adjacent daughter board, and the mother board being vertically coupled to the top or bottom of the topmost or bottommost daughter board of the stacked set. If the bottom of one daughter board of the stacked board group is coupled with the mother board, the daughter board can be identified based on the application of the rotary code to the identification bonding pad. The mother board can be identified by the identification bonding pad which is subjected to rotary coding every time the stacking board group has one more daughter board. In certain alternative embodiments, an LED may be configured on the motherboard to indicate each daughter board stacked, among other functions. The present invention does not limit the order of the top recognition pads and the bottom recognition pads, which can be interchanged or flexibly adjusted.

In some embodiments, every other daughter board, a certain ID pad at the top or/and bottom of the daughter board is pulled up or pulled down, and ID _0 is pulled up for example, but not limited to. By identifying which pads on the motherboard are pulled up or the number of the pads pulled up, it can be determined how many daughter boards in the stacked board set or/and whether a daughter board is the top-level or bottom-level daughter board in the stacked board set.

In a preferred embodiment, assuming that the mother Board is above (in the figure) the stacked Board set, the daughter boards are stacked sequentially from top to bottom with Board _0 to Board _5. If the identification pads on all circuit Board (daughter Board and motherboard) pads in the system default to low level, when a daughter Board is connected to the motherboard, for example, the bottom of the topmost daughter Board _0 in the stacked Board set is coupled to the motherboard, the top and bottom pads ID _0 in the daughter Board _0 are powered up and pulled up to high level, and correspondingly, the pad ID _0 on the motherboard is also pulled up.

The daughter Board continues to be stacked, because of the aforementioned plane symmetry, the top pad of Board _0 is coupled to the bottom pad of daughter Board _1, and pad ID _0 on daughter Board _1 is also powered up and pulled up to 1. Correspondingly, through the transition of the top and bottom pads ID1 of the Board _0, the pad ID _1 on the motherboard is also pulled up, i.e. there are two daughter boards stacked, and at this time, the pads ID _0 and ID _1 on the motherboard are both pulled up, and at this time, the daughter Board Board _1 is the bottom of the stacked Board group.

And continuing to stack the daughter Board, wherein the top bonding pad of the Board _1 is coupled with the bottom bonding pad of the daughter Board Board _2, and the ID _0 on the daughter Board Board _2 is also electrified and pulled up to be 1. Correspondingly, through the transition of the top and bottom pads ID1 of Board _1 and the transition of the top and bottom pads ID2 of Board _0, the pad ID _2 on the motherboard is pulled up, i.e. there are three daughter boards stacked. Pads ID _0, ID _1 and ID _2 on the motherboard are pulled up at this time, and daughter Board _2 is the bottom of the stacked Board group at this time.

By analogy, when there are 6 daughter boards stacked, the pads ID _0 to ID _5 on the motherboard are all pulled up. Thus, through the identification pads (ID _0 to ID _ 5) pulled up on the motherboard, it can be determined that 6 daughter boards are stacked, and at this time, the daughter Board _6 is the bottom of the stacked Board group.

Further, if it is detected that the pad ID _1 at the top or bottom of any daughter board is pulled up to 1, it means that the daughter board is not the topmost (or uppermost, or lowermost in fig. 10) board in the stack. If it is detected that the pad ID _1 at the top or bottom of a daughter board is not pulled up, and still is 0, it means that the daughter board is the topmost board. Similarly, if the ID _7 (see fig. 10) pad voltage at the bottom or top of any daughter board is detected to be high, it indicates that the daughter board is not the lowest (or lowest) board in the stack.

If any daughter board bottom or top ID _7 (i.e., pad logically swapped with ID _ 0) pad is detected to be low, it means that the daughter board is the lowest level (closest to the motherboard) circuit board, because: every time a new daughter Board is stacked, besides the fact that one pad of the mother Board can be pulled up through the ID _0 at the bottom, the ID _7 of the daughter Board at the layer above the bottom can be pulled up through the ID _0 at the bottom, and generally, the ID _7 of the daughter Board _0 at the bottommost layer cannot be pulled up through the ID _0 than the daughter Board at the layer below the bottom, because the daughter Board _0 is already at the bottommost part.

In one embodiment, counting from the bottom to the top of the stacked plate set or from the top to the bottom, the number of daughter boards with a voltage of 1 (high) on the ID _1 (another pad in logical exchange with ID _ 0) pad at the bottom or top of all the daughter boards is counted until the voltage on the ID _1 pad is 0 (low). The pads (logic) with ID _1 high among all the daughter boards are counted (alternatively, the number of daughter boards with ID _0 high may be counted), and the counting result is equal to the number of daughter boards in the stacked board group minus one. For the example shown in FIG. 10, the detailed statistical record should be 1+ 0=5from Board _0 to Board _5 for 6 circuit boards in total.

Alternatively, counting from the top to the bottom or from the bottom to the top of the stacked plate group, the number of daughter boards with ID _7 of 1 (high) at the bottom or top of all the daughter boards is counted, and the counting result is equal to the number of daughter boards in the stacked plate group minus one. For the example shown in FIG. 10, the detailed statistical record should be 0+1 =5for 6 circuit boards from Board _0 to Board _5.

For any daughter board, by identifying the number of pads pulled up from the top/bottom pads thereon, it can also be determined how many daughter boards are in the stacked board set, and specifically, refer to fig. 12.

For any motherboard, which may be located at the bottom or top of the stacked set of boards, the total number of circuit boards in the system is equal to the number of daughter boards plus the number of motherboards in the stacked set. Stacking between circuit boards (daughter board to daughter board or daughter board to motherboard) may be achieved by board to board connectors, or any reasonable board level connection.

In other embodiments, when the bottom of daughter Board _0 at the bottom of the stacked Board group is coupled to the motherboard, without loss of generality, ID _0 on daughter Board _0 is said to be powered up and pulled up to 1 (high) (by way of example only), while two pads on the daughter Board pad adjacent to ID _0 are pulled down, and ID _1 and ID _ N +1 (ID _7 in fig. 10) corresponding thereto are pulled down to 0 (low). Since the recognition pad having the same projected position as that of the top pad in any one of the daughter boards is rotated by one position, the top pad corresponding to the position of the bottom pad ID _0 becomes ID _1.

In some embodiments, the aforementioned signal identifying that pad ID _0 is pulled high comes from a pin of the chip (as shown in fig. 7); in another class of embodiments, the aforementioned signal identifying that pad ID _0 is pulled high comes from the peripheral/auxiliary circuit of the respective daughter board.

As shown in fig. 9 and 10, if the ID _1 pad of any daughter board is detected to be 1, the high level is from the ID _0 pad of the daughter board at the top of the daughter board, which is not the daughter board at the topmost layer of the stacked board set; when the ID _1 pad of any daughter board is detected to be 0, the daughter board is the daughter board at the topmost layer of the stacked board set. Similarly, if the ID _ N +1 (i.e., ID _ 7) pad of any daughter board is detected to be 1, it is not the circuit board at the bottom layer in the stacked board set, and if the ID _7 pad of the daughter board is detected to be 0, the daughter board is the circuit board at the bottom layer (closest to the motherboard) in the stacked board set.

Alternatively, the drawing up, drawing down, or/and top, bottom, or/and uppermost, lowermost layers herein are merely examples, or are for ease of description to distinguish, and the invention is not limited to such description.

In a preferred embodiment, at least 2 daughter boards are stacked to enable larger scale network expansion. The method is characterized in that M stacked plate groups are provided, the maximum number of the daughter boards supported by each plate group is N, the M stacked plate groups are stacked, a fourth type of independent pin signals from a chip need to be expanded, N M bonding pads are needed on the top and bottom vertical plates of the daughter boards related to the signals to the bonding pads of the daughter boards, and M and N are non-zero integers.

Fig. 11 is a schematic diagram of the rotational connection of the identification signals on multiple daughter boards during stacking in a preferred embodiment, where a maximum of 7 daughter boards can be stacked, and each daughter board has N +1 identification pads at the top and bottom (N is the maximum number of identifiable daughter boards supported by the stacking board group). With the foregoing method, the level condition on the pads (ID _0 to ID _ 7) can be identified by the mother board, or the level condition on the pads (ID _0 to ID _ 7) can be identified by the daughter board, so that the number of the daughter boards stacked in the stacked board assembly, the daughter boards at the uppermost layer and the lowermost layer in the stacked board assembly, and the position of any daughter board in the stacked board assembly can be easily determined.

Fig. 12 is a diagram showing the number of stacked daughter boards corresponding to each daughter Board identification signal in the embodiment, which corresponds to the embodiment of fig. 9, when there are 1 daughter Board in the stacked Board group, the pad levels of ID _0 to ID _7 (hereinafter referred to as ID [0 ] for short) at the top and bottom of the daughter Board _0 are 1000 0000, when there are 2 daughter boards in the stacked Board group, the ID [0 ] pad level on the daughter Board _0 is 1100 0000, the ID [ 7] pad level on the daughter Board _1 is 1000 0001, and it is recognized from the daughter Board _0 to the daughter Board _1 that the pad level is rotated by one position; when there are 3 daughter boards in the stacked Board group, the ID [0 ] pad level on the daughter Board _0 is 1110 0000, the ID [ 7] pad level on the daughter Board _1 is 1000 0001, and the rotation of one position is performed in order from the daughter Board _0 to the daughter Board _1 to the Board _2 recognition pad level, and so on. It is easy to obtain that for any daughter board, the number of the daughter boards in the stacking plate set can be obtained by counting the number of the pads with the level being 1 in the corresponding pads, and the numerical values of the daughter boards are equal to those of the corresponding pads.

The present invention does not limit the specific location and arrangement order of the identification pads on the top and bottom pads as long as the location of the identification pads on the top and bottom pads correspond (vertically/directly below) and a positional rotation is achieved. Further, in some other embodiments, the position rotation or shift is not limited to one bit rotation, and in some modified embodiments, the configuration may be performed by using two or more position rotation codes.

Fig. 13 shows a diagram of the electrical connection relationship and signal logic transfer relationship of the present invention. The bottom and the top of the two first type circuit boards (or bare chips) respectively comprise pads (or the like) 0 to 6 and 0' to 6' (possibly only a part of the bottom or the top pads), the pads with the same number are symmetrical about the plane where the first type circuit board (also called a daughter board) is located, namely, the pad with the number 0' is directly below the pad with the number 0 (in the direction established by the picture), and so on, which is the position relationship of the pads in the physical space.

An example selected rotation coding mapping relationship is: 0

1’，1

2’，2

3’，3

4’，4

5’，5

6’，6

0' (i.e., one rotation encoding). As shown in the figure, according to the rotation coding rule, the pad 0 is coupled with the pad 1' by a trace, the pad 1 is coupled with the pad 2' by a trace, \8230 \ 8230;, the pad 5 is coupled with the pad 6' by a trace, which is the electrical connection relationship of the pads. The actual physical traces may not simply be straight or diagonal connections, but rather may be longer paths of windings (e.g., broken lines), where the dashed lines are merely illustrative of the logic of the connections.

In terms of signal logic transfer relationship, pad 0 'outputs the signal input by pad 6, pad 6' outputs the signal input by pad 5, pad 5 'outputs the signal input by pad 4, and pad 4' outputs the signal input by pad 3. As shown in the figure, pad 1 inputs the "1110101" signal sequence and pad 2 'outputs the same "1110101" signal sequence as if pad 1 at the bottom was shifted to pad 2' at the top. In the lower right corner of the drawing, the logic marks (0 to 6) represented by each top pad (0 ' to 6 ') after the signal logic transfer are marked, for example, the pad with the logic mark 1 in the lower right corner actually physically corresponds to the pad 2', and the signal logic is electrically coupled to the pad 1. In other words, in the upper right and lower right areas of the figure, the color blocks are labeled with the same pad, transmitting the same signal sequence, with the difference that one set is the input signal and the other set is the output signal.

FIG. 14 is a diagram of Bus (Bus) type rotary encoder electrical connections. The bottom of the two first type circuit boards (or bare chips) comprises pads (or the like) a 0-a 6, b 0-b 6 and c 0-c 6, and the top comprises pads (or the like) a '0' -a '6', b '0' -b '6' and c '0' -c '6'. Wherein a 0-a 6 and a '0' -a '6', b 0-b 6 and b '0' -b '6', c 0-c 6 and c '0' -c '6' are respectively symmetrical about the plane of the first type of circuit board (also called daughter board) where the first type of circuit board is located. In the figure, the area a (or group a) represents the welding plates a 0-a 6, and the other 5 areas are marked in a similar way.

An example selected rotation coding mapping is: a is a

c’，b

a’，c

b', where each symbol represents 1 region/group. In this figure, pad a0 is coupled to pad c '0', a1 is coupled to pad c '1' \ 8230 \ 8230;, pad a6 is coupled to pad c '6'; pad b0 is coupled to pad a '0', b1 is coupled to pad a '1' \8230; pad b6 is coupled to pad a '6'; pad c0 is coupled to pad b '0', c1 is coupled to pad b '1', 82308230, and pad c6 is coupled to pad b '6'. Therefore, the purpose of intra-region (intra-group) non-coding and inter-region (inter-group) application of rotation coding is realized, so that the scheme can be called a first-order bus type rotation coding scheme。

From another perspective, a first order bus-type rotational encoding scheme may be considered as multiple copies of the encoding scheme shown in FIG. 13. a1 to a6 can be regarded as 6 copies of a 0. Thus, the coding mapping relation between a0, b0, c0 and a '0, b '0, c '0 is generalized in 6 physically-redundant copies. It can be seen in fig. 14 that there are m (= 7) land groups, and there are n (= 3) pairs of (total 6) symmetrically arranged lands to which rotational coding is applied in each land group.

The second-order bus-type rotation coding scheme, not shown, is based on the first-order scheme, and further uses rotation coding in the group. For example, according to a

The mapping relationship of c 'is that when the pads in the area a are coupled to the pads in the area c' (first order), a rotation encoding scheme as shown in fig. 13 is further applied between the pads a0 to a6 and c '0' to c '6' (second order), and therefore the principle is similar and will not be described herein again.

Fig. 15 shows a logical relationship of electrical connections of the grid pins and the grid pads of the chip. In the figure, a top bonding pad and a bottom bonding pad in grid bonding pads on the same daughter board are not directly connected, but provide a communication line for a resource expandable chip on the daughter board so as to realize resource expansion. Output pins Out _ E _1 and Out _ E _2 of the chip are coupled to 2 top pads of the chip, and based on the stacking of the daughter boards, signals output by the chip, such as AER events, are transmitted to corresponding bottom pads of an adjacent daughter board, and the 2 bottom pads are coupled to In _ W _1 and In _ W _2 of the resource-expandable chip on the adjacent daughter board, respectively. Overall, the resource-scalable chips on all the daughter boards are interconnected to communicate data with each other.

The invention also relates to a circuit board (i.e. the daughter board and the first type of circuit board described above), which includes top pads and bottom pads, wherein at least n top pads and n bottom pads are symmetrically arranged with respect to the plane of the circuit board, and n is a positive integer; for example, n is greater than or equal to 3;

the circuit board is provided with at least one resource expandable chip, the resource expandable chip comprises an independent pin, and the independent pin of the resource expandable chip is coupled with one of the n top bonding pads and one of the n bottom bonding pads of the circuit board;

establishing electrical connection relationships between the n top pads and the n bottom pads using a rotating code mapping logic. In other words, there is at least one shifted/misaligned electrical connection relationship between the n bottom pads and the n top pads of the circuit board that are symmetrical.

The technical features of the (first) circuit board in other aspects, such as the expansion, have been described in the foregoing, and are not described herein again.

An electronic device comprising any one of the three-dimensional stacked devices or any one of the circuit boards.

The method of three-dimensional stacking according to the present invention is described above by taking the circuit board as an example, but the present invention is not limited thereto.

In the prior art, neuromorphic devices implementing SNN network expansion based on three-dimensional devices (such as RRAM on silicon, MRAM) are often layered in the following manner: the device comprises a plurality of synapse layers, a routing layer and a neuron layer which are stacked in sequence, wherein the neuron layer can penetrate through the routing layer to access any synapse layer by means of three-dimensional stacking technologies such as through holes and the like. However, each layer is designed differently, and can only be designed to a specific resource size, and flexible multiplexing of each layer is not supported, which can be referred to in detail in U.S. Pat. No. 10,832,127b2.

In the present invention, for the stacked chip and the method according to the chip-class embodiment, for example, referring to fig. 16, a schematic diagram of an electrical connection logic between pads to which rotation coding is applied of a three-dimensional stacked chip is shown, which is not limited to the redistribution layer shown in the figure, and the specific manufacturing example generally requires the cooperation of various components and materials (such as redistribution layer/conductive pattern, dielectric material, metal layer, substrate, etc.), and the present invention is not limited to a specific embodiment.

The figure shows, taking 3 dies as an example, the electrical logic connection relationship between different dies (also called dies, which include various expandable resources, such as storage resources and neuron resources), where each of the dies 1 to 3 (i.e. the first type die) includes a plurality of pads (pads, also called pads, which are similar to the pads in the circuit board type embodiment) for electrical connection, and at least a part of the pads (shown in the figure) are used for implementing the foregoing rotation coding.

For example, the redistribution layers 1 and 2 (the daughter boards described above) having one or more layers of dielectric material, through holes, and conductive patterns, which are constructed at least based on dielectric material, through holes, and conductive patterns, are used to electrically connect the bare chips 1 to 3. From the viewpoint of the redistribution layer 1 (redistribution layer 2), the pads of the foregoing bare dies 1 and 2 (2 and 3) connected in the redistribution layer 1, and the electrical connections in the redistribution layers 1 and 2 perform the foregoing rotation coding. Thus, in some embodiments, the bare chips 1 to 3 can be manufactured in the same way without being separately designed in the EDA, which not only reduces the cycle of design, tape-out and test caused by different chips, but also improves the comprehensive utilization rate of silicon affected by different scrap chips due to yield problems, and reduces the average cost of a single chip. These problems can be solved by the aforementioned chip packaging technology, and technical advantages are obtained.

Illustratively, the bare die includes a neural network processor, preferably a spiking neural network processor.

The first type bare wafer comprises n groups of bonding pads, and each group of bonding pads comprises a plurality of bonding pads; the rotation coding mapping logic is applied between groups and also between pads within a group.

Based on the above teachings of the present invention, how to implement the foregoing coding in the redistribution layer is a technical goal that can be achieved by those skilled in the art based on the prior art without creative effort, and the present invention is not described in detail.

Regarding the technique of 3D packaging, reference may be made to: WO2021/062742A1, CN113130414A, CN103296009B, US20220199583A1, CN111883481A and the like, and the technical details of the invention which can be used by those skilled in the art are not repeated.

It should be noted that the structure shown in fig. 16 is merely a schematic diagram of the electrical connection logic, and does not constitute an absolute limitation in the actual physical implementation, for example, the bare die and the redistribution layer do not necessarily constitute an inclusion-inclusion relationship. Furthermore, for the chip-class embodiment, all the implementation details thereof are similar to the circuit board-class embodiment (some terms need to be transferred to the chip-domain terms, some terms are the same but some specific physical meanings may not be fully equivalent, such as the aforementioned pads), and since the redistribution layer in the chip-class embodiment may be abstractly equivalent to the aforementioned circuit board (daughterboard), the counterpart of the board-to-board connector does not need to be specifically configured due to the presence of the pads of the die (such as the pads of die 2 in fig. 16); in addition, the chips on the daughter boards are coupled to the pads through pins (ID — 0 pads and Chip pins in fig. 10), which can be directly realized by the die pads in fig. 16 (the die is the Chip itself).

The stacked chip further includes a control die coupled to the at least n pads of the first type die. The first type of die includes an independent pad for each first type of die and control die coupling; the first type bare chips also comprise grid bonding pads for realizing the resource expansion among the first type bare chips; the first type of die further comprises a shared pad for power or information sharing among all the first type of dies; applying rotary coding mapping logic between the independent bonding pads of two adjacent first type bare crystals; output pads in the grid pads of two adjacent first type bare crystals are coupled with corresponding input pads; the oppositely positioned pads in the shared pads of the two adjacent first type bare chips are coupled.

Based on this, all embodiments of the circuit board class are referred to as chip class embodiments by way of reference, for example, the die further includes a local pad, a grid pad, a shared pad, and/or an independent pad, unless obviously not complying with logic, technical means/features of the circuit board class embodiments are applicable to the chip class embodiments, and are not described herein again.

For example, fig. 17 shows a logic diagram of electrical connections of grid pads in a chip-like embodiment. For die 1, which like dies 2-3 includes a number of mesh pads for communication that extend resources, for each of which an input or output function is intended, it belongs to one of an input pad, an output pad. With die 1, its output pad (black solid arrow) is connected to the input pad (black solid arrow) of die 2, and the data transferred is processed (e.g., routed) through die 2 and then transferred, if necessary, to the output pad of die 2 and, if further necessary, to the input pad of die 3.

Conversely and similarly, the output pad (open arrow) of die 3 is coupled to the input pad of die 2, and the output pad of die 2 is coupled to the input pad of die 1. Since the dies 1 and 3 are located at the end of the stacked chips, part of their input/output pads (pads without arrows) do not transfer data.

In other words, the output pads of the grid pads of two adjacent first type dies are coupled with the corresponding input pads.

FIG. 18 shows a logic diagram of the electrical connections of the shared pads in the chip class embodiment. For the shared pads, power or information sharing between all the first type dies is used, so that the oppositely located ones of the shared pads of two adjacent first type dies are coupled, as shown in fig. 18.

Event driven sensors (including but not limited to event cameras/DVS, ATIS, DAVIS, celeX, etc., not shown) may also be packaged together with the aforementioned expandable resource die (preferably a die containing an SNN processor) preferably by 2.5D or 3D packaging to form a chip.

Preferably, control dies (equivalent to the aforementioned motherboard) are built by, for example, a microprocessor (e.g., based on an ARM-M0 core, RISC-V core, etc., not shown), which may be referred to as core dies, different types of core dies may be fabricated using different process nodes.

Preferably, the bare chip comprises a neural network processor, and a neural network processor chip is formed. The neural network processor chip is preferably a neuromorphic chip.

The bare chip comprises: the grid bonding pad is complementarily communicated with the adjacent neural network processor chip to realize the expansion of the scale of the neural network; or/and share the pad, realize the sharing of information or energy among all neural network processor chips; or/and an independent bonding pad independently connected to the control bare chip; or/and a local pad for being externally accessed.

In some embodiments, individual pads of the die are rotation encoded using a rotation/shift strategy. Further, the rotation coding is implemented in a redistribution layer. Optionally, the individual pads include identification pads for ID identification.

In addition, the invention also discloses an electronic device which comprises any one of the stacked chips.

While the present invention has been described with reference to particular features and embodiments thereof, various modifications, combinations, and substitutions may be made thereto without departing from the invention. The scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification, and it is intended that the method, means, and method may be practiced in association with, inter-dependent on, inter-operative with, or after one or more other products, methods.

Therefore, the specification and drawings should be considered simply as a description of some embodiments of the technical solutions defined by the appended claims, and therefore the appended claims should be interpreted according to the principles of maximum reasonable interpretation and are intended to cover all modifications, variations, combinations, or equivalents within the scope of the disclosure as possible, while avoiding an unreasonable interpretation.

To achieve better technical results or for certain applications, a person skilled in the art may make further improvements on the technical solution based on the present invention. However, even if the partial improvement/design is inventive or/and advanced, the technical idea of the present invention is covered by the technical features defined in the claims, and the technical solution is also within the protection scope of the present invention.

Several technical features mentioned in the attached claims may be replaced by alternative technical features or the order of some technical processes, the order of materials organization may be recombined. Those skilled in the art will readily appreciate that various modifications, changes and substitutions can be made without departing from the scope of the present invention, and the technical problems and/or the sequences can be substantially solved by the same means.

The steps and components of the embodiments described in connection with the embodiments disclosed herein may be embodied in hardware, software, or a combination of both, and have been described in a functional generic sense in the foregoing description for the purpose of clearly illustrating the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application or design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention as claimed.

Claims

1. A stacked chip, comprising:

the stacked chip comprises a plurality of first type bare chips;

the first type bare chip comprises at least n bonding pads, wherein n is a positive integer;

and realizing rotary coding mapping logic through at least one redistribution layer, and establishing an electrical connection relationship between the at least n pads of the two adjacent first type bare chips.

2. The stacked chip of claim 1, wherein:

3. The stacked chip of claim 1, wherein:

4. The stacked chip of claim 1, wherein:

5. The stacked chip of claim 1, wherein:

the first type bare wafer comprises n groups of bonding pads, and each group of bonding pads comprises a plurality of bonding pads;

the rotation encoding mapping logic is applied between groups and also between pads within a group.

6. The stacked chip of claim 1, wherein:

the first type die includes an independent pad for each first type die and control die coupling.

7. The stacked chip of claim 6, wherein:

8. The stacked chip of claim 7, wherein:

9. The stacked chip of claim 6, wherein:

10. An electronic device, characterized in that:

the electronic device comprising the stacked chip of any one of claims 1-9.