CN115799055A - Semiconductor structure manufacturing method and semiconductor structure processing equipment - Google Patents
Semiconductor structure manufacturing method and semiconductor structure processing equipment Download PDFInfo
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
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Abstract
The embodiment of the application belongs to the technical field of semiconductor manufacturing, and particularly relates to a semiconductor structure manufacturing method and semiconductor structure processing equipment, which can solve the problem that a gate dielectric layer is easy to warp and deform to cause electric leakage of a gate structure in the related technology. Performing first temperature reduction treatment to cool the substrate to a first preset temperature, wherein the temperature variation per unit time in the first temperature reduction treatment is a first rate; and carrying out second temperature reduction treatment to cool the substrate to a second preset temperature, wherein the temperature variation of the unit time in the second temperature reduction treatment is a second rate, the first rate is less than the second rate, and the second preset temperature is less than the first preset temperature. Through carrying out first cooling treatment for the substrate carries out slowly cooling earlier, then carries out the second cooling stage, makes the substrate cool down to second preset temperature, avoids leading to the cracked grid dielectric layer because of the difference in temperature is too big, thereby reduces the electric leakage phenomenon of grid structure.
Description
Technical Field
The embodiment of the application relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure manufacturing method and semiconductor structure processing equipment.
Background
Electronic devices such as memories and controllers are usually provided with a Semiconductor structure, and the Semiconductor structure includes a Metal Oxide Semiconductor Field Effect Transistor (MOS fet) for implementing functions such as switching and amplification. The MOS tube comprises a substrate and a grid structure arranged on the surface of the substrate, wherein the grid structure comprises a grid dielectric layer, a work function layer and a grid conducting layer, the grid dielectric layer is located between the work function layer and the substrate, and the grid conducting layer covers the work function layer.
In the related art, after the gate dielectric layer is formed on the substrate, the substrate needs to enter a high temperature processing chamber to form a work function layer, and then enters a cooling chamber to be cooled. However, in the cooling process, the substrate is easily warped and deformed due to large temperature difference, and further cracked, which easily causes the leakage phenomenon of the gate structure.
Disclosure of Invention
The embodiment of the application provides a semiconductor structure manufacturing method and semiconductor structure processing equipment, which can solve the problem that in the related technology, a substrate is easy to warp and deform, and further cracks occur, so that the phenomenon of electric leakage of a grid structure is caused.
According to some embodiments, a first aspect of embodiments of the present application provides a method for fabricating a semiconductor structure, including:
providing a substrate;
forming a grid dielectric layer, wherein the grid dielectric layer covers the substrate;
forming a work function layer, wherein the work function layer covers the grid dielectric layer;
carrying out first temperature reduction treatment to cool the substrate to a first preset temperature, wherein the temperature variation per unit time in the first temperature reduction treatment is a first rate;
and carrying out second cooling treatment to cool the substrate to a second preset temperature, wherein the temperature variation of unit time in the second cooling treatment is a second rate, the first rate is less than the second rate, and the second preset temperature is less than the first preset temperature.
In one possible implementation, the performing the first cool-down process to cool the substrate to the first preset temperature includes:
transferring the substrate to a first chamber; the first cavity comprises a first cooling table for bearing the substrate, and the first cooling table is provided with a lifting device which is used for bearing the substrate, so that a preset height is formed between the substrate and the first cooling table;
and introducing cooling liquid into the first cooling table at a first flow rate until the substrate is cooled to the first preset temperature.
In one possible implementation manner, working gas is introduced above the first cooling stage at a first gas flow rate, and the maximum gas pressure of the working gas is a first gas pressure value.
In one possible implementation, performing the second temperature reduction process to cool the substrate to the second preset temperature includes:
transferring the substrate to a second chamber; the second cavity comprises a second cooling table for receiving the substrate;
introducing cooling liquid into the second cooling table at a second flow rate until the substrate is cooled to a second preset temperature; the first flow rate is less than or equal to the second flow rate.
In a possible implementation manner, working gas is introduced above the second cooling platform at a second gas flow rate, and the maximum gas pressure of the working gas is a second gas pressure value; the first gas pressure value is less than or equal to the second gas pressure value, and the first gas flow rate is less than or equal to the second gas flow rate.
In one possible implementation, performing the second temperature reduction process to cool the substrate to the second preset temperature includes:
moving the lifting device to the interior of the first cooling table until the first cooling table receives and bears the substrate;
introducing cooling liquid into the first cooling table at a second flow rate until the substrate is cooled to a second preset temperature; the first flow rate is less than or equal to the second flow rate.
In one possible implementation, the working gas is introduced above the first cooling stage at a second gas flow rate: the maximum air pressure of the working gas is a second air pressure value, the first air pressure value is smaller than or equal to the second air pressure value, and the flow rate of the first gas is smaller than or equal to the flow rate of the second gas.
In one possible implementation, forming the work function layer includes:
transferring the substrate to a reaction chamber; the reaction cavity comprises a reaction table for bearing the substrate, and the reaction table is used for heating the substrate;
and introducing reaction gas above the reaction platform to form the work function layer.
In one possible implementation, the reactant gases include titanium tetrachloride and ammonia, and the working gas includes nitrogen.
According to some embodiments, a second aspect of embodiments of the present application further provides a semiconductor structure processing apparatus comprising: the device comprises a processing table, a reaction cavity, a cooling cavity and a carrying arm, wherein the reaction cavity, the cooling cavity and the carrying arm are all connected with the processing table;
the reaction cavity is used for forming a work function layer of the semiconductor structure;
the cooling cavity is used for carrying out first cooling treatment on the semiconductor structure so as to cool the semiconductor structure to a first preset temperature, wherein the temperature variation per unit time in the first cooling treatment is a first rate, the cooling cavity is also used for carrying out second cooling treatment on the semiconductor structure so as to cool the semiconductor structure to a second preset temperature, the temperature variation per unit time in the second cooling treatment is a second rate, the first rate is smaller than the second rate, and the second preset temperature is smaller than the first preset temperature;
the carrying arm is used for transferring the semiconductor structure in the reaction cavity to the cooling cavity.
In a possible implementation manner, the cooling cavity includes a first cavity, the first cavity is used for performing the first cooling process, a first cooling table is disposed in the first cavity, the first cooling table has a plurality of retractable holes, a lifting device is further disposed in the first cooling table, the lifting device has a lifting pin, the lifting device is used for driving the lifting pin to extend out of the first cooling table along the retractable holes, the first cooling table is used for receiving the semiconductor structure through the lifting pin, a first channel is further disposed in the first cooling table, and the first channel is used for allowing a cooling liquid to pass through at a first flow rate, so that the semiconductor structure is cooled to the first preset value;
the cooling cavity further comprises a second cavity body, the second cavity body is used for performing the second cooling treatment, a second cooling table for receiving the semiconductor structure is arranged in the second cavity body, a second channel is arranged in the second cooling table, and cooling liquid passes through the second channel at a second flow rate so as to cool the semiconductor structure to the second preset value;
the first flow rate is less than or equal to the second flow rate.
In a possible implementation manner, a first gas inlet pipe is further disposed in the first cavity, and the first gas inlet pipe allows a working gas to pass through at a first gas flow rate so as to cool the semiconductor structure to the first preset value, where a maximum gas pressure of the working gas is a first gas pressure value;
a second air inlet pipe is further arranged in the second cavity, working gas passes through the second air inlet pipe at a second gas flow rate, so that the semiconductor structure is cooled to the second preset value, and the maximum air pressure of the working gas is a second air pressure value;
the first gas pressure value is less than or equal to the second gas pressure value, and the first gas flow rate is less than or equal to the second gas flow rate.
In a possible implementation manner, the cooling device includes a cooling cavity, a cooling table is disposed in the cooling cavity, the cooling table has a plurality of telescopic holes, a lifting device is further disposed in the cooling table, the lifting device has a lifting needle, a channel for passing a cooling liquid is disposed in the cooling table, the cooling cavity further includes a control device, a first valve is further disposed in the channel, and the control device is connected to the first valve;
the lifting device is used for driving the lifting needle to extend out of the cooling table along the telescopic hole, the cooling table is used for bearing the semiconductor structure through the lifting needle, and the control device is used for controlling the cooling liquid to pass through the channel at a first flow rate;
the lifting device is further used for driving the lifting needle to descend into the cooling table along the telescopic hole, the cooling table is further used for directly bearing the semiconductor structure, and the control device is further used for controlling the cooling liquid to pass through the channel at a second flow rate; the first flow rate is less than or equal to the second flow rate.
In a possible implementation manner, the cooling cavity further comprises a third air inlet pipe for introducing working gas, the third air inlet pipe is further provided with a second valve, the control device is connected with the second valve,
the control device is also used for controlling the maximum air pressure of the working gas to be a first air pressure value, and the gas flow rate of the working gas to be a first gas flow rate;
the control device is also used for controlling the maximum air pressure of the working gas to be a second air pressure value, and the gas flow rate of the working gas is a second gas flow rate; the first gas pressure value is less than or equal to the second gas pressure value, and the first gas flow rate is less than or equal to the second gas flow rate.
In a possible implementation manner, the reaction chamber includes a reaction table, the reaction table is used for heating and placing the semiconductor structure on the reaction table, a fourth air inlet pipe is further arranged in the reaction chamber, and the fourth air inlet pipe is used for introducing reaction gas to form the work function layer.
In one possible implementation, the reactant gases include titanium tetrachloride and ammonia, and the working gas includes nitrogen. The embodiment of the application provides a method for manufacturing a semiconductor structure, which comprises the following steps: providing a substrate; forming a grid dielectric layer, wherein the grid dielectric layer covers the substrate; forming a work function layer, wherein the work function layer covers the grid dielectric layer; performing first temperature reduction treatment to cool the substrate to a first preset temperature, wherein the temperature variation per unit time in the first temperature reduction treatment is a first rate; and carrying out second temperature reduction treatment to cool the substrate to a second preset temperature, wherein the temperature variation of the unit time in the second temperature reduction treatment is a second rate, the first rate is less than the second rate, and the second preset temperature is less than the first preset temperature. Through carrying out first cooling treatment for the substrate carries out the slow cooling earlier, then carries out the second cooling stage again, makes the substrate cool down to the second and predetermines the temperature, avoids leading to the cracked grid dielectric layer because of the difference in temperature is too big, thereby reduces the electric leakage phenomenon of grid structure.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic flow chart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;
FIG. 2 is a graph illustrating temperature variation of a temperature reduction process in a semiconductor structure fabrication method according to the related art;
fig. 3 is a temperature variation graph of a temperature reduction process of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;
FIG. 4 is a first schematic structural diagram of a semiconductor structure processing apparatus according to an embodiment of the present disclosure;
FIG. 5 is a schematic view of the reaction chamber shown in FIG. 4;
FIG. 6 is a schematic structural view of the first chamber shown in FIG. 4;
FIG. 7 is a schematic structural view of the second chamber shown in FIG. 4;
fig. 8 is a second schematic structural diagram of a semiconductor structure processing apparatus according to an embodiment of the present disclosure;
fig. 9 is a schematic structural view of the cooling cavity in fig. 8.
Description of reference numerals:
10. a semiconductor structure; 11. a substrate; 12. a gate dielectric layer; 13. a work function layer;
20. a reaction chamber; 21. a reaction platform; 22. a fourth intake pipe;
30. cooling the cavity; 301. a first cavity; 31. a first cooling stage; 311. a lifting device; 312. a first channel; 32. a first intake pipe; 302. a second cavity; 33. a second cooling stage; 332. a second channel; 34. a second intake pipe; 35. a cooling table; 351. a lifting device; 352. a channel; 36. a third intake pipe;
40. carrying an arm;
50. and a processing table.
Detailed Description
For clear understanding of the technical solutions of the present application, the solutions of the related art will be described in detail first.
The MOS tube comprises a substrate and a grid structure arranged on the surface of the substrate, wherein the grid structure comprises a grid dielectric layer, a work function layer and a grid conducting layer, the grid dielectric layer is located between the work function layer and the substrate, and the grid conducting layer covers the work function layer.
In the related art, after the gate dielectric layer is formed, the film structure needs to be transferred into a high temperature processing chamber and placed on a reaction platform of the high temperature processing chamber, and a reaction gas is introduced above the reaction platform, so as to cover the gate dielectric layer to form a work function layer. After the work function layer is formed, the film structure needs to be transferred into a cooling chamber and placed on a cooling table in the cooling chamber, and the cooling table can be cooled by water cooling. However, in the cooling process, the substrate is easily warped and deformed due to an excessively fast cooling rate, so that the gate dielectric layer is broken, and the leakage phenomenon of the gate structure is caused.
In view of the above, embodiments of the present disclosure provide a method for fabricating a semiconductor structure and a semiconductor structure processing apparatus, after forming a work function layer, performing a first temperature reduction process to cool a substrate to a first predetermined temperature, where a temperature variation per unit time in the first temperature reduction process is a first rate; and carrying out second temperature reduction treatment to cool the substrate to a second preset temperature, wherein the temperature variation of the unit time in the second temperature reduction treatment is a second rate, the first rate is less than the second rate, and the second preset temperature is less than the first preset temperature. Through carrying out first cooling treatment for the substrate slowly cools down, then carries out the second cooling stage again, makes the substrate cool down to the second and predetermines the temperature, is favorable to avoiding the cracked gate dielectric layer, thereby reduces the electric leakage phenomenon of gate structure.
In order to make the aforementioned objects, features and advantages of the embodiments of the present application more comprehensible, embodiments of the present application are described in detail below with reference to the accompanying drawings. It is to be understood that the described embodiments are merely a few embodiments of the present application and not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without any creative effort belong to the protection scope of the present application.
As shown in fig. 1, the method for manufacturing a semiconductor structure in this embodiment specifically includes:
step S101, providing a substrate.
In the present embodiment, referring to the semiconductor structure 10 in fig. 5, the substrate 11 may be a semiconductor substrate 11, such as silicon or silicon germanium (SiGe) of single crystal silicon, polycrystalline silicon or amorphous structure, or a mixed semiconductor structure, such as silicon carbide, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, an alloy semiconductor, or a combination thereof. The present embodiment is not limited thereto.
And S102, forming a grid dielectric layer, wherein the grid dielectric layer covers the substrate.
It is noted that the gate dielectric Layer 12 may be formed by at least one of In-Situ steam oxidation (ISSG), chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), rapid Thermal Chemical Vapor Deposition (RTCVD).
In this embodiment, the second layer may be formed by an in-situ steam oxidation processSilicon oxide serves as the gate dielectric layer 12. Specifically, hydrogen (H) gas may be used 2 ) Oxygen (O) 2 ) Dinitrogen monoxide (N) 2 O) as a reaction gas, and a chemical reaction similar to detonation occurs on the surface of the silicon wafer in a high-temperature atmosphere in the reaction chamber 20, so that defects in the finally obtained oxide film are reduced, and the gate dielectric layer 12 with uniform thickness is formed. In this embodiment, the gate dielectric layer 12 is formed to have a thickness of 2nm to 20nm, so that the gate dielectric layer 12 can isolate the substrate 11 from the gate conductive layer.
And S103, forming a work function layer, wherein the work function layer covers the grid dielectric layer.
The work function of the work function layer 13 is close to the work function of the semiconductor structure 10, which is beneficial to reducing the work function difference between the semiconductor structure 10 and the gate structure, so as to improve the performance of the semiconductor structure 10.
Note that the work function layer 13 may be formed by at least one of atomic Vapor Deposition, chemical Vapor Deposition, sequential Flow Deposition (SFD), and Metal-organic Chemical Vapor Deposition (MOCVD).
In this embodiment, the work function layer 13 may be formed by an atomic vapor deposition process, and referring to fig. 5, the step of forming the work function layer 13 includes: the semiconductor structure 10 is transferred to the reaction chamber 20. The reaction chamber 20 includes a reaction stage 21 for carrying the substrate 11, and the reaction stage 21 is for heating the substrate 11.
After the semiconductor structure 10 is placed on the reaction platform 21, the substrate 11 can be heated by means of thermal conduction in the reaction platform 21, and simultaneously the gate dielectric layer 12 covering the substrate 11 is heated, so as to provide forming conditions for the subsequent formation of the work function layer 13. The reaction table 21 can be realized by one of electric heating, laser heating, frequency heating, and the like.
In this embodiment, the step of forming the work function layer 13 further includes: after the substrate 11 is transferred to the reaction chamber 20, a reaction gas is introduced over the reaction table 21 to form the work function layer 13.
Alternatively, the reaction gas may include titanium tetrachloride and ammonia gas to form the work function layer 13, which may be titanium nitride (TiN). Specifically, titanium tetrachloride and ammonia react chemically under heating to form titanium nitride on the surface of the gate dielectric layer 12.
Step S104, a first temperature reduction process is performed to cool the substrate to a first preset temperature, and a temperature variation per unit time in the first temperature reduction process is a first rate.
It should be noted that after the work-function layer 13 is deposited in a high temperature environment, the temperature of the work-function layer 13 is lowered to room temperature to facilitate the next operation of taking the semiconductor structure 10 out of the device.
By performing the first temperature reduction process, the substrate 11 can be cooled to the first predetermined temperature, and at the same time, the gate dielectric layer 12 and the work function layer 13 covering the substrate 11 can also be cooled to the first predetermined temperature. It should be noted that the first temperature reduction process may be performed in the reaction chamber 20, and may of course be performed in other chambers. For example, in this embodiment, the first temperature reduction process may be performed in the cooling chamber. The first temperature reduction treatment process can adopt water cooling, air cooling or a combination mode of the water cooling and the air cooling to be cooled to a first preset temperature.
And step S105, performing a second temperature reduction treatment to cool the substrate to a second preset temperature, wherein the temperature variation per unit time in the second temperature reduction treatment is a second rate, the first rate is smaller than the second rate, and the second preset temperature is smaller than the first preset temperature.
By performing the second temperature reduction process, the substrate 11 can be cooled from the first preset temperature to the second preset temperature, and at the same time, the gate dielectric layer 12 and the work function layer 13 covering the substrate 11 can also be cooled from the first preset temperature to the second preset temperature. Wherein the second predetermined temperature is the room temperature at which the work function layer 13 is lowered. It should be noted that the second temperature reduction treatment is performed in the cooling cavity, and the second temperature reduction treatment process may be performed by water cooling, air cooling, or a combination thereof to be cooled to a second preset temperature.
The following describes the processes of performing the first temperature reduction process and the second temperature reduction process in this embodiment with reference to fig. 2 and fig. 3.
As shown in fig. 2, in the related art, the temperature of the work function layer 13 is reduced to the second predetermined temperature by directly performing the temperature reduction process, and the temperature variation is Δ T.
As shown in fig. 3, in this embodiment, the first temperature reduction process and the second temperature reduction process are performed successively, so that the temperature of the work function layer 13 can be reduced to a first preset temperature, and then reduced to a second preset temperature from the first preset temperature. Since the first rate is lower than the second rate, the first temperature reduction process performs a slow temperature reduction operation with respect to the second temperature reduction process. When the first temperature lowering treatment is performed, the temperature change amount is Δ T 1 When the second temperature lowering treatment is performed, the temperature change amount is Δ T 2 And Δ T 1 And Δ T 2 Is equal to deltat. It is thus clear that, compare in prior art, this embodiment is when carrying out cooling treatment, and temperature variation reduces, avoids warping and warping the deformation because of the too big wafer that leads to of the temperature difference to avoid grid dielectric layer 12 to take place fragmentation.
It should be noted that, in the embodiment, the first temperature reduction process is used to perform slow temperature reduction, so as to reduce the temperature variation of the second temperature reduction process. In other examples, the temperature may be slowly decreased to the first preset temperature through a plurality of times of the first temperature decrease process.
The embodiment of the application provides a manufacturing method of a semiconductor structure, which comprises the following steps: providing a substrate 11; forming a gate dielectric layer 12, wherein the gate dielectric layer 12 covers the substrate 11; forming a work function layer 13, wherein the work function layer 13 covers the grid dielectric layer 12; performing a first temperature reduction process to cool the substrate 11 to a first preset temperature, wherein a temperature variation per unit time in the first temperature reduction process is a first rate; a second temperature reduction process is performed to cool the substrate 11 to a second preset temperature, in which the temperature change amount per unit time is a second rate, the first rate is smaller than the second rate, and the second preset temperature is smaller than the first preset temperature. Through carrying out first cooling treatment for substrate 11 carries out the slow cooling at first, then carries out the second cooling stage again, makes substrate 11 cool down to the second and predetermines the temperature, avoids leading to grid dielectric layer 12 cracked because of the difference in temperature is too big, thereby reduces the electric leakage phenomenon of grid structure.
In this embodiment, after the work function layer 13 is formed, the first temperature reduction process is performed by transferring the substrate 11 into a cooling chamber.
In a possible implementation manner, referring to fig. 4, the cooling chamber 30 may include a first chamber 301 for performing a first temperature reduction process and a second chamber 302 for performing a second temperature reduction process, a first cooling stage 31 is disposed in the first chamber 301, and a second cooling stage 33 is disposed in the second chamber 302, so that the substrate 11 needs to be transferred to the first cooling stage 31 during the first temperature reduction process, and the substrate 11 needs to be transferred to the second cooling stage 33 during the second temperature reduction process. The transfer process may use a carrying arm 40 commonly used in the related art.
Optionally, the step of performing the first temperature reduction process to cool the substrate 11 to the first preset temperature includes: transferring the substrate 11 to the first cavity 301; the first chamber 301 includes a first cooling stage 31 for carrying the substrate 11, the first cooling stage 31 has a lifting device 311 thereon, and the lifting device 311 is used for receiving the substrate 11, so that a predetermined height is provided between the substrate 11 and the first cooling stage 31.
As shown in fig. 6, the lifting device 311 may have a lifting pin, and accordingly, the first cooling stage 31 has a telescopic hole, and the lifting device 311 is configured to drive the lifting pin to extend out of the first cooling stage 31 along the telescopic hole, so that the lifting pin can receive the substrate and provide a predetermined height between the substrate 11 and the first cooling stage 31.
The step of performing the first temperature reduction process to cool the substrate 11 to the first preset temperature further includes: after transferring the substrate 11 to the first chamber 301, a cooling liquid is introduced into the first cooling stage 31 at a first flow rate until the substrate 11 is cooled to a first preset temperature.
By passing a cooling liquid through the first cooling stage 31, the first cooling stage 31 can cool the substrate 11 and can cool the gate dielectric layer 12 and the work function layer 13 covering the surface of the substrate 11. Because the substrate 11 and the first cooling platform 31 have a preset height, the substrate 11 can be prevented from directly contacting the first cooling platform 31, and therefore the first cooling treatment process can be slowly cooled.
The step of performing the first temperature reduction process to cool the substrate 11 to the first preset temperature further includes: the cooling liquid is introduced into the first cooling table 31 at a first flow rate, and the working gas is introduced above the first cooling table 31 at a first gas flow rate, wherein the maximum gas pressure of the working gas is a first gas pressure value.
Optionally, the working gas comprises nitrogen. By introducing the working gas, a part of the heat of the substrate 11 can be taken away, thereby further cooling the substrate 11. At the same time, the working gas can also provide a gas atmosphere for the cooling process of the work function layer 13.
It should be noted that, in some other examples, the lifting device 311 may also be configured to drive the lifting pins to enter the first cooling stage 31 along the telescopic holes, so that the first cooling stage 31 directly receives the substrate 11, and at this time, there is no preset height between the substrate 11 and the first cooling stage 31, and the flow rate of the cooling liquid in the first cooling stage 31 is controlled to be smaller than the first flow rate, so as to control the gate dielectric layer 12 to perform slow cooling.
Optionally, as shown in fig. 7, after performing the first temperature-reducing process to cool the substrate to the first preset temperature, the step of performing the second temperature-reducing process to cool the substrate to the second preset temperature includes: transferring the substrate 11 to the second chamber 302; the second chamber 302 includes a second cooling stage 33 for receiving the substrate 11.
In some examples, the second cooling stage 33 may have a lifting device that, after receiving the substrate 11, is also used to move along the extension hole into the interior of the second cooling stage 33 so that the second cooling stage 33 directly receives the substrate 11. Of course, in some other examples, the second cooling stage 33 may omit the lifting device, so that the second cooling stage 33 directly receives the substrate 11. So that the second rate in the second temperature-reducing treatment process is greater than the first rate in the first temperature-reducing treatment process.
The step of performing the second temperature reduction process to cool the substrate 11 to the second preset temperature further includes: after transferring the substrate 11 to the second cooling stage 33, passing a cooling liquid at a second flow rate through the second cooling stage 33 until the substrate 11 is cooled to a second predetermined temperature; the first flow rate is less than or equal to the second flow rate.
By supplying the cooling liquid into the second cooling stage 33, the second cooling stage 33 can cool the substrate 11 and can cool the gate dielectric layer 12 and the work function layer 13 covering the surface of the substrate 11. Since the second cooling stage 33 receives the substrate 11, the substrate 11 is directly brought into contact with the first cooling stage 31, so that the second rate in the second temperature-decreasing process is greater than the first rate in the first temperature-decreasing process.
Further, the second flow rate of the cooling liquid in the second cooling table 33 is greater than the first flow rate in the first cooling table 31, so that the second rate in the second cooling process is further increased, and the cooling process of the second cooling process is further accelerated.
The step of performing the second temperature reduction process to cool the substrate 11 to the second preset temperature further includes: introducing working gas at a second gas flow rate above the second cooling table 33 while introducing cooling liquid at a second flow rate into the second cooling table 33, wherein the maximum gas pressure of the working gas is a second gas pressure value; the first gas pressure value is less than or equal to the second gas pressure value, and the first gas flow rate is less than or equal to the second gas flow rate.
By introducing the working gas, the substrate 11 can be further cooled. At the same time, the working gas also provides a gaseous atmosphere for the cooling process of the substrate 11. Specifically, the working gas may include nitrogen and a small amount of oxygen.
Furthermore, because the first air pressure value is less than or equal to the second air pressure value, and the flow rate of the first gas is less than or equal to the flow rate of the second gas, the second speed in the second temperature reduction treatment process is further improved, and the temperature reduction process of the second temperature reduction treatment is further accelerated.
In another possible implementation manner, as shown in fig. 8 and 9, only the first cooling stage 31 is disposed in the cooling chamber 30, the first cooling stage 31 is used for performing the first temperature reduction process and the second temperature reduction process, and after the first temperature reduction process is completed, the substrate 11 does not need to be transferred, and the second temperature reduction process is continued on the first cooling stage 31.
Optionally, after performing the first temperature reduction process to cool the substrate 11 to the first preset temperature, performing the second temperature reduction process to cool the substrate 11 to the second preset temperature includes: the lift device 311 is moved into the first cooling stage 31 until the first cooling stage 31 receives the substrate 11.
The first cooling stage 31 may have a lifting device 311, the lifting device 311 may have a lifting pin, and accordingly, the first cooling stage 31 has a telescopic hole, and the lifting device 311 is configured to drive the lifting pin to extend out of the first cooling stage 31 along the telescopic hole, so that the lifting pin can receive the substrate 11 and perform the first temperature reduction process. After the first temperature reduction process, the lifting device 311 is further configured to drive the lifting pins to move along the telescopic holes to the inside of the first cooling stage 31, so that the first cooling stage 31 directly receives the substrate 11. So that the second rate in the second temperature-reducing treatment process is greater than the first rate in the first temperature-reducing treatment process.
The step of performing the first temperature reduction process to cool the substrate 11 to the first preset temperature further includes: after the lift device 311 is moved to the inside of the first cooling stage 31, a cooling liquid is introduced into the first cooling stage 31 at a second flow rate until the substrate 11 is cooled to a second preset temperature; the first flow rate is less than or equal to the second flow rate.
After the first temperature reduction treatment, the flow rate of the cooling liquid in the first cooling table 31 is changed, and the cooling liquid is introduced at a second flow rate, and the second flow rate is greater than the first flow rate, so that the second speed in the second temperature reduction treatment process is further increased, and the temperature reduction process of the second temperature reduction treatment process is further accelerated.
The step of performing the second temperature reduction process to cool the substrate 11 to the second preset temperature further includes: while the cooling liquid is introduced at a second flow rate in the first cooling stage 31, the working gas is introduced above the first cooling stage 31 at a second gas flow rate: the maximum pressure of the working gas is a second pressure value, the first pressure value is smaller than or equal to the second pressure value, and the flow rate of the first gas is smaller than or equal to the flow rate of the second gas.
Optionally, the working gas comprises nitrogen. After the first temperature lowering process is performed, the working gas above the first cooling stage 31 changes the gas flow rate and the gas pressure, further cooling the substrate 11. At the same time, the working gas also provides a gaseous atmosphere for the cooling process of the substrate 11.
Furthermore, because the first air pressure value is less than or equal to the second air pressure value, and the flow rate of the first gas is less than or equal to the flow rate of the second gas, the second speed in the second temperature reduction treatment process is further improved, and the temperature reduction process of the second temperature reduction treatment is further accelerated.
The embodiment of the application also provides semiconductor structure processing equipment which can be used for manufacturing by adopting the semiconductor structure manufacturing method.
The semiconductor structure 10 includes a substrate 11 and a gate structure disposed on the substrate 11, the gate structure including a gate dielectric layer 12, a work function layer 13, and a gate conductive layer, which are stacked. A work function layer 13 overlies the gate dielectric layer 12 and a gate conductive layer overlies the work function layer 13.
The semiconductor structure 10 processing equipment comprises a processing table 50, a reaction chamber 20, a cooling chamber 30 and a carrying arm 40, wherein the reaction chamber 20, the cooling chamber 30 and the carrying arm 40 are all connected with the processing table 50.
The reaction chamber 20 is used to form the work function layer 13 of the semiconductor structure 10.
Optionally, in this embodiment, the reaction chamber 20 forms a closed space, so that the processing operation can be performed in the reaction chamber 20. Reaction chamber 20 may include a reaction platen 21, reaction platen 21 being configured to heat semiconductor structure 10 disposed on reaction platen 21 to facilitate providing reaction conditions for the formation of work function layer 13. The reaction table 21 can be realized by one of electric heating, laser heating, frequency heating, and the like. A fourth gas inlet pipe 22 is further disposed in the reaction chamber 20, and the fourth gas inlet pipe 22 is used for introducing a reaction gas to form the work function layer 13. Illustratively, the fourth gas inlet pipe 22 is disposed above the reaction table 21, and a gas outlet of the fourth gas inlet pipe 22 faces the reaction table 21, so that the reaction gas can contact the semiconductor structure 10 placed on the reaction table 21 and form the work function layer 13 on the substrate 11.
Alternatively, the reaction gas may include titanium tetrachloride and ammonia gas to form the work function layer 13, which may be titanium nitride (TiN). Specifically, titanium tetrachloride and ammonia gas chemically react under heating, thereby forming titanium nitride on the surface of the gate dielectric layer 12. The cooling cavity 30 is configured to perform a first temperature reduction process on the semiconductor structure 10 to cool the semiconductor structure to a first preset temperature, where a temperature variation per unit time in the first temperature reduction process is a first rate, the cooling cavity 30 is further configured to perform a second temperature reduction process on the semiconductor structure 10 to cool the semiconductor structure to a second preset temperature, where the temperature variation per unit time in the second temperature reduction process is a second rate, the first rate is smaller than the second rate, and the second preset temperature is smaller than the first preset temperature.
It should be noted that after the work-function layer 13 is deposited in a high temperature environment, the temperature of the work-function layer 13 is lowered to room temperature to facilitate the next operation of taking the semiconductor structure 10 out of the device. Cooling chamber 30 may be water cooled, air cooled, or a combination thereof to cool semiconductor structure 10.
By performing the first temperature reduction process and the second temperature reduction process in the cooling cavity 30, the temperature of the work function layer 13 can be reduced to a first preset temperature, and then reduced to a second preset temperature from the first preset temperature. Since the first rate is lower than the second rate, the temperature variation per unit time in the first temperature reduction process is lower than the temperature variation per unit time in the second temperature reduction process, that is, the first temperature reduction process performs a slow temperature reduction operation with respect to the second temperature reduction process. In the second cooling process, the temperature variation is reduced, and the wafer warping deformation caused by the excessive temperature difference is avoided, so that the gate dielectric layer 12 is prevented from being cracked.
It should be noted that, in the present embodiment, the temperature change amount is reduced by two-stage cooling processing. In other examples, the temperature change amount may also be reduced by performing the cooling process three times, four times, and the like in a multi-stage manner.
The handling arm 40 is used for transferring the semiconductor structure 10 in the reaction chamber 20 to the cooling chamber 30, so that the cooling chamber 30 cools the semiconductor structure 10. The structure of the carrying arm 40 can be the same as the conventional one in the related art, and will not be described herein. For example, the semiconductor structure 10 may be picked up by a vacuum chuck on the handling arm 40 and transferred to a corresponding location.
The semiconductor structure 10 processing equipment provided by the embodiment of the application comprises a processing table 50, a reaction cavity 20, a cooling cavity 30 and a carrying arm 40, wherein the reaction cavity 20, the cooling cavity 30 and the carrying arm 40 are all connected with the processing table 50. The reaction chamber 20 is used for forming the work function layer 13 of the semiconductor structure 10; the cooling cavity 30 is configured to perform a first temperature reduction process on the semiconductor structure 10 to cool the semiconductor structure to a first preset temperature, where a temperature variation per unit time in the first temperature reduction process is a first rate, the cooling cavity 30 is further configured to perform a second temperature reduction process on the semiconductor structure 10 to cool the semiconductor structure to a second preset temperature, where the temperature variation per unit time in the second temperature reduction process is a second rate, the first rate is smaller than the second rate, and the second preset temperature is smaller than the first preset temperature; the handling arm 40 is used to transfer the semiconductor structure 10 in the reaction chamber 20 to the cooling chamber 30. The manufacturing method of the semiconductor structure 10 needs to use the processing equipment of the semiconductor structure 10 for manufacturing, and the substrate 11 is slowly cooled first by performing the first cooling process, and then is cooled to the second preset temperature by performing the second cooling stage, so that the substrate 11 is cooled to the second preset temperature, the gate dielectric layer 12 is prevented from being cracked due to the overlarge temperature difference, and the electric leakage phenomenon of the gate structure is reduced.
In one possible implementation, as shown in fig. 4, 5, 6 and 7, the cooling chamber 30 may include a first cooling stage 31 for performing a first temperature reduction process, in which the substrate 11 needs to be transferred onto the first cooling stage 31, and a second cooling stage 33 for performing a second temperature reduction process, in which the substrate 11 needs to be transferred onto the second cooling stage 33. The transfer process may use the transfer arm 40 in this embodiment.
Illustratively, a first cooling stage 31 is disposed in the first cavity 301, the first cooling stage 31 has a plurality of retractable holes, a lifting device 311 is further disposed in the first cooling stage 31, the lifting device 311 has lifting pins, the lifting device 311 is configured to drive the lifting pins to extend out from the first cooling stage 31 along the retractable holes, and the first cooling stage 31 is configured to receive the semiconductor structure 10 through the lifting pins, so that a certain preset distance is provided between the semiconductor structure 10 and the first cooling stage 31. Because the substrate 11 and the first cooling platform 31 have a preset height, the substrate 11 can be prevented from directly contacting the first cooling platform 31, and therefore the first cooling treatment process can be slowly cooled.
The first cooling stage 31 further has a first channel 312 inside, and the first channel 312 allows a cooling liquid to pass through at a first flow rate, so as to cool the semiconductor structure 10 to a first preset value. By passing a cooling liquid through the first cooling stage 31, the first cooling stage 31 can cool the substrate 11 and can cool the gate dielectric layer 12 and the work function layer 13 covering the surface of the substrate 11. Because the substrate 11 and the first cooling platform 31 have a preset height, the substrate 11 can be prevented from directly contacting the first cooling platform 31, and therefore the first cooling treatment process can be slowly cooled.
Illustratively, a second cooling stage 33 for receiving the semiconductor structure 10 is disposed in the second cavity 302, the second cooling stage 33 has a second channel 332 therein, and the second channel 332 allows a cooling liquid to pass therethrough at a second flow rate, so as to cool the semiconductor structure 10 to a second preset value; the first flow rate is less than or equal to the second flow rate.
By passing a cooling liquid through the second cooling stage 33, the second cooling stage 33 can cool the substrate 11 and can cool the gate dielectric layer 12 and the work function layer 13 covering the surface of the substrate 11. Since the second cooling stage 33 receives the substrate 11, the substrate 11 is directly brought into contact with the first cooling stage 31, so that the second rate in the second temperature-decreasing process is greater than the first rate in the first temperature-decreasing process.
In an embodiment where the cooling cavity 30 includes a first cavity 301 and a second cavity 302, a first gas inlet pipe 32 is further disposed in the first cavity 301, the first gas inlet pipe 32 allows the working gas to pass through at a first gas flow rate, so as to cool the semiconductor structure 10 to a first preset value, and the maximum gas pressure of the working gas is a first gas pressure value.
For example, the first gas inlet pipe 32 may be connected to a sidewall of the first chamber 301, and the substrate 11 may be further cooled by introducing the working gas during the first temperature reduction process. Optionally, the working gas comprises nitrogen, and the working gas can also provide a gas atmosphere for the cooling process of the substrate 11.
A second air inlet pipe 34 is further disposed in the second cavity 302, and the second air inlet pipe 34 allows the working gas to pass through at a second gas flow rate, so that the semiconductor structure 10 is cooled to a second preset value, and the maximum pressure of the working gas is a second pressure value; the first gas pressure value is less than or equal to the second gas pressure value, and the first gas flow rate is less than or equal to the second gas flow rate.
For example, the second inlet pipe 34 may be connected to a sidewall of the second chamber 302, and similarly, the substrate 11 may be further cooled by introducing the working gas during the second temperature reduction process. Optionally, the working gas comprises nitrogen, and the working gas can also provide a gas atmosphere for the cooling process of the substrate 11.
Furthermore, because the first air pressure value is less than or equal to the second air pressure value, and the flow rate of the first gas is less than or equal to the flow rate of the second gas, the second speed in the second temperature reduction treatment process is further improved, and the temperature reduction process of the second temperature reduction treatment is further accelerated.
In another possible implementation manner, as shown in fig. 8 and 9, only the cooling stage 35 is disposed in the cooling chamber 30, and the cooling stage 35 is used for performing the first temperature reduction process and the second temperature reduction process at the same time, and after the first temperature reduction process is completed, the substrate 11 does not need to be transferred, and the second temperature reduction process is continued on the cooling stage 35.
Illustratively, the cooling platform 35 has a plurality of telescopic holes, and a lifting device 351 is further provided in the cooling platform 35, wherein the lifting device 351 has a lifting pin, so that the lifting pin is driven by the lifting device 351 to move along the telescopic holes. The cooling stage 35 has a passage 352 therein through which a cooling liquid passes. A control device is also arranged in the cooling chamber 30, and a first valve is also arranged in the channel 352, and the control device is connected with the first valve.
When first cooling is performed, the lifting device 351 drives the lifting pins to extend out from the cooling platform 35 along the telescopic holes, so that the cooling platform 35 can receive the semiconductor structure 10 through the lifting pins, and a certain preset distance is reserved between the cooling platform 35 and the semiconductor structure 10. The control device is configured to control the flow of cooling fluid through the channel 352 at a first flow rate. Specifically, the control device may control the flow rate of the coolant flowing through the first valve by controlling the flow rate of the first valve.
When carrying out the second cooling and handling, elevating gear 351 drives the lift needle and descends to inside cooling platform 35 along the shrinkage cavity, and the cooling platform 35 of being convenient for directly accepts semiconductor structure 10, does not have the distance of predetermineeing between cooling platform 35 and the semiconductor structure 10 this moment to make the second speed in the second cooling and handling process be greater than the first speed in the first cooling and handling process. The control means is also operable to control the passage of cooling fluid through the passage 352 at a second flow rate. Similarly, the control means may control the flow rate of the cooling liquid flowing through the first valve by controlling the flow rate of the first valve.
It should be noted that the first flow rate is less than or equal to the second flow rate, so as to further increase the second rate in the second temperature reduction process, and further accelerate the temperature reduction process of the second temperature reduction process.
In the embodiment where only one cooling stage 35 is disposed in the cooling chamber 30, the cooling chamber 30 further includes a third air inlet pipe 36 for introducing the working gas, the third air inlet pipe 36 is further provided with a second valve, and the control device is connected to the second valve.
Illustratively, the third intake pipe 36 may be connected to a sidewall of the cooling cavity 30. The substrate 11 can be further cooled by introducing the working gas in the second temperature reduction treatment process. Optionally, the working gas comprises nitrogen, and the working gas can also provide a gas atmosphere for the cooling process of the substrate 11.
When the first temperature reduction treatment is carried out, the control device is also used for controlling the maximum air pressure of the working gas to be a first air pressure value, and the gas flow rate of the working gas to be a first gas flow rate. Specifically, the control device may control the flow rate and pressure of the working gas flowing through the second valve by controlling the flow rate of the second valve.
And when the second temperature reduction treatment is carried out, the control device is also used for controlling the maximum air pressure of the working gas to be a second air pressure value, and the gas flow rate of the working gas to be a second gas flow rate. Similarly, the control means may control the gas flow rate and pressure of the working gas flowing through the second valve by controlling the flow of the second valve.
It should be noted that the first air pressure value is less than or equal to the second air pressure value, and the flow rate of the first gas is less than or equal to the flow rate of the second gas, so as to further increase the second rate in the second temperature reduction process, and further accelerate the temperature reduction process of the second temperature reduction process.
It is obvious to those skilled in the art that, for convenience and simplicity of description, the foregoing division of the functional modules is merely used as an example, and in practical applications, the above function distribution may be performed by different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to perform all or part of the above described functions. For the specific working process of the device described above, reference may be made to the corresponding process in the foregoing method embodiment, which is not described herein again.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.
Claims (16)
1. A method for fabricating a semiconductor structure, comprising:
providing a substrate;
forming a grid dielectric layer, wherein the grid dielectric layer covers the substrate;
forming a work function layer, wherein the work function layer covers the grid dielectric layer;
performing first temperature reduction treatment to cool the substrate to a first preset temperature, wherein the temperature variation per unit time in the first temperature reduction treatment is a first rate;
and carrying out second cooling treatment to cool the substrate to a second preset temperature, wherein the temperature variation of unit time in the second cooling treatment is a second rate, the first rate is less than the second rate, and the second preset temperature is less than the first preset temperature.
2. The method of claim 1, wherein performing a first cool-down process to cool the substrate to a first predetermined temperature comprises:
transferring the substrate to a first chamber; a first cooling table for bearing the substrate is arranged in the first cavity, a lifting device is arranged on the first cooling table, and the lifting device is used for bearing the substrate, so that a preset height is formed between the substrate and the first cooling table;
and introducing cooling liquid into the first cooling table at a first flow speed until the substrate is cooled to the first preset temperature.
3. The method of fabricating a semiconductor structure according to claim 2,
and introducing working gas above the first cooling table at a first gas flow rate, wherein the maximum gas pressure of the working gas is a first gas pressure value.
4. The method of claim 3, wherein performing a second cool-down process to cool the substrate to a second predetermined temperature comprises:
transferring the substrate to a second cavity; a second cooling table for receiving the substrate is arranged in the second cavity;
introducing cooling liquid into the second cooling table at a second flow rate until the substrate is cooled to the second preset temperature; the first flow rate is less than or equal to the second flow rate.
5. The method of fabricating a semiconductor structure according to claim 4,
introducing working gas above the second cooling table at a second gas flow rate, wherein the maximum gas pressure of the working gas is a second gas pressure value; the first gas pressure value is less than or equal to the second gas pressure value, and the first gas flow rate is less than or equal to the second gas flow rate.
6. The method of claim 3, wherein performing a second cool-down process to cool the substrate to a second predetermined temperature comprises:
moving the lifting device to the interior of the first cooling table until the first cooling table receives the substrate;
introducing cooling liquid into the first cooling table at a second flow rate until the substrate is cooled to a second preset temperature; the first flow rate is less than or equal to the second flow rate.
7. The method of claim 6, wherein the step of forming the semiconductor structure comprises,
introducing working gas above the first cooling table at a second gas flow rate: the maximum air pressure of the working gas is a second air pressure value, the first air pressure value is smaller than or equal to the second air pressure value, and the flow rate of the first gas is smaller than or equal to the flow rate of the second gas.
8. The method for fabricating a semiconductor structure according to claim 5 or 7, wherein forming a work function layer comprises:
transferring the substrate to a reaction chamber; the reaction cavity comprises a reaction table for bearing the substrate, and the reaction table is used for heating the substrate;
and introducing reaction gas above the reaction platform to form the work function layer.
9. The method of claim 8, wherein said reactant gases comprise titanium tetrachloride and ammonia, and wherein said working gas comprises nitrogen.
10. A semiconductor structure processing apparatus, comprising: the device comprises a processing table, a reaction cavity, a cooling cavity and a carrying arm, wherein the reaction cavity, the cooling cavity and the carrying arm are all connected with the processing table;
the reaction cavity is used for forming a work function layer of the semiconductor structure;
the cooling cavity is used for carrying out first cooling treatment on the semiconductor structure so as to cool the semiconductor structure to a first preset temperature, wherein the temperature variation per unit time in the first cooling treatment is a first rate, the cooling cavity is also used for carrying out second cooling treatment on the semiconductor structure so as to cool the semiconductor structure to a second preset temperature, the temperature variation per unit time in the second cooling treatment is a second rate, the first rate is smaller than the second rate, and the second preset temperature is smaller than the first preset temperature;
the carrying arm is used for transferring the semiconductor structure in the reaction cavity to the cooling cavity.
11. The semiconductor structure processing apparatus of claim 10,
the cooling cavity comprises a first cavity body, the first cavity body is used for carrying out first cooling treatment, a first cooling table is arranged in the first cavity body, the first cooling table is provided with a plurality of telescopic holes, a lifting device is further arranged in the first cooling table, the lifting device is provided with a lifting needle, the lifting device is used for driving the lifting needle to extend out of the first cooling table along the telescopic holes, the first cooling table is used for bearing the semiconductor structure through the lifting needle, a first channel is further arranged in the first cooling table, and cooling liquid passes through the first channel at a first flow rate so as to cool the semiconductor structure to the first preset temperature;
the cooling cavity further comprises a second cavity, the second cavity is used for performing the second cooling treatment, a second cooling table for receiving the semiconductor structure is arranged in the second cavity, a second channel is arranged in the second cooling table, and cooling liquid passes through the second channel at a second flow rate so as to cool the semiconductor structure to the second preset temperature;
the first flow rate is less than or equal to the second flow rate.
12. The semiconductor structure processing apparatus according to claim 11, wherein a first gas inlet pipe is further disposed in the first chamber, the first gas inlet pipe being configured to allow a working gas to pass therethrough at a first gas flow rate so as to cool the semiconductor structure to the first predetermined temperature, and a maximum gas pressure of the working gas is a first gas pressure value;
a second air inlet pipe is further arranged in the second cavity, working gas passes through the second air inlet pipe at a second gas flow rate, so that the semiconductor structure is cooled to the second preset temperature, and the maximum air pressure of the working gas is a second air pressure value;
the first gas pressure value is less than or equal to the second gas pressure value, and the first gas flow rate is less than or equal to the second gas flow rate.
13. The semiconductor structure processing apparatus according to claim 10, wherein a cooling stage is disposed in the cooling chamber, the cooling stage has a plurality of retractable holes, the cooling stage further has a lifting device therein, the lifting device has a lifting pin, the cooling stage has a channel therein through which a cooling liquid passes, the cooling chamber further includes a control device, the channel further has a first valve disposed therein, and the control device is connected to the first valve;
the lifting device is used for driving the lifting needle to extend out of the cooling table along the telescopic hole, the cooling table is used for bearing the semiconductor structure through the lifting needle, and the control device is used for controlling the cooling liquid to pass through the channel at a first flow rate;
the lifting device is further used for driving the lifting needle to descend into the cooling table along the telescopic hole, the cooling table is further used for directly bearing the semiconductor structure, and the control device is further used for enabling the cooling liquid to pass through the channel at a second flow rate;
the first flow rate is less than or equal to the second flow rate.
14. The semiconductor structure processing apparatus according to claim 13, further comprising a third gas inlet pipe for introducing a working gas into the cooling chamber, wherein the third gas inlet pipe is further provided with a second valve, and wherein the control device is connected to the second valve,
the control device is also used for controlling the maximum air pressure of the working gas to be a first air pressure value, and the gas flow rate of the working gas to be a first gas flow rate;
the control device is also used for controlling the maximum air pressure of the working gas to be a second air pressure value, and the gas flow rate of the working gas is a second gas flow rate;
the first gas pressure value is less than or equal to the second gas pressure value, and the first gas flow rate is less than or equal to the second gas flow rate.
15. The semiconductor structure processing apparatus according to claim 12 or 14, wherein the reaction chamber comprises a reaction stage for heating the semiconductor structure placed on the reaction stage, and a fourth gas inlet pipe is further provided in the reaction chamber for introducing a reaction gas to form the work function layer.
16. The semiconductor structure processing apparatus of claim 15, wherein the reactant gases comprise titanium tetrachloride and ammonia, and the working gas comprises nitrogen.
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| CN202111063143.3A CN115799055A (en) | 2021-09-10 | 2021-09-10 | Semiconductor structure manufacturing method and semiconductor structure processing equipment |
| PCT/CN2022/091210 WO2023035639A1 (en) | 2021-09-10 | 2022-05-06 | Manufacturing method for semiconductor structure, and treatment device for semiconductor structure |
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| CN202111063143.3A CN115799055A (en) | 2021-09-10 | 2021-09-10 | Semiconductor structure manufacturing method and semiconductor structure processing equipment |
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| US6492712B1 (en) * | 1999-06-24 | 2002-12-10 | Agere Systems Guardian Corp. | High quality oxide for use in integrated circuits |
| JP3535457B2 (en) * | 2000-09-11 | 2004-06-07 | 東京エレクトロン株式会社 | Substrate heat treatment equipment |
| CN204243004U (en) * | 2014-12-02 | 2015-04-01 | 上海和辉光电有限公司 | Heat annealing equipment |
| CN111383915B (en) * | 2018-12-28 | 2021-03-23 | 中国科学院上海微系统与信息技术研究所 | Preparation method of heterogeneous bonding structure |
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