JP2010212391A - Method of manufacturing semiconductor device and substrate processing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device that forms a high dielectric insulation film having higher dielectric constant, and to provide a substrate processing apparatus. <P>SOLUTION: The method of manufacturing the semiconductor device includes step S106 to form a high dielectric insulation film on a substrate, step S110 of applying heat treatment to the high dielectric insulation film under vacuum, and a step of holding oxygen partial pressure in a space wherein the high dielectric insulation film exists, equal to or less than the partial pressure in a space wherein the high dielectric insulation film exists during the heat treatment, until the high dielectric insulation film after the heat treatment is at a room temperature. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device and a substrate processing apparatus, and more particularly to a method and apparatus for forming a high dielectric constant insulating film used for, for example, a gate insulating film of a MOSFET or a capacitor insulating film of a DRAM.

In this type of semiconductor device manufacturing method, a silicon oxide film (SiO ₂ film), a silicon oxynitride film (SiON film), or the like is used as a gate insulating film of a MOSFET (Metal Oxide Field Effect Effect Transistor) device. . With higher integration and higher performance of devices, it is required to reduce the thickness of the gate insulating film. In silicon oxide films and silicon oxynitride films, it is possible to suppress leakage current that flows through the gate insulating film. It is becoming difficult. Therefore, application of a high dielectric constant insulating film to the gate insulating film has been studied. In addition, in a DRAM capacitor, a high dielectric constant insulating film such as a hafnium oxide film (HfO ₂ film) or an aluminum oxide film (Al ₂ O ₃ film) is used, and the dielectric constant thereof is about 15-20. (See, for example, Non-Patent Document 1 and Non-Patent Document 2). In addition, a method is known in which a film formation process and a modification process are continuously performed, and a specific element in the film formed in the film formation process is quickly removed to modify the film (for example, Patent Documents). 1).

JP 2004-158811 A

Y. K. Kim et al. Symp. VLSI Tech. 52, 1998 L. Kang et al. , IEEE Electron Device Lett. VOL. 21, no. 4,2000

  However, with further higher integration and higher performance of devices, an insulating film with a higher dielectric constant is required from the viewpoint of the equivalent oxide thickness (EOT) of the gate insulating film, and From the viewpoint of leakage current, both a high dielectric constant and a wide band gap are required.

  An object of the present invention is to provide a method for manufacturing a semiconductor device and a substrate processing apparatus for forming a high dielectric constant insulating film having a higher dielectric constant.

  According to one aspect of the present invention, there is provided a step of forming a high dielectric constant insulating film on a substrate, a step of subjecting the high dielectric constant insulating film to a heat treatment under vacuum, and the high dielectric constant insulating film after the heat treatment. Until the temperature reaches room temperature, the oxygen partial pressure in the space where the high dielectric constant insulating film exists is maintained equal to or lower than the oxygen partial pressure in the space where the high dielectric constant insulating film exists during the heat treatment. A semiconductor device manufacturing method is provided.

  According to another aspect of the present invention, a first processing chamber for forming a high dielectric constant insulating film on a substrate, a second processing chamber for performing a heat treatment on the substrate, a holding chamber for holding a substrate, and the first A transfer chamber provided between the processing chamber, the second processing chamber, and the holding chamber; and a transfer chamber for transferring a substrate between the first processing chamber, the second processing chamber, and the holding chamber; and the transfer chamber A transfer robot provided for transferring a substrate; and transferring the substrate into the first processing chamber by the transfer robot; forming a high dielectric constant insulating film on the substrate in the first processing chamber; The formed substrate is transferred from the first processing chamber to the second processing chamber by the transfer robot, and the high dielectric constant insulating film is subjected to a heat treatment under vacuum in the second processing chamber, and the substrate after the heat treatment is performed. From the second processing chamber by the transfer robot. The oxygen partial pressure in the space where the high dielectric constant insulating film is present is transferred to the room until the high dielectric constant insulating film after the heat treatment reaches room temperature. There is provided a substrate processing apparatus comprising: a controller that controls to maintain the pressure equal to or less than the pressure.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method and substrate processing apparatus of a semiconductor device which form the high dielectric constant insulating film which has a higher dielectric constant can be provided.

3 is a flowchart showing a gate stack forming process of a MOSFET according to an embodiment of the present invention. It is a plane sectional view showing a cluster device concerning an embodiment of the present invention. It is front sectional drawing which shows the film-forming apparatus which concerns on embodiment of this invention. It is front sectional drawing which shows the RTP apparatus which concerns on embodiment of this invention. It is an expanded sectional view which shows the wafer of each step. It is a figure which shows the example of a process sequence concerning an Example and a comparative example. It is a figure which shows the In-plane XRD analysis result concerning an Example and a comparative example. It is a figure which shows the relationship of the capacity-voltage characteristic concerning an Example and a comparative example. It is a figure which shows the relationship between EOT concerning an Example and a comparative example, and a physical film thickness.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a flowchart showing a MOSFET gate stack forming step in an IC manufacturing method according to an embodiment of the present invention.
FIG. 2 and subsequent figures show a substrate processing apparatus according to an embodiment of the present invention.
First, a substrate processing apparatus according to an embodiment of the present invention will be described.

  In the present embodiment, the substrate processing apparatus according to the present invention is structurally configured as a cluster apparatus as shown in FIG. 2, and is functionally used for the MOSFET gate stack forming process. It is comprised so that. In the cluster apparatus according to the present embodiment, a FOUP (front opening unified pod) 1 is used as a wafer transfer carrier (substrate storage container) for transferring a wafer 2 as a substrate. ing.

  As shown in FIG. 2, the cluster apparatus 10 has a first wafer transfer chamber (hereinafter referred to as a negative pressure transfer chamber) as a transfer chamber configured to withstand a pressure (negative pressure) below atmospheric pressure. 11, a housing 12 of the negative pressure transfer chamber 11 (hereinafter referred to as a negative pressure transfer chamber housing) 12 is formed in a box shape having a heptagonal plan view and closed at both upper and lower ends. A wafer transfer device (hereinafter referred to as a negative pressure transfer device) 13 as a transfer robot for transferring the wafer 2 under a negative pressure is installed in the center of the negative pressure transfer chamber 11. The negative pressure transfer device 13 is configured by a SCARA (selective compliance assembly robot arm).

  Of the seven side walls of the negative pressure transfer chamber housing 12, a long side wall has a carry-in spare chamber (hereinafter referred to as a carry-in chamber) 14 as a holding chamber for holding the wafer 2 and a carry-out spare chamber (hereinafter referred to as a carry-out chamber). (Referred to as “chambers”) 15 are connected adjacently. Each of the housing of the carry-in chamber 14 and the housing of the carry-out chamber 15 is formed in a box shape with a substantially rhombus in plan view and closed at both upper and lower ends, and has a load lock chamber structure that can withstand negative pressure. .

  On the opposite side of the loading chamber 14 and the unloading chamber 15 from the negative pressure transfer chamber 11, a second wafer transfer chamber (hereinafter, referred to as a structure that can maintain a pressure equal to or higher than the atmospheric pressure (hereinafter referred to as positive pressure)). (Referred to as a positive pressure transfer chamber) 16 are connected adjacent to each other, and the casing of the positive pressure transfer chamber 16 is formed in a box shape with a horizontally long rectangle in a plan view and closed at both upper and lower ends. A gate valve 17A is installed at the boundary between the carry-in chamber 14 and the positive pressure transfer chamber 16, and a gate valve 17B is installed between the carry-in chamber 14 and the negative pressure transfer chamber 11. A gate valve 18 </ b> A is installed at the boundary between the carry-out chamber 15 and the positive pressure transfer chamber 16, and a gate valve 18 </ b> B is installed between the carry-out chamber 15 and the negative pressure transfer chamber 11. The positive pressure transfer chamber 16 is provided with a second wafer transfer device (hereinafter referred to as a positive pressure transfer device) 19 for transferring the wafer 2 under positive pressure. The positive pressure transfer device 19 is a SCARA robot. It is constituted by. The positive pressure transfer device 19 is configured to be moved up and down by an elevator installed in the positive pressure transfer chamber 16, and is configured to be reciprocated in the left-right direction by a linear actuator. A notch aligning device 20 is installed at the left end of the positive pressure transfer chamber 16.

Three wafer loading / unloading outlets 21, 22, and 23 are opened next to each other on the front wall of the positive pressure transfer chamber 16, and these wafer loading / unloading holes 21, 22, and 23 are used to positively move the wafer 2 forward. It is set so that it can be carried into and out of the pressure transfer chamber 16. Pod openers 24 are installed at the wafer loading / unloading exits 21, 22, and 23, respectively.
The pod opener 24 includes a mounting table 25 for mounting the pod 1 and a cap attaching / detaching mechanism 26 for mounting and removing the cap of the pod 1 mounted on the mounting table 25, and the pod 1 mounted on the mounting table 25. By attaching / detaching the cap by the cap attaching / detaching mechanism 26, the wafer loading / unloading opening of the pod 1 is opened and closed. The pod 1 is supplied to and discharged from the mounting table 25 of the pod opener 24 by an in-process transfer device (RGV) (not shown).

  As shown in FIG. 2, among the seven side walls of the negative pressure transfer chamber housing 12, three side walls located on the side opposite to the positive pressure transfer chamber 16 are provided with the first processing unit 31. The second processing unit 32 and the third processing unit 33 are connected adjacently. A gate valve 44 is installed between the first processing unit 31 and the negative pressure transfer chamber 11. A gate valve 82 is installed between the second processing unit 32 and the negative pressure transfer chamber 11. A gate valve 118 is installed between the third processing unit 33 and the negative pressure transfer chamber 11. Further, the other two side walls of the seven side walls in the negative pressure transfer chamber housing 12 are connected to the first cooling unit 35 and the second cooling unit 36, respectively. The unit 35 and the second cooling unit 36 are both configured to cool the processed wafer 2.

  The cluster apparatus 10 includes a controller 37 for comprehensively controlling a sequence flow to be described later.

  Next, a case where the gate stack forming process shown in FIG. 1 is performed using the cluster apparatus 10 having the above-described configuration will be described. Here, an example of processing using the first processing unit 31 and the third processing unit 33 without using the second processing unit 32 will be described.

  In the wafer loading step S100 shown in FIG. 1, the cap of the pod 1 supplied to the mounting table 25 of the cluster apparatus 10 is removed by the cap attaching / detaching mechanism 26, and the wafer loading / unloading port of the pod 1 is opened. When the pod 1 is opened, the positive pressure transfer device 19 installed in the positive pressure transfer chamber 16 picks up the wafers 2 one by one from the pod 1 through the wafer carry-in / out port, and puts them into the carry-in chamber 14. 2 is transferred to the temporary storage table for the loading room. During this transfer operation, the positive pressure transfer chamber 16 side of the carry-in chamber 14 is opened by the gate valve 17A, and the negative pressure transfer chamber 11 side of the carry-in chamber 14 is closed by the gate valve 17B. The pressure in the negative pressure transfer chamber 11 is maintained at 100 Pa, for example.

  In the wafer loading step S102 shown in FIG. 1, the positive pressure transfer chamber 16 side of the carry-in chamber 14 is closed by the gate valve 17A, and the carry-in chamber 14 is exhausted to a negative pressure by an exhaust device (not shown). When the inside of the carry-in chamber 14 is depressurized to a preset pressure value, the negative pressure transfer chamber 11 side of the carry-in chamber 14 is opened by the gate valve 17B. Next, the negative pressure transfer device 13 in the negative pressure transfer chamber 11 picks up the wafers 2 one by one from the temporary placement table for the carry-in chamber and loads them into the negative pressure transfer chamber 11. Thereafter, the negative pressure transfer chamber 11 side of the carry-in chamber 14 is closed by the gate valve 17B. Subsequently, the gate valve 44 of the first processing unit 31 is opened, and the negative pressure transfer device 13 performs the interface layer forming step and the high dielectric constant insulating film forming step shown in FIG. The wafer is transferred to the processing unit 31 and loaded into the processing chamber of the first processing unit 31 (wafer loading). Note that when the wafer is loaded into the first processing unit 31, the loading chamber 14 and the negative pressure transfer chamber 11 are evacuated to remove internal oxygen and moisture in advance. Is reliably prevented from entering the processing chamber of the first processing unit 31 when the wafer is carried into the first processing unit 31.

  In the present embodiment, the first processing unit 31 is structurally configured as a single wafer type warm wall type substrate processing apparatus as shown in FIG. 3, and functionally, it is an ALD (Atomic). It is configured as a Layer Deposition apparatus or a cyclic CVD apparatus (hereinafter referred to as a film forming apparatus) 40. As shown in FIG. 3, the film forming apparatus 40 includes a casing 42 that forms a processing chamber 41 as a first processing chamber. A wafer loading / unloading port 43 is opened at the boundary between the housing 42 and the negative pressure transfer chamber 11, and the wafer loading / unloading port 43 is configured to be opened and closed by a gate valve 44. A support base 45 for supporting the wafer 2 is provided in the processing chamber 41 formed by the housing 42. A susceptor 46 that supports the wafer 2 is provided on the upper portion of the support base 45. A heater 47 is provided inside the support base 45. The heater 47 heats the wafer 2 placed on the susceptor 46. The heater 47 is controlled by a temperature controller 48 as a temperature control unit (temperature control means) so that the temperature of the wafer 2 becomes a predetermined temperature. A rotation mechanism (rotation means) 49 is provided outside the processing chamber 41. The rotation mechanism 49 rotates the support base 45 in the processing chamber 41 to rotate the wafer 2 on the susceptor 46. An elevating mechanism (elevating means) 50 is provided outside the processing chamber 41. The elevating mechanism 50 moves the support base 45 up and down in the processing chamber 41.

  A shower head 51 that ejects gas in a shower shape is provided in the upper part of the processing chamber 41, and the shower head 51 is provided to face the susceptor 46. The shower head 51 includes a dispersion plate 51a and a shower plate 51b. The dispersion plate 51a has a large number of gas ejection ports 51f (not shown), and disperses the gas supplied to the inside. The shower plate 51b has a large number of gas ejection ports 51e (not shown), and the gas dispersed by the dispersion plate 51a is ejected into the processing chamber 41 in a shower shape. A first buffer space 51c is provided between the ceiling of the shower head 51 and the dispersion plate 51a, and a second buffer space 51d is provided between the dispersion plate 51a and the shower plate 51b.

  Outside the processing chamber 41, a first raw material supply source 52a that supplies a first raw material that is a liquid raw material and a second raw material supply source 52d that supplies a second raw material that is a liquid raw material are provided. A first liquid source supply pipe 53a is connected to the first source supply source 52a, and a second liquid source supply pipe 53d is connected to the second source supply source 52d. The first liquid raw material supply pipe 53a and the second liquid raw material supply pipe 53d are respectively connected via liquid flow rate controllers (liquid mass flow controllers) 54a and 54d as flow rate control devices (flow rate control means) for controlling the liquid supply flow rate of the raw material. The vaporizers 55a and 55d for vaporizing the raw material are connected. A first source gas supply pipe 56a and a second source gas supply pipe 56d are connected to the vaporizers 55a and 55d, respectively. The first source gas supply pipe 56a and the second source gas supply pipe 56d are connected to valves 57a and 57d, respectively. To the shower head 51.

An inert gas supply source 52c is provided outside the processing chamber 41, and the inert gas supply source 52c supplies an inert gas as a non-reactive gas. An inert gas supply pipe 53c is connected to the inert gas supply source 52c, and a gas as a flow rate control device (flow rate control means) for controlling the supply flow rate of the inert gas is provided in the middle of the inert gas supply pipe 53c. A flow rate controller (mass flow controller) 54c is provided. The inert gas supply pipe 53c branches into two supply pipes downstream of the gas flow rate controller 54c. One branched supply pipe is connected to the first source gas supply pipe 56a via a valve 57c, and the other branched supply pipe is connected to the second source gas supply pipe 56d via a valve 57e. For example, Ar, He, or N ₂ is used as the inert gas.

  In the first raw material gas supply pipe 56a, the first raw material gas obtained by vaporizing the first raw material in the vaporizer 55a and the inert gas from the inert gas supply pipe 53c are mixed. In the second source gas supply pipe 56d, the second source gas obtained by vaporizing the second source in the vaporizer 55d and the inert gas from the inert gas supply pipe 53c are mixed. The mixed gas is supplied from the first source gas supply pipe 56a and the second source gas supply pipe 56d to the first buffer space 51c of the shower head 51, respectively. Valves 57a, 57d, 57c, and 57e provided in the first source gas supply pipe 56a, the second source gas supply pipe 56d, and the inert gas supply pipe 53c are opened and closed to control the supply of the respective gases.

An ozonizer 58 is provided outside the processing chamber 41, and the ozonizer 58 generates ozone gas (O ₃ ) from oxygen gas (O ₂ ). An oxygen gas supply pipe 53b is provided on the upstream side of the ozonizer 58, and an oxygen gas supply source 52b is connected to the oxygen gas supply pipe 53b. The oxygen gas supply source 52b supplies oxygen gas to the ozonizer 58 through the oxygen gas supply pipe 53b. The oxygen gas supply pipe 53b is provided with a gas flow rate controller 54b and a valve 57b for controlling the supply flow rate of oxygen gas. The valve 57b is opened and closed to control the supply of oxygen gas. An ozone gas supply pipe 59b is provided on the downstream side of the ozonizer 58, and the ozone gas supply pipe 59b is connected to the shower head 51 via a valve 60b. The ozone gas supply pipe 59 b supplies the ozone gas generated by the ozonizer 58 to the first buffer space 51 c of the shower head 51. The supply of ozone gas is controlled by opening and closing the valve 60b. A steam generator may be provided in place of the ozonizer 58, and steam (H ₂ O) may be used as the oxidant instead of ozone (O ₃ ) gas.

  An exhaust port 61 is provided in the lower side wall of the housing 42, and one end of an exhaust pipe 62 is connected to the exhaust port 61. The other end of the exhaust pipe 62 is connected to a vacuum pump 63 as an exhaust device (exhaust means) and an abatement device (not shown). An exhaust system is constituted by the exhaust port 61 and the exhaust pipe 62. The exhaust pipe 62 is provided with a pressure controller 64 as a pressure control unit (pressure control means) and a raw material recovery trap 65. The pressure controller 64 controls the pressure in the processing chamber 41. The raw material recovery trap 65 recovers the raw material.

  The first source gas supply pipe 56a, the second source gas supply pipe 56d, and the ozone gas supply pipe 59b include a first source gas bypass pipe (vent pipe) 66a connected to the source recovery trap 65, and a second source gas bypass. A tube (vent tube) 66c and an ozone gas bypass tube (vent tube) 66b are provided. Valves 67a, 67c, and 67b are provided in the bypass pipes 66a, 66c, and 66b, respectively.

  A plate 68 as a rectifying plate is provided on the support base 45 in the processing chamber 41. The plate 68 includes a first buffer space 51c, a dispersion plate 51a, a second buffer space 51d, and a shower plate 51b of the shower head 51. The flow of gas supplied through the The plate 68 has a ring shape and is located around the wafer 2. The gas supplied to the wafer 2 via the shower head 51 flows radially outward of the wafer 2, passes over the plate 68, passes between the plate 68 and the side wall (inner wall) of the housing 42, and exhausts. The air is exhausted from the port 61.

  Control of the valves 57a to 67c, flow rate controllers 54a to 54d, temperature controller 48, pressure controller 64, vaporizers 55a and 55d, ozonizer 58, rotation mechanism 49, and lifting mechanism 50 is the main control unit (main control means). Performed by the controller 69. The main controller 69 is controlled by the controller 37.

  Next, the interface layer forming step S104 and the high dielectric constant insulating film forming step S106 shown in FIG. 1 performed as one step of the semiconductor device manufacturing process are performed using the film forming apparatus 40 to form hafnium which is a high dielectric constant film. A case where an aluminate (HfAlO) film is formed on the wafer 2 by the ALD method or the cyclic CVD method will be described. In the following description, the operation of each part constituting the film forming apparatus 40 is controlled by the main controller 69.

  Here, the structure of the wafer 2 before the high dielectric constant film is formed is as shown in FIG. That is, the element isolation region 3 is formed in the silicon wafer 2, and the P well region 4 and the N well region 5 are formed in the active region isolated by the element isolation region 3.

In this embodiment, TDMAHf (Hf [N (CH ₃ ) ₂ ] ₄ ) is used as the hafnium-based precursor, and TMA (Al (CH ₃ ) ₃ ) is used as the aluminum-based precursor. An example using raw material gas obtained by vaporizing the raw material with a vaporizer will be described.

  In FIG. 3, when the gate valve 44 is opened and the wafer loading / unloading port 43 is opened while the support 45 is lowered to the wafer transfer position, the wafer 2 is moved into the processing chamber 41 by the negative pressure transfer device 13. Carry in (wafer carry-in step). After the wafer 2 is loaded into the processing chamber 41 and placed on push-up pins (not shown), the gate valve 44 is closed. The support base 45 rises from the wafer transfer position to a wafer processing position above it. Meanwhile, the wafer 2 is placed on the susceptor 46 from the push-up pins (wafer placing step).

  When the support table 45 reaches the wafer processing position, the wafer 2 is rotated by the rotation mechanism 49. Further, by supplying electric power to the heater 47, the wafer 2 is uniformly heated to a predetermined processing temperature (wafer heating step). At the same time, the inside of the processing chamber 41 is evacuated by the vacuum pump 63 and controlled so as to reach a predetermined processing pressure (pressure adjustment step). Note that the valves 57c and 57e provided in the inert gas supply pipe 53c are always open during wafer transfer, wafer temperature rise, and pressure adjustment, and the inside of the processing chamber 41 is supplied from the inert gas supply source 52c. An inert gas is always flowed into the tank. Thereby, adhesion of particles and metal contaminants to the wafer 2 can be prevented.

First, the interface layer forming step S104 will be described.
When the pressure in the processing chamber 41 reaches a predetermined processing pressure and stabilizes, ozone gas is supplied into the processing chamber 41. That is, when the valve 57b is opened, the oxygen gas supplied from the oxygen gas supply source 52b passes through the oxygen gas supply pipe 53b, and the flow rate is controlled by the gas flow rate controller 54b to be supplied to the ozonizer 58. The ozonizer 58 generates ozone gas. When the valve 67b is closed after the ozone gas is generated and the valve 60b is opened, the generated ozone gas passes from the ozonizer 58 through the ozone gas supply pipe 59b, and the first buffer space 51c of the shower head 51, the dispersion plate 51a, It is supplied in a shower form onto the wafer 2 via the second buffer space 51d and the shower plate 51b. The ozone gas supplied to the wafer 2 is exhausted from the exhaust pipe 62. When the ozone gas comes into contact with the surface of the wafer 2, as shown in FIG. 5B, a silicon oxide film (SiO ₂ film) 6 as an extremely thin interface layer is formed on the surface of the wafer 2 (interface layer). Forming step). At this time, water vapor (H ₂ O) may be used instead of ozone (O ₃ ) gas.

  After supplying ozone gas for a predetermined time and forming the silicon oxide film 6 as an interface layer, the valve 60b is closed and supply of ozone gas to the wafer 2 is stopped. Also at this time, since the valves 57c and 57e remain open, the supply of the inert gas into the processing chamber 41 is maintained. The inert gas supplied to the processing chamber 41 is exhausted from the exhaust pipe 62. Thereby, the inside of the processing chamber 41 is purged with the inert gas, and the residual gas in the processing chamber 41 is removed (purge step).

  After the purge in the processing chamber 41 is performed for a predetermined time and the temperature of the wafer 2 and the pressure in the processing chamber 41 reach a predetermined processing temperature and a predetermined processing pressure and stabilize, respectively, a high dielectric constant insulating film forming step S106 is performed.

Next, the high dielectric constant insulating film forming step S106 will be described.
After the silicon oxide film 6 as the interface layer is formed on the surface of the wafer 2, when the temperature of the wafer 2 and the pressure in the processing chamber 41 reach a predetermined film formation temperature and a predetermined film formation pressure, respectively, A first source gas is supplied into the processing chamber 41. That is, the organometallic liquid raw material, for example, TDMAHf supplied from the first raw material supply source 52a passes through the first liquid raw material supply pipe 53a, the flow rate is controlled by the liquid flow rate controller 54a, and the vaporized material 55a is supplied. Is done. The vaporizer 55a vaporizes the first raw material. When the valve 67a is closed and the valve 57a is opened, the first source gas vaporized by the first source passes through the first source gas supply pipe 56a, passes through the first buffer space 51c of the shower head 51, the dispersion plate 51a, the second source gas. It is supplied onto the wafer 2 via the two buffer space 51d and the shower plate 51b. At this time as well, the valves 57c and 57e remain open, and an inert gas is always flowed into the processing chamber 41. The first source gas and the inert gas are mixed in the first source gas supply pipe 56a and guided to the shower head 51, and pass through the first buffer space 51c, the dispersion plate 51a, the second buffer space 51d, and the shower plate 51b. Then, it is supplied as a shower onto the wafer 2 on the susceptor 46 (first source gas supply step). The first source gas supplied to the wafer 2 is exhausted from the exhaust pipe 62. The first source gas is easily stirred by being diluted with an inert gas.

  After supplying the first source gas for a predetermined time, the valve 57a is closed, and the supply of the first source gas to the wafer 2 is stopped. Also at this time, since the valves 57c and 57e remain open, the supply of the inert gas into the processing chamber 41 is maintained. The inert gas supplied to the processing chamber 41 is exhausted from the exhaust pipe 62. Thereby, the inside of the processing chamber 41 is purged with the inert gas, and the residual gas in the processing chamber 41 is removed (purge step).

  After the residual gas purge in the processing chamber 41 is performed for a predetermined time, the second source gas is supplied into the processing chamber 41. That is, the organometallic liquid raw material, for example, TMA supplied from the second raw material supply source 52d passes through the second liquid raw material supply pipe 53d, the flow rate is controlled by the liquid flow rate controller 54d, and the vaporized material 55d is supplied. Is done. The vaporizer 55d vaporizes the second raw material. When the valve 67c is closed and the valve 57d is opened, the vaporized second source gas passes through the second source gas supply pipe 56d and passes through the first buffer space 51c, the dispersion plate 51a, and the second buffer space 51d of the shower head 51. And supplied onto the wafer 2 via the shower plate 51b. Also at this time, the valves 57e and 57c are kept open, and an inert gas is always flowed into the processing chamber 41. The second source gas and the inert gas are mixed in the second source gas supply pipe 56d and guided to the shower head 51, and pass through the first buffer space 51c, the dispersion plate 51a, the second buffer space 51d, and the shower plate 51b. Then, it is supplied as a shower onto the wafer 2 on the susceptor 46 (second source gas supply step). The second source gas supplied to the wafer 2 is exhausted from the exhaust pipe 62. The second source gas is easily stirred by being diluted with an inert gas.

  After the second source gas is supplied for a predetermined time, the valve 57d is closed and the supply of the second source gas to the wafer 2 is stopped. Also at this time, since the valves 57e and 57c remain open, the supply of the inert gas into the processing chamber 41 is maintained. The inert gas supplied to the processing chamber 41 is exhausted from the exhaust pipe 62. Thereby, the inside of the processing chamber 41 is purged with the inert gas, and the residual gas in the processing chamber 41 is removed (purge step).

After purging the residual gas in the processing chamber 41 for a predetermined time, ozone gas as an oxidant is supplied into the processing chamber 41. That is, as described above, when the valve 67b is closed and the valve 60b is opened while the supply of the ozone gas from the ozonizer 58 is stopped without stopping the supply of the processing chamber 41, it is generated. The ozone gas passes from the ozonizer 58 through the ozone gas supply pipe 59b, and is supplied in a shower form onto the wafer 2 via the first buffer space 51c, the dispersion plate 51a, the second buffer space 51d, and the shower plate 51b of the shower head 51. (Oxidant supply step). The ozone gas supplied to the wafer 2 is exhausted from the exhaust pipe 62. At this time, the valves 57c and 57e are kept open, and an inert gas is always supplied into the processing chamber 41. As the oxidizing agent, ozone (O ₃₎ may be used water vapor (H 2 _O) in place of the gas.

  After the ozone gas is supplied for a predetermined time, the valve 60b is closed and the supply of the ozone gas to the wafer 2 is stopped. Also at this time, since the valves 57c and 57e remain open, the supply of the inert gas into the processing chamber 41 is maintained. The inert gas supplied to the processing chamber 41 is exhausted from the exhaust pipe 62. Thereby, the inside of the processing chamber 41 is purged with the inert gas, and the residual gas in the processing chamber 41 is removed (purge step).

  After the residual gas purge in the processing chamber 41 is performed for a predetermined time, when the valve 67a is closed again and the valve 57a is opened, the vaporized first source gas together with the inert gas is in the first buffer space of the shower head 51. It is supplied onto the wafer 2 via 51c, the dispersion plate 51a, the second buffer space 51d, and the shower plate 51b. That is, the first source gas supply step is performed.

  The above-described first source gas supply step, purge step, second source gas supply step, purge step, oxidant supply step and purge step are taken as one cycle, and a cycle process for repeating this cycle a plurality of times is performed as shown in FIG. As shown in c), an amorphous hafnium aluminate (HfAlO) film 7 as a high dielectric constant insulating film is formed on the silicon oxide film 6 as an interface layer formed on the surface of the wafer 2. (High dielectric constant insulating film forming step).

  In the case where the high dielectric constant film forming step S106 is performed by the cyclic CVD method, the film forming temperature is controlled to be a temperature range in which the source gas is self-decomposed. In this case, in the source gas supply step, the source gas is thermally decomposed to form a high dielectric constant film of about several to several tens of atomic layers on the wafer 2. In the oxidizing agent supplying step, impurities such as C and H are removed from the high dielectric constant film of about several to several tens of atomic layers formed on the wafer 2 by the oxidizing agent.

  Further, when the high dielectric constant film forming step S106 is performed by the ALD method, the film forming temperature is controlled so as to be a temperature range in which the source gas is not self-decomposed. In this case, the source gas is adsorbed onto the wafer 2 in the source gas supply step. In the oxidant supply step, the raw material adsorbed on the wafer 2 and the oxidant react to form a high dielectric constant film of less than one atomic layer on the wafer 2. At this time, impurities such as C and H mixed in the high dielectric constant film can be eliminated by the oxidizing agent.

The processing conditions for forming a hafnium aluminate film by cyclic CVD are as follows: processing temperature: 390 to 450 ° C., processing pressure: 50 to 400 Pa, first raw material (TDMAHf) supply flow rate: 0.01 to 0.2 g / Minute, second raw material (TMA) supply flow rate: 0.01 to 0.2 g / min, oxidant supply flow rate: 100 to 3000 sccm.
The processing conditions for forming a hafnium aluminate film by the ALD method are as follows: processing temperature: 200 to 350 ° C., processing pressure: 50 to 400 Pa, first raw material (TDMAHf) supply flow rate: 0.01 to 0.2 g / Minute, second raw material (TMA) supply flow rate: 0.01 to 0.2 g / min, oxidant supply flow rate: 100 to 3000 sccm.

  As described above, as shown in FIG. 5C, the hafnium aluminate (HfAlO) film as the high dielectric constant insulating film is formed on the silicon oxide film 6 as the interface layer formed on the wafer 2. 7 is formed. When the formation of the hafnium aluminate film is completed, the gate valve 44 is opened as a transfer step S108 in a vacuum, and the deposited wafer 2 is maintained at a negative pressure from the first processing unit 31 by the negative pressure transfer device 13. It is carried out (wafer unloading) to the negative pressure transfer chamber 11 thus formed. Subsequently, after the gate valve 44 is closed, the gate valve 118 is opened, and the negative pressure transfer device 13 transports the wafer 2 to the third processing unit 33 that performs the heat treatment step shown in FIG. Then, the wafer is loaded into the processing chamber of the third processing unit 33 (wafer loading).

In the present embodiment, RTP (Rapid Thermal Processing) apparatus 110 shown in FIG. 4 is used for third processing unit 33 that performs the heat treatment step.
As shown in FIG. 4, the RTP apparatus 110 includes a casing 112 in which a processing chamber 111 as a second processing chamber for processing the wafer 2 is formed. The casing 112 has a cylindrical shape with upper and lower surfaces opened. The cup 113 formed on the upper surface of the cup 113, the disk-shaped top plate 114 that closes the upper surface opening of the cup 113, and the disk-shaped bottom plate 115 that closes the lower surface opening of the cup 113 are combined into a cylindrical hollow body shape. Has been built. An exhaust port 116 is formed in a part of the side wall of the cup 113 so as to communicate with the inside and outside of the processing chamber 111. The processing chamber 111 is exhausted to less than atmospheric pressure (hereinafter referred to as negative pressure) through the exhaust port 116. The resulting exhaust device (not shown) is connected. A wafer loading / unloading port 117 for loading / unloading the wafer 2 into / from the processing chamber 111 is opened at a position opposite to the exhaust port 116 on the side wall of the cup 113, and the wafer loading / unloading port 117 is opened and closed by a gate valve 118. It has come to be.

  An elevating drive device 119 is installed on the center line of the lower surface of the bottom plate 115, and the elevating drive device 119 is inserted into the bottom plate 115 and is configured to be slidable in the vertical direction with respect to the bottom plate 115. It is comprised so that 120 may be raised / lowered. A lifting plate 121 is horizontally fixed to the upper end of the lifting shaft 120, and a plurality of (usually three or four) lifter pins 122 are vertically fixed and fixed to the upper surface of the lifting plate 121. Each lifter pin 122 moves up and down as the elevating plate 121 moves up and down, thereby supporting the wafer 2 horizontally from below and moving it up and down.

  A support cylinder 123 protrudes outside the lifting shaft 120 on the upper surface of the bottom plate 115, and a cooling plate 124 is installed horizontally on the upper end surface of the support cylinder 123. Above the cooling plate 124, a first heating lamp group 125 and a second heating lamp group 126 composed of a plurality of heating lamps are arranged in order from the bottom, and are laid horizontally, respectively. The group 125 and the second heating lamp group 126 are horizontally supported by the first support 127 and the second support 128, respectively. The power supply wires 129 of the first heating lamp group 125 and the second heating lamp group 126 are inserted through the bottom plate 115 and drawn to the outside.

  A turret 131 is disposed in the processing chamber 111 concentrically with the processing chamber 111. The turret 131 is concentrically fixed to the upper surface of the internal spur gear 133, and the internal spur gear 133 is supported horizontally by a bearing 132 interposed in the bottom plate 115. A drive side spur gear 134 is engaged with the internal spur gear 133. The drive side spur gear 134 is horizontally supported by a bearing 135 interposed in the bottom plate 115, and is a susceptor installed under the bottom plate 115. The rotating device 136 is rotationally driven. An outer platform 137 formed in a flat circular ring shape is horizontally installed on the upper end surface of the turret 131, and an inner platform 138 is horizontally installed inside the outer platform 137. A susceptor 140 is engaged with and held by an engaging portion 139 projecting radially inward from the lower end portion of the inner peripheral surface at the lower end portion of the inner periphery of the inner platform 138. Insertion holes 141 are formed at positions facing the lifter pins 122 of the susceptor 140.

  An annealing gas supply pipe 142 and an inert gas supply pipe 143 are connected to the top plate 114 so as to communicate with the processing chamber 111. Further, a plurality of radiation thermometer probes 144 are respectively inserted in the top plate 114 so as to be shifted from each other in the radial direction from the center to the periphery of the wafer 2 so as to face the upper surface of the wafer 2. The thermometer is configured to sequentially transmit measured temperatures based on the radiated light respectively detected by the plurality of probes 144 to the controller. An emissivity measuring device 145 that measures the emissivity of the wafer 2 in a non-contact manner is installed at another location on the top plate 114. The emissivity measuring device 145 includes a reference probe 146, and the reference probe 146 is rotated in a vertical plane by a reference probe motor 147. On the upper side of the reference probe 146, a reference lamp 148 for irradiating the reference light is installed so as to face the tip of the reference probe 146. The reference probe 146 is optically connected to the radiation thermometer, which calibrates the measured temperature by comparing the photon density from the wafer 2 with the photon density of the reference light from the reference lamp 148. It has become.

  Next, the case where the heat treatment step S110 shown in FIG. 1 is annealed to the hafnium aluminate film 7 formed on the wafer 2 using the RTP apparatus having the above configuration will be described. That is, the step of densifying or crystallizing the high dielectric constant insulating film will be described.

  When the gate valve 118 is opened, the wafer 2 to be annealed is loaded into the processing chamber 111 of the RTP apparatus 110 as the third processing unit 33 from the wafer loading / unloading port 117 by the negative pressure transfer device 13, and a plurality of wafers 2 are loaded. It is transferred between the upper ends of the lifter pins 122. When the negative pressure transfer device 13 that transfers the wafer 2 to the lifter pins 122 is retracted out of the processing chamber 111, the wafer loading / unloading port 117 is closed by the gate valve 118. Further, the lift shaft 120 is lowered by the lift drive device 119, whereby the wafer 2 on the lifter pins 122 is transferred onto the susceptor 140. With the processing chamber 111 closed in an airtight manner, the processing chamber 111 is exhausted through the exhaust port 116 so as to have a predetermined pressure in the range of 10 to 10000 Pa. The oxygen partial pressure in the processing chamber 111 is maintained at a pressure of 25000 Pa or less, preferably about 1 to 1000 Pa.

  When the wafer 2 is transferred to the susceptor 140, the turret 131 holding the wafer 2 by the susceptor 140 is rotated by the susceptor rotating device 136 via the internal spur gear 133 and the driving side spur gear 134. The wafer 2 held on the susceptor 140 is rapidly heated by the first heating lamp group 125 and the second heating lamp group 126 so as to reach a predetermined temperature in the range of 600 to 1050 ° C. while being rotated by the susceptor rotating device 136. And kept at the processing temperature as it is. During the rotation and heating, an inert gas such as nitrogen gas or argon gas is supplied to the processing chamber 111 from the annealing gas supply pipe 142. Since the wafer 2 held on the susceptor 140 is uniformly heated by the first heating lamp group 125 and the second heating lamp group 126 while the susceptor 140 is rotated by the susceptor rotating device 136, the hafnium aluminum on the wafer 2. Nate film 7 is uniformly annealed over the entire surface. The annealing treatment time is 5 to 120 seconds. By the above heat treatment step, a densified or crystallized hafnium aluminate film 8 is formed on the wafer 2 as shown in FIG. After the above heat treatment step, the heating by the first heating lamp group 125 and the second heating lamp group 126 is finished, and the wafer 2 is rapidly cooled.

  When a predetermined processing time set in advance in the RTP apparatus 110 elapses, the processing chamber 111 is evacuated to a predetermined negative pressure through the exhaust port 116, and then the gate valve 118 is moved as a transfer step S112 under vacuum. The wafer 2 that has been opened and annealed is unloaded (wafer unloading) from the processing chamber 111 to the negative pressure transfer chamber 11 by the negative pressure transfer device 13 in the reverse order of loading. At this time, the temperature of the wafer 2 is about 300 to 400 ° C.

  The wafer after the interface layer forming step, the high dielectric constant insulating film forming step, and the heat treatment step may be cooled as necessary using the first cooling unit 35 or the second cooling unit 36.

  In the wafer unloading step S114 shown in FIG. 1 after the heat treatment step in the cluster apparatus 10, the negative pressure transfer chamber 11 side of the unloading chamber 15 is opened by the gate valve 18B, and the negative pressure transfer device 13 is connected to the wafer 2 Is transferred from the negative pressure transfer chamber 11 to the carry-out chamber 15 and transferred onto the temporary storage stand for the carry-out chamber in the carry-out chamber 15. At this time, the positive pressure transfer chamber 16 side of the carry-out chamber 15 is closed by the gate valve 18A in advance, and the carry-out chamber 15 is exhausted to a negative pressure by an exhaust device (not shown). When the unloading chamber 15 is depressurized to a preset pressure value, the negative pressure transfer chamber 11 side of the unloading chamber 15 is opened by the gate valve 18B, and a wafer unloading step is performed. After the wafer unloading step, the gate valve 18B is closed.

  Note that, during the period from the transfer step S112 under vacuum after the heat treatment step S110 described above to the wafer unloading step S114 until the temperature of the wafer 2 reaches about 300 to 400 ° C. to about room temperature, the process chamber 111 and the negative pressure transfer are performed. The inside of the loading chamber 11, the carry-out chamber 15, the first cooling unit 35, and the second cooling unit 36 is maintained in a vacuum and at a low oxygen partial pressure that is equal to or lower than that during heat treatment and an inert gas atmosphere. Thus, the annealed hafnium aluminate film 8 is held in a state where oxygen is not supplied until the temperature reaches about room temperature. For this reason, an appropriate amount of oxygen vacancies is maintained in the hafnium aluminate film 8, and the hafnium aluminate film 8 having a higher dielectric constant than the conventional one can be obtained. Note that these pressure control and atmosphere control are performed by the controller 37. Here, the preferable oxygen partial pressure in each chamber until the temperature of the wafer 2 reaches about room temperature is 25000 Pa or less, preferably about 1 to 1000 Pa.

  By these operations, a dense or crystallized hafnium aluminate film 8 having a high dielectric constant is formed on the wafer 2.

  By repeating the above operation, the steps shown in FIG. 1 are sequentially performed on the 25 wafers 2 that are collectively loaded into the loading chamber 14. When a series of predetermined processes are completed for the 25 wafers 2, the processed wafers 2 are stored on the temporary placement table in the carry-out chamber 15.

  In the wafer discharge step S116 shown in FIG. 1, nitrogen gas is supplied into the unloading chamber 15 maintained at a negative pressure and a low oxygen partial pressure, and after the inside of the unloading chamber 15 reaches atmospheric pressure, the unloading chamber 15 The positive pressure transfer chamber 16 side is opened by the gate valve 18A. Next, the cap of the empty pod 1 mounted on the mounting table 25 is opened by the cap attaching / detaching mechanism 26 of the pod opener 24. Subsequently, the positive pressure transfer device 19 in the positive pressure transfer chamber 16 picks up the wafer 2 from the carry-out chamber 15 and carries it out to the positive pressure transfer chamber 16, and passes through the wafer loading / unloading port 23 in the positive pressure transfer chamber 16. The pod 1 is stored (charged). When the storage of the 25 processed wafers 2 in the pod 1 is completed, the cap of the pod 1 is attached to the wafer loading / unloading port by the cap attaching / detaching mechanism 26 of the pod opener 24 and the pod 1 is closed.

  In the present embodiment, the wafer 2 that has undergone a series of steps in the cluster apparatus 10 is hermetically stored in the pod 1 and is shown in FIG. The pod is transported in the in-process transport step S118. Examples of the film forming apparatus that performs the gate electrode forming step include a batch type vertical hot wall type CVD apparatus, a single wafer type ALD apparatus, and a single wafer type CVD apparatus.

[Example]
An example of a process sequence in the embodiment of the present invention is shown in FIG. FIG. 6A shows a process sequence flow for creating a sample for In-plane XRD measurement, and FIG. 6B shows a process sequence flow for creating a sample for a MOS capacitor. ing. Each of the above samples was prepared by these process sequences. Of the steps in the figure, SiO ₂ formation, HfAlO deposition, and PDA correspond to the interface layer forming step (S104), the high dielectric constant insulating film forming step (S106), and the heat treatment step (S110) in the above embodiment, respectively. . In this example, among these steps, HfAlO deposition and PDA were performed using the semiconductor device manufacturing method and the substrate processing apparatus according to the above-described embodiment. That is, an HfAlO film is formed to a desired thickness in the processing chamber 41 of the film forming apparatus 40 that is the first processing unit 31 (HfAlO deposition), and then the processing chamber of the RTP apparatus 110 that is the third processing unit 33. The HfAlO film is crystallized by heat treatment in a nitrogen atmosphere at 111 (PDA), and the processing chamber 111 in which the wafer 2 is placed, the negative pressure transfer chamber 11, and the unloading until the temperature of the wafer 2 reaches about room temperature. The inside of the chamber 15, the first cooling unit 35, and the second cooling unit 36 was maintained in a vacuum and a low oxygen partial pressure (25000 Pa or less). In forming the HfAlO film, TDMAHf was used as the hafnium precursor, TMA was used as the aluminum precursor, and H ₂ O was used as the oxidizing agent.

[Comparative example]
Each sample (In-plane XRD measurement sample, MOS capacitor sample) was prepared in the same manner as in the above-described example. However, HfAlO deposition and PDA were performed as follows. That is, an HfAlO film is formed to a desired thickness in the processing chamber 41 of the film forming apparatus 40 that is the first processing unit 31 (HfAlO deposition), and then the processing chamber of the RTP apparatus 110 that is the third processing unit 33. The HfAlO film is crystallized by heat treatment in a nitrogen atmosphere at 111 (PDA), but after the heat treatment, the wafer 2 was exposed to the atmosphere before the wafer temperature reached about room temperature.

FIG. 7 is a diagram showing the results of In-plane XRD analysis in In-plane XRD measurement samples according to Examples and Comparative Examples.
FIG. 8 is a diagram illustrating the relationship between the capacitance-voltage characteristics of the MOS capacitor samples according to the example and the comparative example.
FIG. 9 is a diagram illustrating the relationship between EOT and physical film thickness in the MOS capacitor samples according to the example and the comparative example.

According to the In-plane XRD analysis result of FIG. 7, the HfAlO film formed by the method of the example has one peak near 30 degrees and the second peak around 35 degrees. It was found that the crystal structure is likely to be tetragonal or cubic. On the other hand, since the HfAlO film formed by the method of the comparative example has peaks near 28 degrees and 31.6 degrees, it was found that the crystal structure is likely to be monoclinic.
Further, from the capacitance-voltage characteristics shown in FIG. 8, the capacitance obtained from the MOS capacitor using the HfAlO film formed by the method of the embodiment as the insulating film is the same as the capacitance obtained from the HfAlO film formed by the method of the comparative example. As compared with the capacitance obtained from the MOS capacitor used as a capacitor, it was found that a high capacitance value was obtained.
Further, from the relationship between EOT and physical film thickness shown in FIG. 9, the dielectric constant of the HfAlO film formed by the method of the example is about 34, which is about three times the dielectric constant of the HfAlO film formed by the method of the comparative example. It was found that a dielectric constant of

  Needless to say, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention. For example, in the above-described embodiment, a device (cluster device 10) in which a single-wafer type warm wall type high dielectric constant insulating film forming device (film forming device 40) and a lamp heating rapid heating / cooling heat treatment device (RTP device 110) are integrated. However, the present invention is not limited to this, and the present invention is also applicable to the case where a single-wafer type cold wall type device or a single-wafer type hot wall type device is used as the high dielectric constant insulating film forming device. Furthermore, the present invention can be applied to the case where the high dielectric constant insulating film forming step and the heat treatment step are performed in the same reaction tube. Furthermore, the present invention can be applied to a case where a high dielectric constant insulating film forming step and a heat treatment step are performed in a batch type hot wall type apparatus.

In addition to HfAlO, as a material for forming a high dielectric constant film for forming a gate insulating film, HfSiO, HfSiON, Ta ₂ O ₅ , Al ₂ O ₃ , ZrO ₂ , HfAlOx, HfAlON, La ₂ O ₃ , Y ₂ O ₃ etc.

  According to the present invention, when a high dielectric constant insulating film such as a formed hafnium aluminate film (HfAlO film) is crystallized, a heat treatment is performed to crystallize in a state where the oxygen partial pressure is reduced as much as possible. Thereafter, the high dielectric constant insulating film is kept under a low oxygen partial pressure until the wafer temperature is returned to room temperature. As a result, oxygen vacancies in the high dielectric constant insulating film are appropriately created, and as a result, a high dielectric constant insulating film having a higher dielectric constant than that of the prior art can be formed.

    Hereinafter, preferred embodiments of the present invention will be additionally described.

  According to one aspect of the present invention, there is provided a step of forming a high dielectric constant insulating film on a substrate, a step of subjecting the high dielectric constant insulating film to a heat treatment under vacuum, and the high dielectric constant insulating film after the heat treatment. Until the temperature reaches room temperature, the oxygen partial pressure in the space where the high dielectric constant insulating film exists is maintained equal to or lower than the oxygen partial pressure in the space where the high dielectric constant insulating film exists during the heat treatment. A semiconductor device manufacturing method is provided.

  Preferably, the oxygen partial pressure in the space where the high dielectric constant insulating film exists is set to 25000 Pa or less until the high dielectric constant insulating film after the heat treatment reaches room temperature.

  Preferably, the oxygen partial pressure in the space where the high dielectric constant insulating film exists is set to 1 to 1000 Pa until the high dielectric constant insulating film after the heat treatment reaches room temperature.

  According to another aspect of the present invention, a first processing chamber for forming a high dielectric constant insulating film on a substrate, a second processing chamber for performing a heat treatment on the substrate, a holding chamber for holding a substrate, and the first A transfer chamber provided between the processing chamber, the second processing chamber, and the holding chamber; and a transfer chamber for transferring a substrate between the first processing chamber, the second processing chamber, and the holding chamber; and the transfer chamber A transfer robot provided for transferring a substrate; and transferring the substrate into the first processing chamber by the transfer robot; forming a high dielectric constant insulating film on the substrate in the first processing chamber; The formed substrate is transferred from the first processing chamber to the second processing chamber by the transfer robot, and the high dielectric constant insulating film is subjected to a heat treatment under vacuum in the second processing chamber, and the substrate after the heat treatment is performed. From the second processing chamber by the transfer robot. The oxygen partial pressure in the space where the high dielectric constant insulating film is present is transferred to the room until the high dielectric constant insulating film after the heat treatment reaches room temperature. There is provided a substrate processing apparatus comprising: a controller that controls to maintain the pressure equal to or less than the pressure.

2 Wafer (substrate)
DESCRIPTION OF SYMBOLS 10 Cluster apparatus 11 Negative pressure transfer chamber 13 Negative pressure transfer apparatus 14 Carry-in chamber 15 Carry-out chamber 16 Positive pressure transfer chamber 31 1st processing unit 32 2nd processing unit 33 3rd processing unit

Claims (2)

Forming a high dielectric constant insulating film on the substrate;
Applying heat treatment to the high dielectric constant insulating film under vacuum;
The oxygen partial pressure in the space where the high dielectric constant insulating film exists until the high dielectric constant insulating film after the heat treatment reaches room temperature is the oxygen partial pressure in the space where the high dielectric constant insulating film exists during the heat treatment. A method for manufacturing a semiconductor device, characterized in that the semiconductor device is held equal to or less than A first processing chamber for forming a high dielectric constant insulating film on the substrate;
A second processing chamber for performing heat treatment on the substrate;
A holding chamber for holding a substrate and the first processing chamber, the second processing chamber, and the holding chamber are provided between the first processing chamber, the second processing chamber, and the holding chamber. A transfer chamber for transferring;
A transfer robot provided in the transfer chamber for transferring a substrate;
The substrate is transferred into the first processing chamber by the transfer robot, a high dielectric constant insulating film is formed on the substrate in the first processing chamber, and the substrate on which the high dielectric constant insulating film is formed is transferred by the transfer robot. The substrate is transferred from the first processing chamber to the second processing chamber, the high dielectric constant insulating film is heat-treated in vacuum in the second processing chamber, and the substrate after the heat treatment is transferred to the second processing chamber by the transfer robot. The oxygen partial pressure in the space where the high dielectric constant insulating film exists is transferred to the second processing chamber during the heat treatment until the high dielectric constant insulating film after the heat treatment reaches room temperature. A controller that controls the oxygen partial pressure to be equal to or less than
A substrate processing apparatus comprising:

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