CN115794711B - High-speed serial computer expansion bus standard backboard - Google Patents
High-speed serial computer expansion bus standard backboard Download PDFInfo
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- CN115794711B CN115794711B CN202211338698.9A CN202211338698A CN115794711B CN 115794711 B CN115794711 B CN 115794711B CN 202211338698 A CN202211338698 A CN 202211338698A CN 115794711 B CN115794711 B CN 115794711B
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- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 2
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- 238000004891 communication Methods 0.000 description 1
- 238000013135 deep learning Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application provides a high-speed serial computer expansion bus standard backboard, which comprises a high-speed serial computer expansion bus standard slot, a switching chip, an Ethernet interface and a serial connection small computer system interface, wherein the high-speed serial computer expansion bus standard slot is connected with the switching chip, the Ethernet interface is connected with the switching chip, and the serial connection small computer system interface is connected with the switching chip.
Description
Technical Field
The application relates to the field of artificial intelligent servers, in particular to a standard backboard of a high-speed serial computer expansion bus.
Background
In the prior art, the artificial intelligence server is widely applied to the fields of deep learning, computer vision, voice recognition, natural language processing, video analysis and the like. Along with the wider and wider application range of artificial intelligence, the data calculation amount is increasingly huge, so how to improve the calculation performance and expansibility of the artificial intelligence server becomes a technical problem to be solved urgently.
Disclosure of Invention
The application provides a high-speed serial computer expansion bus standard backboard, which is used for enhancing the expansibility of an artificial intelligent server and improving the calculation performance of a single artificial intelligent server.
The application provides a high-speed serial computer expansion bus standard backboard, which comprises a high-speed serial computer expansion bus standard slot, a switching chip, an Ethernet interface and a serial connection small computer system interface; wherein:
the high-speed serial computer expansion bus standard slot is connected with the exchange chip, the Ethernet interface is connected with the exchange chip, and the serial connection small computer system interface is connected with the exchange chip.
The application provides a high-speed serial computer expansion bus standard backboard, wherein the exchange chip comprises a first high-speed serial computer expansion bus standard exchange chip and a second high-speed serial computer expansion bus standard exchange chip; the number of the high-speed serial computer expansion bus standard slots is n, and n is a positive integer; wherein:
the number of the high-speed serial computer expansion bus standard slots connected with the first high-speed serial computer expansion bus standard exchange chip is m, wherein n=2m;
the number of the high-speed serial computer expansion bus standard slots connected with the second high-speed serial computer expansion bus standard exchange chip is m.
The application provides a high-speed serial computer expansion bus standard backboard, wherein the Ethernet interface comprises a first Ethernet interface and a second Ethernet interface; the first Ethernet interface is connected with the first high-speed serial computer expansion bus standard exchange chip;
the second Ethernet interface is connected with the second high-speed serial computer expansion bus standard exchange chip.
The application provides a high-speed serial computer expansion bus standard backboard, wherein the serial connection small computer system interface comprises a first serial connection small computer system interface and a second serial connection small computer system interface; the first serial connection small computer system interface is connected with the first high-speed serial computer expansion bus standard exchange chip;
the second serial connection small computer system interface is connected with the second high-speed serial computer expansion bus standard exchange chip.
According to the high-speed serial computer expansion bus standard backboard provided by the application, the high-speed serial computer expansion bus standard backboard further comprises a first multiplexer and a second multiplexer; and establishing connection between the first high-speed serial computer expansion bus standard exchange chip and the second high-speed serial computer expansion bus standard exchange chip through the first multiplexer and the second multiplexer.
According to the high-speed serial computer expansion bus standard backboard provided by the application, a first high-speed serial computer expansion bus standard slot is connected with the first high-speed serial computer expansion bus standard exchange chip through the first multiplexer, and a second high-speed serial computer expansion bus standard slot is connected with the second high-speed serial computer expansion bus standard exchange chip through the second multiplexer; the establishing connection between the first high-speed serial computer expansion bus standard exchange chip and the second high-speed serial computer expansion bus standard exchange chip through the first multiplexer and the second multiplexer comprises the following steps:
disconnecting the first high-speed serial computer expansion bus standard slot from the first high-speed serial computer expansion bus standard switching chip through the first multiplexer, and disconnecting the second high-speed serial computer expansion bus standard slot from the second high-speed serial computer expansion bus standard switching chip through the second multiplexer;
and establishing connection between the first high-speed serial computer expansion bus standard exchange chip and the first multiplexer and connection between the second high-speed serial computer expansion bus standard exchange chip and the second multiplexer.
According to the high-speed serial computer expansion bus standard backboard provided by the application, the high-speed serial computer expansion bus standard backboard further comprises a microcontroller; and supplying power to the switching chip, the first multiplexer, the second multiplexer and the microcontroller through the voltage reducing circuit corresponding to the high-speed serial computer expansion bus standard backboard.
According to the high-speed serial computer expansion bus standard backboard provided by the application, the voltage reducing circuit comprises a first voltage reducing circuit and a second voltage reducing circuit; supplying power to the first high-speed serial computer expansion bus standard exchange chip through the first voltage reducing circuit;
and supplying power to the second high-speed serial computer expansion bus standard exchange chip through the second voltage reducing circuit.
According to the high-speed serial computer expansion bus standard backboard provided by the application, the voltage reducing circuit further comprises a third voltage reducing circuit; and supplying power to the first multiplexer, the second multiplexer and the microcontroller through the third voltage dropping circuit.
According to the high-speed serial computer expansion bus standard backboard provided by the application, the microcontroller resets the exchange chip;
the clock circuit of the exchange chip is configured and controlled by the microcontroller;
monitoring the current of the exchange chip through the microcontroller, and calculating the power consumption of the exchange chip;
monitoring the temperature of the high-speed serial computer expansion bus standard backboard through the microcontroller;
and when the temperature of the high-speed serial computer expansion bus standard backboard is greater than or equal to a preset threshold value, starting a radiator corresponding to the high-speed serial computer expansion bus standard backboard through the microcontroller.
The high-speed serial computer expansion bus standard backboard provided by the application comprises a high-speed serial computer expansion bus standard slot, a switching chip, an Ethernet interface and a serial connection small computer system interface, wherein the high-speed serial computer expansion bus standard slot is connected with the switching chip, the Ethernet interface is connected with the switching chip, and the serial connection small computer system interface is connected with the switching chip.
Drawings
In order to more clearly illustrate the application or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a standard backplane of a high-speed serial computer expansion bus according to the present application;
FIG. 2 is a schematic diagram of a structural connection of a standard backplane of a high-speed serial computer expansion bus according to the present application;
FIG. 3 is a schematic diagram showing a second structural connection of the standard back plane of the expansion bus of the high-speed serial computer according to the present application;
FIG. 4 is a power topology of a standard backplane of a high-speed serial computer expansion bus provided by the present application;
fig. 5 is a functional schematic of a microcontroller of the standard backplane of the expansion bus of the high-speed serial computer provided by the application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The high speed serial computer expansion bus standard backplane of the present application is described below in conjunction with fig. 1-5.
Referring to fig. 1, the present application provides a high-speed serial computer expansion bus standard back board, which comprises a high-speed serial computer expansion bus standard slot, a switch chip, an ethernet interface and a serial connection small computer system interface; wherein: the high-speed serial computer expansion bus standard slot is connected with the exchange chip, the Ethernet interface is connected with the exchange chip, and the serial connection small computer system interface is connected with the exchange chip.
Specifically, a PCIE (peripheral component interconnect express, high-speed serial computer expansion bus standard) backplane includes two PCIE 4.0Switch chips (i.e., switch chips), a microcontroller and an external interface. The external interfaces include 10 PCIE 4.0x16 slots (i.e., high-speed serial computer expansion bus standard slots), two Slim SAS (Serial Attached SCSI, serial attached small computer system) interfaces, two gigabit ethernet interfaces, and a power interface (i.e., a power interface).
The high-speed serial computer expansion bus standard slot is used for installing acceleration cards of PCIE interfaces, such as GPU (graphics processing unit, graphic processor) and FPGA (Field Programmable Gate Array ) acceleration cards, etc., 10 acceleration cards can be installed, and other PCIE devices can be connected according to requirements besides the acceleration cards. The serial connection small computer system interface is connected with the existing server or is connected with an interface of expansion calculation inside the existing server; the Ethernet interface can be in interconnection communication with other Ethernet devices; the power interface is externally connected with a nominal +12V power supply.
As shown in FIG. 2, the high-speed serial computer expansion bus standard slot is connected with the switch chip, the Ethernet interface is connected with the switch chip, and the serial connection small computer system interface is connected with the switch chip.
The high-speed serial computer expansion bus standard backboard provided by the embodiment comprises a high-speed serial computer expansion bus standard slot, a switching chip, an Ethernet interface and a serial connection small computer system interface, wherein the high-speed serial computer expansion bus standard slot is connected with the switching chip, the Ethernet interface is connected with the switching chip, and the serial connection small computer system interface is connected with the switching chip. The expansibility of the artificial intelligent server is enhanced and the calculation performance of the single artificial intelligent server is improved by expanding the high-speed serial computer expansion bus standard slot on the high-speed serial computer expansion bus standard backboard of the single artificial intelligent server.
In one embodiment, the switching chip provided by the embodiment of the application comprises a first high-speed serial computer expansion bus standard switching chip and a second high-speed serial computer expansion bus standard switching chip, wherein the number of the high-speed serial computer expansion bus standard slots is n, and n is a positive integer; wherein: the number of the high-speed serial computer expansion bus standard slots connected with the first high-speed serial computer expansion bus standard exchange chip is m, wherein n=2m; the number of the high-speed serial computer expansion bus standard slots connected with the second high-speed serial computer expansion bus standard exchange chip is m.
Specifically, the two PCIE 4.0Switch chips are PCIE Switch1 and PCIE Switch2, that is, the first high-speed serial computer expansion bus standard Switch chip and the second high-speed serial computer expansion bus standard Switch chip, respectively.
As shown in fig. 2, half of the high-speed serial computer expansion bus standard slots are connected to the first high-speed serial computer expansion bus standard switch chip, and the other half of the high-speed serial computer expansion bus standard slots are connected to the first high-speed serial computer expansion bus standard switch chip, and if the number of the high-speed serial computer expansion bus standard slots is n (n is an even number in a positive integer), the number of the high-speed serial computer expansion bus standard slots connected to the first high-speed serial computer expansion bus standard switch chip is m, and the number of the high-speed serial computer expansion bus standard slots connected to the second high-speed serial computer expansion bus standard switch chip is also m, where n=2m.
The exchange chips provided in this embodiment are respectively connected to a corresponding number of high-speed serial computer expansion bus standard slots, and by expanding the high-speed serial computer expansion bus standard slots on the high-speed serial computer expansion bus standard back plate of a single artificial intelligent server, the expansibility of the artificial intelligent server is enhanced, and the computing performance of the single artificial intelligent server is improved.
In one embodiment, the ethernet interface provided in the embodiment of the present application includes a first ethernet interface and a second ethernet interface, where the first ethernet interface is connected to a first high-speed serial computer expansion bus standard switching chip; the second Ethernet interface is connected with a second high-speed serial computer expansion bus standard exchange chip.
Specifically, the two gigabit ethernet interfaces are respectively an ethernet port 1 (i.e., a first ethernet interface) and an ethernet port 2 (i.e., a second ethernet interface), as shown in fig. 2, where the first ethernet interface is connected to the first high-speed serial computer expansion bus standard switching chip, and the second ethernet interface is connected to the second high-speed serial computer expansion bus standard switching chip.
The two ethernet interfaces provided in this embodiment are respectively connected to corresponding switching chips.
In one embodiment, the serial connection small computer system interface provided by the embodiment of the application comprises a first serial connection small computer system interface and a second serial connection small computer system interface, wherein the first serial connection small computer system interface is connected with a first high-speed serial computer expansion bus standard exchange chip; the second serial connection small computer system interface is connected with the second high-speed serial computer expansion bus standard exchange chip.
Specifically, the two serial connection small computer system interfaces are a serial connection small computer system interface 1 (i.e., a first serial connection small computer system interface) and a serial connection small computer system interface 2 (i.e., a second serial connection small computer system interface), respectively, as shown in fig. 2, where the first serial connection small computer system interface is connected to a first high-speed serial computer expansion bus standard exchange chip, and the second serial connection small computer system interface is connected to a second high-speed serial computer expansion bus standard exchange chip.
The two serial connection small computer system interfaces provided in this embodiment are respectively connected with the corresponding exchange chips.
In one embodiment, the high-speed serial computer expansion bus standard back board provided by the embodiment of the application further comprises a first multiplexer and a second multiplexer, and the connection between the first high-speed serial computer expansion bus standard exchange chip and the second high-speed serial computer expansion bus standard exchange chip is established through the first multiplexer and the second multiplexer.
Specifically, as shown in fig. 2 and 3, when connection needs to be established between the first high-speed serial computer expansion bus standard switch chip and the second high-speed serial computer expansion bus standard switch chip, first, connection between the first high-speed serial computer expansion bus standard switch chip and the high-speed serial computer expansion bus standard slot 5 is disconnected by the first multiplexer, connection between the second high-speed serial computer expansion bus standard switch chip and the high-speed serial computer expansion bus standard slot 6 is disconnected by the second multiplexer, and then connection between the first high-speed serial computer expansion bus standard switch chip and the second high-speed serial computer expansion bus standard switch chip is established by the first multiplexer and the second multiplexer.
The present embodiment establishes a connection between a first high-speed serial computer expansion bus standard switching chip and a second high-speed serial computer expansion bus standard switching chip through a first multiplexer and a second multiplexer.
In one embodiment, the first high-speed serial computer expansion bus standard slot is connected with the first high-speed serial computer expansion bus standard exchange chip through a first multiplexer, and the second high-speed serial computer expansion bus standard slot is connected with the second high-speed serial computer expansion bus standard exchange chip through a second multiplexer; establishing connection of the first high-speed serial computer expansion bus standard exchange chip with the second high-speed serial computer expansion bus standard exchange chip through the first multiplexer and the second multiplexer comprises: disconnecting the first high-speed serial computer expansion bus standard slot from the first high-speed serial computer expansion bus standard switching chip through a first multiplexer, and disconnecting the second high-speed serial computer expansion bus standard slot from the second high-speed serial computer expansion bus standard switching chip through a second multiplexer; and establishing connection between the first high-speed serial computer expansion bus standard exchange chip and the first multiplexer, and connection between the second high-speed serial computer expansion bus standard exchange chip and the second multiplexer.
Specifically, as shown in fig. 2 and 3, when connection needs to be established between the first high-speed serial computer expansion bus standard exchange chip and the second high-speed serial computer expansion bus standard exchange chip, first, connection between the first high-speed serial computer expansion bus standard exchange chip and the high-speed serial computer expansion bus standard slot 5 is disconnected by the first multiplexer, and connection between the second high-speed serial computer expansion bus standard exchange chip and the high-speed serial computer expansion bus standard slot 6 is disconnected by the second multiplexer, and then connection between the first high-speed serial computer expansion bus standard exchange chip and the first multiplexer is established, and connection between the second high-speed serial computer expansion bus standard exchange chip and the second high-speed serial computer expansion bus standard exchange chip is established by the first multiplexer and the second multiplexer, so that connection between the first high-speed serial computer expansion bus standard exchange chip and the second high-speed serial computer expansion bus standard exchange chip is realized by the first multiplexer and the second multiplexer.
The connection between the first high-speed serial computer expansion bus standard exchange chip and the second high-speed serial computer expansion bus standard exchange chip is realized through the first multiplexer and the second multiplexer.
In one embodiment, the switch chip, the first multiplexer, the second multiplexer, and the microcontroller are powered by a buck circuit corresponding to the high-speed serial computer expansion bus standard backplane.
Specifically, the standard backboard of the high-speed serial computer expansion bus provided by the embodiment is a high-speed device, and needs to support a DC-DC (direct current to direct current) circuit with high current output and reasonable power distribution to meet the requirement of stable operation of the backboard, as shown in fig. 4, the power supply is powered by nominal +12v, passes through an anti-reverse connection circuit and then is transmitted to each DC-DC circuit, and the anti-reverse connection circuit reduces the loss of the anti-reverse connection circuit, simultaneously strengthens the use safety and protects the post-stage circuit.
In this embodiment, the voltage-reducing circuit corresponding to the standard back board of the expansion bus of the high-speed serial computer supplies power to the switching chip, the first multiplexer, the second multiplexer and the microcontroller.
In one embodiment, the voltage reducing circuit comprises a first voltage reducing circuit and a second voltage reducing circuit, and the first high-speed serial computer expansion bus standard exchange chip is powered by the first voltage reducing circuit; and supplying power to the second high-speed serial computer expansion bus standard exchange chip through the second voltage reducing circuit.
Specifically, as shown in fig. 4, the voltage reducing circuit includes a first voltage reducing circuit and a second voltage reducing circuit, and supplies power to the first high-speed serial computer expansion bus standard exchange chip through the first voltage reducing circuit; the second step-down circuit is used for supplying power to the second high-speed serial computer expansion bus standard exchange chip, the voltage for supplying power to the high-speed serial computer expansion bus standard exchange chip comprises 0.9V, 1.2V and 1.8V, and the power supply of the first high-speed serial computer expansion bus standard exchange chip and the power supply of the second high-speed serial computer expansion bus standard exchange chip are mutually independent.
The present embodiment supplies power to the switching chip through the first step-down circuit and the second step-down circuit.
In one embodiment, the step-down circuit further comprises a third step-down circuit through which the microcontroller is powered.
Specifically, as shown in fig. 4, the step-down circuit further includes a third step-down circuit, and the third step-down circuit is used for supplying power to the first multiplexer, the second multiplexer and the microcontroller, wherein the first multiplexer, the second multiplexer and the microcontroller are mainly supplied with 3.3V power with other circuits, and the power consumption of the circuit is lower than that of the switching chip.
The present embodiment provides power to the microcontroller through a third buck circuit.
In one embodiment, the microcontroller performs a reset process on the switch chip; the clock circuit of the exchange chip is configured and controlled by the microcontroller; monitoring the current of the exchange chip through the microcontroller, and calculating the power consumption of the exchange chip; monitoring the temperature of the high-speed serial computer expansion bus standard backboard through the microcontroller; and when the temperature of the high-speed serial computer expansion bus standard backboard is greater than or equal to a preset threshold value, starting a radiator corresponding to the high-speed serial computer expansion bus standard backboard through the microcontroller.
Specifically, as shown in fig. 5, the microcontroller provided in this embodiment mainly can control system reset, clock circuit, power supply current, and temperature monitoring and heat dissipation control. Under the condition of abnormal system operation or special condition, the microcontroller can directly reset the output signal of the exchange chip, and the microcontroller resets the exchange chip; the microcontroller can configure and control the clock circuit of the exchange chip according to the requirement; the current of the exchange chip is larger in the running process, the current of the exchange chip is monitored by the microcontroller, and the power consumption of the exchange chip is calculated; the exchange chip can generate certain heat when in full-speed operation, the normal operation of the chip can be influenced when the temperature is too high, and the microcontroller can monitor the temperature of the standard backboard of the high-speed serial computer expansion bus (a temperature sensor is placed close to the exchange chip); when the temperature of the high-speed serial computer expansion bus standard backboard is larger than or equal to a preset threshold value, the heat radiator corresponding to the high-speed serial computer expansion bus standard backboard is started by the microcontroller to radiate, so that the temperature of a chip is reduced, and the stable operation of the system is ensured.
The embodiment ensures the stable operation of the system through the microcontroller.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims (8)
1. The high-speed serial computer expansion bus standard backboard is characterized by comprising a high-speed serial computer expansion bus standard slot, a switching chip, an Ethernet interface and a serial connection small computer system interface; the exchange chip comprises a first high-speed serial computer expansion bus standard exchange chip and a second high-speed serial computer expansion bus standard exchange chip; wherein:
the high-speed serial computer expansion bus standard backboard further comprises a first multiplexer and a second multiplexer, and the connection between the first high-speed serial computer expansion bus standard exchange chip and the second high-speed serial computer expansion bus standard exchange chip is established through the first multiplexer and the second multiplexer;
the high-speed serial computer expansion bus standard slot is connected with the exchange chip, the Ethernet interface is connected with the exchange chip, and the serial connection small computer system interface is connected with the exchange chip;
the first high-speed serial computer expansion bus standard slot is connected with the first high-speed serial computer expansion bus standard exchange chip through the first multiplexer, and the second high-speed serial computer expansion bus standard slot is connected with the second high-speed serial computer expansion bus standard exchange chip through the second multiplexer; the establishing connection between the first high-speed serial computer expansion bus standard exchange chip and the second high-speed serial computer expansion bus standard exchange chip through the first multiplexer and the second multiplexer comprises the following steps:
disconnecting the first high-speed serial computer expansion bus standard slot from the first high-speed serial computer expansion bus standard switching chip through the first multiplexer, and disconnecting the second high-speed serial computer expansion bus standard slot from the second high-speed serial computer expansion bus standard switching chip through the second multiplexer;
and establishing connection between the first high-speed serial computer expansion bus standard exchange chip and the first multiplexer and connection between the second high-speed serial computer expansion bus standard exchange chip and the second multiplexer.
2. The high-speed serial computer expansion bus standard back plate according to claim 1, wherein the number of the high-speed serial computer expansion bus standard slots is n, n being a positive integer; wherein:
the number of the high-speed serial computer expansion bus standard slots connected with the first high-speed serial computer expansion bus standard exchange chip is m, wherein n=2m;
the number of the high-speed serial computer expansion bus standard slots connected with the second high-speed serial computer expansion bus standard exchange chip is m.
3. The high-speed serial computer expansion bus standard backplane according to claim 2, wherein the ethernet interface comprises a first ethernet interface and a second ethernet interface; the first Ethernet interface is connected with the first high-speed serial computer expansion bus standard exchange chip;
the second Ethernet interface is connected with the second high-speed serial computer expansion bus standard exchange chip.
4. The high-speed serial computer expansion bus standard backplane of claim 2, wherein the serial connection small computer system interface comprises a first serial connection small computer system interface and a second serial connection small computer system interface; the first serial connection small computer system interface is connected with the first high-speed serial computer expansion bus standard exchange chip;
the second serial connection small computer system interface is connected with the second high-speed serial computer expansion bus standard exchange chip.
5. The high-speed serial computer expansion bus standard backplane of claim 1, further comprising a microcontroller; and supplying power to the switching chip, the first multiplexer, the second multiplexer and the microcontroller through the voltage reducing circuit corresponding to the high-speed serial computer expansion bus standard backboard.
6. The high-speed serial computer expansion bus standard back plate according to claim 5, wherein the step-down circuit comprises a first step-down circuit and a second step-down circuit; supplying power to the first high-speed serial computer expansion bus standard exchange chip through the first voltage reducing circuit;
and supplying power to the second high-speed serial computer expansion bus standard exchange chip through the second voltage reducing circuit.
7. The high-speed serial computer expansion bus standard back plate according to claim 5, wherein the step-down circuit further comprises a third step-down circuit; and supplying power to the first multiplexer, the second multiplexer and the microcontroller through the third voltage dropping circuit.
8. The high-speed serial computer expansion bus standard back plate according to claim 5, wherein the exchange chip is reset by the microcontroller;
the clock circuit of the exchange chip is configured and controlled by the microcontroller;
monitoring the current of the exchange chip through the microcontroller, and calculating the power consumption of the exchange chip;
monitoring the temperature of the high-speed serial computer expansion bus standard backboard through the microcontroller;
and when the temperature of the high-speed serial computer expansion bus standard backboard is greater than or equal to a preset threshold value, starting a radiator corresponding to the high-speed serial computer expansion bus standard backboard through the microcontroller.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211338698.9A CN115794711B (en) | 2022-10-28 | 2022-10-28 | High-speed serial computer expansion bus standard backboard |
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| CN202211338698.9A CN115794711B (en) | 2022-10-28 | 2022-10-28 | High-speed serial computer expansion bus standard backboard |
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| CN115794711B true CN115794711B (en) | 2023-12-08 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109408440A (en) * | 2018-11-06 | 2019-03-01 | 郑州云海信息技术有限公司 | A kind of PCIE expanding unit |
| CN110908475A (en) * | 2019-12-26 | 2020-03-24 | 中航鸿电(北京)信息科技有限公司 | Shenwei 1621CPU ICH-free 2 suite server mainboard |
| CN111538693A (en) * | 2020-04-27 | 2020-08-14 | 中国科学院自动化研究所 | PCIE bus expansion system and method |
| CN215599631U (en) * | 2021-08-16 | 2022-01-21 | 中航鸿电(北京)信息科技有限公司 | Double-circuit server mainboard based on Shenwei 3231 processor |
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2022
- 2022-10-28 CN CN202211338698.9A patent/CN115794711B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109408440A (en) * | 2018-11-06 | 2019-03-01 | 郑州云海信息技术有限公司 | A kind of PCIE expanding unit |
| CN110908475A (en) * | 2019-12-26 | 2020-03-24 | 中航鸿电(北京)信息科技有限公司 | Shenwei 1621CPU ICH-free 2 suite server mainboard |
| CN111538693A (en) * | 2020-04-27 | 2020-08-14 | 中国科学院自动化研究所 | PCIE bus expansion system and method |
| CN215599631U (en) * | 2021-08-16 | 2022-01-21 | 中航鸿电(北京)信息科技有限公司 | Double-circuit server mainboard based on Shenwei 3231 processor |
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