CN115768130A - Semiconductor integrated circuit device and method for manufacturing the same - Google Patents
Semiconductor integrated circuit device and method for manufacturing the same Download PDFInfo
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- CN115768130A CN115768130A CN202211500818.0A CN202211500818A CN115768130A CN 115768130 A CN115768130 A CN 115768130A CN 202211500818 A CN202211500818 A CN 202211500818A CN 115768130 A CN115768130 A CN 115768130A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
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Abstract
The application discloses semiconductor integrated circuit device and manufacturing method thereof, the semiconductor integrated circuit device controls the etching times and the depth of each etching when the etching of the side wall layer is formed, so that the top of the side wall layer is lower than the top of the upper electrode and/or the bottom of the side wall layer is higher than the bottom of the lower electrode as far as possible on the basis that the side wall layer is ensured to cover the resistance change layer, and an optimized structure is formed. When the top of the side wall layer is lower than the top of the upper electrode, a deposition space with a wide upper part and a narrow lower part can be formed, and holes formed during deposition of the dielectric layer are reduced; when the bottom of the side wall layer is higher than the bottom of the lower electrode, the lower electrode can form a structure with a narrow top and a wide bottom, and the resistance change layer and the upper electrode can be better supported, so that the structure of the whole element is more stable. Therefore, the semiconductor integrated circuit device can meet the miniaturization requirement more easily and has better quality.
Description
Technical Field
The present invention relates to the field of semiconductors, and more particularly, to a semiconductor integrated circuit device and a method of manufacturing the same.
Background
The resistive memory generally includes a plurality of resistive memory cells, wherein the resistive memory cells generally have a sandwich structure in which a bottom electrode, a resistive layer, and a top electrode are stacked from bottom to top.
In order to further protect the resistance change layer, it is often necessary to cover a sidewall layer on the outside of the resistance change layer. In view of simplifying the manufacturing process, the sidewall layer may cover the element formed by the lower electrode, the resistance change layer and the upper electrode from top to bottom, rather than only the outer side of the resistance change layer. However, the stability of the element (including the lower electrode, the resistive layer, and the upper electrode) with the above structure is poor, and the element is easily collapsed when the size of the resistive memory cell is continuously reduced; voids are also easily created when depositing the dielectric layer.
The above problems all cause defects in the function and quality of the semiconductor integrated circuit device.
Disclosure of Invention
In view of the above technical problems, the present applicant has creatively provided a semiconductor integrated circuit device and a method of manufacturing the same.
According to a first aspect of the embodiments of the present application, a semiconductor integrated circuit device is provided, which includes at least one resistive memory cell, where the resistive memory cell includes an upper electrode, a resistive layer, and a lower electrode, the upper electrode and the lower electrode are respectively located at upper and lower sides of the resistive layer, the resistive memory cell is provided with a first sidewall layer, the first sidewall layer covers an outer side of the resistive layer, a top of the first sidewall layer is lower than a top of the upper electrode, and/or a bottom of the first sidewall layer is higher than a bottom of the lower electrode.
According to an embodiment of the application, the resistance change memory cell is further provided with at least one second side wall layer, and the second side wall layer covers the outer side of the upper electrode.
According to an embodiment of the present application, the second sidewall layer is sleeved with the first sidewall layer, and the second sidewall layer is located inside the first sidewall layer.
According to an embodiment of the present application, the material used for the sidewall layer includes alumina Al2O3.
According to a second aspect of embodiments of the present application, there is provided a manufacturing method of a semiconductor integrated circuit device, the manufacturing method including: forming a lower electrode on a substrate; forming a resistance change layer; forming an upper electrode; and forming a first side wall layer so that the first side wall layer covers the outer side of the resistance change layer, wherein the top of the first side wall layer is lower than the top of the upper electrode and/or the bottom of the side wall layer is higher than the bottom of the lower electrode.
According to an embodiment of the present application, forming a first sidewall layer includes: etching to the specified position of the lower electrode, wherein the specified position is higher than the bottom of the lower electrode; depositing a sidewall layer material, and etching the sidewall layer material to form a first sidewall layer.
According to an embodiment of the present application, before forming the first sidewall layer, the manufacturing method further includes: at least one second sidewall layer is formed, and the second sidewall layer covers the outer side of the upper electrode.
According to an embodiment of the present application, forming at least one second sidewall layer includes: etching at least once to the designated position of the upper electrode; after etching the designated position of the upper electrode each time, depositing a side wall layer material, and etching the side wall layer material to form one second side wall layer in at least one second side wall layer.
According to an embodiment of the present application, forming a first sidewall layer includes: etching to the bottom of the lower electrode; depositing a sidewall layer material, and etching the sidewall layer material to form a first sidewall layer.
According to an embodiment of the present application, etching the sidewall layer material includes: the sidewall material is anisotropically etched.
The application discloses a semiconductor integrated circuit device and a manufacturing method thereof, the semiconductor integrated circuit device controls the etching times and the depth of each etching when the etching for forming a side wall layer is carried out, so that the top of the side wall layer is lower than the top of an upper electrode and/or the bottom of the side wall layer is higher than the bottom of a lower electrode as far as possible on the basis that the side wall layer is ensured to cover a resistance change layer, and a more optimized structure is formed.
When the top of the sidewall layer is lower than the top of the upper electrode, a dielectric layer deposition space with a wide top and a narrow bottom can be formed, and holes which may be formed during the deposition of the dielectric layer can be reduced.
When the bottom of the side wall layer is higher than the bottom of the lower electrode, the lower electrode can form a structure with a narrow top and a wide bottom, and the resistance change layer and the upper electrode can be better supported, so that the structure of the whole element is more stable.
When the top of the sidewall layer is lower than the top of the top electrode and the bottom of the sidewall layer is higher than the bottom of the bottom electrode, all the above effects can be obtained. Therefore, the semiconductor integrated circuit device can more easily meet the miniaturization requirement, and the defects in function or quality are further reduced.
It is to be understood that the implementation of the embodiments of the present application does not need to achieve all the above advantages, but a specific technical solution may achieve a specific technical effect, and other implementations of the embodiments of the present application can achieve advantages not mentioned above.
Drawings
The above and other objects, features and advantages of exemplary embodiments of the present application will become readily apparent from the following detailed description read in conjunction with the accompanying drawings. Several embodiments of the present application are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which:
in the drawings, the same or corresponding reference numerals indicate the same or corresponding parts.
Fig. 1 is a schematic structural cross-sectional view illustrating a resistive random access memory in the prior art;
FIG. 2 is a schematic diagram illustrating a hole that may be generated during the deposition of a dielectric layer according to the prior art;
FIG. 3 is a schematic cross-sectional view of one embodiment of the semiconductor integrated circuit device of the present application;
FIG. 4 is a schematic cross-sectional view of another embodiment of a semiconductor integrated circuit device according to the present application;
FIG. 5 is a schematic cross-sectional view of another embodiment of a semiconductor integrated circuit device of the present application;
FIG. 6 is a schematic flow chart showing a method for manufacturing a semiconductor integrated circuit device according to the present application;
FIG. 7 is a schematic view of a manufacturing process for the embodiment of FIG. 3 of the present application;
FIG. 8 is a schematic cross-sectional view of the structure at a stage in the manufacture of the embodiment of FIG. 3 of the present application;
FIG. 9 is a schematic cross-sectional view of the structure at a stage in the manufacture of the embodiment of the present application shown in FIG. 3;
FIG. 10 is a schematic cross-sectional view of the structure at a stage in the manufacture of the embodiment of FIG. 3 of the present application;
FIG. 11 is a schematic cross-sectional view of the structure at a stage in the manufacture of the embodiment of the present application shown in FIG. 3;
FIG. 12 is a schematic cross-sectional view of the structure at a stage in the manufacture of the embodiment of the present application shown in FIG. 3;
FIG. 13 is a schematic cross-sectional view of the structure at a stage in the manufacture of the embodiment of FIG. 3 of the present application;
FIG. 14 is a schematic cross-sectional view of the structure at a stage in the manufacture of the embodiment of FIG. 3 of the present application;
FIG. 15 is a schematic cross-sectional view of the structure at a stage in the manufacture of the embodiment of the present application illustrated in FIG. 3;
FIG. 16 is a schematic cross-sectional view of the structure at a stage in the manufacture of the embodiment of FIG. 3 of the present application;
FIG. 17 is a schematic cross-sectional view of the structure at a stage in the manufacture of the embodiment of the present application shown in FIG. 3;
fig. 18 shows a schematic cross-sectional view of the structure at a stage in the manufacturing process of the embodiment of the present application shown in fig. 3.
Detailed Description
In order to make the objects, features and advantages of the present application more obvious and understandable, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments obtained by a person skilled in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.
In the description herein, reference to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In order to describe the three-dimensional structure of the semiconductor integrated circuit device in a multi-angle manner, the structural schematic diagram obtained by vertically cutting the semiconductor integrated circuit device is called a structural cross-sectional schematic diagram; the schematic structural view obtained by horizontally cutting the semiconductor integrated circuit device is referred to as a structural cross-sectional view.
At present, a common resistive random access memory cell, as shown in fig. 1, often adopts a sandwich structure stacked from the bottom up layer by layer, including: the semiconductor device comprises a substrate 101, a through hole 102 connected with a first metal layer of the substrate, a lower electrode 103, a resistance change layer 104, an oxygen storage layer 105, an upper electrode 106 and a metal layer 107. In addition, in order to protect the resistance change layer 104 and to generate conductive filaments more stably, a sidewall layer 108 is further coated on the outside of the resistance change layer to prevent the dielectric layer 109 from interfering with the resistance change layer 104.
As shown in fig. 1, for the sake of simplifying the manufacturing process, the sidewall layer 108 may form a full coverage from top to bottom for the device formed by the lower electrode 103, the resistance change layer 104, the oxygen storage layer 105 and the upper electrode 106, i.e. the top of the sidewall layer 108 is flush with the top of the upper electrode 106, and the bottom of the sidewall layer 108 is flush with the bottom of the lower electrode 103.
However, the element (including the lower electrode 103, the resistive layer 104, the oxygen storage layer 105, and the upper electrode 106) having the above structure has a pillar-shaped structure without a pedestal, and is poor in stability, and when the size of the resistive memory cell is continuously reduced, particularly when the area is reduced, the element becomes thin and is easily collapsed.
In addition, the adoption of the structure can cause some defects in function or quality in the process of manufacturing the resistance variable memory unit.
For example, since the angle of the sidewall layer 108 to the substrate is almost 90 degrees vertical, this results in the need to deposit the dielectric layer 109 into the trench 201 that is straight up and down as shown in the left side (a) of fig. 2 during the formation of the dielectric layer 109. Since the dielectric layer 109 may be overhung (overhung) in the early stage of deposition, when the bottom dielectric layer is not completely filled with the dielectric layer material and the upper dielectric layer is sealed, the hole 202 shown in the left side (b) of fig. 2 is likely to be formed.
For example, since the sidewall layer 108 is formed by etching from the upper electrode 106 to the lower electrode 103. While dry etch (DryEtch) is the most commonly used etch process in forming the sidewall layer. Dry etching refers to an etching technique for performing pattern transfer by generating plasma containing charged particles such as particles and electrons, first-order neutral atoms, molecules, and radicals having high chemical activity by a glow discharge (glow discharge) method.
In the process of forming the sidewall layer by using dry etching, the area of the exposed metal part on the outer side of the upper electrode is continuously increased, and the exposed metal part can absorb charged particles in plasma, so that more and more charged particles are received by the upper electrode, and when enough charged particles are received by the upper electrode, the voltage difference between the upper electrode and the lower electrode is too large, a strong current is formed to break through the resistance change layer, and the plasma is damaged.
Therefore, when etching is performed from the upper electrode 106 to the lower electrode 103, the exposed metal portion outside the upper electrode 106 continuously absorbs the charged particles in the plasma, so that the voltage difference between the upper electrode 106 and the lower electrode 103 is too large, and a strong current is formed to break through the resistive layer 104, thereby causing plasma damage.
For this reason, the present inventors have creatively conceived that the main function of the sidewall layer 108 is to protect the resistive layer 104, and if etching is performed several times during the manufacturing process and the depth of each etching is controlled, it is highly possible to make the top of the sidewall layer lower than the top of the upper electrode and/or to make the bottom of the sidewall layer higher than the bottom of the lower electrode, thereby solving the above-mentioned problems.
Based on the above inventive concept, the present application provides a semiconductor integrated circuit device and a method of manufacturing the same.
Fig. 3 is a schematic cross-sectional view of a semiconductor integrated circuit device according to an embodiment of the present invention. As shown in fig. 3, the semiconductor integrated circuit device includes at least one resistive memory cell, wherein each resistive memory cell includes an upper electrode 306, a resistive layer 304, and a lower electrode 303, the upper electrode 306 and the lower electrode 303 are respectively located at upper and lower sides of the resistive layer 304, the resistive memory cell is provided with a first sidewall layer 308, the first sidewall layer 308 covers an outer side of the resistive layer 304, a top of the first sidewall layer 308 is lower than a top of the upper electrode 306, and a bottom of the first sidewall layer 308 is higher than a bottom of the lower electrode 303.
Since the top of the first sidewall layer 308 is lower than the top of the upper electrode 306, a deposition space with a wider top and a narrower bottom is formed, so as to reduce the voids that may be formed when depositing the dielectric layer 310.
Moreover, since the bottom of the first sidewall layer 308 is higher than the bottom of the lower electrode 303, the lower electrode 303 can form a more stable structure with a narrow top and a wide bottom, like a step, so as to better support the resistive layer 304 and the upper electrode 306, so that the structure of the whole device (including the lower electrode 303, the resistive layer 304 and the upper electrode 306) is more stable, and the requirement of miniaturization can be better satisfied.
Thus, the structure adopted by the embodiment of the semiconductor integrated circuit device of the present application shown in fig. 3 can make the semiconductor integrated circuit device more easily meet the miniaturization requirement, and further reduce the defects in function or quality.
Further, in the embodiment of the semiconductor integrated circuit device of the present application shown in fig. 3, a second sidewall layer 309 is provided in addition to the first sidewall layer 308. The second sidewall layer 309 covers the outside of the upper electrode 306, is located inside the first sidewall layer 308, and is sleeved with the first sidewall layer 308.
Therefore, on one hand, the metal part outside the upper electrode 306 can be prevented from being exposed to plasma used in subsequent etching after the first etching, and the plasma damage possibly generated in the subsequent etching can be avoided; on the other hand, the second sidewall layer 309 is located inside the first sidewall layer 308 and sleeved with the first sidewall layer 308, and can also form a more stable sleeved structure with the first sidewall layer 308, so that the structure of the whole device (including the lower electrode 303, the resistive layer 304 and the upper electrode 306) is more stable, and the requirement of miniaturization can be better satisfied.
The second sidewall layer 309 belongs to a gain structure, and the second sidewall layer 309 may not be provided in other embodiments of the semiconductor integrated circuit device of the present application, so as to simplify the manufacturing process.
In addition to the second sidewall layer 309, in the embodiment of the semiconductor integrated circuit device of the present application shown in fig. 3, a common structure of the operation of the resistance change type memory cell is provided, including: the resistive random access memory comprises a substrate 301, a through hole 302 for connecting the resistive random access memory unit and the substrate 301, an oxygen storage layer 305 for attracting oxygen to generate more oxygen vacancy, a metal layer 307 connected with an upper electrode 306, a dielectric layer 310 for filling the gap between the resistive random access units and blocking the electric communication between the resistive random access units, and the like. The oxygen storage layer 305 also belongs to a gain structure, and an implementer may set or not set the oxygen storage layer according to actual needs.
It should be noted that, in a specific application scenario, the above problems do not occur at the same time. For example, in an application scenario with low requirements on miniaturization, the risk of collapse is low; under the conditions that the height of the device is limited and the groove is wider, the probability of generating holes in the deposited dielectric layer is correspondingly reduced; plasma damage can be avoided even when the antenna ratio is suitable. In the above case, the structure of the semiconductor integrated device of the present application shown in fig. 3 may be substituted to further simplify the manufacturing process.
Fig. 4 shows another embodiment of the semiconductor integrated circuit device according to the present application, which is mainly applied in a scenario where requirements for miniaturization are not high and a risk of collapse is small.
As shown in fig. 4, the semiconductor integrated circuit device includes at least one resistive memory cell, where each resistive memory cell includes an upper electrode 406, a resistive layer 404, and a lower electrode 403, the upper electrode 406 and the lower electrode 403 are respectively located at upper and lower sides of the resistive layer 404, the resistive memory cell is provided with a first sidewall layer 408, the first sidewall layer 408 covers an outer side of the resistive layer 404, a top of the first sidewall layer 408 is lower than a top of the upper electrode 406, but a bottom of the first sidewall layer 408 is flush with a bottom of the lower electrode 403.
In addition, in the embodiment shown in fig. 4 showing the semiconductor integrated device of the present application, a second side wall layer 409 is also provided, as well as the substrate 401, the via hole 402 for connecting the resistive memory cell and the substrate 401, the oxygen storage layer 405 for attracting oxygen to generate more oxygen vacancies, the metal layer 407 connected to the upper electrode 406, and the dielectric layer 410 for filling the gap between the resistive cells and blocking the electrical connection between the resistive cells, and the like.
Since the top of the first sidewall layer 408 is lower than the top of the upper electrode 406, a deposition space with a wide top and a narrow bottom can be formed, so that holes possibly formed during the deposition of the dielectric layer 410 can be reduced; similarly, by multiple etching, the time for exposing the metal area of the upper electrode 406 to each etching is reduced, so that the absorbed electric particles are reduced, thereby avoiding or reducing the plasma loss to the resistive layer 404.
As the application scenario of the embodiment of the semiconductor integrated circuit device of the present application shown in fig. 4 has low requirements for miniaturization and has a low risk of collapse, the step of etching the lower electrode 403 for multiple times can be omitted, so that the manufacturing process is simpler.
Fig. 5 shows another embodiment of the semiconductor integrated circuit device of the present application, which is mainly applied in a scenario where the antenna ratio is acceptable, there is no risk of plasma damage, but the requirement for miniaturization is high, and there may be a risk of collapse.
As shown in fig. 5, the semiconductor integrated circuit device includes at least one resistive memory cell, where each resistive memory cell includes an upper electrode 506, a resistive layer 504, and a lower electrode 503, the upper electrode 506 and the lower electrode 503 are respectively located at upper and lower sides of the resistive layer 504, the resistive memory cell is provided with a first sidewall layer 508, the first sidewall layer 508 covers an outer side of the resistive layer 504, a bottom of the first sidewall layer 508 is higher than a bottom of the lower electrode 503, but a top of the first sidewall layer 508 is flush with a top of the upper electrode 506.
In addition, in the embodiment of the semiconductor integrated device of the present application shown in fig. 5, a substrate 501, a through hole 502 for connecting the resistive random access memory cell and the substrate 501, an oxygen storage layer 505 for attracting oxygen to generate more oxygen vacancies, a metal layer 507 connected to the upper electrode 506, and a dielectric layer 510 for filling the gap between the resistive random access cells and blocking the electrical communication between the resistive random access cells are further provided.
Since the bottom of the first sidewall layer 508 is higher than the bottom of the lower electrode 503, the lower electrode 503 can form a more stable structure with a narrow top and a wide bottom, like a step, so as to better support the resistive layer 504 and the upper electrode 506, so that the structure of the whole device (including the lower electrode 503, the resistive layer 504 and the upper electrode 506) is more stable, and the requirement of miniaturization can be better satisfied.
Since the semiconductor integrated device shown in fig. 5 is mainly applied in a scene where the antenna ratio is acceptable and there is no risk of plasma damage, the step of etching the upper electrode 506 for many times can be omitted, and the second sidewall layer does not need to be formed, so that the manufacturing process is simpler.
Further, the present application also provides a method of manufacturing a semiconductor integrated circuit device, as shown in fig. 6, the method including:
operation S610 of forming a lower electrode on a substrate;
the substrate refers to a generic term for manufacturing electronic components based on embodiments of the semiconductor integrated circuit device of the present application, and generally includes a bottom plate, a dielectric material layer on the bottom plate, a via hole formed in the dielectric material layer and having a metal material deposited therein, and a metal layer and a circuit connected to the via hole.
The lower electrode is formed on the substrate by depositing electrode material. Any suitable deposition process may be used to deposit the electrode material, such as physical vapor deposition, chemical vapor deposition, or atomic deposition, for example.
Operation S620, forming a resistance change layer;
wherein, the formation of the resistance-change layer can be realized by depositing the material of the resistance-change layer. Any suitable deposition process may be used to deposit the resistive layer material, such as physical vapor deposition, chemical vapor deposition, or atomic deposition.
Operation S630, forming an upper electrode;
wherein, the formation of the upper electrode can be realized by depositing electrode material. Any suitable deposition process may be used to deposit the electrode material, such as physical vapor deposition, chemical vapor deposition, or atomic deposition, among others.
In operation S640, a first sidewall layer is formed such that the first sidewall layer covers an outer side of the resistance change layer, a top of the first sidewall layer is lower than a top of the upper electrode and/or a bottom of the sidewall layer is higher than a bottom of the lower electrode.
In order to enable the first side wall layer to cover the outer side of the resistance change layer, the top of the first side wall layer is lower than the top of the upper electrode and/or the bottom of the side wall layer is higher than the bottom of the lower electrode, and the etching can be achieved through multiple times of etching. Namely, after etching to a specified depth each time, stopping etching, depositing materials, then etching next time, and etching to a deeper specified depth.
Therefore, a better structure with the top lower than the top of the upper electrode and/or the bottom of the side wall layer higher than the bottom of the lower electrode can be obtained by controlling the etching times and the etching depth, and the functional or quality defects possibly caused to the semiconductor integrated circuit device in the manufacturing process are reduced, so that the quality of the semiconductor integrated circuit device is better, and the service life of the semiconductor integrated circuit device is longer.
The etching is mainly realized by a dry etching process.
It should be noted that the above steps shown in fig. 6 are only main steps of manufacturing the semiconductor integrated circuit device according to the embodiment of the present application, and not all the steps. In the process of manufacturing a semiconductor integrated circuit device, other steps including grinding down the top, depositing an oxygen storage layer, depositing a dielectric layer, wiring, soldering, etc. may also be included depending on the product design of the semiconductor integrated circuit device.
Fig. 7 shows a manufacturing method used for manufacturing the semiconductor integrated circuit device embodiment of the present application shown in fig. 3, and as shown in fig. 7, the manufacturing method mainly includes:
step S7010, depositing a lower electrode material 303, a resistance change layer material 304, an oxygen storage layer material 305, an upper electrode material 306, and a hard mask layer material 311 in sequence over the substrate 301 and the via hole 302 shown in fig. 8, to obtain the structure shown in fig. 9;
the via 302 is connected to the first metal layer on the substrate 301, and may serve as a lower terminal of the resistive memory cell, where the terminal is a component for connecting an external wire.
Step S7020, coating a photoresist 312 and exposing to obtain the structure shown in fig. 10;
step S7030, etching the hard mask 311, and removing the photoresist 312 to obtain the structure shown in fig. 11;
wherein, dry etching process can be used for etching the hard mask 311 and removing the photoresist 312.
It should be noted that in this step, etching is stopped only to the bottom of the hard mask, and the etching does not continue to the upper electrode 306, and even does not etch to the bottom of the lower electrode 303 at one time.
Therefore, the metal on the side surface of the upper electrode can be prevented from being exposed in the plasma, and the absorption of charged particles is reduced.
Step S7040, etching the upper electrode 306 to a specific position with a specific depth to obtain the structure shown in fig. 12;
since the deeper the etching, the larger the area of the metal portion of the upper electrode 306 exposed to the plasma, the larger the antenna ratio, and when the antenna ratio is increased to a certain degree, a stronger current will be formed to penetrate the resistive layer to form plasma damage. Wherein, the antenna ratio refers to the ratio of the area of the upper electrode contacting the plasma (including the side surface without the upper sidewall) and the area of the resistive layer.
Therefore, the specific depth can be determined by the antenna ratio, and the depth is sufficient to keep the antenna ratio within a safe range.
To reduce plasma damage, multiple depositions and multiple etches may be performed until the etch depth can be below the bottom of the top electrode 306.
Step 7050, depositing a second sidewall layer 309, and performing anisotropic etching to obtain the structure shown in fig. 13;
the second sidewall layer 309 formed in this step can protect the top electrode 306, so that the metal portion outside the top electrode 306 is not exposed to plasma during the subsequent etching process, and plasma damage is not formed.
The anisotropic etching and the prolonged etching time can form better opening and reduce the formation of holes during the deposition of dielectric layer.
Step S7060, etching is performed again to reach a specified position (where the specified position is higher than the bottom of the lower electrode) of a specific depth in the lower electrode 303, so as to obtain the structure shown in fig. 14;
wherein, the specific depth needs to exceed the resistance change layer, and the optimal value of the specific depth needs to be larger than the thickness of the side wall layer, so that the protection effect of the side wall layer is better; the optimum value of the specific depth can be as small as possible under the premise of satisfying the protection effect of the sidewall layer, so as to prevent the device (including the bottom electrode 303, the resistive layer 304 and the top electrode 306) from collapsing.
Step S7070, depositing a first sidewall layer 308, and performing anisotropic etching to obtain the structure shown in fig. 15;
when depositing and etching the first sidewall layer 308, the deposition amount and the etching amount are controlled so that the top of the first sidewall layer 308 is lower than the top of the second sidewall layer 309 outside the first electrode, so that a space with a wide top and a narrow bottom (W1 > W2) of the deposited dielectric layer can be formed between two adjacent resistive random access memory cells as shown in fig. 16, thereby reducing holes that may be generated when depositing the dielectric layer.
Step S7080, etching the lower electrode 303, and distinguishing an independent resistance change memory cell to obtain the structure shown in fig. 17;
step S7090, depositing a dielectric layer 310, and removing the hard mask layer 311 to obtain the structure shown in fig. 18;
in step S7100, the metal layer 307 is formed and wiring is performed to obtain the semiconductor integrated circuit device embodiment of the present application shown in fig. 4.
If the semiconductor integrated circuit device is mainly applied to the scene with low requirements on miniaturization and low collapse risk, the semiconductor integrated circuit device embodiment of the present application shown in fig. 4 can be obtained by etching to the bottom of the lower electrode in step S7060, depositing the first sidewall layer, skipping step 7080, and continuing step 7090.
If the semiconductor integrated circuit device is mainly applied in a situation where the antenna ratio is acceptable and there is no risk of plasma damage, but the requirement for miniaturization is high and there may be a risk of collapse, the semiconductor integrated circuit device of the present application shown in fig. 5 can be obtained by etching to the bottom of the lower electrode at one time in the above step 7030, skipping steps S7040 to S7060, and continuing steps S7070 to S7100.
In the above embodiments of the semiconductor integrated circuit device of the present application, including the manufacturing process of the embodiments by applying the semiconductor integrated circuit device manufacturing method of the present application, the material used for each component is not limited.
For example, the first and second electrodes may use any suitable electrode material or materials, including but not limited to: aluminum (Al), copper (Cu), gold (Au), platinum (Pt), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), and the like.
The resistive layer may use any suitable resistive layer material or materials, including but not limited to: alumina (Al) x O y ) Copper oxide (Cu) x O y ) Hafnium oxide (Hf) x O y ) And Transition Metal Oxides (TMO).
The sidewall layer can be any suitable dielectric material or materials, including but not limited to: aluminum oxide (Al 2O 3), and the like.
The oxygen storage layer may use any suitable oxygen storage layer material or materials, including but not limited to: titanium (Ti) and tantalum (Ta).
The hard mask layer may use any suitable hard mask layer material or materials, including but not limited to: may be SiN or other material having a selective ratio to the oxygen storage layer. The material with the selectivity ratio to the oxygen storage layer is different from the material used by the oxygen storage layer, and the ratio of the etching rates of the hard mask and the oxygen storage layer is different.
The dielectric material may use any suitable dielectric material or materials, including but not limited to: ultra Low K (ULK) materials or other dielectric materials such as Nitride (Nitride), oxide (Oxide), etc.
The metal layer may use any suitable metal material or materials, including but not limited to: aluminum (Al), copper (Cu), gold (Au), platinum (Pt), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), and the like.
Further, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a component of' 8230; \8230;" does not exclude the presence of another like element in a process, method, article, or apparatus that comprises the element.
In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods may be implemented in other ways. The above-described device embodiments are merely illustrative, for example, the division of the cell is only one logic function division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another device, or some features may be omitted, or not implemented. In addition, the coupling, direct coupling or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between the devices or units may be electrical, mechanical or other forms.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A semiconductor integrated circuit device comprising at least one resistance change memory cell, the resistance change memory cell comprising an upper electrode, a resistance change layer, and a lower electrode, the upper electrode and the lower electrode being respectively located at upper and lower sides of the resistance change layer,
the resistance change type memory unit is provided with a first side wall layer, the first side wall layer covers the outer side of the resistance change layer, and the top of the first side wall layer is lower than the top of the upper electrode and/or the bottom of the first side wall layer is higher than the bottom of the lower electrode.
2. The semiconductor integrated circuit device according to claim 1, wherein the resistance change memory cell is further provided with at least one second sidewall layer covering an outer side of the upper electrode.
3. The semiconductor integrated circuit device of claim 2, wherein the second sidewall layer is nested with the first sidewall layer, the second sidewall layer being located inside the first sidewall layer.
4. The semiconductor integrated circuit device according to any one of claims 1 to 3, wherein the material used for the sidewall layer comprises alumina ai 2O3.
5. A method of manufacturing a semiconductor integrated circuit device, the method comprising:
forming a lower electrode on a substrate;
forming a resistance change layer;
forming an upper electrode;
forming a first sidewall layer such that the first sidewall layer covers an outer side of the resistance change layer, a top of the first sidewall layer being lower than a top of the upper electrode and/or a bottom of the sidewall layer being higher than a bottom of the lower electrode.
6. The method of manufacturing according to claim 5, wherein said forming a first sidewall layer includes:
etching to the specified position of the lower electrode, wherein the specified position is higher than the bottom of the lower electrode;
and depositing a side wall layer material, and etching the side wall layer material to form a first side wall layer.
7. The manufacturing method according to claim 5, wherein before the forming the first sidewall layer, the manufacturing method further includes:
forming at least one second sidewall layer covering an outer side of the upper electrode.
8. The method of manufacturing of claim 7, wherein said forming at least one second sidewall layer comprises:
etching at least once to the designated position of the upper electrode;
after each etching to the designated position of the upper electrode, depositing a sidewall layer material, and etching the sidewall layer material to form one second sidewall layer in the at least one second sidewall layer.
9. The method of manufacturing of claim 7, wherein said forming a first sidewall layer comprises:
etching to the bottom of the lower electrode;
and depositing a side wall layer material, and etching the side wall layer material to form a first side wall layer.
10. The method of manufacturing according to any one of claims 6, 8, and 9, wherein the etching the sidewall layer material comprises:
and carrying out anisotropic etching on the material of the side wall layer.
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| CN202211500818.0A CN115768130A (en) | 2022-11-28 | 2022-11-28 | Semiconductor integrated circuit device and method for manufacturing the same |
| PCT/CN2023/096741 WO2024113728A1 (en) | 2022-11-28 | 2023-05-29 | Semiconductor integrated circuit device and manufacturing method therefor |
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| CN202211500818.0A CN115768130A (en) | 2022-11-28 | 2022-11-28 | Semiconductor integrated circuit device and method for manufacturing the same |
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| WO2024113728A1 (en) * | 2022-11-28 | 2024-06-06 | 厦门半导体工业技术研发有限公司 | Semiconductor integrated circuit device and manufacturing method therefor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2014056941A (en) * | 2012-09-12 | 2014-03-27 | Toshiba Corp | Resistance change type memory |
| KR20150007520A (en) * | 2013-07-11 | 2015-01-21 | 에스케이하이닉스 주식회사 | Phase-change random access memory device and method of manufacturing the same |
| WO2015071982A1 (en) * | 2013-11-13 | 2015-05-21 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Storage device and storage device manufacturing method |
| CN113497183A (en) * | 2020-04-03 | 2021-10-12 | 中芯北方集成电路制造(北京)有限公司 | Semiconductor structure and forming method thereof |
| CN114665013A (en) * | 2022-03-23 | 2022-06-24 | 北京大学 | High-consistency memristor with annular side wall and preparation method thereof |
| CN115768130A (en) * | 2022-11-28 | 2023-03-07 | 厦门半导体工业技术研发有限公司 | Semiconductor integrated circuit device and method for manufacturing the same |
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| WO2024113728A1 (en) * | 2022-11-28 | 2024-06-06 | 厦门半导体工业技术研发有限公司 | Semiconductor integrated circuit device and manufacturing method therefor |
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