CN115763649A - Micro light-emitting element and preparation method thereof - Google Patents
Micro light-emitting element and preparation method thereof Download PDFInfo
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Abstract
The application discloses a micro light-emitting element and a preparation method thereof, wherein an ITO process is moved forward, ITO/MESA is combined for photoetching to simplify the process flow, the ITO over-etching phenomenon caused by overlay offset of ITO and MESA patterns is reduced, the MESA/DE patterns are simultaneously formed by secondary photoresist homogenizing and photoetching under the condition of not removing photoresist and one-time ICP etching, the one-time ICP etching is reduced, the chip manufacturing cost is reduced, and SiO is increased 2 The mask layer effectively protects the P-type gallium nitride layer and the ITO conducting layer in the ICP etching process, and avoids damage to the P-type gallium nitride layer and the ITO conducting layer caused by ICP over etching.
Description
Technical Field
The application relates to the technical field of optoelectronic devices, in particular to a micro light-emitting element and a preparation method thereof.
Background
An LED is a semiconductor device that converts electrical energy into optical energy, and is widely used in the fields of illumination, display, backlight, and the like because of its advantages of small size, long service life, rich color, low energy consumption, and the like. Miniled is a sub-millimeter light emitting diode, the size of which is usually 80-200 um, is a new generation LED technology, and has the characteristics of high efficiency, high reliability, high brightness and fast reaction time of small-spacing LEDs, and the smaller-spacing LEDs have lower power consumption and lower cost.
The prior Mini LED adopts an inverted structure, and the preparation process flow of the prior Mini LED is as follows: firstly, MESA etching is carried out, namely after a positive photoresist mask, an ICP etching process is adopted to expose an N-GaN MESA; then, performing DE etching, namely performing deep etching by adopting ICP after adopting a positive photoresist mask again after MESA etching to realize the separation of devices among the Mini LEDs; and finally, preparing ITO after DE etching to serve as a current conducting layer, and photoetching the ITO to form an ITO pattern.
The existing preparation process of the Mini LED has the following problems:
1. MESA, DE and ITO patterns are respectively formed by three-path photoetching, twice ICP etching and once ITO etching, the process is complex, and the cost is high.
2. The smaller the chip size is, the positive photoresist mask is adopted, and the problems of serious diffraction, serious change of the photoresist appearance after high-temperature baking, deformation of an etching pattern caused by the alignment thickness of ITO and MESA and over-etching of ITO etching are brought along because the upper surface of the positive photoresist mask is exposed to light with larger thickness.
Disclosure of Invention
In view of this, the present application provides a micro light emitting device and a method for manufacturing the same, so as to solve the problems of complicated process, high cost, and easy pattern deformation and over-etching when the manufacturing size is smaller.
In order to solve the above problems, embodiments of the present invention provide the following technical solutions:
the first aspect of the embodiments of the present invention provides a method for manufacturing a micro light emitting device, where the method includes:
providing an LED epitaxial chip, wherein the LED epitaxial chip comprises a substrate, an N-type gallium nitride layer, an active layer and a P-type gallium nitride layer;
forming an ITO conductive layer and SiO on the upper surface of the LED epitaxial chip 2 A mask layer;
in the SiO 2 Performing two times of photoresist uniformization on a partial area of the mask layer, wherein an MESA pattern is formed by photoetching after the first photoresist uniformization, an ITO pattern is etched, and a DE channel is exposed by photoetching after the second photoresist uniformization;
performing ICP etching on the photoetching layer formed after the photoresist is homogenized for two times, and simultaneously forming an MESA/DE pattern and an N-type gallium nitride table top;
forming an N electrode and a P electrode on the N-type gallium nitride table-board and the ITO conducting layer respectively;
forming a composite DBR reflecting layer on the upper surface of the current LED epitaxial chip;
forming pad openings at positions of the DBR reflecting layer corresponding to the N electrode and the P electrode;
forming a PAD at the PAD opening.
Optionally, an ITO conductive layer and SiO are formed on the upper surface of the LED epitaxial chip 2 A mask layer comprising:
forming an ITO conducting layer on the upper surface of the LED epitaxial chip by adopting magnetron sputtering equipment or ion reaction coating RPD equipment, wherein the thickness range of the ITO conducting layer comprises 600A-5000A;
depositing SiO on the surface of the ITO conducting layer 2 As SiO 2 And (5) masking the layer.
Optionally, an ITO conductive layer and SiO are formed on the upper surface of the LED epitaxial chip 2 A mask layer, comprising:
depositing an ITO conductive material with a preset thickness on the upper surface of the LED epitaxial chip, and annealing in an oxygen environment with a preset flow by adopting a Rapid Thermal Annealing (RTA) process to form an ITO conductive layer; the preset thickness range comprises 600A to 5000A, the preset flow range comprises 0.5sccm to 4sccm, and the annealing temperature range comprises 400 ℃ to 600 ℃;
depositing SiO on the surface of the annealed ITO conductive layer by adopting a PECVD process 2 Formation of SiO 2 And (5) masking the layer.
Optionally, in the SiO 2 And performing twice glue homogenizing on a partial area of the mask layer, wherein the twice glue homogenizing comprises the following steps:
in the SiO 2 Performing first photoresist homogenizing on partial area of the mask layer to form a first photoresist layer;
exposing, developing and hardening the first photoresist layer by adopting the temperature T1 to form an MESA pattern;
etching SiO outside the first photoresist layer 2 A mask layer, etching the ITO conductive layer outside the MESA pattern to expose the P-type gallium nitride layer, and placing the etched ITO conductive layer on the SiO 2 Under the mask layer;
executing second photoresist homogenizing to form a second photoresist layer covering the first photoresist layer and the exposed P-type gallium nitride layer;
exposing, developing, hardening the second photoresist layer by adopting temperature T2, and exposing the DE channel;
wherein the temperature T1 is greater than the temperature T2.
Optionally, the temperature T1-temperature T2 is greater than 5 ℃, the ratio of the thickness of the first photoresist layer to the thickness of the second photoresist layer is greater than 1.2, and the sum of the thickness of the first photoresist layer and the thickness of the second photoresist layer is greater than 6um.
Optionally, the etching is performed on SiO outside the first photoresist layer 2 A mask layer, comprising:
etching the SiO outside the first photoresist layer according to 1:5 buffer oxide etching liquid BOE 2 A mask layer;
etching the ITO conductive layer outside the MESA pattern, comprising:
and etching the ITO conductive layer outside the MESA pattern by using ITO etching liquid.
Optionally, performing an ICP etching, and forming an MESA of MESA/DE pattern and an N-type gan MESA at the same time, includes:
sequentially performing multi-step ICP etching once on the photoetching layer formed after twice photoresist homogenizing, and removing the photoetching layer after the ICP etching;
removing the SiO 2 A mask layer, forming an MESA/DE graph and an N-type gallium nitride table-board;
the ratio of the depth of the first step ICP etching to the depth of the third step ICP etching ranges from 2:1 to 4:1.
Optionally, the condition for performing the first step of ICP etching includes: by using Cl 2 And BCl 3 Gas, cl 2 :BCl 3 The excitation power SRF is larger than 8:1, the value range of the excitation power SRF is 1000W-1500W, and the value range of the bias power BRF is 300W-500W;
the conditions for performing the second step of ICP etching include: by using O 2 And Ar gas, O 2 Ar is more than 4:1, the value range of the excitation power SRF is 600W-900W, and the value range of the bias power BRF is 100W-200W;
the etching conditions for performing the third step ICP include: using Cl 2 And BCl 3 Gas, cl 2 :BCl 3 Greater than 8:1, the excitation power SRF ranges from 600W to 900W, and the bias power BRF ranges from 100W to 200W.
Optionally, forming an N electrode and a P electrode on the N-type gallium nitride mesa and the ITO conductive layer, respectively, includes:
preparing NP-Metal on the N-type gallium nitride table board and the ITO conducting layer through glue homogenizing, photoetching, developing and evaporation to form an N electrode and a P electrode;
the N electrode and the P electrode are structurally one or a plurality of combinations of Cr, ni, al, ti, pt and Au, and the surface layer cut-off layers of the N electrode and the P electrode are Pt.
Optionally, forming a composite DBR reflective layer on the upper surface of the current LED epitaxial chip includes:
under the preset growth condition, ti is evaporated on the upper surface of the current LED epitaxial chip in an overlapping mode 3 O 5 And SiO 2 Form a high/low refractive index Ti 3 O 5 /SiO 2 A thin film constituting the reflective layer of the DBR,
depositing SiO on the DBR reflecting layer by PECVD 2 An insulating cover layer forming a composite DBR reflective layer;
wherein the preset growth condition is that an ion source baffle is opened, and O with the volume of 40sccm to 60sccm is introduced 2 The ion source power range is 600W to 1000W, the process vacuum is 2.0E-2Pa to 9.0E-Pa, the coating temperature range is 120 ℃ to 150 ℃, and each layer of Ti 3 O 5 Using O after evaporation 2 Bombarding each layer of Ti 3 O 5 A surface; the SiO 2 The thickness range of insulating overburden is 800A to 10000A, the thickness range of compound DBR reflection stratum is 2um to 5um.
A second aspect of embodiments of the present invention provides a micro light-emitting element, including:
the LED epitaxial chip consists of a substrate, an N-type gallium nitride layer, an active layer and a P-type gallium nitride layer;
forming a step structure on the N-type gallium nitride layer by secondary glue homogenizing and primary ICP etching, wherein the step structure comprises an N-type gallium nitride table top, an ITO conductive layer and an MESA/DE pattern;
an N electrode and a P electrode formed by the N-type gallium nitride mesa and the NP-Metal electrode on the ITO conductive layer;
the composite DBR reflecting layer covers the upper part of the LED epitaxial chip, and the bonding pad opening is formed in the composite DBR reflecting layer and located above the N electrode and the P electrode;
and a PAD connected to the N electrode and the P electrode through the PAD opening.
Optionally, the N electrode and the P electrode are in the structure of one or a combination of Cr, ni, al, ti, pt, and Au, and the surface layer cut-off layer of the N electrode and the P electrode is Pt.
Optionally, the thickness of the ITO conductive layer ranges from 600A to 5000A.
Optionally, the composite DBR reflective layer is formed by overlapping evaporated Ti 3 O 5 And SiO 2 And SiO on the alternating layers 2 Insulating coating layer of SiO 2 The thickness of the insulating covering layer ranges from 800A to 10000A, and the composite DBR reflecting layerThe thickness of (2) is in the range of 2um to 5um.
Based on the micro light-emitting element and the preparation method thereof provided by the embodiment of the invention, the LED epitaxial chip is provided and comprises a substrate, an N-type gallium nitride layer, an active layer and a P-type gallium nitride layer; forming an ITO conductive layer and SiO on the upper surface of the LED epitaxial chip 2 A mask layer; in the SiO 2 Performing two times of photoresist uniformization on a partial area of the mask layer, forming an MESA pattern through photoetching after the first photoresist uniformization, etching an ITO pattern, and exposing a DE channel through photoetching after the second photoresist uniformization; performing ICP etching on the photoetching layer formed after the photoresist is homogenized for two times, and simultaneously forming an MESA/DE pattern and an N-type gallium nitride table top; forming an N electrode and a P electrode on the N-type gallium nitride table-board and the ITO conducting layer respectively; forming a composite DBR reflecting layer on the upper surface of the current LED epitaxial chip; forming pad openings at positions of the DBR reflecting layer corresponding to the N electrode and the P electrode; a PAD PAD is formed at the PAD opening. In the embodiment of the invention, the ITO working procedure is moved forward, the ITO/MESA combined photoetching simplifies the process flow, the over-etching phenomenon caused by the overlay offset of the ITO and MESA patterns is reduced, the MESA/DE patterns are simultaneously formed by the secondary photoresist homogenizing and photoetching under the condition of not removing the photoresist and the primary ICP etching, the primary ICP etching is reduced, the chip manufacturing cost is reduced, the SiO is increased 2 The mask layer effectively protects the P-type gallium nitride layer and the ITO conducting layer in the ICP etching process, and avoids damage to the P-type gallium nitride layer and the ITO conducting layer caused by ICP over etching.
Drawings
In order to more clearly illustrate the embodiments of the present application or technical solutions in related arts, the drawings used in the description of the embodiments or prior arts will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
The structures, the proportions, the sizes, and the like shown in the drawings are only used for matching the disclosure disclosed in the specification, so that those skilled in the art can understand and read the disclosure, and do not limit the conditions and conditions for implementing the present application, so that the present disclosure has no technical essence, and any structural modifications, changes of the proportion relation, or adjustments of the sizes, should still fall within the scope of the disclosure which can be covered by the disclosure in the present application without affecting the efficacy and the achievable purpose of the present application.
Fig. 1 is a flowchart of a method for manufacturing a micro light emitting device according to an embodiment of the present invention;
fig. 2 to fig. 12 are process flow charts of a method for manufacturing a micro light emitting device according to an embodiment of the present invention.
Wherein, the substrate 1, the N-type gallium nitride layer 2, the active layer 3, the P-type gallium nitride layer 4, the ITO conductive layer 5 and SiO 2 Mask layer 6, first photoresist layer 7.1, second photoresist layer 7.2, DE pattern 8, MESA pattern 9, NP-Metal electrode 10, composite DBR layer 11, PAD PAD 12.
Detailed Description
Embodiments of the present application will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the application are shown, and in which it is to be understood that the embodiments described are merely illustrative of some, but not all, of the embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, the present application is described in further detail with reference to the accompanying drawings and the detailed description.
Fig. 1 is a flowchart illustrating a method for manufacturing a micro light emitting device according to an embodiment of the present invention. The preparation method mainly comprises the following steps:
s101: an LED epitaxial chip is provided.
In S101, as shown in fig. 2, the LED epitaxial chip includes a substrate 1, an N-type gallium nitride layer 2, an active layer 3, and a P-type gallium nitride layer 4.
The LED epitaxial chip is a normally grown LED epitaxial chip.
In an embodiment of the present invention, the substrate 1 is preferably a sapphire substrate.
S102: forming an ITO conductive layer and SiO on the upper surface of the LED epitaxial chip 2 And (5) masking the layer.
In the process of implementing S102, the process of forming ITO is moved forward, transparent conducting layers such as ITO are prepared on the upper surface of the LED epitaxial chip, namely the upper surface of the P-type gallium nitride layer 4, and then SiO is deposited on the formed ITO conducting layer 5 2 As a mask layer, siO is formed 2 And a mask layer 6. The structure formed in detail is shown in fig. 3.
In an embodiment of the present invention, first, an ITO conductive layer is formed on the upper surface of the LED epitaxial chip by using a magnetron sputtering Sputter device or an ion reactive deposition (RPD) device.
Preferably, the thickness of the ITO conductive layer ranges from 600A to 5000A.
Then, siO is deposited on the surface of the formed ITO conductive layer 2 As SiO 2 And (5) masking the layer.
In an embodiment of the invention, first, an ITO conductive material with a preset thickness is deposited on the upper surface of the LED epitaxial chip, and an rapid thermal annealing RTA process is adopted to anneal in an oxygen environment with a preset flow rate, so as to form an ITO conductive layer.
Preferably, the predetermined thickness range includes 600A to 5000A.
Preferably, the predetermined flow range includes 0.5sccm to 4sccm, and the annealing temperature range includes 400 ℃ to 600 ℃.
Then, depositing SiO on the surface of the annealed ITO conducting layer by adopting a PECVD process 2 Formation of SiO 2 And (5) masking the layer.
S103: in the SiO 2 And performing first photoresist homogenizing on the surface of the mask layer, and exposing the MESA pattern by photoetching after the photoresist is homogenized.
S104: etching of SiO 2 And etching the mask layer and the ITO conductive layer to form an ITO pattern.
S105: and performing second photoresist homogenizing on the surface of the photoresist formed by the first photoresist homogenizing, and exposing the DE channel by photoetching.
The specific implementation of S103 to S105 described above can be understood as being in SiO 2 And performing two times of photoresist uniformization on a partial area of the mask layer, wherein an MESA pattern is formed by photoetching after the first time of photoresist uniformization, an ITO pattern is etched, and a DE channel is exposed by photoetching after the second time of photoresist uniformization.
In the process of specifically realizing S103 to S105, after first glue homogenizing, exposing, developing, hardening to expose MESA patterns, etching a SiO2 mask layer by BOE, and etching an ITO pattern by ITO etching liquid; the ITO/MESA photoetching is combined, so that the process flow is simplified, and the over-etching phenomenon caused by overlay offset of the ITO and MESA patterns is reduced. And after ITO etching, photoresist is not removed, second photoresist homogenizing is carried out, and then exposure, development and film hardening are carried out to expose the DE channel.
In one embodiment of the present invention, first, as shown in FIG. 4, on the SiO 2 And performing first photoresist uniformizing on partial areas of the mask layer 6 to form a first photoresist layer 7.1.
Then, exposing, developing and hardening the first photoresist layer by adopting the temperature T1 to form an MESA pattern.
Then, as shown in fig. 5 and 6, the SiO layer other than the first photoresist layer 7.1 is etched 2 A mask layer 6 and an ITO conducting layer 5 outside the MESA pattern are etched to expose the P-type gallium nitride layer 4, and the etched ITO conducting layer 5 is arranged on the SiO 2 Below the mask layer 6.
Note that specific values of the etching time of the ITO conductive layer 5 are only required to be ensured. The etched ITO conductive layer 5 is arranged on the SiO 2 Just below the mask layer 6.
Then, as shown in fig. 7, a second photoresist leveling is performed to form a second photoresist layer 7.2 covering the first photoresist layer 7.1 and the exposed P-type gallium nitride layer 4.
Finally, the second photoresist layer 7.2 is exposed, developed, and hardened with a temperature T2, exposing the ED channel.
Wherein the temperature T1 is greater than the temperature T2.
Preferably, the temperature T1-temperature T2 is greater than 5 ℃, the ratio of the thickness of the first photoresist layer 7.1 to the thickness of the second photoresist layer 7.2 is greater than 1.2, and the sum of the thickness of the first photoresist layer 7.1 and the thickness of the second photoresist layer 7.2 is greater than 6um.
In the whole process, after the ITO etching, the photoresist is not removed, the photoresist is homogenized for the second time, and then the exposed DE channel is exposed and developed. By controlling the hardening temperature of the first photoresist uniformization and the second photoresist uniformization and the thickness ratio of the first photoresist to the second photoresist, the MESA/DE step height difference can be formed simultaneously.
In an embodiment of the invention, the SiO outside the first photoresist layer is etched 2 The mask layer comprises the following specific processes: etching the SiO outside the first photoresist layer according to 1:5 buffer oxide etching liquid BOE 2 And (5) masking the layer.
In an embodiment of the present invention, the ITO conductive layer outside the MESA pattern is etched by a specific process including: and etching the ITO conductive layer except the MESA pattern by using an ITO etching solution.
S106: and performing ICP etching on the photoetching layer formed after the photoresist is homogenized twice, and simultaneously forming an MESA/DE pattern and an N-type gallium nitride MESA.
In the specific execution process of S106, the MESA pattern 9, the DE pattern 8 and the N-type gallium nitride MESA are formed on the photoetching layer formed after twice glue homogenizing through one multi-step ICP etching. The structure formed in detail is shown in fig. 8.
In one embodiment of the invention, multi-step ICP etching is sequentially performed once on a photoetching layer formed after twice photoresist homogenizing, and the photoetching layer is removed after the ICP etching; then, the SiO is removed 2 And forming an MESA \ DE graph and an N-type gallium nitride table top by using the mask layer.
The ratio of the depth of the first step ICP etching to the depth of the third step ICP etching ranges from 2:1 to 4:1.
In addition, the SiO 2 The mask layer can effectively protect the P-type gallium nitride layer and prevent the P-type gallium nitride layer from being damaged by ICP over etching. Thereby contributing to an increase in the effective area of the chip.
In an embodiment of the present invention, the process of performing one-time three-step ICP etching specifically comprises:
the conditions for performing the first step ICP etching include: by using Cl 2 And BCl 3 Gaseous Cl 2 :BCl 3 Greater than 8:1, the excitation power SRF ranges from 1000W to 1500W, and the bias power BRF ranges from 300W to 500W.
The conditions for performing the second step of ICP etching include: by the use of O 2 And Ar gas, O 2 Ar is more than 4:1, the excitation power SRF ranges from 600W to 900W, and the bias power BRF ranges from 100W to 200W.
The etching conditions for performing the third step ICP include: by using Cl 2 And BCl 3 Gas, cl 2 :BCl 3 Greater than 9:1, the excitation power SRF ranges from 600W to 900W, and the bias power BRF ranges from 100W to 200W.
Preferably, in the above-mentioned process of etching by ICP etching in multiple steps at one time, the etching depth ratio of the first step and the third step is controlled, and O is etched by the second step 2 Plasma removes the residual glue in the N-type gallium nitride region, and guarantees the etching flatness of the MESA and the etching depth of the third step.
S107: and respectively forming an N electrode and a P electrode on the N-type gallium nitride table board and the ITO conductive layer.
In the process of implementing S107 specifically, as shown in fig. 9, an NP-Metal electrode 10 is prepared on the N-type gallium nitride mesa and the ITO conductive layer 5 by spin coating, photolithography, development, and evaporation, so as to form an N electrode and a P electrode.
The N electrode and the P electrode are structurally made of one or a combination of multiple metals of Cr, ni, al, ti, pt and Au, and the surface cut-off layers of the N electrode and the P electrode are made of Pt.
S108: and forming a composite DBR reflecting layer on the upper surface of the current LED epitaxial chip.
In an embodiment of the invention, first, under a preset growth condition, ti is deposited on the upper surface of the current LED epitaxial chip by overlapping evaporation 3 O 5 And SiO 2 Form a high/low refractive index Ti 3 O 5 /SiO 2 Thin film DBR reflective layer.
Then, siO is deposited on the DBR reflecting layer by PECVD 2 And an insulating coating layer forming the composite DBR reflective layer 11. The structure formed in detail is shown in fig. 10.
Wherein the preset growth condition is that an ion source baffle is opened, and O with the volume of 40sccm to 60sccm is introduced 2 The ion source power range is 600W to 1000W, the process vacuum is 2.0E-2Pa to 9.0E-Pa, the coating temperature range is 120 ℃ to 150 ℃, and each layer of Ti 3 O 5 Using O after evaporation 2 Bombarding each layer of Ti 3 O 5 A surface; wherein, siO 2 The thickness range of insulating overburden layer is 800A to 10000A, and the thickness range of compound DBR reflection stratum is 2um to 5um.
S109: and forming pad openings at the positions of the DBR reflecting layers corresponding to the N electrode and the P electrode.
In the process of implementing S109, the DBR-structure pad opening region is etched using CF4/CHF3 or the like etching gas through spin coating, exposure, and development. The structure formed in detail is shown in fig. 11.
S110: a PAD PAD is formed at the PAD opening.
In the process embodying S110, as shown in fig. 12, the PAD 12 is formed at the PAD opening via a photolithography mask.
Preferably, the metal structure of the PAD is one or a combination of more of Cr, ni, al, ti, pt and Au.
In the preparation method of the micro light-emitting element provided by the embodiment of the invention, the ITO working procedure is moved forward, the ITO/MESA is combined for photoetching to simplify the process flow, the ITO over-etching phenomenon caused by the overlay offset of the ITO and the MESA patterns is reduced, the MESA/DE patterns are simultaneously formed by two-time photoresist uniformizing and photoetching under the condition of not removing photoresist and one ICP etching, the one-time ICP etching is reduced, the chip manufacturing cost is reduced, and the SiO is increased 2 The mask layer effectively protects the P-type gallium nitride layer and the ITO conducting layer in the ICP etching process, avoids damage to the P-type gallium nitride layer and the ITO conducting layer caused by ICP over etching, and the preparation method disclosed by the embodiment of the invention not only simplifies the process, but also reduces the chip manufacturing costThe effective area of the chip is also increased.
Based on the above method for manufacturing a micro light emitting device disclosed in the embodiment of the present invention, the embodiment of the present invention further discloses a micro light emitting device, as shown in fig. 12, which mainly includes:
the LED epitaxial chip is composed of a substrate 1, an N-type gallium nitride layer 2, an active layer 3 and a P-type gallium nitride layer 4.
And forming a stepped structure on the N-type gallium nitride layer 2 by secondary glue homogenizing and primary ICP etching, wherein the stepped structure comprises an N-type gallium nitride table top, an ITO conductive layer 5, an MESA pattern 9 and a DE pattern 8.
An N electrode and a P electrode are formed by the N-type gallium nitride mesa and the NP-Metal electrode 10 on the ITO conductive layer 4.
Cover in the compound DBR reflector layer 11 of LED epitaxial chip top, and compound DBR reflector layer 11 is located the pad trompil of N electrode and P electrode top.
And a PAD 12 connected to the N electrode and the P electrode through the PAD opening.
In the embodiment of the present invention, an N electrode is formed on the N-type gallium nitride mesa, and a P electrode is formed on the ITO conductive layer 4, preferably, the N electrode and the P electrode have one or more combinations of Cr, ni, al, ti, pt, and Au structures, and the surface layer cut-off layer of the N electrode and the P electrode is Pt.
In an embodiment of the invention, the thickness of the ITO conductive layer 4 ranges from 600A to 5000A.
In one embodiment of the present invention, the composite DBR reflective layer 11 is formed by overlapped evaporation of Ti 3 O 5 And SiO 2 And SiO on the alternating layers 2 An insulating coating layer, the thickness of the composite DBR reflective layer 11 is 2um to 5um, and the SiO 2 The insulating cover layer has a thickness ranging from 800A to 10000A.
In summary, the micro light emitting device formed by the method for manufacturing the micro light emitting device disclosed in the embodiments of the present invention has a larger effective area than that of the conventional micro light emitting device, and is simple and low in manufacturing cost.
The embodiments in the present description are described in a progressive manner, or in a parallel manner, or in a combination of a progressive manner and a parallel manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments can be referred to each other.
It is to be understood that in the description of the present application, the drawings and the description of the embodiments are to be regarded as illustrative in nature and not as restrictive. Like numerals refer to like structures throughout the description of the embodiments. Additionally, the figures may exaggerate the thicknesses of some layers, films, panels, regions, etc. for ease of understanding and ease of description. It will also be understood that when an element such as a layer, film, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In addition, "on …" means that an element is positioned on or under another element, but does not essentially mean that an element is positioned on the upper side of another element according to the direction of gravity.
The terms "upper," "lower," "top," "bottom," "inner," "outer," and the like refer to an orientation or positional relationship relative to an orientation or positional relationship shown in the drawings for ease of description and simplicity of description, but do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present application. When a component is referred to as being "connected" to another component, it can be directly connected to the other component or intervening components may also be present.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in an article or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (14)
1. A method of making a micro-emissive element, the method comprising:
providing an LED epitaxial chip, wherein the LED epitaxial chip comprises a substrate, an N-type gallium nitride layer, an active layer and a P-type gallium nitride layer;
forming an ITO conductive layer and SiO on the upper surface of the LED epitaxial chip 2 A mask layer;
in the SiO 2 Performing two times of photoresist uniformization on a partial area of the mask layer, wherein an MESA pattern is formed by photoetching after the first photoresist uniformization, an ITO pattern is etched, and a DE channel is exposed by photoetching after the second photoresist uniformization;
performing ICP etching on the photoetching layer formed after the photoresist is homogenized for two times, and simultaneously forming an MESA/DE pattern and an N-type gallium nitride table top;
forming an N electrode and a P electrode on the N-type gallium nitride table board and the ITO conductive layer respectively;
forming a composite DBR reflecting layer on the upper surface of the current LED epitaxial chip;
forming pad openings at positions of the DBR reflecting layer corresponding to the N electrode and the P electrode;
a PAD PAD is formed at the PAD opening.
2. The method according to claim 1, wherein an ITO conductive layer and SiO are formed on the upper surface of the LED epitaxial chip 2 A mask layer comprising:
forming an ITO conducting layer on the upper surface of the LED epitaxial chip by adopting magnetron sputtering equipment or ion reaction coating RPD equipment, wherein the thickness range of the ITO conducting layer comprises 600A-5000A;
depositing SiO on the surface of the ITO conductive layer 2 As SiO 2 And (5) masking the layer.
3. The method according to claim 1, wherein an ITO conductive layer and SiO are formed on the upper surface of the LED epitaxial chip 2 A mask layer, comprising:
depositing an ITO conductive material with a preset thickness on the upper surface of the LED epitaxial chip, and annealing in an oxygen environment with a preset flow by adopting a Rapid Thermal Annealing (RTA) process to form an ITO conductive layer; the preset thickness range comprises 600A to 5000A, the preset flow range comprises 0.5sccm to 4sccm, and the annealing temperature range comprises 400 ℃ to 600 ℃;
depositing SiO on the surface of the annealed ITO conductive layer by adopting a PECVD process 2 Formation of SiO 2 And (5) masking the layer.
4. The method of claim 1, wherein the SiO is in the form of a film 2 And performing twice glue homogenizing on partial area of the mask layer, wherein the twice glue homogenizing comprises the following steps:
in the SiO 2 Performing first photoresist homogenizing on partial area of the mask layer to form a first photoresist layer;
exposing, developing and hardening the first photoresist layer by adopting a temperature T1 to form an MESA pattern;
etching SiO outside the first photoresist layer 2 A mask layer, etching the ITO conductive layer outside the MESA pattern to expose the P-type gallium nitride layer, and placing the etched ITO conductive layer on the SiO 2 Under the mask layer;
executing second photoresist homogenizing to form a second photoresist layer covering the first photoresist layer and the exposed P-type gallium nitride layer;
exposing, developing and hardening the second photoresist layer at the temperature T2 to expose the DE channel;
wherein the temperature T1 is greater than the temperature T2.
5. The method according to claim 4, wherein the temperature T1-temperature T2 is greater than 5 ℃, the ratio of the thickness of the first photoresist layer to the thickness of the second photoresist layer is greater than 1.2, and the sum of the thickness of the first photoresist layer and the thickness of the second photoresist layer is greater than 6um.
6. The method of claim 4, wherein the etching SiO outside the first photoresist layer 2 A mask layer, comprising:
etching the SiO outside the first photoresist layer according to 1:5 buffer oxide etching liquid BOE 2 A mask layer;
etching the ITO conductive layer outside the MESA pattern, comprising:
and etching the ITO conductive layer except the MESA pattern by using an ITO etching solution.
7. The method of claim 1, wherein performing an ICP etch while forming the MESA/DE pattern and N-type gallium nitride MESA comprises:
sequentially performing multi-step ICP etching once on the photoetching layer formed after twice photoresist homogenizing, and removing the photoetching layer after the ICP etching;
removing the SiO 2 A mask layer, forming an MESA/DE graph and an N-type gallium nitride table-board;
the ratio of the depth of the first step ICP etching to the depth of the third step ICP etching ranges from 2:1 to 4:1.
8. The production method according to claim 7, wherein the conditions for performing the first step ICP etching include: by using Cl 2 And BCl 3 Gas, cl 2 :BCl 3 The excitation power SRF is larger than 8:1, the value range of the excitation power SRF is 1000W-1500W, and the value range of the bias power BRF is 300W-500W;
the conditions for performing the second step of ICP etching include: by using O 2 And Ar gas, O 2 Ar is more than 4:1, the value range of the excitation power SRF is 600W-900W, and the value range of the bias power BRF is 100W-200W;
the etching conditions for performing the third step ICP include: by using Cl 2 And BCl 3 Gas, cl 2 :BCl 3 Greater than 9:1, the excitation power SRF ranges from 600W to 900W, and the bias power BRF ranges from 100W to 200W.
9. The method according to claim 1, wherein forming an N electrode and a P electrode on the N-type gallium nitride mesa and the ITO conductive layer, respectively, comprises:
preparing NP-Metal on the N-type gallium nitride table board and the ITO conducting layer through glue homogenizing, photoetching, developing and evaporation to form an N electrode and a P electrode;
the N electrode and the P electrode are structurally one or a plurality of combinations of Cr, ni, al, ti, pt and Au, and the surface layer cut-off layers of the N electrode and the P electrode are Pt.
10. The method according to claim 1, wherein forming a composite DBR reflective layer on an upper surface of the LED epitaxial chip comprises:
under the preset growth condition, ti is evaporated on the upper surface of the current LED epitaxial chip in an overlapping mode 3 O 5 And SiO 2 Form a high/low refractive index Ti 3 O 5 /SiO 2 A thin film constituting the reflective layer of the DBR,
depositing SiO on the DBR reflecting layer by adopting PECVD 2 An insulating cover layer forming a composite DBR reflective layer;
wherein the preset growth condition is that an ion source baffle is opened, and O with the volume of 40sccm to 60sccm is introduced 2 The ion source power range is 600W to 1000W, the process vacuum is 2.0E-2Pa to 9.0E-Pa, the coating temperature range is 120 ℃ to 150 ℃,each layer of Ti 3 O 5 Using O after evaporation 2 Bombarding each layer of Ti 3 O 5 A surface; the SiO 2 The thickness range of insulating overburden is 800A to 10000A, the thickness range of compound DBR reflection stratum is 2um to 5um.
11. A micro light-emitting element, comprising:
the LED epitaxial chip consists of a substrate, an N-type gallium nitride layer, an active layer and a P-type gallium nitride layer;
forming a step structure on the N-type gallium nitride layer by secondary glue homogenizing and primary ICP etching, wherein the step structure comprises an N-type gallium nitride table top, an ITO conductive layer and an MESA/DE pattern;
an N electrode and a P electrode formed by the N-type gallium nitride mesa and the NP-Metal electrode on the ITO conductive layer;
the composite DBR reflecting layer covers the upper part of the LED epitaxial chip, and the bonding pad opening is formed in the composite DBR reflecting layer and located above the N electrode and the P electrode;
and a PAD connected to the N electrode and the P electrode through the PAD opening.
12. A micro-luminescent element as claimed in claim 11, wherein the N-electrode and P-electrode structure is one or more of Cr, ni, al, ti, pt, au, and the surface cut-off layer of the N-electrode and P-electrode is Pt.
13. A micro-light-emitting element according to claim 11, wherein the ITO conductive layer has a thickness ranging from 600A to 5000A.
14. A micro-luminescent element as claimed in claim 11, wherein the composite DBR reflective layer is formed by overlapping evaporated Ti 3 O 5 And SiO 2 And SiO on the alternating layers 2 Insulating coating layer of SiO 2 The thickness range of insulating overburden is 800A to 10000A, the thickness range of compound DBR reflection stratum is 2um to 5um.
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