CN115763526A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
- Publication number
- CN115763526A CN115763526A CN202211476768.7A CN202211476768A CN115763526A CN 115763526 A CN115763526 A CN 115763526A CN 202211476768 A CN202211476768 A CN 202211476768A CN 115763526 A CN115763526 A CN 115763526A
- Authority
- CN
- China
- Prior art keywords
- region
- drift
- atom
- doping
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A semiconductor structure and a method of forming the same, wherein the method comprises: providing a substrate; forming a body region within the substrate, the body region having a first conductivity type; forming a first drift doping region and a plurality of second drift doping regions positioned in the first drift doping region in the substrate, wherein the first drift doping region is adjacent to the body region, the plurality of second drift doping regions are mutually separated, the first drift doping region has a second conductive type, the second drift doping region has a first conductive type, and the first conductive type is different from the second conductive type; forming a gate layer on the substrate, wherein one part of the gate layer is positioned on the body region, and the other part of the gate layer is also positioned on the first drift doping region; and a drain region and a source region are respectively formed on two sides of the gate layer, the drain region is positioned in the first drift doping region, the source region is positioned in the body region, and the source region and the drain region have a second conductivity type, so that the voltage withstanding property of the device is improved, the on-resistance of the device is reduced, and the performance of the LDMOS device is improved.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
An LDMOS (laterally Double-Diffused Metal Oxide Semiconductor Field Effect Transistor) in a high-voltage power device has good process compatibility with a CMOS (complementary Metal Oxide Semiconductor) device due to the characteristic that current flows laterally on the surface of the device. Meanwhile, compared with the traditional power device, the LDMOS device is widely applied due to the good characteristics of high breakdown voltage and low on-resistance.
However, the conventional LDMOS device has a significant contradiction between withstand voltage and on-resistance. The LDMOS devices formed by the prior art are difficult to meet the performance requirements at the same time, and need further improvement.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which can improve the performance of the semiconductor structure.
In order to solve the above technical problem, an aspect of the present invention provides a semiconductor structure, including: a substrate; a body region within the substrate, the body region having a first conductivity type; a first drift doped region in the substrate and a plurality of second drift doped regions in the first drift doped region, the first drift doped region being adjacent to the body region, the plurality of second drift doped regions being discrete from one another, the first drift doped region having a second conductivity type, the second drift doped region having the first conductivity type, the first conductivity type being different from the second conductivity type; a gate layer located on the substrate, a portion of the gate layer being located on the body region, and another portion of the gate layer also being located on the first drift doped region; and the drain region and the source region are respectively positioned at two sides of the gate layer, the drain region is positioned in the first drift doping region, the source region is positioned in the body region, and the source region and the drain region have a second conductivity type.
Optionally, the method includes: the plurality of second drift doping regions are parallel to a first direction and are arranged along a second direction, and the first direction is vertical to the second direction; the gate layer extends in the second direction.
Optionally, a size of the second drift doping region along the second direction is in a range of 0.5 μm to 10 μm, and a distance between adjacent second drift doping regions is in a range of 0.5 μm to 10 μm.
Optionally, the method further includes: and the drain region is positioned on one side of the isolation structure far away from the gate layer.
Optionally, the first conductivity type is an N type, and the second conductivity type is a P type; the concentration range of the first drift doped region is 1 multiplied by 10 12 atom/cm 3 To 1X 10 21 atom/cm 3 The depth of the first drift doping region ranges from 0.5 μm to 30 μm; the concentration range of the second drift doped region is 1 multiplied by 10 12 atom/cm 3 To 1X 10 21 atom/cm 3 And the depth of the second drift doping region ranges from 0.5 μm to 30 μm.
Optionally, the first conductivity type is a P type, and the second conductivity type is an N type; the concentration range of the first drift doping region is 1 multiplied by 10 12 atom/cm 3 To 1X 10 21 atom/cm 3 The depth of the first drift doping region ranges from 0.5 μm to 30 μm; the concentration range of the second drift doped region is 1 multiplied by 10 12 atom/cm 3 To 1X 10 21 atom/cm 3 And the depth of the second drift doping region ranges from 0.5 μm to 30 μm.
Optionally, the distance between the second drift doping region and the body region ranges from 0.5 μm to 10 μm.
Optionally, the number of the second drift doping regions ranges from greater than or equal to 3.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate; forming a body region within the substrate, the body region having a first conductivity type; forming a first drift doping region and a plurality of second drift doping regions in the first drift doping region in the substrate, wherein the first drift doping region is adjacent to the body region, the plurality of second drift doping regions are separated from each other, the first drift doping region has a second conductivity type, the second drift doping region has the first conductivity type, and the first conductivity type is different from the second conductivity type; forming a gate layer on the substrate, wherein one part of the gate layer is positioned on the body region, and the other part of the gate layer is also positioned on the first drift doping region; and forming a drain region and a source region on two sides of the gate layer respectively, wherein the drain region is positioned in the first drift doping region, the source region is positioned in the body region, and the source region and the drain region have a second conductivity type.
Optionally, the method includes: the plurality of second drift doping regions are parallel to a first direction and are arranged along a second direction, and the first direction is vertical to the second direction; the gate layer extends in the second direction.
Optionally, a size of the second drift doping region along the second direction is in a range of 0.5 μm to 10 μm, and a distance between adjacent second drift doping regions is in a range of 0.5 μm to 10 μm.
Optionally, before forming the gate layer, the method further includes: forming an isolation structure in the first drift doped region; the gate layer is also positioned on a part of the isolation structure; the drain region is located on one side of the isolation structure away from the gate layer.
Optionally, the forming method of the first drift doping region and the plurality of second drift doping regions includes: forming a first mask layer on the surface of the substrate, wherein the first mask layer exposes the surface of the first drift doping region; injecting first doping ions into the substrate by taking the first mask layer as a mask; forming a second mask layer on the surface of the substrate, wherein the second mask layer exposes the surface of the second drift doping region; and injecting second doping ions into the substrate by taking the second mask layer as a mask.
Optionally, the first conductivity type is an N type, and the second conductivity type is a P type; the implantation process parameters of the first doping ions comprise: the dosage range of the first doping ions is 1 x 10 11 atom/cm 2 To 1X 10 16 atom/cm 2 The energy range is 2KeV to 100KeV; the implantation process parameters of the second doping ions comprise: the dosage range of the second doping ions is 1 x 10 11 atom/cm 2 To 1X 10 16 atom/cm 2 In an energy range of2KeV to 100KeV.
Optionally, the first conductivity type is a P type, and the second conductivity type is an N type; the implantation process parameters of the first doping ions comprise: the dosage range of the first doping ions is 1 x 10 11 atom/cm 2 To 1 × 10 16 atom/cm 2 The energy range is 2KeV to 100KeV; the implantation process parameters of the second doping ions comprise: the dosage range of the second doping ions is 1 x 10 11 atom/cm 2 To 1 × 10 16 atom/cm 2 The energy range is 2KeV to 100KeV.
Optionally, the first conductivity type is a P type, and the second conductivity type is an N type; the concentration range of the first drift doping region is 1 multiplied by 10 12 atom/cm 3 To 1X 10 21 atom/cm 3 The depth of the first drift doping region ranges from 0.5 μm to 30 μm; the concentration range of the second drift doped region is 1 multiplied by 10 12 atom/cm 3 To 1X 10 21 atom/cm 3 The depth of the second drift doping region ranges from 0.5 μm to 30 μm.
Optionally, the first conductivity type is an N type, and the second conductivity type is a P type; the concentration range of the first drift doped region is 1 multiplied by 10 12 atom/cm 3 To 1 × 10 21 atom/cm 3 The depth of the first drift doping region ranges from 0.5 μm to 30 μm; the concentration range of the second drift doped region is 1 multiplied by 10 12 atom/cm 3 To 1X 10 21 atom/cm 3 And the depth of the second drift doping region ranges from 0.5 μm to 30 μm.
Optionally, the distance between the second drift doping region and the body region ranges from 0.5 μm to 10 μm.
Optionally, the number of the second drift doping regions ranges from greater than or equal to 3.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the method for forming a semiconductor structure in the technical scheme of the invention, a first drift doping region and a plurality of second drift doping regions located in the first drift doping region are formed in a substrate, the first drift doping region is adjacent to a body region, the plurality of second drift doping regions are separated from each other, the first drift doping region and the second drift doping region form a PN junction due to different conduction types, a depletion region is generated between the first drift doping region and the second drift doping region, the depletion region can even be expanded to the whole drift region by adjusting the sizes and the doping ion concentrations of the first drift doping region and the second drift doping region, and due to the existence of the depletion region, the drift region composed of the first drift doping region and the second drift doping region is approximately an 'intrinsic layer' in a voltage withstanding direction, which is beneficial to improving the voltage withstanding characteristic of a device; in addition, due to the aggregation of carriers near an N/P interface, the conductivity of the device is improved, and the on-resistance of the device is reduced. On the whole, the voltage-resistant characteristic of the device is improved, meanwhile, the on-resistance of the device is reduced, and the performance of the LDMOS device is improved.
According to the semiconductor structure provided by the technical scheme of the invention, the semiconductor structure comprises a first drift doping region and a plurality of second drift doping regions, wherein the first drift doping region is positioned in the substrate, the second drift doping regions are positioned in the first drift doping region, the first drift doping region is adjacent to the body region, the second drift doping regions are separated from each other, the first drift doping region and the second drift doping regions form a PN junction due to different conduction types, a depletion region is generated between the first drift doping region and the second drift doping region, the depletion region can even be expanded to the whole drift region by adjusting the sizes and the doping ion concentrations of the first drift doping region and the second drift doping region, and due to the existence of the depletion region, the drift region formed by the first drift doping region and the second drift doping region is approximately an 'intrinsic layer' in a voltage-resisting direction, so that the voltage-resisting characteristic of a device is favorably improved; in addition, due to the aggregation of carriers near an N/P interface, the conductivity of the device is improved, and the on-resistance of the device is reduced. On the whole, the voltage withstanding characteristic of the device is improved, meanwhile, the on-resistance of the device is reduced, and the performance of the LDMOS device is improved.
Drawings
Fig. 1 to 11 are schematic cross-sectional views corresponding to steps in a method for forming a semiconductor structure according to an embodiment of the invention.
Detailed Description
It should be noted that "surface" and "upper" in the present specification are used to describe a relative positional relationship in space, and are not limited to direct contact or not.
As described in the background, the performance of a semiconductor structure formed by using the conventional lateral double diffused mosfet needs to be improved.
In order to solve the technical problem, the invention provides a semiconductor structure and a forming method thereof, wherein a first drift doping region and a plurality of second drift doping regions are formed in a substrate, the first drift doping region is adjacent to a body region, the plurality of second drift doping regions are separated from each other, the first drift doping region and the second drift doping region form a PN junction due to different conductivity types, a depletion region is generated between the first drift doping region and the second drift doping region, the depletion region can even extend to the whole drift region by adjusting the size and the doping ion concentration of the first drift doping region and the second drift doping region, and due to the existence of the depletion region, the drift region formed by the first drift doping region and the second drift doping region is approximately an "intrinsic layer" in a voltage-resistant direction, which is beneficial to improving the voltage-resistant characteristic of a device; in addition, due to the aggregation of carriers near an N/P interface, the conductivity of the device is improved, and the on-resistance of the device is reduced. On the whole, the voltage-resistant characteristic of the device is improved, meanwhile, the on-resistance of the device is reduced, and the performance of the LDMOS device is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 to 11 are schematic cross-sectional views corresponding to steps in a method for forming a semiconductor structure according to an embodiment of the invention.
Referring to fig. 1 and fig. 2, fig. 1 is a schematic top view, and fig. 2 is a schematic cross-sectional view along direction DD1 in fig. 1, providing a substrate 100; a body region 101 is formed within the substrate 100, the body region 101 having a first conductivity type.
In this embodiment, a base (not shown) is further provided, and the substrate 100 is located on the base.
In this embodiment, the substrate is made of silicon. In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multielement semiconductor material formed by III-V group elements comprises InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP.
In this embodiment, the method for forming the substrate 100 includes: and forming an epitaxial layer on the substrate, wherein the epitaxial layer is internally provided with doping ions.
In this embodiment, the conductive type of the substrate 100 is P-type.
In this embodiment, the first conductive type is a P type. In another embodiment, the first conductivity type is N-type.
In this embodiment, the method for forming the body region 101 includes: forming a third mask layer (not shown) on the surface of the substrate 100, wherein the third mask layer exposes a part of the substrate 100; and injecting third doping ions into the substrate 100 by taking the third mask layer as a mask.
Referring to fig. 3 to 5, fig. 3 is a schematic top view, fig. 4 is a schematic cross-sectional view taken along a direction DD1 in fig. 3, fig. 5 is a schematic cross-sectional view taken along a direction EE1 in fig. 3, a first drift doped region 102 and a plurality of second drift doped regions 103 located in the first drift doped region 102 are formed in the substrate 100, the first drift doped region 102 is adjacent to the body region 101, the plurality of second drift doped regions 103 are separated from each other, the first drift doped region 102 has a second conductivity type, the second drift doped region 103 has the first conductivity type, and the first conductivity type is different from the second conductivity type.
The first drift doping region 102 and the second drift doping region 103 form a PN junction due to different conductivity types, a depletion region is generated between the first drift doping region 102 and the second drift doping region 103, the depletion region can even extend to the whole drift region by adjusting the size and the doping ion concentration of the first drift doping region 102 and the second drift doping region 103, and due to the existence of the depletion region, the drift region composed of the first drift doping region 102 and the second drift doping region 103 is approximately an "intrinsic layer" in the direction of the withstand voltage, which is beneficial to improving the withstand voltage characteristic of the device; in addition, due to the aggregation of carriers near an N/P interface, the conductivity of the device is improved, and the on-resistance of the device is reduced. On the whole, the voltage-resistant characteristic of the device is improved, meanwhile, the on-resistance of the device is reduced, and the performance of the LDMOS device is improved.
In this embodiment, the plurality of second drift doping regions 103 are parallel to a first direction X and are arranged along a second direction Y, and the first direction X is perpendicular to the second direction Y.
In this embodiment, the second conductive type is N-type. In another embodiment, the second conductivity type is P-type.
In this embodiment, the forming method of the first drift doping region 102 and the plurality of second drift doping regions 103 includes: forming a first mask layer (not shown) on the surface of the substrate 100, wherein the first mask layer exposes the surface of the first drift doping region 102; injecting first doping ions into the substrate 100 by taking the first mask layer as a mask; forming a second mask layer (not shown) on the surface of the substrate 100, wherein the second mask layer exposes the surface of the second drift doping region 103; and injecting second doping ions into the substrate 100 by taking the second mask layer as a mask.
In this embodiment, a dimension d1 of the second drift doping region 103 along the second direction Y ranges from 0.5 μm to 10 μm, and a distance d2 between adjacent second drift doping regions 103 ranges from 0.5 μm to 10 μm.
In this embodiment, a distance d3 between the second drift doping region 103 and the body region 101 ranges from 0.5 μm to 10 μm.
In this embodiment, the number of the second drift doping regions 103 is greater than or equal to 3.
In this embodiment, the first conductive type is an N-type, and the second conductive type is a P-type.
In this embodiment, the implantation process parameters of the first doped ions include: the dosage range of the first doping ions is 1 x 10 11 atom/cm 2 To 1X 10 16 atom/cm 2 The energy range is 2KeV to 100KeV.
In this embodiment, the implantation process parameters of the second doped ions include: the dosage range of the second doping ions is 1 x 10 11 atom/cm 2 To 1X 10 16 atom/cm 2 The energy range is 2KeV to 100KeV.
In this embodiment, the first conductive type is an N-type, and the second conductive type is a P-type; the concentration range of the first drift doping region 102 is 1 × 10 12 atom/cm 3 To 1X 10 21 atom/cm 3 The depth h of the first drift doping region 102 ranges from 0.5 μm to 30 μm; the concentration range of the second drift doping region 103 is 1 × 10 12 atom/cm 3 To 1X 10 21 atom/cm 3 The depth of the second drift doping region 103 ranges from 0.5 μm to 30 μm.
The depth refers to a dimension of a bottom edge of the first drift doping region 102 (the second drift doping region 103) from the surface of the substrate 100. In this embodiment, the depths of the first drift doping region 102 and the second drift doping region 103 are the same.
In another embodiment, the first conductivity type is P-type and the second conductivity type is N-type; the implantation process parameters of the first doping ions comprise: the dosage range of the first doping ions is 1 x 10 11 atom/cm 2 To 1X 10 16 atom/cm 2 The energy range is 2KeV to 100KeV; the implantation process parameters of the second doping ions comprise: the dosage range of the second doping ions is 1 x 10 11 atom/cm 2 To 1X 10 16 atom/cm 2 The energy range is 2KeV to 100KeV.
In another embodiment, the first conductivity type is P-type and the second conductivity type is N-type; the concentration range of the first drift doping region is 1 multiplied by 10 12 atom/cm 3 To 1X 10 21 atom/cm 3 The depth of the first drift doping region ranges from 0.5 μm to 30 μm; the concentration range of the second drift doped region is 1 multiplied by 10 12 atom/cm 3 To 1X 10 21 atom/cm 3 And the depth of the second drift doping region ranges from 0.5 μm to 30 μm.
Referring to fig. 6 to 8, fig. 6 is a schematic top view, fig. 7 is a schematic cross-sectional view taken along the direction DD1 in fig. 6, and fig. 8 is a schematic cross-sectional view taken along the direction EE1 in fig. 6, wherein a gate layer 104b is formed on the substrate 100, a portion of the gate layer 104b is located on the body region 101, and another portion of the gate layer 104b is also located on the first drift doped region 102.
In this embodiment, the gate layer 104b extends along the second direction Y.
The material of the gate layer 104b includes polysilicon or metal. In this embodiment, the material of the gate layer 104b is polysilicon.
In this embodiment, a gate oxide layer 104a is further disposed between the gate layer 104b and the substrate 100.
In this embodiment, before forming the gate layer 104b, an isolation structure 105 is further formed in the first drift doped region 102; the gate layer 104b is also located on a portion of the isolation structure 105. The isolation structure 105 serves to further improve the withstand voltage performance of the device. In another embodiment, the isolation structure may not be formed.
The material of the isolation structure 105 is a dielectric material. In this embodiment, the isolation structure 105 is made of silicon oxide.
The method for forming the isolation structure 105 comprises the following steps: forming an isolation trench (not shown) in the first drift doped region 102; forming an isolation material layer (not shown) in the substrate 100 and the isolation trench; the layer of isolation material is planarized until the substrate 100 surface is exposed.
Referring to fig. 9 to 11, fig. 9 is a schematic top view, fig. 10 is a schematic cross-sectional view taken along the direction DD1 in fig. 9, fig. 11 is a schematic cross-sectional view taken along the direction EE1 in fig. 9, a drain region 106 and a source region 107 are respectively formed on two sides of the gate layer 104b, the drain region 106 is located in the first drift doping region 102, the source region 107 is located in the body region 101, and the source region 107 and the drain region 106 have the second conductivity type.
In this embodiment, the conductivity types of the drain region 106 and the source region 107 are N-type. In another embodiment, the conductivity types of the drain region and the source region are P-type.
In this embodiment, the drain region 106 is located on a side of the isolation structure 105 away from the gate layer 104 b.
Accordingly, another embodiment of the present invention further provides a semiconductor structure formed by the above method, with reference to fig. 9 to 11, including: a substrate 100; a body region 101 located within the substrate 100, the body region 101 having a first conductivity type; a first drift-doped region 102 located in the substrate 100, and a plurality of second drift-doped regions 103 located in the first drift-doped region 102, wherein the first drift-doped region 102 is adjacent to the body region 101, the plurality of second drift-doped regions 103 are separated from each other, the first drift-doped region 102 has a second conductivity type, the second drift-doped region 103 has the first conductivity type, and the first conductivity type is different from the second conductivity type; a gate layer 104b located on the substrate 100, a portion of the gate layer 104b being located on the body region 101, and another portion of the gate layer 104b being further located on the first drift doped region 102; a drain region 106 and a source region 107 respectively located at two sides of the gate layer 104b, wherein the drain region 106 is located in the first drift doping region 102, the source region 107 is located in the body region 101, and the source region 107 and the drain region 106 have a second conductivity type.
In this embodiment, the semiconductor structure includes: the plurality of second drift doping regions 103 are parallel to a first direction X and arranged along a second direction Y, and the first direction X is perpendicular to the second direction Y.
In this embodiment, the gate layer 104b extends along the second direction Y.
In this embodiment, a gate oxide layer 104a is further disposed between the gate layer 104b and the substrate 100.
In this embodiment, a dimension d1 of the second drift doping region 103 along the second direction Y ranges from 0.5 μm to 10 μm, and a distance d2 between adjacent second drift doping regions 103 ranges from 0.5 μm to 10 μm.
In this embodiment, the semiconductor structure further includes: an isolation structure 105 located in the first drift doped region 102, the gate layer 104b further located on a portion of the isolation structure 105, and the drain region 106 located on a side of the isolation structure 105 away from the gate layer 104 b.
In this embodiment, the first conductive type is an N-type, and the second conductive type is a P-type; the concentration range of the first drift doping region 102 is 1 × 10 12 atom/cm 3 To 1X 10 21 atom/cm 3 The depth of the first drift doping region 102 ranges from 0.5 μm to 30 μm; the concentration range of the second drift doping region 103 is 1 × 10 12 atom/cm 3 To 1X 10 21 atom/cm 3 The depth of the second drift doping region 103 ranges from 0.5 μm to 30 μm.
In another embodiment, the first conductivity type is P-type and the second conductivity type is N-type; the concentration range of the first drift doping region is 1 multiplied by 10 12 atom/cm 3 To 1X 10 21 atom/cm 3 The depth of the first drift doping region ranges from 0.5 μm to 30 μm; the concentration range of the second drift doped region is 1 multiplied by 10 12 atom/cm 3 To 1 × 10 21 atom/cm 3 The depth of the second drift doping region ranges from 0.5 μm to 30 μm.
In this embodiment, the distance d3 between the second drift doping region 103 and the body region 101 is in a range from 0.5 μm to 10 μm.
In this embodiment, the number of the second drift doping regions 103 is greater than or equal to 3.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (19)
1. A semiconductor structure, comprising:
a substrate;
a body region within the substrate, the body region having a first conductivity type;
a first drift doping region located in the substrate and a plurality of second drift doping regions located in the first drift doping region, wherein the first drift doping region is adjacent to the body region, the plurality of second drift doping regions are mutually separated, the first drift doping region has a second conductivity type, the second drift doping region has the first conductivity type, and the first conductivity type is different from the second conductivity type;
a gate layer on the substrate, a portion of the gate layer being on the body region and another portion of the gate layer also being on the first drift doped region;
and the drain region and the source region are respectively positioned at two sides of the gate layer, the drain region is positioned in the first drift doping region, the source region is positioned in the body region, and the source region and the drain region have a second conductivity type.
2. The semiconductor structure of claim 1, comprising: the plurality of second drift doping regions are parallel to a first direction and are arranged along a second direction, and the first direction is vertical to the second direction; the gate layer extends in the second direction.
3. The semiconductor structure of claim 2, wherein the second drift doped regions have a dimension along the second direction in a range from 0.5 μm to 10 μm, and a distance between adjacent second drift doped regions is in a range from 0.5 μm to 10 μm.
4. The semiconductor structure of claim 1, further comprising: and the drain region is positioned on one side of the isolation structure far away from the gate layer.
5. The semiconductor structure of claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type; the concentration range of the first drift doping region is 1 multiplied by 10 12 atom/cm 3 To 1X 10 21 atom/cm 3 The depth of the first drift doping region ranges from 0.5 μm to 30 μm; the concentration range of the second drift doped region is 1 multiplied by 10 12 atom/cm 3 To 1X 10 21 atom/cm 3 And the depth of the second drift doping region ranges from 0.5 μm to 30 μm.
6. The semiconductor structure of claim 1, wherein the first conductivity type is P-type and the second conductivity type is N-type; the concentration range of the first drift doping region is 1 multiplied by 10 12 atom/cm 3 To 1X 10 21 atom/cm 3 The depth of the first drift doping region ranges from 0.5 μm to 30 μm; the concentration range of the second drift doped region is 1 multiplied by 10 12 atom/cm 3 To 1X 10 21 atom/cm 3 The depth of the second drift doping region ranges from 0.5 μm to 30 μm.
7. The semiconductor structure of claim 1, in which a distance between the second drift doped region and the body region is in a range from 0.5 μ ι η to 10 μ ι η.
8. The semiconductor structure of claim 1, wherein the number of the second drift doped regions ranges from greater than or equal to 3.
9. A method of forming a semiconductor structure, comprising:
providing a substrate;
forming a body region within the substrate, the body region having a first conductivity type;
forming a first drift doping region and a plurality of second drift doping regions in the first drift doping region in the substrate, wherein the first drift doping region is adjacent to the body region, the plurality of second drift doping regions are separated from each other, the first drift doping region has a second conductivity type, the second drift doping region has the first conductivity type, and the first conductivity type is different from the second conductivity type;
forming a gate layer on the substrate, wherein one part of the gate layer is positioned on the body region, and the other part of the gate layer is also positioned on the first drift doping region;
and forming a drain region and a source region on two sides of the gate layer respectively, wherein the drain region is positioned in the first drift doping region, the source region is positioned in the body region, and the source region and the drain region have a second conductivity type.
10. The method of forming a semiconductor structure of claim 9, comprising: the plurality of second drift doping regions are parallel to a first direction and are arranged along a second direction, and the first direction is vertical to the second direction; the gate layer extends in the second direction.
11. The method of claim 10, wherein the second drift doped regions have a dimension along the second direction in a range of 0.5 μm to 10 μm, and a distance between adjacent second drift doped regions is in a range of 0.5 μm to 10 μm.
12. The method of forming a semiconductor structure of claim 9, further comprising, prior to forming the gate layer: forming an isolation structure in the first drift doping region; the gate layer is also positioned on a part of the isolation structure; the drain region is located on one side of the isolation structure away from the gate layer.
13. The method of forming a semiconductor structure of claim 9, wherein the method of forming the first drift doped region and the plurality of second drift doped regions comprises: forming a first mask layer on the surface of the substrate, wherein the first mask layer exposes the surface of the first drift doping region; injecting first doping ions into the substrate by taking the first mask layer as a mask; forming a second mask layer on the surface of the substrate, wherein the second mask layer exposes the surface of the second drift doping region; and injecting second doping ions into the substrate by taking the second mask layer as a mask.
14. The method of forming a semiconductor structure of claim 13, wherein the first conductivity type is N-type and the second conductivity type is P-type; the implantation process parameters of the first doping ions comprise: the dosage range of the first doping ions is 1 x 10 11 atom/cm 2 To 1X 10 16 atom/cm 2 The energy range is 2KeV to 100KeV; the implantation process parameters of the second doping ions comprise: the dosage range of the second doping ions is 1 x 10 11 atom/cm 2 To 1X 10 16 atom/cm 2 The energy range is 2KeV to 100KeV.
15. The method of forming a semiconductor structure of claim 13, wherein the first conductivity type is P-type and the second conductivity type is N-type; the implantation process parameters of the first doping ions comprise: the dosage range of the first doping ions is 1 x 10 11 atom/cm 2 To 1 × 10 16 atom/cm 2 The energy range is 2KeV to 100KeV; the implantation process parameters of the second doping ions comprise: the dosage range of the second doping ions is 1 x 10 11 atom/cm 2 To 1X 10 16 atom/cm 2 The energy range is 2KeV to 100KeV.
16. The method of forming a semiconductor structure of claim 9, wherein the first conductivity type is P-type and the second conductivity type is N-type; the concentration range of the first drift doping region is 1 multiplied by 10 12 atom/cm 3 To 1 × 10 21 atom/cm 3 The depth of the first drift doping region ranges from 0.5 μm to 30 μm; the concentration range of the second drift doped region is 1 multiplied by 10 12 atom/cm 3 To 1X 10 21 atom/cm 3 And the depth of the second drift doping region ranges from 0.5 μm to 30 μm.
17. The method of forming a semiconductor structure of claim 9, wherein the first conductivity type is N-type and the second conductivity type is P-type; the concentration range of the first drift doping region is 1 multiplied by 10 12 atom/cm 3 To 1X 10 21 atom/cm 3 The depth of the first drift doping region ranges from 0.5 μm to 30 μm; the concentration range of the second drift doped region is 1 multiplied by 10 12 atom/cm 3 To 1X 10 21 atom/cm 3 And the depth of the second drift doping region ranges from 0.5 μm to 30 μm.
18. The method of forming a semiconductor structure of claim 9, wherein a distance between the second drift doped region and the body region is in a range of 0.5 μ ι η to 10 μ ι η.
19. The method of claim 9, wherein the number of the second drift doping regions is greater than or equal to 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211476768.7A CN115763526A (en) | 2022-11-23 | 2022-11-23 | Semiconductor structure and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211476768.7A CN115763526A (en) | 2022-11-23 | 2022-11-23 | Semiconductor structure and forming method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115763526A true CN115763526A (en) | 2023-03-07 |
Family
ID=85336214
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211476768.7A Pending CN115763526A (en) | 2022-11-23 | 2022-11-23 | Semiconductor structure and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115763526A (en) |
-
2022
- 2022-11-23 CN CN202211476768.7A patent/CN115763526A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8294235B2 (en) | Edge termination with improved breakdown voltage | |
| US7626233B2 (en) | LDMOS device | |
| US8659076B2 (en) | Semiconductor device structures and related processes | |
| US7928505B2 (en) | Semiconductor device with vertical trench and lightly doped region | |
| US8772871B2 (en) | Partially depleted dielectric resurf LDMOS | |
| TWI475614B (en) | Trench device structure and fabrication | |
| US10861965B2 (en) | Power MOSFET with an integrated pseudo-Schottky diode in source contact trench | |
| KR20060051752A (en) | Metal-oxide-semiconductor device having trenched diffusion region and method of forming same | |
| US20220130996A1 (en) | Gate trench power semiconductor devices having improved deep shield connection patterns | |
| CN114744049B (en) | Silicon carbide MOSFET semiconductor device and manufacturing method thereof | |
| US8575688B2 (en) | Trench device structure and fabrication | |
| KR20070032995A (en) | High voltage device and method of forming the same | |
| US20220157959A1 (en) | Semiconductor power devices having multiple gate trenches and methods of forming such devices | |
| GB2607292A (en) | Semiconductor device | |
| EP4228003A1 (en) | Semiconductor device having a current spreading region | |
| US20170352756A1 (en) | Semiconductor device and method of making | |
| US11316021B2 (en) | High density power device with selectively shielded recessed field plate | |
| CN115763526A (en) | Semiconductor structure and forming method thereof | |
| CN113871456B (en) | LDMOS device and forming method thereof | |
| TW201901811A (en) | Vertical power transistor with improved conductivity and high reverse bias performance | |
| KR102359373B1 (en) | Method of fabricating a high voltage semiconductor device | |
| CN114765221A (en) | Semiconductor structure and forming method thereof | |
| CN116417519A (en) | Power MOSFET device and preparation method | |
| CN115020474A (en) | Semiconductor structure and forming method thereof | |
| CN114823904A (en) | Semiconductor structure and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |