CN114765221A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN114765221A
CN114765221A CN202110050105.8A CN202110050105A CN114765221A CN 114765221 A CN114765221 A CN 114765221A CN 202110050105 A CN202110050105 A CN 202110050105A CN 114765221 A CN114765221 A CN 114765221A
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Prior art keywords
gate
region
gate structure
isolation
isolation structure
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CN202110050105.8A
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Chinese (zh)
Inventor
王孝远
张进书
侯永田
冯军宏
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202110050105.8A priority Critical patent/CN114765221A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

A semiconductor structure and a method of forming the same, wherein the structure comprises: the substrate is provided with a drift region and a body region which are adjacent, and the conductivity type of the drift region is opposite to that of the body region; the first gate structure is positioned on the substrate, and transversely crosses the boundary between the drift region and the body region along a first direction, wherein the first direction is a vertical direction of the extending direction of the first gate structure; a source region located in the body region; the source region and the drain region are respectively positioned on two sides of the first gate structure, the first isolation structure is positioned between the first gate structure and the drain region, and a distance is reserved between the first gate structure and the first isolation structure along a first direction; and the second gate structure is positioned on the surface of the first isolation structure. Thus, the performance of the LDMOS transistor is improved.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
An LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor is a power device that forms a lateral current path on the surface of a Semiconductor substrate through planar diffusion (planar diffusion), and is commonly used in radio frequency power circuits, and in high voltage power integrated circuits, a high voltage LDMOS is often used to meet the requirements of high voltage resistance, power control, and the like. In contrast to conventional MOS transistors, a lightly doped region, referred to as a drift region, is typically provided between the source and drain regions of an LDMOS transistor. Therefore, when the LDMOS transistor is connected to a high voltage between the source region and the drain region, the drift region can withstand a higher voltage drop due to the relatively low impurity concentration and the high resistance state of the drift region, so that the LDMOS transistor can have a higher breakdown voltage.
The LDMOS transistor is compatible with a Complementary Metal Oxide Semiconductor (CMOS) process, so that the LDMOS transistor is widely used in a power device. For an LDMOS transistor used as a power integrated circuit, the on-resistance (Rdson) and the Breakdown Voltage (BV) are two important metrics for measuring the device performance.
However, the performance of the conventional LDMOS transistor is still poor.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which aims to improve the performance of an LDMOS transistor.
To solve the above technical problem, an aspect of the present invention provides a semiconductor structure, including: the substrate is provided with a drift region and a body region which are adjacent, and the conductivity type of the drift region is opposite to that of the body region; the first gate structure is positioned on the substrate, and transversely crosses the boundary between the drift region and the body region along a first direction, wherein the first direction is a vertical direction of the extending direction of the first gate structure; a source region and a second isolation structure in the body region; the source region and the drain region are respectively positioned on two sides of the first gate structure, the first isolation structure is positioned between the first gate structure and the drain region, the first isolation structure and the second isolation structure are respectively positioned on two sides of the source region, and a space is formed between the first gate structure and the first isolation structure along a first direction; the second grid structure is positioned on the surface of the first isolation structure; a fourth gate structure located on the body region, the fourth gate structure being located between the second isolation structure and the source region, and the fourth gate structure further extending to a portion of the surface of the second isolation structure; and the fifth gate structure and the fourth gate structure are respectively positioned at two sides of the second isolation structure, and the fifth gate structure also extends to part of the surface of the second isolation structure.
Optionally, a distance between the first gate structure and the first isolation structure is greater than 0 micron and less than 0.3 micron.
Optionally, the method further includes: a first gate conductive structure on the first gate structure; a second gate conductive structure on the second gate structure.
Optionally, the first gate conductive structure is electrically connected to the second gate conductive structure.
Optionally, the drift region has a first heavily doped region therein, the conductivity type of the first heavily doped region is the same as the conductivity type of the drift region, and the first heavily doped region is located between the first gate structure and the first isolation structure.
Optionally, the method further includes: and the drain region and the first isolation structure are respectively positioned at two sides of the third gate structure.
Optionally, a space is formed between the third gate structure and the first isolation structure along the first direction.
Optionally, a distance between the third gate structure and the first isolation structure is greater than 0 micron and less than 0.2 micron.
Optionally, the first heavily doped region is further located between the third gate structure and the first isolation structure.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: forming a substrate, wherein the substrate is provided with a drift region and a body region which are adjacent, and the conductivity type of the drift region is opposite to that of the body region; forming a first isolation structure in the drift region; after the first isolation structure is formed, forming a first gate structure and a second gate structure on the substrate, wherein the first gate structure crosses the boundary between the drift region and the body region along a first direction, the second gate structure is positioned on the surface of the first isolation structure, and the first gate structure and the first isolation structure are spaced along the first direction, and the first direction is a direction perpendicular to the extending direction of the first gate structure; and forming a source region in the body region and a drain region in the drift region, wherein the source region and the drain region are respectively positioned at two sides of the first gate structure, and the first isolation structure is positioned between the first gate structure and the drain region.
Optionally, the method further includes: and forming a first heavily doped region in the drift region while forming the source region and the drain region, wherein the conductivity type of the first heavily doped region is the same as that of the drift region, and the first heavily doped region is positioned between the first gate structure and the first isolation structure.
Optionally, the method further includes: and forming a third gate structure on the substrate at the same time of forming the first gate structure, wherein the third gate structure is also positioned between the first isolation structure and the drain region.
Optionally, a space is formed between the third gate structure and the first isolation structure along the first direction.
Optionally, the process of forming the first heavily doped region includes an epitaxial growth process.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
in the semiconductor structure provided by the technical solution of the present invention, on one hand, since the first gate structure and the first isolation structure have a gap therebetween along the first direction (the direction perpendicular to the extending direction of the first gate structure), not only the electric field strength generated at the boundary between the first isolation structure and the drift region and the vicinity thereof is not easily enhanced by the influence of the high voltage applied to the first gate structure, but also the hot carriers generated at the boundary between the first isolation structure and the drift region and the vicinity thereof are reduced. Meanwhile, the path distance for the hot carriers generated at the boundary of the first isolation structure and the drift region and the vicinity thereof to move to the first gate structure is increased, so that the difficulty of injecting the hot carriers into the first gate structure is increased. Therefore, under the action of the two aspects, hot carriers injected into the first grid structure are well reduced, the influence on the electrical characteristics of the semiconductor structure is reduced, and the performance of the semiconductor structure is further improved. On the other hand, because the semiconductor structure further comprises the second gate structure positioned on the surface of the first isolation structure, the control capability of carriers in the drift region around the first isolation structure can be enhanced by applying higher voltage on the second gate structure, so that the voltage division capability of the drift region is improved, the semiconductor structure has better voltage withstanding capability, and further, the performance of the semiconductor structure is improved.
Further, the first heavily doped region is arranged in the drift region, the conductivity type of the first heavily doped region is the same as that of the drift region, and the first heavily doped region is positioned between the first gate structure and the first isolation structure, so that the contact resistance of the surface of the drift region between the first gate structure and the first isolation structure is reduced through the first heavily doped region, the resistance of the semiconductor structure is reduced while the semiconductor structure has better voltage endurance capability, and the performance of the semiconductor structure is improved.
Further, as the third gate structure and the first isolation structure are spaced in the first direction, that is, the first isolation structure and the drain region are spaced relatively, the size of a moving region of carriers between the third gate structure and the first isolation structure and in the vicinity of the third gate structure and the first isolation structure is increased, so that the situation of carrier crowding is reduced, the problem of heat generation caused by carrier crowding is solved, the performance of the semiconductor structure is improved, and the service life of the semiconductor structure is prolonged.
Drawings
FIG. 1 is a schematic cross-sectional view of an LDMOS transistor;
fig. 2 to 8 are schematic cross-sectional views of steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Detailed Description
As mentioned in the background, the performance of the existing LDMOS transistors is still poor. The following detailed description will be made with reference to the accompanying drawings.
Fig. 1 is a schematic cross-sectional view of an LDMOS transistor.
Referring to fig. 1, the LDMOS transistor includes: a substrate 100, wherein the substrate 100 has a doped drift region 101 and a doped body region 102 therein, and the conductivity type of the drift region 101 is opposite to that of the body region 102; a source region 103 located in the body region 102; a drain region 104 and an isolation structure 110 in the drift region 101, wherein the source region 103 and the drain region 104 are respectively located at two sides of the isolation structure 110; a gate structure 120 on the substrate 100, wherein the gate structure 120 crosses the boundary between the drift region 101 and the body region 102, and the gate structure 120 extends onto the isolation structure 110 along a direction perpendicular to the extending direction of the gate structure 120; and a first conductive plug 131 positioned on a surface of the source region 103.
In the above embodiment, by extending the gate structure 120 onto the isolation structure 110, the control capability of the gate structure 120 for the carriers in the offset region 101 is increased, so that the voltage division capability of the LDMOS transistor is improved, and the voltage withstanding capability of the LDMOS transistor is improved.
However, since a high voltage is applied to the drain region 104 and the gate structure 120, a strong electric field is generated in the region a (as shown in fig. 1), and thus hot carriers are easily generated in the region a under the influence of the strong electric field, resulting in hot carrier injection into the gate structure 120, which affects the electrical characteristics of the LDMOS transistor, thereby causing poor performance of the LDMOS transistor.
In order to solve the technical problem, embodiments of the present invention provide a semiconductor structure and a method for forming the same, in which a first gate structure and a first isolation structure are spaced apart from each other along a first direction, and a second gate structure is further included on a surface of the first isolation structure, so that a performance of an LDMOS transistor is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
It should be noted that "surface" in this specification is used to describe a relative positional relationship in space, and is not limited to defining whether or not direct contact is made.
Fig. 2 to 8 are schematic cross-sectional views of steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Referring to fig. 2, a substrate 200 is formed, the substrate 200 has a drift region 201 and a body region 202 adjacent to each other, and the conductivity type of the drift region 201 is opposite to that of the body region 202.
The material of the substrate 200 includes silicon, germanium, silicon germanium, or silicon carbide; silicon-on-insulator (SOI), germanium-on-insulator (GOI); or may be other materials such as group iii-v compounds such as gallium arsenide.
In this embodiment, the material of the substrate 200 is silicon.
In this embodiment, the method of forming the substrate 200 includes: providing an initial substrate (not shown); forming a doped drift region 201 in the initial substrate by adopting an ion implantation process; and forming a doped body region 202 in the initial substrate to form the substrate 200, wherein the conductivity type of the drift region 201 is opposite to that of the body region 202, and the drift region 201 is adjacent to the body region 202.
The drift region 201 is used for separating a drain region and a channel region which are formed subsequently, so that a current channel of the semiconductor structure is prolonged, and breakdown voltage is improved.
The drift region 201 is doped with first ions.
In this embodiment, the semiconductor structure to be formed is an N-type LDMOS, and the first ions are N-type ions, which includes: one or more of phosphorus ions, arsenic ions or antimony ions, that is, the conductivity type of the drift region 201 is N-type.
In other embodiments, the semiconductor structure to be formed is a P-type LDMOS, and the first ions may also be P-type ions, including: one or more of boron ions, indium ions, or gallium ions.
The forming method of the drift region 201 comprises the following steps: forming a drift region mask layer (not shown) on the surface of the initial substrate, wherein the drift region mask layer is used for defining the position and the size of a drift region; and performing an ion implantation process on the initial substrate by using the drift region mask layer as a mask to form the drift region 201 in the initial substrate.
In this embodiment, after forming the drift region 201, the method for forming the semiconductor structure further includes: and removing the mask layer of the drift region.
In this embodiment, the drift region mask layer is made of a photoresist, and is removed by an ashing process.
The body region 202 serves to separate a source region and a channel region which are formed later.
The body region 202 is doped with second ions.
The method for forming the body region 202 comprises the following steps: forming a body mask layer (not shown) on the surface of the initial substrate, wherein the body mask layer is used for defining the position and the size of a body; and performing an ion implantation process on the initial substrate by using the body region mask layer as a mask to form the body region 202 in the initial substrate.
In this embodiment, the semiconductor structure to be formed is an N-type LDMOS, and the second ions are P-type ions, which includes: one or more of boron ions, indium ions, or gallium ions, that is, the conductivity type of the body region 202 is P-type.
The conductivity types of the drift region 201 and the body region 202 are opposite due to the opposite conductivity types of the first ions and the second ions.
In other embodiments, the semiconductor structure to be formed is a P-type LDMOS, and the second ions may also be N-type ions, including: one or more of phosphorus ions, arsenic ions, or antimony ions.
In this embodiment, after forming the body region 202, the method for forming the semiconductor structure further includes: and removing the body mask layer.
In this embodiment, the material of the body region mask layer is photoresist, and the body region mask layer is removed by an ashing process.
In this embodiment, the substrate includes: a substrate (not shown), and a plurality of fin structures (not shown) located on the surface of the substrate and separated from each other.
In other embodiments, the base is a planar substrate.
Referring to fig. 3, a first isolation structure 211 is formed in the drift region 201.
In the present embodiment, the second isolation structure 212 is formed in the body region 202 at the same time as the first isolation structure 211 is formed.
Specifically, in this embodiment, the method for forming the first isolation structure 211 and the second isolation structure 212 includes: forming an isolation structure mask layer (not shown) on the surface of the substrate 200, wherein the isolation structure mask layer exposes a part of the drift region 201 and a part of the body region 202; etching the substrate 200 by using the isolation structure mask layer as a mask, forming a first isolation opening (not shown) in the drift region 201, and forming a second isolation opening (not shown) in the body region 202; forming isolation structure material layers in the first isolation opening, the second isolation opening and the surface of the substrate 200, wherein the isolation structure material layers fill the first isolation opening and the second isolation opening; and planarizing the isolation structure material layer until the surface of the substrate 200 is exposed. Thereby, a first isolation structure 211 is formed in a first isolation opening in the drift region 201 and a second isolation structure 212 is formed in a second isolation opening in the body region 202.
In this embodiment, the isolation structure mask layer is made of photoresist. And after the first isolation opening and the second isolation opening are formed and before the isolation structure material layer is formed, removing the isolation structure mask layer by adopting an ashing process.
Referring to fig. 4, after the first isolation structure 211 is formed, a first gate structure 221 and a second gate structure 222 are formed on the substrate 200.
The first gate structure 221 crosses a boundary between the drift region 201 and the body region 202 along a first direction X, and a distance W1 exists between the first gate structure 221 and the first isolation structure 211 along the first direction X, wherein the first direction X is perpendicular to an extending direction of the first gate structure 221.
In this embodiment, the first gate structure 221 includes: a first gate (not shown) on the substrate 200, a first gate dielectric layer (not shown) between the first gate and the substrate 200, and first gate spacers (not shown) on sidewalls of the first gate.
The first gate side wall is used for protecting the side wall surfaces of the first gate dielectric layer and the first gate electrode from being influenced by a subsequent process, so that the appearance is kept, and the stability of electrical performance is improved; on the other hand, for subsequently defining the location of the source region.
In this embodiment, the first gate structure 221 is a dummy gate, and the position of the first gate opening can be defined subsequently by the first gate sidewall, so as to form a first metal gate in the first gate opening.
In this embodiment, through the first gate sidewall and the first isolation structure 211, the position of the first heavily doped region between the first gate sidewall and the first isolation structure 211 can also be defined in the following.
The second gate structure 222 is located on the surface of the first isolation structure 211.
In this embodiment, the second gate structure 222 includes: a second gate (not shown) on the substrate 200, a second gate dielectric layer (not shown) between the second gate and the substrate 200, and second gate spacers (not shown) on the sidewalls of the second gate.
The second gate side wall has the functions of protecting the side wall surfaces of the second gate dielectric layer and the second gate electrode and preventing the side wall surfaces of the second gate dielectric layer and the second gate electrode from being influenced by subsequent processes, so that the appearance is maintained, and the stability of the electrical performance is improved.
In this embodiment, the second gate structure 222 is a dummy gate, and the position of the second gate opening can be further defined by the second gate sidewall, so as to form a second metal gate in the second gate opening.
In the present embodiment, a third gate structure 223 is formed on the substrate 200 at the same time as the first gate structure 221 and the second gate structure 222 are formed.
The third gate structure 223 is located on the drift region 201, and the first gate structure 221 and the third gate structure 223 are respectively located at two sides of the first isolation structure 211.
In the present embodiment, the third gate structure 223 and the first isolation structure 211 have a distance W2 therebetween along the first direction X.
In this embodiment, the third gate structure 223 includes: a third gate (not shown) on the substrate 200, a third gate dielectric layer (not shown) between the third gate and the substrate 200, and third gate spacers (not shown) on the sidewalls of the third gate.
The third gate side wall is used for protecting the side wall surfaces of the third gate dielectric layer and the third gate electrode from being influenced by a subsequent process, so that the appearance is kept, and the stability of the electrical performance is improved; on the other hand, for subsequently defining the location of the drain region.
In this embodiment, the position of the first heavily doped region between the third gate sidewall and the first isolation structure 211 can be further defined through the third gate sidewall and the first isolation structure 211.
In this embodiment, the third gate structure 223 is a dummy gate, and the position of the third gate opening can be defined subsequently by the third gate sidewall, so as to form a third metal gate in the third gate opening.
In the present embodiment, a fourth gate structure 224 and a fifth gate structure 225 are formed on the substrate 200 at the same time as the first gate structure 221 and the second gate structure 222 are formed.
Specifically, the fourth gate structure 224 is located on the body region 202, the fourth gate structure 224 is located between the second isolation structure 212 and the source region 232, and the fourth gate structure 224 further extends to a portion of the surface of the second isolation structure 212.
The fifth gate structure 225 is located on the body region 202, and the fourth gate structure 224 and the fifth gate structure 225 are respectively located on two sides of the second isolation structure 212 along the first direction X, and the fifth gate structure 225 further extends to a portion of the surface of the second isolation structure 212.
In this embodiment, the fourth gate structure 224 includes: a fourth gate (not shown) on the substrate 200, a fourth gate dielectric layer (not shown) between the fourth gate and the substrate 200, and fourth gate spacers (not shown) on the sidewalls of the fourth gate.
The fourth gate side wall is used for protecting the side wall surfaces of the fourth gate dielectric layer and the fourth gate electrode from being influenced by a subsequent process, so that the appearance is kept, and the stability of the electrical performance is improved; on the other hand, the source region is defined in the position of the first gate structure 221.
In this embodiment, the fourth gate structure 224 is a dummy gate, and the position of the fourth gate opening can be further defined through the fourth gate sidewall, so as to form a fourth metal gate in the fourth gate opening.
In this embodiment, the fifth gate structure 225 includes: a fifth gate (not shown) on the substrate 200, a fifth gate dielectric layer (not shown) between the fifth gate and the substrate 200, and fifth gate spacers (not shown) on the sidewalls of the fifth gate.
The fifth gate side wall is used for protecting the side wall surfaces of the fifth gate dielectric layer and the fifth gate electrode from being influenced by a subsequent process, so that the appearance is kept, and the stability of the electrical performance is improved; on the other hand, for subsequently defining the location of the second heavily doped region.
In this embodiment, the fifth gate structure 225 is a dummy gate, and the position of the fifth gate opening can be defined in the subsequent step by the fifth gate sidewall, so as to form a fifth metal gate in the fifth gate opening.
Specifically, in this embodiment, the method for forming the first gate structure 221, the second gate structure 222, the third gate structure 223, the fourth gate structure 224, and the fifth gate structure 225 includes: forming a gate material layer (not shown) on the substrate 200; forming a gate structure mask layer (not shown) on the surface of the gate material layer, wherein the gate structure mask layer covers a part of the gate material layer on the drift region 201 and a part of the body region 202; etching the gate material layer by using the gate structure mask layer as a mask until the surface of the substrate 200 is exposed, so as to form the first gate, the second gate, the third gate, the fourth gate and the fifth gate on the substrate 200; forming a side wall material film on the surface of the substrate 200, the surface of the first gate, the surface of the second gate, the surface of the third gate, the surface of the fourth gate and the surface of the fifth gate; and etching the side wall material film by adopting an anisotropic etching process until the surface of the substrate 200, the top surface of the first grid, the top surface of the second grid, the top surface of the third grid, the top surface of the fourth grid and the top surface of the fifth grid are exposed, forming a first grid side wall on the side wall of the first grid, forming a second grid side wall on the side wall of the second grid, forming a third grid side wall on the side wall of the third grid, forming a fourth grid side wall on the side wall of the fourth grid and forming a fifth grid side wall on the side wall of the fifth grid.
In this embodiment, the material of the first gate, the second gate, the third gate, the fourth gate, and the fifth gate includes polysilicon.
In this embodiment, the method for forming the first gate structure 221, the second gate structure 222, the third gate structure 223, the fourth gate structure 224, and the fifth gate structure 225 further includes: forming a gate dielectric material layer (not shown) on the substrate 200 before forming the gate material layer; forming the gate material layer on the surface of the gate dielectric material layer; and with the gate structure mask layer as a mask, etching the gate dielectric material layer until the surface of the substrate 200 is exposed in the process of etching the gate material layer, so as to form the first gate dielectric layer, the second gate dielectric layer, the third gate dielectric layer, the fourth gate dielectric layer and the fifth gate dielectric layer.
In this embodiment, the gate structure mask layer is made of photoresist. And after the grid material layer is etched and before the side wall material layer is formed, removing the grid structure mask layer by adopting an ashing process.
In the present embodiment, in the extending direction of the first gate structure 221, the second gate structure 222, the third gate structure 223, the fourth gate structure 224 and the fifth gate structure 225 respectively cross over the fin structure.
Referring to fig. 5, a source region 232 is formed in the body region 202, and a drain region 231 is formed in the drift region 201, the source region 232 and the drain region 231 are respectively located at two sides of the first gate structure 221, and the first isolation structure 211 is located between the first gate structure 221 and the drain region 231.
The first isolation structure 211 and the second isolation structure 212 are also respectively located at two sides of the source region 232.
In this embodiment, the third gate structure 223 is also located between the first isolation structure 211 and the drain region 231.
Specifically, in this embodiment, the method for forming the source region 232 and the drain region 231 includes: etching the substrate of the drift region 201, and forming a drain region opening (not shown) in the drift region 201, wherein the position of the drain region opening is defined by the third gate sidewall; etching the substrate of the body region 202, and forming a source region opening (not shown) in the body region 202, where the position of the source region opening is defined by the first gate sidewall and the fourth gate sidewall; and forming a doped drain material in the drain region opening by using an epitaxial growth process to form the drain region 231, and forming a doped source material in the source region opening to form the source region 232.
The drain region 231 is doped with third ions, the source region 232 is doped with fourth ions, and the conductivity types of the third ions and the fourth ions are the same.
In this embodiment, the semiconductor structure to be formed is an N-type LDMOS, and the third ions and the fourth ions are N-type ions, which includes: one or more of phosphorus ion, arsenic ion or antimony ion, and correspondingly, the drain region 231 and the source region 232 are both N-type in conductivity type.
In other embodiments, the semiconductor structure to be formed is a P-type LDMOS, and the third ions and the fourth ions may also be P-type ions, including: one or more of boron ions, indium ions, or gallium ions.
In this embodiment, while the source region 232 and the drain region 231 are formed, a first heavily doped region 241 is formed in the drift region 201, a conductivity type of the first heavily doped region 241 is the same as a conductivity type of the drift region 201, and the first heavily doped region 241 is located between the first gate structure 221 and the first isolation structure 211.
In this embodiment, the first heavily doped region 241 is also located between the third gate structure 223 and the first isolation structure 211.
In this embodiment, the method for forming the first heavily doped region 241 includes: in the etching process of forming the source region opening and the drain region opening, the surface of the substrate 200 exposed between the first isolation structure 211 and the first gate structure 221, and between the first isolation structure 211 and the third gate structure 223 in the drift region 201 is further etched, first heavily doped openings (not shown) are formed between the first isolation structure 211 and the first gate structure 221, and between the first isolation structure 211 and the third gate structure 223, and the positions of the first heavily doped openings are defined by the first isolation structure 211, the first gate sidewall, and the third gate sidewall; and filling a material in the first heavily doped opening by the epitaxial growth process while forming a doped source material and a doped drain material to form the first heavily doped region 241.
Fifth ions are doped in the first heavily doped region 241, and the conductivity types of the fifth ions and the third ions are the same.
Specifically, in this embodiment, the fifth ions are N-type ions, and include: one or more of phosphorus ions, arsenic ions, or antimony ions.
Referring to fig. 6, a second heavily doped region 242 is formed in the body region 202, and the conductivity type of the second heavily doped region 242 is the same as the conductivity type of the body region 202.
Specifically, the second heavily doped region 242 and the source region 232 are respectively located at two sides of the second isolation structure 212.
In this embodiment, the method for forming the second heavily doped region 242 includes: etching the substrate 200 of the body region 202, and forming a second heavily doped opening (not shown) in the body region 202, where the position of the second heavily doped opening is defined by the fifth gate sidewall; and filling a material in the second heavily doped opening by using an epitaxial growth process to form a second heavily doped region 242.
The second heavily doped region 242 is doped with sixth ions, and the conductivity types of the sixth ions and the second ions are the same.
Specifically, in this embodiment, the sixth ions are P-type ions, and include: one or more of boron ions, indium ions, or gallium ions.
Referring to fig. 7, after the source region 232, the drain region 231, the first heavily doped region 241 and the second heavily doped region 242 are formed, the first gate is removed to form a first gate opening; a metal gate material is filled in the first gate opening to form a first metal gate, so as to form a first gate structure 321.
In this embodiment, the second gate, the third gate, the fourth gate, and the fifth gate are removed while the first gate is removed, and a second gate opening, a third gate opening, a fourth gate opening, and a fifth gate opening are formed, respectively; and filling a metal gate material in the first gate opening, and simultaneously filling a metal gate material in the second gate opening, the third gate opening, the fourth gate opening and the fifth gate opening to form a second gate structure 322, a third gate structure 323, a fourth gate structure 324 and a fifth gate structure 325.
Specifically, the method for forming the first gate structure 321, the second gate structure 322, the third gate structure 323, the fourth gate structure 324, and the fifth gate structure 325 includes: after the source region 232, the drain region 231, the first heavily doped region 241 and the second heavily doped region 242 are formed, a first dielectric layer 250 is formed on the surface of the source region 232, the surface of the drain region 231, the surface of the first heavily doped region 241, the surface of the second heavily doped region 242, the surface of the first isolation structure 211, the surface of the second isolation structure 212, the surface of the substrate 200, the side wall surface of the first gate structure 221, the side wall surface of the second gate structure 222, the side wall surface of the third gate structure 223, the side wall surface of the fourth gate structure 224 and the side wall surface of the fifth gate structure 225, and the first dielectric layer 250 exposes the top surfaces of the first gate, the second gate, the third gate, the fourth gate and the fifth gate; after the dielectric layer is formed, etching the exposed first grid, the exposed second grid, the exposed third grid, the exposed fourth grid and the exposed fifth grid until the first grid, the exposed second grid, the exposed third grid, the exposed fourth grid and the exposed fifth grid are removed, so that a first grid opening is formed between the first grid side walls, a second grid opening is formed between the second grid side walls, a third grid opening is formed between the third grid side walls, a fourth grid opening is formed between the fourth grid side walls, and a fifth grid opening is formed between the fifth grid side walls; and filling metal gate materials in the first gate opening, the second gate opening, the third gate opening, the fourth gate opening and the fifth gate opening to form a first gate structure 321, a second gate structure 322, a third gate structure 323, a fourth gate structure 324 and a fifth gate structure 325.
Referring to fig. 8, after forming a first gate structure 321, a second gate structure 322, a third gate structure 323, a fourth gate structure 324, and a fifth gate structure 325, etching the first dielectric layer 250 until the surfaces of the drain region 231, the source region 232, and the second heavily doped region 242 are exposed, and forming a first conductive opening (not shown), a second conductive opening (not shown), and a third conductive opening (not shown) in the first dielectric layer 250, wherein the first conductive opening exposes the surface of the drain region 231, the second conductive opening exposes the surface of the source region 232, and the third conductive opening exposes the surface of the second heavily doped region 242; conductive material is filled in the first conductive opening, the second conductive opening and the third conductive opening to form a first conductive structure 261 in the first conductive opening, a second conductive structure 262 in the second conductive opening and a third conductive structure 263 in the third conductive opening.
The first conductive structure 261 is located on the drain region 231, the second conductive structure 262 is located on the source region 232, and the third conductive structure 263 is located on the second heavily doped region 242.
In this embodiment, the method for forming a semiconductor structure further includes: after the first conductive structure 261, the second conductive structure 262 and the third conductive structure 263 are formed, a second dielectric layer is further formed on the first dielectric layer 250, and the second dielectric layer covers the body region 202 and the drift region 201; etching the second dielectric layer, and forming a first gate conductive opening and a second gate conductive opening in the second dielectric layer, where the first gate conductive opening exposes the surface of the first gate structure 321, and the second gate conductive opening exposes the surface of the second gate structure 322; conductive material is filled in the first gate conductive opening and the second gate conductive opening to form a first gate conductive structure (not shown) and a second gate conductive structure.
In this embodiment, the first gate conductive structure and the second gate conductive structure are electrically connected.
In other embodiments, no electrical connection is made between the first gate conductive structure and the second gate conductive structure.
Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method, with reference to fig. 8, including: a substrate 200, wherein the substrate 200 is provided with a drift region 201 and a body region 202 which are adjacent, and the conductivity type of the drift region 201 is opposite to that of the body region 202; a first gate structure 321 located on the substrate 200, wherein the first gate structure 321 crosses a boundary between the drift region 201 and the body region 202 along a first direction X, and the first direction X is a direction perpendicular to an extending direction of the first gate structure 321; a source region 232 and a second isolation structure 212 located in the body region 202; a drain region 231 and a first isolation structure 211 located in the drift region 201, wherein the source region 232 and the drain region 231 are located on two sides of the first gate structure 321, respectively, the first isolation structure 211 is located between the first gate structure 321 and the drain region 231, the first isolation structure 211 and the second isolation structure 212 are also located on two sides of the source region 232, respectively, and a distance W1 is located between the first gate structure 231 and the first isolation structure 211 along the first direction X (as shown in fig. 4); a second gate structure 322 on the surface of the first isolation structure 211; a fourth gate structure 324 located on the body region 202, wherein the fourth gate structure 324 is located between the second isolation structure 212 and the source region 232, and the fourth gate structure 324 further extends to a portion of the surface of the second isolation structure 212; the fifth gate structure 325 is located on the body region 202, the fifth gate structure 325 and the fourth gate structure 324 are respectively located at two sides of the second isolation structure 212, and the fifth gate structure 325 further extends to a portion of the surface of the second isolation structure 212.
On the other hand, since the first gate structure 321 and the first isolation structure 211 have the distance W1 therebetween along the first direction X, not only the electric field intensity generated at the boundary between the first isolation structure 211 and the drift region 201 and the vicinity thereof is not easily affected by the high voltage applied to the first gate structure 321, but also the electric field intensity is not easily increased, so that the hot carriers generated at the boundary between the first isolation structure 211 and the drift region 201 and the vicinity thereof are reduced. Meanwhile, the path distance for the hot carriers generated at the boundary between the first isolation structure 211 and the drift region 201 and the vicinity thereof to move to the first gate structure 321 is increased, and thus, the difficulty of injecting the hot carriers into the first gate structure 321 is increased. Therefore, under the above two actions, hot carriers injected into the first gate structure 321 are preferably reduced, and the influence on the electrical characteristics of the semiconductor structure is reduced, thereby improving the performance of the semiconductor structure. On the other hand, since the semiconductor structure further includes the second gate structure 322 located on the surface of the first isolation structure 211, by applying a higher voltage to the second gate structure 322, the control capability of carriers in the drift region 201 around the first isolation structure 211 can be enhanced, so as to improve the voltage dividing capability of the drift region 201, so that the semiconductor structure has a better voltage withstanding capability, and further, the performance of the semiconductor structure is improved.
Specifically, the fourth gate structure 324 and the fifth gate structure 325 are respectively located at two sides of the second isolation structure 212 along the first direction X.
In this embodiment, the substrate includes: a substrate (not shown), and a plurality of fin structures (not shown) located on the surface of the substrate and separated from each other.
In other embodiments, the base is a planar substrate.
The material of the substrate 200 includes silicon, germanium, silicon germanium, or silicon carbide; silicon-on-insulator (SOI), germanium-on-insulator (GOI); or may be other materials such as group iii-v compounds such as gallium arsenide.
In this embodiment, the material of the substrate 200 is silicon.
The drift region 201 is doped with first ions, and the body region 202 is doped with second ions.
In this embodiment, the semiconductor structure is an N-type LDMOS. The first ions are N-type ions, including: one or more of phosphorus ions, arsenic ions or antimony ions, that is, the conductivity type of the drift region 201 is N-type. The second ions are P-type ions, including: one or more of boron ions, indium ions, or gallium ions, that is, the conductivity type of the body region 202 is P-type. The conductivity types of the drift region 201 and the body region 202 are opposite due to the opposite conductivity types of the first ions and the second ions.
In other embodiments, the semiconductor structure is a P-type LDMOS, and the first ions may also be P-type ions, which includes: one or more of boron ions, indium ions, or gallium ions. The second ions may also be N-type ions, including: one or more of phosphorus ions, arsenic ions, or antimony ions.
The drain region 231 is doped with third ions, the source region 232 is doped with fourth ions, and the conductivity types of the third ions and the fourth ions are the same.
In this embodiment, the third ion and the fourth ion are N-type ions, including: one or more of phosphorus ion, arsenic ion or antimony ion, and correspondingly, the drain region 231 and the source region 232 are both N-type in conductivity type.
In other embodiments, the semiconductor structure is a P-type LDMOS. The third and fourth ions may also be P-type ions, including: one or more of boron ions, indium ions, or gallium ions.
In this embodiment, the first gate structure 321 includes: a first metal gate (not shown) on the substrate 200, a first gate dielectric layer (not shown) between the first metal gate and the substrate 200, and a first gate sidewall spacer (not shown) on a sidewall surface of the first metal gate.
In other embodiments, the first gate structure includes: the grid structure comprises a first grid positioned on a substrate, a first grid dielectric layer positioned between the first grid and the substrate, and a first grid side wall positioned on the side wall surface of the first grid. Wherein the material of the first gate comprises polysilicon.
In this embodiment, the second gate structure 322 includes: a second metal gate (not shown) on the substrate 200, a second gate dielectric layer (not shown) between the second metal gate and the substrate 200, and a second gate sidewall spacer (not shown) on a sidewall surface of the second metal gate.
In this embodiment, the second gate structure includes: the second grid electrode is positioned on the substrate, the second grid dielectric layer is positioned between the second grid electrode and the substrate, and the second grid side wall is positioned on the side wall surface of the second grid electrode. Wherein the material of the second gate comprises polysilicon.
In the present embodiment, the distance W1 between the first gate structure 321 and the first isolation structure 211 is greater than 0 micron and less than 0.3 micron.
If the distance W1 is too large, the control capability of carriers in the drift region 201 between the first gate structure 321 and the first isolation structure 211 near the middle is poor, resulting in poor performance of the semiconductor structure. If the distance W1 is too small, the effect of reducing hot carrier injection is poor, which is not favorable for reducing the influence on the electrical characteristics of the semiconductor structure. Therefore, when a proper range of the spacing W1 is selected, that is, the spacing W1 is greater than 0 micrometers and less than 0.3 micrometers, on one hand, the control capability of carriers in all the drift regions 201 between the first gate structures 321 and the first isolation structures 211 is better, and on the other hand, the influence on the electrical characteristics of the semiconductor structure is better reduced, so that the performance of the semiconductor structure is better improved.
In this embodiment, the semiconductor structure further includes: a first gate conductive structure (not shown) on the first gate structure 321; a second gate conductive structure (not shown) on the second gate structure 322.
In this embodiment, the first gate conductive structure is electrically connected to the second gate conductive structure. Accordingly, a high voltage can be simultaneously applied to the first gate structure 321 and the second gate conductive structure 322, thereby achieving control of carriers in the drift region 201 around the first isolation structure 211 by the second gate conductive structure 322.
In other embodiments, no electrical connection is made between the first gate conductive structure and the second gate conductive structure. That is, voltages are applied to the first gate structure and the second gate structure, respectively.
In this embodiment, the drift region 201 has a first heavily doped region 241 therein, the conductivity type of the first heavily doped region 241 is the same as the conductivity type of the drift region 201, and the first heavily doped region 241 is located between the first gate structure 321 and the first isolation structure 211.
Because the first heavily doped region 241 is arranged in the drift region 201, the conductivity type of the first heavily doped region 241 is the same as that of the drift region 201, and the first heavily doped region 241 is located between the first gate structure 321 and the first isolation structure 211, the contact resistance of the surface of the drift region 201 between the first gate structure 321 and the first isolation structure 211 is reduced through the first heavily doped region 241, so that the semiconductor structure has better withstand voltage capability, the resistance of the semiconductor structure is reduced, and the performance of the semiconductor structure is improved.
Fifth ions are doped in the first heavily doped region 241, and the conductivity types of the fifth ions and the third ions are the same.
Specifically, in this embodiment, the fifth ions are N-type ions, and include: one or more of phosphorus ions, arsenic ions, or antimony ions.
In this embodiment, the depth of the first heavily doped region 241 is less than the depth of the drain region 231 and the source region 232, respectively.
In this embodiment, the depth of the first heavily doped region 241 ranges from 200 angstroms to 500 angstroms. Therefore, the influence of the first heavily doped region 241 on other electrical characteristics of the semiconductor structure is avoided while the contact resistance is reduced.
In this embodiment, the semiconductor structure further includes: a third gate structure 323 on the substrate 200.
Specifically, the third gate structure 323 is located on the drift region 201, and the drain region 231 and the first isolation structure 211 are located at both sides of the third gate structure 323, respectively.
In this embodiment, the third gate structure 323 includes: a third metal gate (not shown) on the substrate 200, a third gate dielectric layer (not shown) between the third metal gate and the substrate 200, and a third gate sidewall spacer (not shown) on the sidewall of the third gate.
In other embodiments, the third gate structure includes: the third grid electrode is positioned on the substrate, the third grid dielectric layer is positioned between the third grid electrode and the substrate, and the third grid side wall is positioned on the side wall surface of the third grid electrode. Wherein the material of the third gate comprises polysilicon.
In the present embodiment, the third gate structure 323 and the first isolation structure 211 have a distance W2 therebetween along the first direction X (as shown in fig. 4).
Since the third gate structure 323 and the first isolation structure 211 have a distance W2 therebetween along the first direction X, that is, the distance between the first isolation structure 211 and the drain region 231 is relatively large, the size of the moving region of carriers between and near the third gate structure 323 and the first isolation structure 211 is increased, thereby reducing the carrier crowding, improving the heat generation problem caused by carrier crowding, improving the performance of the semiconductor structure, and prolonging the service life of the semiconductor structure.
In the present embodiment, the distance W2 between the third gate structure 323 and the first isolation structure 211 is greater than 0 micron and less than 0.2 micron.
The distance W2 is too large to facilitate the control of carriers in the drift region 201 between the first isolation structure 211 and the third gate structure 323 near the middle by the second gate structure 322 and the third gate structure 323, resulting in poor performance of the semiconductor structure. If the distance W2 is too small, the effect of improving the carrier crowding is poor, and it is not preferable to improve the heat generation problem due to the carrier crowding. Therefore, when a proper range of the spacing W2 is selected, that is, the spacing W2 is greater than 0 micrometers and less than 0.2 micrometers, on one hand, the control capability of carriers in the drift region 201 between the first isolation structure 211 and the third gate structure 323 is better, and on the other hand, the problem of heat generation caused by carrier crowding is better solved, so that the performance of the semiconductor structure is better improved, and the service life of the semiconductor structure is prolonged.
In this embodiment, the first heavily doped region 241 is also located between the third gate structure 323 and the first isolation structure 211.
Therefore, the contact resistance of the surface of the drift region 201 between the third gate structure 323 and the first isolation structure 211 can also be reduced by the first heavily doped region 241, so that the resistance of the semiconductor structure is further reduced, and the performance of the semiconductor structure is improved.
In this embodiment, the fourth gate structure 324 includes: a fourth metal gate (not shown) on the substrate 200, a fourth gate dielectric layer (not shown) between the fourth metal gate and the substrate 200, and a fourth gate sidewall spacer (not shown) on a sidewall of the fourth gate.
In other embodiments, the fourth gate structure includes: the gate structure comprises a fourth gate on the substrate, a fourth gate dielectric layer between the fourth gate and the substrate, and a fourth gate sidewall on the sidewall of the fourth gate. Wherein the material of the fourth gate comprises polysilicon.
In this embodiment, the fifth gate structure 325 includes: a fifth metal gate (not shown) on the substrate 200, a fifth gate dielectric layer (not shown) between the fifth metal gate and the substrate 200, and a fifth gate sidewall spacer (not shown) on a sidewall surface of the fifth gate.
In other embodiments, the fifth gate structure includes: the grid structure comprises a fifth grid positioned on the substrate, a fifth grid dielectric layer positioned between the fifth grid and the substrate, and a fifth grid side wall positioned on the side wall surface of the fifth grid. Wherein the material of the fifth gate comprises polysilicon.
In the present embodiment, in the extending direction of the first gate structure 321, the second gate structure 322, the third gate structure 323, the fourth gate structure 324, and the fifth gate structure 325 respectively cross over the fin structure.
In this embodiment, the semiconductor structure further includes: a second heavily doped region 242 located in the body region 202, the conductivity type of the second heavily doped region 242 being the same as the conductivity type of the body region 202.
Specifically, the second heavily doped region 242 and the source region 232 are respectively located at two sides of the second isolation structure 212, and the fifth gate structure 325 is located between the second heavily doped region 242 and the second isolation structure 212.
The second heavily doped region 242 is doped with sixth ions, and the conductivity types of the sixth ions and the second ions are the same.
Specifically, in this embodiment, the sixth ions are P-type ions, and include: one or more of boron ions, indium ions, or gallium ions.
In this embodiment, the semiconductor structure further includes: a first conductive structure 261 on the drain region 231; a second conductive structure 262 on the source region 232; a third conductive structure 263 disposed on the second heavily doped region 242.
Although the present invention is disclosed above, the invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (14)

1. A semiconductor structure, comprising:
the substrate is provided with a drift region and a body region which are adjacent, and the conductivity type of the drift region is opposite to that of the body region;
the first gate structure is positioned on the substrate, and transversely crosses the boundary between the drift region and the body region along a first direction, wherein the first direction is a vertical direction of the extending direction of the first gate structure;
a source region and a second isolation structure in the body region;
the source region and the drain region are respectively positioned on two sides of the first gate structure, the first isolation structure is positioned between the first gate structure and the drain region, the first isolation structure and the second isolation structure are respectively positioned on two sides of the source region, and a space is formed between the first gate structure and the first isolation structure along a first direction;
The second grid structure is positioned on the surface of the first isolation structure;
a fourth gate structure located on the body region, the fourth gate structure being located between the second isolation structure and the source region, and the fourth gate structure further extending to a portion of the surface of the second isolation structure;
and the fifth gate structure and the fourth gate structure are respectively positioned at two sides of the second isolation structure, and the fifth gate structure also extends to part of the surface of the second isolation structure.
2. The semiconductor structure of claim 1, wherein a spacing between the first gate structure and the first isolation structure is greater than 0 microns and less than 0.3 microns.
3. The semiconductor structure of claim 1, further comprising: a first gate conductive structure on the first gate structure; a second gate conductive structure on the second gate structure.
4. The semiconductor structure of claim 3, wherein the first gate conductive structure is electrically connected to the second gate conductive structure.
5. The semiconductor structure of claim 1, wherein the drift region has a first heavily doped region therein, the first heavily doped region having a same conductivity type as the drift region, the first heavily doped region being located between the first gate structure and the first isolation structure.
6. The semiconductor structure of claim 5, further comprising: and the drain region and the first isolation structure are respectively positioned at two sides of the third gate structure.
7. The semiconductor structure of claim 6, in which the third gate structure is spaced apart from the first isolation structure along the first direction.
8. The semiconductor structure of claim 7, wherein a spacing between the third gate structure and the first isolation structure is greater than 0 microns and less than 0.2 microns.
9. The semiconductor structure of claim 7, wherein the first heavily doped region is further located between the third gate structure and the first isolation structure.
10. A method of forming a semiconductor structure, comprising:
forming a substrate, wherein the substrate is provided with a drift region and a body region which are adjacent, and the conductivity type of the drift region is opposite to that of the body region;
forming a first isolation structure in the drift region;
after the first isolation structure is formed, forming a first gate structure and a second gate structure on the substrate, wherein the first gate structure crosses the boundary between the drift region and the body region along a first direction, the second gate structure is positioned on the surface of the first isolation structure, and the first gate structure and the first isolation structure are spaced along the first direction, and the first direction is a direction perpendicular to the extending direction of the first gate structure;
And forming a source region in the body region and a drain region in the drift region, wherein the source region and the drain region are respectively positioned at two sides of the first gate structure, and the first isolation structure is positioned between the first gate structure and the drain region.
11. The method of forming a semiconductor structure of claim 10, further comprising: and forming a first heavily doped region in the drift region while forming the source region and the drain region, wherein the conductivity type of the first heavily doped region is the same as that of the drift region, and the first heavily doped region is positioned between the first gate structure and the first isolation structure.
12. The method of forming a semiconductor structure of claim 11, further comprising: and forming a third gate structure on the substrate while forming the first gate structure, wherein the third gate structure is also positioned between the first isolation structure and the drain region.
13. The method of forming a semiconductor structure of claim 12, wherein the third gate structure is spaced apart from the first isolation structure along the first direction.
14. The method of forming a semiconductor structure of claim 11, wherein the process of forming the first heavily doped region comprises an epitaxial growth process.
CN202110050105.8A 2021-01-14 2021-01-14 Semiconductor structure and forming method thereof Pending CN114765221A (en)

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