CN115762611A

CN115762611A - Anti-Fuse circuit structure and chip system

Info

Publication number: CN115762611A
Application number: CN202211439655.XA
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Chuangshi Microelectronics Chengdu Co ltd
Current assignee: Chuangshi Microelectronics Chengdu Co ltd
Priority date: 2022-11-17
Filing date: 2022-11-17
Publication date: 2023-03-07

Abstract

The invention discloses a circuit structure and a chip system of Anti-Fuse, which comprise a logic control module, a power supply control module, a row selection module, a column selection module, a comparator array and a data processing module, wherein the logic control module is used for receiving an external control signal and an address signal, generating a control signal and controlling the actions of other modules; the programming voltage and the reading voltage are connected to the power supply control module through an IO interface from the outside of the chip; and the power supply control module is used for controlling the logic control module to generate a power supply control signal according to the requirement of a read or write mode, switching the power supply control signal and selecting a power supply during programming or reading, supplying the selected voltage to the row selection module, and controlling the row selection module to release corresponding voltage to the selected storage unit. The invention greatly reduces the area of Anti-Fuse and the production cost of the chip; the chip can be well adapted to the use environment of the chip to make a rapid design.

Description

Anti-Fuse circuit structure and chip system

Technical Field

The invention relates to the technical field of OTP (one time programmable) one-time programmable memories, in particular to a circuit structure of Anti-Fuse and a chip system.

Background

OTP (One Time Programmable) is a One-Time Programmable memory, which is usually used to store chip information: such as the power supply voltage available to the chip, the version number of the chip, the date of manufacture, etc. And can also be used to repair SRAM bad point data. The current design method of OTP mainly adopts the following three schemes of E-Fuse/Anti-Fuse/I-Fuse. The Anti-Fuse has great development potential due to the perfect compatibility with the standard CMOS process. And as the process feature size shrinks, it becomes easier to complete programming at low programming voltages.

The currently mainstream Anti-Fuse design mainly comprises: memory array, read circuit, control logic, charge pump, bandgap reference, and linear regulator. In such a design, the memory array usually occupies only a quarter of the area of the entire Anti-Fuse, and most of the other area is occupied by analog modules such as a bandgap reference, a charge pump and a linear regulator, which results in a large area redundancy if the Anti-Fuse of the architecture is used, and is very disadvantageous for reducing the cost.

Disclosure of Invention

The invention aims to provide an Anti-Fuse circuit structure and a chip system, and the Anti-Fuse design scheme only comprises the following steps: the chip system comprises a storage array, a reading circuit, a control logic and a power supply control module, wherein the required band-gap reference is shared with the band-gap reference of the chip system. On one hand, the Anti-Fuse based circuit structure can be flexibly selected according to needs during chip design, for example, when the chip needs to reduce the area, the output voltage of the charge pump and the linear voltage stabilizer can be provided from an IO port outside the chip; and if the using scene of the chip is not suitable for supplying extra voltage from the outside, the mode can be quickly restored to the mode of supplying power to the charge pump and the linear voltage regulator, and the circuit structure of the Anti-Fuse can be designed without any modification. On the other hand, the Anti-Fuse circuit structure does not comprise a charge pump and a linear voltage regulator, so that the risk of the circuit failing to work due to the fault of a power supply module is greatly reduced. When a fault occurs, the fault is also convenient to debug due to the reason of the core circuit part with high probability. Therefore, the scheme of the invention can greatly reduce the area of Anti-Fuse, thereby reducing the production cost of the chip; secondly, the scheme of the invention can be well adapted to the chip use environment to make a rapid design; finally, the risk of circuit failure is reduced because the circuit is simplified.

The invention is realized by the following technical scheme:

in a first aspect, the present invention provides a circuit structure of an Anti-Fuse, the circuit structure comprising:

the logic control module is used for receiving an external control signal and an address signal and generating a control signal; the actions of the column selection module, the row selection module, the data processing module and the power control module are controlled through control signals;

the power supply control module is connected with the programming voltage VCP and the reading voltage VLDO from the outside of the chip through an IO interface and supplies power to the whole circuit structure; the power control module is used for controlling the logic control module to generate a power control signal according to the requirement of a read or write mode, switching the power control signal and selecting a power supply when programming or reading is required, supplying the selected voltage to the row selection module, and controlling the row selection module to release corresponding voltage to the selected storage unit;

the row selection module is used for executing selection of one row from the storage array after receiving the row selection signal given by the logic control module;

the column selection module is used for selecting one column from the memory array according to the received column selection signal given by the logic control module; when the row and the column are selected simultaneously, the memory cell is subjected to read or write operation;

the comparator array is used for receiving data in the memory array selected by the row and column selection module during reading action, comparing the data with reference data and then outputting the data to the data processing module;

and the data processing module is used for processing the data according to the requirement and outputting the data to the outside of the circuit structure.

Further, the row selection module is further configured to release the programming voltage VCP to the selected memory cell for a programming action during the programming action; for releasing a read voltage VLDO to a selected memory cell during a read operation.

Furthermore, the power control module comprises a power control signal unit and a control switch selection unit; when the power control module is used for programming or reading, the power switch is controlled according to the power control signal given by the logic control module, and the selected voltage is provided for the row selection module to be used for reading and writing the storage unit.

The power supply control signal unit is used for controlling the power supply control module to select the maximum potential in the programming voltage and the reading voltage, providing the maximum potential to the control signal amplification circuit, and converting the low-voltage control signal into a high-voltage control signal of 0-Max (VCP, VLDO) through the control signal amplification circuit; wherein VCP is a programming voltage and VLDO is a reading voltage;

and the control switch selection unit is used for selecting a programming voltage or a reading voltage by using the high-voltage control signal and outputting the selected voltage to the row selection module.

Further, the power supply control signal unit comprises a first substrate potential control circuit, a first MOS transistor M1, a second MOS transistor M2, a second substrate potential control circuit, a control signal amplification circuit and an inverter INV;

the S end of the first substrate potential control circuit is connected with the source electrode of the first MOS transistor M1, the D end of the first substrate potential control circuit is connected with the drain electrode of the first MOS transistor M1, and the B end of the first substrate potential control circuit is connected with the substrate of the first MOS transistor M1; the source electrode of the first MOS tube M1 is also connected with a programming voltage VCP, the drain electrode of the first MOS tube M1 is also connected with the control signal amplification circuit and the power supply end of the inverter INV, and the grid electrode of the first MOS tube M1 is connected with the source electrode of the second MOS tube M2; the grid electrode of the second MOS tube M2 is connected with the source electrode of the first MOS tube M1, the source electrode of the second MOS tube M2 is connected with the S end of the second substrate potential control circuit, and the drain electrode of the second MOS tube M2 is connected with the drain electrode of the first MOS tube M1; the grid electrode of the second MOS tube M2 is connected with the source electrode of the first MOS tube M1 and is also connected with a reading voltage VLDO; the D end of the second substrate potential control circuit is connected with the drain electrode of the second MOS transistor M2, and the B end of the second substrate potential control circuit is connected with the substrate of the second MOS transistor M2;

the input end of the control signal amplification circuit inputs a low-voltage control signal, the output end of the control signal amplification circuit outputs a high-voltage control signal, the output end of the control signal amplification circuit is connected with the input end of an inverter INV, and the output end of the inverter INV is connected with the control switch selection unit.

Further, the control switch selection unit comprises a third substrate potential control circuit, a third MOS transistor M3, a fourth MOS transistor M4 and a fourth substrate potential control circuit;

the S end of the third substrate potential control circuit is connected with the source electrode of the third MOS transistor M3, the D end of the third substrate potential control circuit is connected with the drain electrode of the third MOS transistor M3, and the B end of the third substrate potential control circuit is connected with the substrate of the third MOS transistor M3; the source electrode of the third MOS transistor M3 is further connected with a programming voltage VCP, the drain electrode of the third MOS transistor M3 is further connected with the row selection module, and the gate electrode of the third MOS transistor M3 is connected with the input end of the inverter INV;

the grid electrode of the fourth MOS tube M4 is connected with the output end of the inverter INV, the source electrode of the fourth MOS tube M4 is connected with the S end of the fourth substrate potential control circuit, and the drain electrode of the fourth MOS tube M4 is connected with the D end of the fourth substrate potential control circuit; the end B of the fourth substrate potential control circuit is connected with the substrate of a fourth MOS transistor M4; the source electrode of the fourth MOS transistor M4 is further connected to the reading voltage VLDO, and the drain electrode of the fourth MOS transistor M4 is further connected to the row selection module.

Furthermore, the first substrate potential control circuit, the second substrate potential control circuit, the third substrate potential control circuit and the fourth substrate potential control circuit all adopt substrate potential control circuits with the same structure.

Further, the first substrate potential control circuit comprises a fifth MOS transistor Sub1 and a sixth MOS transistor Sub2, the source of the fifth MOS transistor Sub1 is connected with the source of the first MOS transistor M1, the gate of the fifth MOS transistor Sub1 is connected with the drain of the first MOS transistor M1, the drain of the fifth MOS transistor Sub1 is connected with the source of the sixth MOS transistor Sub2, the gate of the sixth MOS transistor Sub2 is connected with the source of the first MOS transistor M1, and the drain of the sixth MOS transistor Sub2 is connected with the drain of the first MOS transistor M1; the common end of the drain electrode of the fifth MOS transistor Sub1 and the source electrode of the sixth MOS transistor Sub2 is connected with the substrate of the first MOS transistor M1;

the source of the fifth MOS transistor Sub1 is used as the S terminal of the first substrate potential control circuit, the drain of the sixth MOS transistor Sub2 is used as the D terminal of the first substrate potential control circuit, and the common terminal of the drain of the fifth MOS transistor Sub1 and the source of the sixth MOS transistor Sub2 is used as the B terminal of the first substrate potential control circuit.

Further, the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, and the fourth MOS transistor M4 all adopt P-type MOS transistors.

Further, the execution process of the power control signal unit for implementing the disordered power-on of the chip system is as follows:

when the reading voltage VLDO is started before the programming voltage VCP, if the reading voltage VLDO is larger than the programming voltage VCP, the reading voltage VLDO is transmitted to the control signal amplification circuit to supply power, and the third MOS tube M3 and the fourth MOS tube M4 are controlled according to the control logic at all times, so that an unexpected current path is avoided;

when the programming voltage VCP is started before the reading voltage VLDO, if the programming voltage VCP is larger than the reading voltage VLDO, the programming voltage VCP is transmitted to the control signal amplification circuit to supply power, and the third MOS tube M3 and the fourth MOS tube M4 are controlled according to the control logic at any time, so that an unexpected current path is avoided.

Through the processing, the problems caused by the power-on sequence are effectively avoided, and the chip still supports disordered power-on.

In a second aspect, the invention further provides a chip system, where the chip system includes the Anti-Fuse circuit structure, and the Anti-Fuse circuit structure is used to implement normal operation when power is supplied to the Anti-Fuse circuit structure from outside the chip system.

Compared with the prior art, the invention has the following advantages and beneficial effects:

firstly, compared with the prior art, the Anti-Fuse circuit structure and the chip system have the advantages that the area of a chip can be saved by three quarters because a charge pump and a linear voltage stabilizer are not arranged; the area of Anti-Fuse is greatly reduced, and the production cost of the chip is further reduced; secondly, the scheme of the invention can be well adapted to the chip use environment to make a rapid design; when the chip system using scene does not support the extra voltage provided by the outside, the charge pump charge and the linear voltage regulator can be directly integrated in the chip, and the VCP and VLDO generated by the charge pump and the linear voltage regulator can be output to the power control module, and the Anti-Fuse circuit can complete the design without any modification. Finally, the risk of circuit failure is reduced because the circuit is simplified.

(1) The FNC module (namely a substrate potential control circuit) in the power supply control module effectively prevents the conduction of a parasitic PN junction of a PMOS tube switch; the occurrence of the problem 1) is prevented.

(2) In the left dotted line frame of fig. 4, the gate potentials of the first MOS transistor M1 and the second MOS transistor M2 are VLDO and VCP, respectively, because VLDO is smaller than VCP, the first MOS transistor M1 meets the turn-on condition and is turned on, and finally, the maximum value between VCP and VLDO is output to the control signal amplification circuit, so that the control signals controlling the third MOS transistor M3 and the fourth MOS transistor M4 are 0 or Max (VCP, VLDO). When the third MOS transistor M3 needs to be opened and the fourth MOS transistor M4 needs to be closed, the gate voltage of the third MOS transistor M3 will be 0, and the gate voltage of the fourth MOS transistor M4 will be Max (VCP, VLDO); thereby solving problem 2).

(3) First, when the read voltage VLDO is started before the programming voltage VCP, if the read voltage VLDO is greater than the programming voltage VCP, the dashed line frame on the left side of fig. 4 will transmit the VLDO to the control signal amplification circuit and control the third MOS transistor M3 and the third MOS transistor M4 according to the control logic, so that an unexpected current path does not occur. Secondly, when the programming voltage VCP is started before the reading voltage VLDO, if the programming voltage VCP is greater than the reading voltage VLDO, the programming voltage VCP is transmitted to the control signal amplification circuit to supply power, and the third MOS transistor M3 and the fourth MOS transistor M4 are controlled according to the control logic at any time, so that an unexpected current path is avoided. Through the processing, the problems caused by the power-on sequence are effectively avoided, so that the chip still supports disordered power-on; thereby solving problem 3).

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:

FIG. 1 is a schematic diagram of the Anti-Fuse architecture of the prior art.

FIG. 2 is a schematic diagram of an Anti-Fuse architecture with a charge pump and a linear regulator removed in the prior art.

Fig. 3 is a schematic circuit structure diagram of Anti-Fuse according to embodiment 1 of the present invention.

Fig. 4 is a circuit diagram of a power control module according to embodiment 1 of the present invention.

FIG. 5 is a circuit diagram of the FNC module (i.e., substrate potential control circuit) according to embodiment 1 of the present invention.

Fig. 6 is a circuit diagram of a control signal amplification circuit according to embodiment 1 of the present invention.

FIG. 7 is a schematic diagram of the voltage variation of embodiment 1 in which the programming voltage VCP is started before the reading voltage VLDO.

FIG. 8 is a diagram illustrating the voltage variation of embodiment 1 in which the read voltage VLDO is activated before the program voltage VCP.

Detailed Description

Hereinafter, the term "comprising" or "may include" used in various embodiments of the present invention indicates the presence of the invented function, operation or element, and does not limit the addition of one or more functions, operations or elements. Furthermore, as used in various embodiments of the present invention, the terms "comprises," "comprising," "includes," "including," "has," "having" and their derivatives are intended to mean that the specified features, numbers, steps, operations, elements, components, or combinations of the foregoing, are only meant to indicate that a particular feature, number, step, operation, element, component, or combination of the foregoing, and should not be construed as first excluding the existence of, or adding to the possibility of, one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing.

In various embodiments of the invention, the expression "or" at least one of a or/and B "includes any or all combinations of the words listed simultaneously. For example, the expression "a or B" or "at least one of a or/and B" may include a, may include B, or may include both a and B.

Expressions (such as "first", "second", and the like) used in various embodiments of the present invention may modify various constituent elements in various embodiments, but may not limit the respective constituent elements. For example, the above description does not limit the order and/or importance of the elements described. The above description is only intended to distinguish one element from another. For example, the first user device and the second user device indicate different user devices, although both are user devices. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of various embodiments of the present invention.

It should be noted that: if it is described that one constituent element is "connected" to another constituent element, the first constituent element may be directly connected to the second constituent element, and a third constituent element may be "connected" between the first constituent element and the second constituent element. In contrast, when one constituent element is "directly connected" to another constituent element, it is understood that there is no third constituent element between the first constituent element and the second constituent element.

The terminology used in the various embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the various embodiments of the invention. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the present invention belong. The terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning that is consistent with their contextual meaning in the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein in various embodiments of the present invention.

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and the accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not used as limiting the present invention.

Based on the Anti-Fuse architecture diagram of the prior art, as shown in fig. 1, a bandgap reference generates a reference voltage and current and provides the reference voltage and current to a charge pump and a linear regulator, and the charge pump and the linear regulator generate a programming voltage and a reading voltage. The program voltage is applied to a gate of the memory cell, and the read voltage is used to supply a voltage to the memory cell when data is read. The logic control module receives an external control signal and an address signal and generates a control signal for controlling the actions of the column selection module, the row selection module and the data processing module. The row selection module is used for receiving a control signal of the logic control module and selecting rows of the memory array according to a set address, releasing a programming voltage to the memory array for programming during programming action, and releasing a reading voltage to the memory array during reading action.

If the charge pump circuit and the linear regulator are simply eliminated as shown in fig. 2 (a) for area reduction, the corresponding power supply is provided outside the chip instead, and only the MOS switch for switching the two voltages as shown in fig. 2 (b) faces 3 problems:

problem 1), the parasitic PN junction of the source terminal of the PMOS as the switching tube may generate forward bias, resulting in the risk of power supply short circuit.

For example, when the memory array needs to be programmed, the left PMOS transistor in fig. 2 (b) is turned on and the right PMOS transistor is turned off. The drain voltage of both switches will now be the programming voltage VCP. Since the program voltage VCP needs to be set much larger than the read voltage VLDO for programming success, the substrate-to-source PN junction of the PMOS transistor on the right side will be in a conducting state (i.e., forward biased state), and the read voltage VLDO and the program voltage VCP will be shorted.

Problem 2), the gate control signal of the PMOS as the switching tube is lower than the source terminal voltage and cannot completely close the switch.

For example, when the programming voltage VCP and the read current VLDO are supplied simultaneously, the control signal is boosted to the highest voltage VCP so that the control signal can be successfully turned off and not used. If the part of the boosting circuit is directly fixed and supplied with power by the VCP, the normal operation can be realized under the condition that the programming voltage VCP and the reading voltage VLDO exist at the same time. However, when only a read operation is performed on the memory array, the program voltage VCP is usually turned off to save power consumption and increase circuit lifetime. When the boost circuit portion has no voltage, the control signal will be disabled.

Problem 3), the additional increase of the programming voltage VCP and the reading voltage VLDO beyond the original power supply to the chip increases the failure possibility of the original chip's power-up sequence.

In order to solve the above problem 2), the programming voltage VCP is selected to be always supplied, and the control circuit for controlling the PMOS switch is supplied with the programming voltage VCP. Therefore, to prevent an unexpected current path from occurring during power-up of the system-on-chip, the programming voltage VCP needs to be started before the reading voltage VLDO. However, the usage scenario of the system-on-chip is often out-of-order power-up, and such additional power-up restriction cannot necessarily be guaranteed.

Therefore, in view of solving the above three problems, the present invention designs an Anti-Fuse circuit structure, and designs a power control module while replacing the charge pump and the linear regulator with external power supply, so as to finally obtain the architecture shown in fig. 3: the invention discloses a circuit structure of Anti-Fuse.

The Anti-Fuse circuit structure only comprises the following components: the storage array, the reading circuit, the control logic and the power supply control module share the required band-gap reference and the band-gap reference of the chip system. The programming voltage VCP and the reading voltage VLDO of the invention are connected to the power supply control module through the IO interface from the outside of the chip and supply power to the whole circuit structure; the power control module is used for controlling a power control signal generated by the logic control module according to the requirement of a read or write mode, switching the power control signal and selecting a power supply when programming or reading is required, providing the selected voltage for the row selection module, and controlling the row selection module to release corresponding voltage to the selected memory cell.

On one hand, the Anti-Fuse based circuit structure can be flexibly selected according to requirements during chip design, for example, when the chip needs to reduce the area, the output voltage of the charge pump and the linear voltage stabilizer can be provided from an IO port outside the chip; and if the using scene of the chip is not suitable for external extra voltage, the power supply mode of the charge pump and the linear voltage regulator can be quickly restored, and the Anti-Fuse circuit structure can be designed without any modification. On the other hand, the Anti-Fuse circuit structure does not comprise a charge pump and a linear voltage stabilizer, and a power supply control module is additionally arranged after the band gap reference, the linear voltage stabilizer and the charge pump in the prior art are deleted, but the size of the power supply control module is far smaller than the sum of the linear voltage stabilizer, the band gap reference and the charge pump, and the area of the newly arranged power supply control module can be almost ignored compared with the sum of the three modules; therefore, the chip system can save three quarters of area, and meanwhile, the invention solves some practical problems faced by directly removing the charge pump and the linear voltage stabilizer in the prior art through the designed power supply control module, so that the design is more flexible and safer in application scene.

The risk of the circuit failing due to a power supply module failure is greatly reduced. When a fault occurs, the fault is also convenient to debug due to the reason of the core circuit part with high probability. Therefore, the scheme of the invention can greatly reduce the area of Anti-Fuse at first, thereby reducing the production cost of the chip; secondly, the scheme of the invention can be well adapted to the use scene of the chip to make rapid design; finally, the risk of circuit failure is reduced because the circuit is simplified.

Example 1

As shown in fig. 3, the circuit structure of an Anti-Fuse of the present invention comprises:

In the invention, the programming voltage VCP and the reading voltage VLDO are connected to the voltage control module of Anti-Fuse of the invention through an IO interface from the outside of a chip system and supply power to the whole circuit. The logic control module receives an external control signal and an address signal and generates a control signal for controlling the actions of the column selection module, the row selection module, the data processing module and the power control module. The row selecting module selects a row from the memory array after receiving the row selecting signal from the logic control module, and the column selecting module selects a column from the memory array after receiving the column selecting signal from the logic control module. When the row and column are selected at the same time, the memory cell will be read or written. The power control module is a control signal generated by the logic control module according to the read or write mode, and when the programming or reading is needed, the control signal is switched and selects the power supply, then the selected voltage is provided to the row selection module, and the row selection module releases the corresponding voltage to the selected memory cell. The row selection module releases the program voltage VCP to the selected memory cell for a programming action at the time of a programming action, and releases the read voltage VLDO to the selected memory cell at the time of a reading action. During the write operation, the comparator array and the data processing module are in the off state because no data is output. When the data processing module reads the data, the data in the memory array selected by the row and column selection module is output to the comparator array, and the comparator array compares the data with the reference data and then outputs the data to the data processing module. The data processing module can process the data according to the requirement and then output the processed data to the exterior of the Anti-Fuse of the invention.

As shown in fig. 4, the power control module includes a power control signal unit and a control switch selection unit; the FNC module in fig. 4 is a substrate potential control circuit (a first substrate potential control circuit, a second substrate potential control circuit, a third substrate potential control circuit, and a fourth substrate potential control circuit), and is configured to detect potentials at two ends of a source and a drain of each PMOS transistor, and pull the substrate potential of the PMOS transistor to a highest potential between the source and the drain potentials, so as to prevent a source and drain PN junction of the PMOS transistor from being forward biased to cause a short circuit.

The left dashed line frame in fig. 4 is a power control signal unit, which is used to control the power control module to automatically select the maximum potential of the programming voltage VCP and the reading voltage VLDO, and provide the maximum potential to the control signal amplification circuit, and the control signal amplification circuit converts the low-voltage control signal into a high-voltage control signal of 0 to Max (VCP, VLDO). The right dashed box in fig. 4 is a control switch selection unit which controls a switch in the right dashed box in fig. 4 using this high voltage control signal and selects either the program voltage VCP or the read voltage VLDO, and then outputs the selected voltage to the row selection module.

Specifically, the power supply control signal unit comprises a first substrate potential control circuit, a first MOS transistor M1, a second MOS transistor M2, a second substrate potential control circuit, a control signal amplification circuit and an inverter INV;

Specifically, the control switch selection unit comprises a third substrate potential control circuit, a third MOS transistor M3, a fourth MOS transistor M4 and a fourth substrate potential control circuit;

The first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3 and the fourth MOS transistor M4 are all P-type MOS transistors.

The first substrate potential control circuit, the second substrate potential control circuit, the third substrate potential control circuit and the fourth substrate potential control circuit all adopt substrate potential control circuits with the same structure.

As shown in fig. 5, fig. 5 (a) is a circuit connection diagram, and fig. 5 (b) is a cross-sectional view of the structure. The first substrate potential control circuit comprises a fifth MOS transistor Sub1 and a sixth MOS transistor Sub2, wherein the source electrode of the fifth MOS transistor Sub1 is connected with the source electrode of the first MOS transistor M1, the grid electrode of the fifth MOS transistor Sub1 is connected with the drain electrode of the first MOS transistor M1, the drain electrode of the fifth MOS transistor Sub1 is connected with the source electrode of the sixth MOS transistor Sub2, the grid electrode of the sixth MOS transistor Sub2 is connected with the source electrode of the first MOS transistor M1, and the drain electrode of the sixth MOS transistor Sub2 is connected with the drain electrode of the first MOS transistor M1; the common end of the drain electrode of the fifth MOS transistor Sub1 and the source electrode of the sixth MOS transistor Sub2 is connected with the substrate of the first MOS transistor M1;

Wherein, sub1/2 is used to detect the voltage of the source and drain (SD terminal) of the first MOS transistor M1 and pull the voltage of the substrate N-Well to the highest voltage of the SD terminal. Assuming that the source (S) voltage is the read voltage VLDO and the drain (D) voltage is the higher programming voltage VCP, with the FNC module (i.e., the substrate potential control circuit), the voltage of the substrate N-Well will become the programming voltage VCP, so that the source-drain PN junction of the PMOS transistor is in the off state in any case.

It should be noted that S, B, D of the FNC module (substrate potential control circuit) in fig. 4 correspondingly represents the S terminal, B terminal, D terminal of the FNC module; s, G, D in fig. 5 correspondingly represents the source, gate and drain of the first MOS transistor.

As shown in fig. 6, fig. 6 shows a control signal amplification circuit, VIN1/2 in fig. 6 is a low voltage signal, and after passing through the amplification circuit, VOUT outputs a control signal of max (VCP, VLDO) voltage amplitude.

The mechanism of action of the Anti-Fuse circuit structure of the invention on the above-mentioned 3 problems (problem 1), problem 2) and problem 3)) is as follows:

problem 1), the parasitic PN junction of the source end of the PMOS as the switching tube has the risk of short circuit due to positive bias.

The FNC module (namely a substrate potential control circuit) in the power supply control module effectively prevents the conduction of a parasitic PN junction of a PMOS tube switch. Assuming that the third MOS transistor M3 is selected to be turned on and the fourth MOS transistor M4 is selected to be turned off in the dashed-line frame on the right side in fig. 4, the voltage outputted to the row selection module is the programming voltage VCP. For the fourth MOS transistor M4, the drain potential is VCP, and the source potential is VLDO, because the FNC module detects the highest voltage of the source-drain potential and biases the substrate to the highest voltage, the source-drain PN junction of the fourth MOS transistor M4 is always in a reverse bias state, thereby preventing the occurrence of the problem 1).

Problem 2), the gate control signal of the PMOS as the switching tube is lower than the source terminal voltage and can not completely close the switch.

In the left dotted line frame of fig. 4, the gate potentials of the first MOS transistor M1 and the second MOS transistor M2 are VLDO and VCP, respectively, because VLDO is smaller than VCP, the first MOS transistor M1 meets the turn-on condition and is turned on, and finally, the maximum value between VCP and VLDO is output to the control signal amplification circuit, so that the control signals controlling the third MOS transistor M3 and the fourth MOS transistor M4 are 0 or Max (VCP, VLDO). When the third MOS transistor M3 needs to be turned on and the fourth MOS transistor M4 needs to be turned off, the gate voltage of the third MOS transistor M3 will be 0, and the gate voltage of the fourth MOS transistor M4 will be Max (VCP, VLDO). Thereby solving problem 2).

Problem 3), the additional VCP and VLDO for the chip beyond the original power supply will increase the failure possibility of the original chip's power-up sequence at start-up.

First, when the read voltage VLDO is started before the programming voltage VCP, if the read voltage VLDO is greater than the programming voltage VCP, the dashed box on the left side of fig. 4 will deliver the VLDO to the control signal amplification circuit and control the third MOS transistor M3 and the third MOS transistor M4 according to the control logic, so that an unexpected current path does not occur. Secondly, when the programming voltage VCP is started before the reading voltage VLDO, if the programming voltage VCP is greater than the reading voltage VLDO, the programming voltage VCP is transmitted to the control signal amplification circuit to supply power, and the third MOS transistor M3 and the fourth MOS transistor M4 are controlled according to the control logic at any time, so that an unexpected current path is avoided. Through the processing, the problems caused by the power-on sequence are effectively avoided, and the chip still supports disordered power-on. Thereby solving problem 3).

The voltage changes at the respective nodes during power-up and switching of control signals are shown in fig. 7 and 8, where fig. 7 shows that the programming voltage VCP is initiated prior to the reading voltage VLDO, and fig. 8 shows that the reading voltage VLDO is initiated prior to the programming voltage VCP.

When the chip system using scene does not support the external supply of extra voltage, the charge pump charge and the linear voltage regulator can be directly integrated in the chip, and VCP and VLDO generated by the charge pump charge and the linear voltage regulator are output to the power control module, and the Anti-Fuse circuit can complete the design without any modification.

Example 2

As shown in fig. 3 to fig. 8, the present embodiment is different from embodiment 1 in that the present embodiment further provides a chip system, where the chip system uses the Anti-Fuse circuit structure described in embodiment 1, and the Anti-Fuse circuit structure is used to enable normal operation when power is supplied to the Anti-Fuse circuit structure from outside the chip system.

The invention is suitable for use when the chip system usage scenario supports the provision of additional voltages from the outside.

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. A circuit structure of an Anti-Fuse, comprising:

the power supply control module is connected with the programming voltage and the reading voltage from the outside of the chip through an IO interface and supplies power to the whole circuit structure; the power control module is used for controlling a power control signal generated by the logic control module according to the requirement of a read or write mode, switching the power control signal and selecting a power supply during programming or reading, supplying the selected voltage to the row selection module, and controlling the row selection module to release corresponding voltage to the selected storage unit;

the row selection module is used for selecting one row from the storage array according to the received row selection signal given by the logic control module;

the column selection module is used for selecting one column from the memory array according to the received column selection signal given by the logic control module;

2. The Anti-Fuse circuit structure according to claim 1, wherein said row selecting module is further configured to release a programming voltage to a selected memory cell for a programming operation; for releasing the read voltage to the selected memory cell during a read operation.

3. The Anti-Fuse circuit structure according to claim 1, wherein said power control module comprises a power control signal unit and a control switch selection unit.

The power supply control signal unit is used for controlling the power supply control module to select the maximum potential in the programming voltage and the reading voltage, providing the maximum potential to the control signal amplification circuit, and converting a low-voltage control signal into a high-voltage control signal of 0-Max (VCP, VLDO) through the control signal amplification circuit; wherein VCP is a programming voltage, VLDO is a reading voltage;

4. The Anti-Fuse circuit structure according to claim 3, wherein said power control signal unit comprises a first substrate potential control circuit, a first MOS transistor, a second substrate potential control circuit, a control signal amplification circuit and an inverter;

the S end of the first substrate potential control circuit is connected with the source electrode of the first MOS tube, the D end of the first substrate potential control circuit is connected with the drain electrode of the first MOS tube, and the B end of the first substrate potential control circuit is connected with the substrate of the first MOS tube; the source electrode of the first MOS tube is also connected with a programming voltage, the drain electrode of the first MOS tube is also connected with the control signal amplification circuit and the power supply end of the reverser, and the grid electrode of the first MOS tube is connected with the source electrode of the second MOS tube; the grid electrode of the second MOS tube is connected with the source electrode of the first MOS tube, the source electrode of the second MOS tube is connected with the S end of the second substrate potential control circuit, and the drain electrode of the second MOS tube is connected with the drain electrode of the first MOS tube; the grid electrode of the second MOS tube is connected with the source electrode of the first MOS tube and is also connected with a reading voltage; the D end of the second substrate potential control circuit is connected with the drain electrode of the second MOS tube, and the B end of the second substrate potential control circuit is connected with the substrate of the second MOS tube;

the input end of the control signal amplification circuit inputs a low-voltage control signal, the output end of the control signal amplification circuit outputs a high-voltage control signal, the output end of the control signal amplification circuit is connected with the input end of the reverser, and the output end of the reverser is connected with the control switch selection unit.

5. The Anti-Fuse circuit structure according to claim 3, wherein said control switch selection unit comprises a third substrate potential control circuit, a third MOS transistor, a fourth MOS transistor and a fourth substrate potential control circuit;

the S end of the third substrate potential control circuit is connected with the source electrode of the third MOS tube, the D end of the third substrate potential control circuit is connected with the drain electrode of the third MOS tube, and the B end of the third substrate potential control circuit is connected with the substrate of the third MOS tube; the source electrode of the third MOS tube is also connected with a programming voltage, the drain electrode of the third MOS tube is also connected with the row selection module, and the grid electrode of the third MOS tube is connected with the input end of the inverter;

the grid electrode of the fourth MOS tube is connected with the output end of the inverter, the source electrode of the fourth MOS tube is connected with the S end of the fourth substrate potential control circuit, and the drain electrode of the fourth MOS tube is connected with the D end of the fourth substrate potential control circuit; the end B of the fourth substrate potential control circuit is connected with the substrate of a fourth MOS tube; the source electrode of the fourth MOS tube is also connected with a reading voltage, and the drain electrode of the fourth MOS tube is also connected with a row selection module.

6. The Anti-Fuse circuit structure according to claim 4, wherein said first substrate potential control circuit and said second substrate potential control circuit are the same.

7. The Anti-Fuse circuit structure according to claim 6, wherein said first substrate potential control circuit comprises a fifth MOS transistor and a sixth MOS transistor, a source of said fifth MOS transistor is connected to a source of said first MOS transistor, a gate of said fifth MOS transistor is connected to a drain of said first MOS transistor, a drain of said fifth MOS transistor is connected to a source of said sixth MOS transistor, a gate of said sixth MOS transistor is connected to a source of said first MOS transistor, and a drain of said sixth MOS transistor is connected to a drain of said first MOS transistor; the common end of the drain electrode of the fifth MOS tube and the source electrode of the sixth MOS tube is connected with the substrate of the first MOS tube;

and the common end of the drain electrode of the fifth MOS tube and the source electrode of the sixth MOS tube is used as the B end of the first substrate potential control circuit.

8. The Anti-Fuse circuit structure according to claim 4 or 5, wherein the first MOS transistor, the second MOS transistor, the third MOS transistor and the fourth MOS transistor are P-type MOS transistors.

9. The Anti-Fuse circuit structure according to claim 4, wherein the execution process of the power control signal unit to realize the disordered power-on of the chip system is as follows:

when the reading voltage is started before the programming voltage, if the reading voltage is greater than the programming voltage, the reading voltage VLDO is transmitted to the control signal amplification circuit to supply power, and the third MOS tube and the fourth MOS tube are controlled according to the control logic all the time, so that an unexpected current path is avoided;

when the programming voltage is started before the reading voltage, if the programming voltage is greater than the reading voltage, the programming voltage is transmitted to the control signal amplification circuit to supply power, and the third MOS tube and the fourth MOS tube are controlled according to the control logic constantly, so that an unexpected current path is prevented.

10. A system-on-chip comprising the Anti-Fuse circuit structure of any one of claims 1 to 9.