CN115755470A - Array substrate, manufacturing method and display panel - Google Patents
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- CN115755470A CN115755470A CN202211423457.4A CN202211423457A CN115755470A CN 115755470 A CN115755470 A CN 115755470A CN 202211423457 A CN202211423457 A CN 202211423457A CN 115755470 A CN115755470 A CN 115755470A
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Abstract
The invention discloses an array substrate, a manufacturing method and a display panel, wherein the array substrate of one embodiment comprises a first electrode layer, an insulating layer and a second electrode layer which are stacked on a substrate, wherein the second electrode layer comprises a plurality of sub-electrodes which are arranged at intervals; the insulating layer comprises insulating blocks which are arranged in one-to-one correspondence with the sub-electrodes, and the orthographic projections of the sub-electrodes on the substrate cover the orthographic projections of the corresponding insulating blocks on the substrate; the array substrate further comprises an insulating medium filled between the adjacent sub-electrodes and between the adjacent insulating blocks. According to the embodiment of the invention, on the basis of insulating the first electrode layer and the second electrode layer by using the insulating blocks to ensure normal operation of the array substrate, the transmittance of the array substrate is improved by filling the insulating medium with transmittance higher than that of the insulating blocks between the adjacent insulating blocks, and the storage capacitance of each pixel of the array substrate is further increased by using the dielectric constant of the insulating medium higher than that of the insulating blocks to ensure the stability of the pixel voltage, so that the embodiment has practical application value.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a manufacturing method and a display panel.
Background
With the development of liquid crystal display technology, the requirements on liquid crystal display products are higher and higher, wherein transmittance and pixel voltage holding ratio become two important indexes which affect the final display effect of the liquid crystal display products, the high transmittance can reduce the requirements of the liquid crystal display products on backlight brightness, and the stable pixel voltage is an important basis for parameters of the products, such as high brightness, high contrast ratio and the like.
How to improve the transmittance and the pixel voltage of the liquid crystal display product becomes a technical problem to be solved urgently by those skilled in the art.
Disclosure of Invention
In order to solve at least one of the above problems, a first aspect of the present invention provides an array substrate including a first electrode layer, an insulating layer, and a second electrode layer stacked on a substrate, wherein
The second electrode layer comprises a plurality of sub-electrodes arranged at intervals;
the insulating layer comprises insulating blocks which are arranged in one-to-one correspondence with the sub-electrodes, and the orthographic projection of the sub-electrodes on the substrate covers the orthographic projection of the corresponding insulating blocks on the substrate;
the array substrate further comprises insulating media filled between the adjacent sub-electrodes and between the adjacent insulating blocks, the transmittance of the insulating media is greater than that of the insulating blocks, and the dielectric constant of the insulating media is greater than that of the insulating blocks.
In an alternative embodiment, the insulation block forms a retraction structure on one side close to the insulation medium;
the orthographic projection area of the insulating medium between the adjacent insulating blocks on the substrate is larger than that of the insulating medium between the corresponding adjacent sub-electrodes on the substrate.
In an optional embodiment, the array substrate includes a plurality of sub-pixels arranged in an array, a plurality of data lines connected to the sub-pixels in each column, a plurality of data transmission lines receiving an input data signal, and a plurality of multiplexing circuits each connected to one of the data transmission lines and connected to at least three of the data lines, wherein each of the multiplexing circuits is connected to one of the data transmission lines and connected to at least three of the data lines
And each multiplexing circuit transmits the data signals transmitted by the data transmission lines to the corresponding data lines in time slots according to a preset time sequence.
In an alternative embodiment, the multiplexing circuits include multiplexing sub-circuits in one-to-one correspondence with the connected data lines, each multiplexing sub-circuit including a first switching transistor connected to the corresponding data transmission line and a second switching transistor connected to the data line, wherein,
the first switch transistor responds to an input first control signal, accesses a data signal transmitted by the data transmission line and transmits the data signal to the data line through the second switch transistor;
the second switching transistor compensates the accessed data signal in response to an input second control signal and transmits the compensated data signal to the data line.
In an alternative embodiment, the first and second switching transistors each comprise a control terminal, a first terminal and a second terminal, wherein
The control end of the first switch transistor is connected with the first control signal, the first end of the first switch transistor is connected with the data transmission line, and the second end of the first switch transistor is connected with the first end of the second switch transistor, the second end of the second switch transistor and the data line;
and the control end of the second switching transistor is connected to the second control signal.
In an alternative embodiment, the aspect ratio of the first switching transistor is the same as the aspect ratio of the second switching transistor.
A second aspect of the present invention provides a display panel including the array substrate as set forth in the first aspect.
A third aspect of the present invention provides a method for manufacturing an array substrate according to the second aspect, comprising:
the array substrate comprises a substrate, and is characterized in that a first electrode layer, an insulating layer and a second electrode layer are formed on the substrate in a stacking mode, wherein the second electrode layer comprises a plurality of sub-electrodes arranged at intervals, the insulating layer comprises insulating blocks arranged in one-to-one correspondence with the sub-electrodes, orthographic projections of the sub-electrodes on the substrate cover orthographic projections of the corresponding insulating blocks on the substrate, and the array substrate further comprises insulating media filled between adjacent sub-electrodes and between adjacent insulating blocks.
In an optional embodiment, the forming of the first electrode layer, the insulating layer, and the second electrode layer on the substrate in a stack further comprises:
forming a first electrode layer on the substrate;
forming an insulating material layer on the first electrode layer;
patterning the insulating material layer to form an insulating layer, wherein the insulating layer comprises a plurality of insulating blocks arranged at intervals;
forming a second electrode layer on the insulating layer, wherein the second electrode layer comprises sub-electrodes formed on the insulating blocks, and the orthographic projections of the sub-electrodes on the substrate cover the orthographic projections of the corresponding insulating blocks on the substrate;
and filling the insulating medium between the adjacent sub-electrodes and between the adjacent insulating blocks.
In an alternative embodiment, the forming of the first electrode layer, the insulating layer, and the second electrode layer stacked on the substrate further includes:
forming a first electrode layer on the substrate;
forming an insulating material layer on the first electrode layer;
forming a second electrode layer on the insulating material layer, wherein the second electrode layer comprises a plurality of sub-electrodes arranged at intervals;
patterning the insulating material layer to form an insulating layer, wherein the insulating material layer is etched by using the plurality of sub-electrodes as mask plates to form a plurality of insulating blocks, and the orthographic projections of the sub-electrodes on the substrate cover the orthographic projections of the corresponding insulating blocks on the substrate;
and filling the insulating medium between the adjacent sub-electrodes and between the adjacent insulating blocks.
In an optional embodiment, after forming the corresponding sub-electrodes and the insulating blocks, the manufacturing method further includes:
and etching each insulating block of the insulating layer to enable the edge block to form a retraction structure on one side close to the insulating medium, wherein the orthographic projection area of the insulating medium between the adjacent insulating blocks on the substrate is larger than that of the insulating medium between the corresponding adjacent sub-electrodes on the substrate.
In an alternative embodiment, the forming of the first electrode layer, the insulating layer, and the second electrode layer stacked on the substrate further includes: forming a driving circuit layer on the substrate, wherein the driving circuit layer comprises a first switching transistor and a second switching transistor of a multiplexing circuit, the multiplexing circuit is connected with one data transmission line and is connected with at least three data lines, the first switching transistor and the second switching transistor respectively comprise a control end, a first end and a second end, and the first end and the second end are connected with the first switching transistor and the second switching transistor respectively
A control end of the first switching transistor is connected with a first control signal, a first end of the first switching transistor is connected with the data transmission line, a second end of the first switching transistor is connected with a first end of the second switching transistor, a second end of the second switching transistor and the data line, and the first switching transistor responds to the input first control signal, is connected with the data signal transmitted by the data transmission line and is transmitted to the data line through the first end of the second switching transistor;
and the control end of the second switching transistor is connected with a second control signal, and the second switching transistor responds to the input second control signal to compensate the connected data signal and transmit the data signal to the data line.
The invention has the following beneficial effects:
aiming at the existing problems, the invention provides an array substrate, a manufacturing method and a display panel, wherein the array substrate of one embodiment improves the transmittance of the array substrate by filling an insulating medium with a transmittance larger than that of an insulating block between adjacent insulating blocks on the basis of insulating a first electrode layer and a second electrode layer by using the insulating block to ensure the normal work of the array substrate, and further increases the storage capacitance of each pixel of the array substrate by using the insulating medium with a dielectric constant larger than that of the insulating block to ensure the stability of the pixel voltage, so that the problems in the related technology can be solved, and the array substrate has practical application value.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a plan view illustrating an opening area of one pixel of an array substrate in the related art;
fig. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 3 is a plan view illustrating an opening area of one pixel of an array substrate according to an embodiment of the present invention;
fig. 4 is a schematic view illustrating a display effect of the array substrate according to an embodiment of the invention;
fig. 5 is a schematic structural diagram of an array substrate according to another embodiment of the present invention;
FIG. 6 is a schematic circuit diagram of a multiplexing circuit of the array substrate according to an embodiment of the invention;
fig. 7a is a schematic circuit diagram of a multiplexing circuit of an array substrate according to another embodiment of the invention;
fig. 7b is a schematic structural diagram of a multiplexing circuit of the array substrate according to another embodiment of the invention;
fig. 7c is an equivalent circuit diagram of a multiplexing circuit of the array substrate according to another embodiment of the invention;
fig. 8 is a schematic diagram illustrating a variation of a pixel voltage of a multiplexing circuit of the array substrate according to an embodiment of the invention;
fig. 9 is a timing diagram of a multiplexing sub-circuit of the multiplexing circuit of the array substrate according to another embodiment of the invention;
fig. 10 is a flow chart illustrating a method for fabricating an array substrate according to another embodiment of the invention;
fig. 11 is a flowchart illustrating a method for manufacturing an array substrate according to another embodiment of the invention.
Detailed Description
In order to more clearly illustrate the invention, the invention is further described below with reference to preferred embodiments and the accompanying drawings. Similar parts in the figures are denoted by the same reference numerals. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and is not to be taken as limiting the scope of the invention.
It is to be noted that the terms "formed on (8230)", "disposed on (8230)", "formed on (8230)") and "disposed on (8230)", as used herein, may mean that one layer is directly formed or disposed on another layer, or that one layer is indirectly formed or disposed on another layer, that is, another layer is present between two layers. As used herein, unless otherwise specified, the term "on the same layer" means that two layers, components, members, elements or portions can be formed by the same patterning process, and the two layers, components, members, elements or portions are generally formed of the same material. Herein, unless otherwise specified, the expression "patterning process" generally includes the steps of coating of a photoresist, exposure, development, etching, stripping of the photoresist, and the like. The expression "one-time patterning process" means a process of forming a patterned layer, member, component, or the like using one mask.
In the related art, an inorganic film is plated between a pixel electrode and a common electrode of a liquid crystal display product driven by a thin film transistor to serve as an insulating protective layer, so that short circuit between the two electrodes is prevented. The main component of the inorganic film layer is silicon nitride, an insulating layer is usually formed by adopting a whole-layer film coating technology in the existing manufacturing process, and a hole is only dug at the joint of a data signal and a pixel electrode to transmit the data signal, so that the normal work of a liquid crystal display product is ensured. As shown in fig. 1, which is a plan view of an opening area of a liquid crystal display product, includes an entire layer of an insulating protective layer 1 and a pixel electrode 2 disposed thereon.
In view of the above circumstances, the inventors have made extensive studies and experiments to provide a liquid crystal display product having a low transmittance, in which the transmittance of the liquid crystal display product is reduced because the insulating layer between the two electrodes is an inorganic film layer in a whole layer, i.e., the pixel opening region is also covered with the inorganic film layer.
In view of the above problems and the causes for the problems, as shown in fig. 2, an embodiment of the present invention provides an array substrate, including a first electrode layer 11, an insulating layer 12, and a second electrode layer 13 stacked on a substrate 10, wherein the second electrode layer 13 includes a plurality of sub-electrodes 131 arranged at intervals;
the insulating layer 12 comprises insulating blocks 121 arranged in one-to-one correspondence with the sub-electrodes 131, and the orthographic projection of the sub-electrodes 131 on the substrate 10 covers the orthographic projection of the corresponding insulating blocks 121 on the substrate 10;
the array substrate further comprises an insulating medium 14 filled between adjacent sub-electrodes 131 and between adjacent insulating blocks 121, wherein the transmittance of the insulating medium 14 is greater than that of the insulating blocks 121, and the dielectric constant of the insulating medium 14 is greater than that of the insulating blocks 121.
For the problem of the related art that the transmittance is affected by covering the whole insulating layer on the opening region, in this embodiment, on the basis of firstly insulating the first electrode layer 11 and the second electrode layer 12 by using the insulating block 121 to ensure the normal operation of the array substrate, specifically, insulating the sub-electrodes 131 of the first electrode layer 11 and the second electrode layer 12 by using the insulating block 121; the insulating dielectric 14 is then filled between adjacent insulating blocks 121, between adjacent sub-electrodes. As shown in fig. 3, insulating blocks 121 for insulating the first electrode layer 11 and the sub-electrodes 131 are formed on the entirely fabricated insulating layer through a patterning process, and as shown in the figure, the sub-electrodes 131 cover the insulating blocks 121, and insulating media 14 are filled between the insulating blocks 121 and between the sub-electrodes 131. The insulating layer mainly comprises SiNx, the insulating medium is a polyimide PI solution, and the transmittance of the polyimide PI solution is greater than that of the insulating layer, so that the loss of the array substrate to the backlight transmittance is reduced, the influence of the whole insulating layer on the whole light emitting efficiency of the array substrate in an opening area is avoided, and the transmittance of the array substrate is improved; meanwhile, the dielectric constant of SiNx is 7, and the dielectric constant of PI solution is 7.1, according to the following capacitance formula:
wherein epsilon is dielectric constant, S is the opposite area of the polar plates, and d is the distance between the polar plates. Therefore, when the PI solution is used for filling gaps between adjacent insulating blocks, the storage capacitance of each pixel of the array substrate is increased, namely the retention capacity of the pixel voltage is improved by increasing the pixel storage capacitance, the display problem caused by unstable pixel voltage is improved, and the stability of the pixel voltage can be improved; furthermore, the PI solution is filled between the insulating blocks of the insulating layer, so that the precipitation of charged particles in the insulating layer can be eliminated, and the problem of image retention caused by the influence of the precipitated charged particles on liquid crystal deflection in the insulating layer film layer is solved; the problems in the related art are effectively solved, and the overall display effect of the liquid crystal array substrate is improved.
As shown in fig. 4, which is a transmittance ratio of the array substrate of the present embodiment and the related art using the entire insulating layer, in particular, fig. 4 is a voltage-transmittance VT curve diagram, in which the horizontal axis is a saturation voltage of the liquid crystal, the vertical axis is the transmittance, the solid line is the VT curve of the array substrate of the present embodiment, and the dotted line is the VT curve of the array substrate of the related art.
Specifically, in this embodiment, the PI solution is filled in each insulating block of the insulating layer, the area of the reduced insulating layer accounts for 56.6% of the entire area of the insulating layer, the lifting rate of the transmittance of each pixel is 2.76%, the overall lifting rate of the array substrate is the ratio of the area occupied by each pixel opening area multiplied by 4.87%, the larger the opening is, the larger the transmittance is, and the maximum value is 4.87%. In addition, the light use efficiency of the liquid crystal also changes, and it can be known from simulation experiments that the transmittance of the array substrate of the embodiment using the positive liquid crystal is improved by 2.8% and the transmittance of the array substrate using the negative liquid crystal is improved by 1.5% compared with the array substrate of the related art. Therefore, the array substrate of the embodiment effectively improves the transmittance.
It should be noted that, in this embodiment, the first electrode layer is a common electrode, and the second electrode layer is a pixel electrode, for example, strip electrodes arranged at intervals. Moreover, those skilled in the art should understand that the positional relationship between the common electrode and the pixel electrode in the present application may be interchanged, and the insulating layer and the filled insulating medium are appropriately adjusted under the condition of determining the positions of the common electrode and the pixel electrode, so as to implement the normal operation of the array substrate as a design criterion, which is not described herein again.
In order to further improve the pixel voltage holding capability, in an alternative embodiment, as shown in fig. 5, the insulating block 121 forms a retraction structure on a side close to the insulating medium 14; the orthographic projection area of the insulating medium 14 between the adjacent insulating blocks 121 on the substrate 10 is larger than that of the insulating medium between the corresponding adjacent sub-electrodes 131.
In this embodiment, the insulating block is close to one side of the insulating medium to form the inward-shrinking structure, so that on the basis of ensuring the insulation of the sub-electrodes of the first electrode and the second electrode, namely, under the condition that the array substrate can normally work, the insulating block with the inward-shrinking structure is formed, the filling area of the PI solution is increased, and the stability of the pixel voltage is further improved by increasing the storage capacitance of each pixel.
Based on the array substrate of the foregoing embodiment, in an optional embodiment, as shown in fig. 6, the array substrate includes a plurality of sub-pixels arranged in an array, a plurality of data lines R/G/B connected to the sub-pixels in each column, a plurality of data transmission lines S1/S2 receiving input data signals, and a plurality of multiplexing circuits, where each multiplexing circuit is connected to one data transmission line and connected to at least three data lines, and each multiplexing circuit transmits the data signals transmitted by the data transmission lines to the corresponding data lines in time-division manner according to a preset time sequence.
In this embodiment, in consideration of the problem that the number of wires is large and the display frame is occupied due to the fact that the data signals output by the data driving chip are transmitted to the data lines one by one through the data transmission lines, the number of the data transmission lines is reduced by using the multiplexing circuit, and therefore the size of the display frame is reduced. As shown in fig. 6, wherein R/G/B/R/G/B are data lines respectively connected to 6 columns of sub-pixels, the 6 columns of sub-pixels respectively correspond to red/green/blue/red/green/blue sub-pixels, and S1/S2 are data transmission lines connected to the data driving chip for transmitting data signals to the data lines; each multiplexing circuit comprises a gating switch T1/T2/T3, each multiplexing circuit is connected to a MUX control signal line for controlling the switching thin film transistors of the sub-pixel columns with different colors, and each multiplexing circuit is connected with one data transmission line such as S1. Specifically, when a frame picture to be displayed is displayed, the multiplexing circuit controls the conduction of the gating switches of different colors of the signal lines according to the received MUX, and transmits the data signal transmitted by the data transmission line S1 to the corresponding data line when the gating switch is turned on, for example, if the control signal transmitted by the MUXR control signal line is effective, the gating switch T1 is turned on, and transmits the data signal transmitted by the data transmission line S1 to the corresponding data line R, that is, the MUXR control signal line, the gating switch T1, the data transmission line S1 and the data line R form a data voltage transmission channel, so that the data signal is transmitted to the corresponding subpixel R; further, the gate switches are controlled by using a preset timing sequence, that is, the gate switches are respectively turned on in time slots during the effective period of the gate signal, so that the data signal on the output transmission line is transmitted to each sub-pixel. According to the embodiment, the number of data transmission lines can be effectively reduced through the multiplexing circuit, the narrow frame design of the display device is further realized, and meanwhile, the storage capacitance of each sub-pixel is increased according to the embodiment, the pixel voltage can be further maintained after the gating switch driven by the MUX multiplexing circuit is turned off, so that the display effect is improved, and the user experience is enhanced.
In consideration of the influence on the pixel voltage when the gate switch of the MUX circuit is turned off, in an alternative embodiment, as shown in fig. 7a to 7c, the MUX circuit includes multiplexing sub-circuits corresponding to the connected data lines one to one, each multiplexing sub-circuit includes a first switching transistor connected to the corresponding data transmission line and a second switching transistor connected to the data line, wherein the first switching transistor switches in a data signal transmitted by the data transmission line in response to an input first control signal and transmits the data signal to the data line through the second switching transistor; the second switching transistor compensates the accessed data signal in response to an input second control signal and transmits the compensated data signal to the data line.
As shown in fig. 8, when the gate switch of the MUX circuit is turned off, Δ V voltage drop occurs on the data line due to the coupling effect of the turned-off gate switch, and the pixel voltage is decreased by Δ V accordingly. Specifically, when the turn-on time of each gate switch MUX in the multiplexing circuit on the array substrate is long enough, the sub-pixels can be fully charged during the turn-on time of the gate switch MUX, and after the gate switch MUX is turned off, the Pixel voltage Pixel is decreased by Δ V due to the Δ V drop generated on the data line by the coupling effect of the turn-off of the gate switch MUX. Wherein, the calculation formula of Δ V is:
wherein, C gs For gating the capacitance formed by the overlap between the gate and the source, C LC Is a liquid crystal capacitor, C st Is the storage capacitance of the pixel and,V gh positive voltage for gate turn-on, V gl A negative voltage for gate turn on.
From the above formula, Δ V is inversely proportional to Cst, and the larger Cst, the lower Δ V. In this embodiment, by filling PI solution between the insulating blocks of the insulating layer, the medium in the pixel opening area and the edge position right below the pixel electrode is changed, i.e., cst is increased by using PI solution having a larger dielectric constant with respect to the insulating block SiNx, and Δ V is effectively reduced.
Specifically, as shown in fig. 7a, in the present embodiment, on the basis of fig. 6, an auxiliary switch is provided for each gate switch, for example, an auxiliary switch T1' is provided for the gate switch T1, and an auxiliary control signal line is provided for the control signal line, for example, an auxiliary control signal line MUXR-1 is provided for the control signal line MUXR.
Specifically, a complex sub-circuit is used for explanation, as shown in fig. 7a, the multiplexing circuit of this embodiment includes three multiplexing sub-circuits, each multiplexing sub-circuit includes two switching transistors, the two switching transistors are respectively connected to different data transmission lines, signals transmitted by the data transmission lines are transmitted to corresponding sub-pixels through a first switching transistor according to a preset time sequence, and a voltage drop caused by a pixel voltage reduction due to the turn-off of the first switching transistor is compensated through a second switching transistor. In this embodiment, each multiplexing circuit has three sets of control signals, which are MUXR and MUXR-1 for controlling the red sub-pixel, MUXG and MUXG-1 for controlling the green sub-pixel, and MUXB-1 for controlling the blue sub-pixel; each multiplexing circuit accesses a data transmission signal, e.g., S1; each multiplexing sub-circuit comprises two switching transistors, for example the multiplexing sub-circuit of a red sub-pixel comprises a first switching transistor T1 and a second switching transistor T1', for example the multiplexing sub-circuit of a blue sub-pixel comprises a first switching transistor T2 and a second switching transistor T2', for example the multiplexing sub-circuit of a green sub-pixel comprises a first switching transistor T3 and a second switching transistor T3'.
Fig. 7b is a schematic cross-sectional view of a layer structure of the multiplexing sub-circuit of this embodiment, referring to fig. 7a and 7b, each of the first switching transistor T1 and the second switching transistor T1' includes a control terminal 24, a first terminal 27 and a second terminal 26, wherein the control terminal of the first switching transistor T1 is connected to the first control signal MUXR, the first terminal of the first switching transistor T1 is connected to the data transmission line S1, and the second terminal of the first switching transistor T1 is connected to the first terminal of the second switching transistor T1', the second terminal of the second switching transistor T1' and the data line R1; the control terminal of the second switching transistor T1' is connected to the second control signal MUXR-1.
The operation of the multiplexing sub-circuit of the red sub-pixel is described with reference to the circuit diagram shown in fig. 9, in which Gate is the Gate signal, MUXR is the control signal for the first switching transistor T1 of the red sub-pixel, and MUXR-1 is the control signal for the second switching transistor T1' of the red sub-pixel. When the Gate signal Gate is valid at the time T1, the MUXR is valid, and at this time, the first switching transistor T1 is turned on, and the data signal transmitted by the data transmission signal S1 is accessed and transmitted to the red sub-pixel through the second switching transistor T1', that is, the storage capacitor is charged; when the MUXR is invalid at the moment of T2, the MUXR-1 is valid, the first switching transistor T1 is closed, the second switching transistor T1 'is valid, and the second switching transistor T1' responds to the MUXR-1 signal accessed by the control terminal to compensate the reduction of the data signal, namely the pixel voltage, caused by the closing of the first switching transistor T1; when the Gate signal Gate is invalid at the time T3, the MUXR-1 is continuously valid, and the second switching transistor T1' compensates the drop of the data signal, i.e., the pixel voltage, caused by the invalid Gate signal in response to the MUXR-1 signal accessed by the control terminal; when MUXR-1 is inactive at time T4, second switching transistor T1' is reset. As shown in fig. 7c, the second switching transistor T1' is equivalent to a variable capacitor, and compensates the pixel voltage transmitted to the red sub-pixel R1 in response to the input control signal MUXR-1.
In other words, in the present embodiment, the second switching transistor is disposed on the basis of the original first switching transistor, and the preset timing sequence is used to control the second switching transistor to be turned on to compensate for the data signal jitter caused by the turn-off of the first switching transistor and the invalidation of the Gate signal, so as to further keep the pixel voltage stable and improve the display effect.
In view of further stabilizing the pixel voltage, in an alternative embodiment, the aspect ratio of the first switching transistor is the same as the aspect ratio of the second switching transistor.
In this embodiment, the second switch transistor and the first switch transistor are set to be transistors with the same structure, so that the second switch transistor is used for compensating the first switch transistor, that is, the first switch transistor causes a large voltage drop of pixel voltage, and the second switch transistor compensates a large voltage, so that the pixel voltage of each sub-pixel is further stabilized, the display effect is improved, and the user experience is increased.
In a specific embodiment, taking the fabrication of the array substrate as an example for illustration, the method specifically includes the following steps:
in a first step, a first electrode layer is formed on the substrate.
In this embodiment, as shown in fig. 2, a first electrode layer 11 is first formed on a substrate 10, and the first electrode layer 11 of this embodiment is a common electrode.
And secondly, forming an insulating material layer on the first electrode layer.
And thirdly, patterning the insulating material layer to form an insulating layer, wherein the insulating layer comprises a plurality of insulating blocks arranged at intervals.
In this embodiment, as shown in fig. 2, an insulating material layer is formed on the common electrode 11, and then the insulating blocks 121 arranged at intervals are formed through a patterning operation. Specifically, the insulating material layer is etched by a dry etching process; for example, in the case of introducing a reaction gas into a reaction chamber under vacuum by using the Plasma principle, the generated atoms or active radical particles collide with the surface of the plated film to selectively remove the film, and dry etching is characterized by a high degree of orientation, for example, the side wall forming the insulating block shown in fig. 2 is almost vertical.
And fourthly, forming a second electrode layer on the insulating layer, wherein the second electrode layer comprises sub-electrodes formed on the insulating blocks, and the orthographic projections of the sub-electrodes on the substrate cover the orthographic projections of the corresponding insulating blocks on the substrate.
In the present embodiment, as shown in fig. 2, each sub-electrode 131 of a second electrode layer, which is a pixel electrode, is formed on the insulating block 121 through a mask plate, each sub-electrode is, for example, a stripe electrode of the pixel electrode, and the pixel electrode is insulated from the common electrode.
And fifthly, filling the insulating medium between the adjacent sub-electrodes and between the adjacent insulating blocks.
In this example, as shown in fig. 2, the array substrate formed as described above was filled with a PI solution.
Thus, the array substrate shown in fig. 2 is formed, and the transmittance of the array substrate is greatly improved compared with the array substrate using the whole insulating layer in the related art because the transmittance of the PI solution is greater than that of the insulating block; in addition, because the dielectric constant of the PI solution is greater than that of the insulating blocks, the storage capacitance of each pixel of the array substrate is effectively increased by the array substrate filled with the PI solution between the adjacent insulating blocks and the adjacent sub-electrodes, namely, the pixel storage capacitance is increased to improve the pixel voltage holding capacity, improve the display problem caused by unstable pixel voltage and improve the stability of the pixel voltage; furthermore, the PI solution is filled between the insulating blocks of the insulating layer, so that the precipitation of charged particles in the insulating layer can be eliminated, and the problem of residual images caused by the influence of the precipitated charged particles on the deflection of the liquid crystal in the film layer of the insulating layer is solved; the problems in the related art are effectively solved, and the overall display effect of the liquid crystal array substrate is improved.
In view of forming the sub-electrodes on the patterned insulating blocks, there is a strict requirement on the alignment accuracy of the mask plates of the sub-electrodes, i.e. alignment deviation is easily generated in the manufacturing process, and in an alternative embodiment, as shown in fig. 11, the method specifically includes:
in a first step, a first electrode layer is formed on the substrate.
In the present embodiment, as shown in fig. 2, a first electrode layer 11 is first formed on a substrate 10, and the first electrode layer 11 of the present embodiment is a common electrode.
And secondly, forming an insulating material layer on the first electrode layer.
And thirdly, forming a second electrode layer on the insulating material layer, wherein the second electrode layer comprises a plurality of sub-electrodes arranged at intervals.
In this embodiment, the second electrode layer is formed on the entire insulating material layer to reduce the requirement of the mask plate for manufacturing the sub-electrodes to the alignment precision, and the sub-electrodes 131 are formed at intervals, in which the sub-electrodes in this embodiment are made of ito.
And fourthly, patterning the insulating material layer to form an insulating layer, wherein the step of etching the insulating material layer by using the plurality of sub-electrodes as mask plates to form a plurality of insulating blocks, and the orthographic projections of the sub-electrodes on the substrate cover the orthographic projections of the corresponding insulating blocks on the substrate.
In this embodiment, since the main component of the sub-electrode is ito, the insulating material layer is not affected by dry etching, and the formed sub-electrode is further used as a mask for etching, and the mask alignment problem does not exist in this process, as shown in fig. 2, the insulating block 121 with the sidewall perpendicular to the common electrode is formed after etching.
And fifthly, filling the insulating medium between the adjacent sub-electrodes and between the adjacent insulating blocks.
In this example, as shown in fig. 2, the array substrate formed as described above was filled with a PI solution.
Thus, in the array substrate shown in fig. 2, since the sub-electrodes of the second electrode layer are formed on the entire insulating material layer, the requirement for alignment accuracy of the mask of the second electrode layer is eliminated, and the sub-electrodes of the second electrode layer are used as the mask to etch the insulating material layer, so that the insulating blocks of the insulator electrode and the common electrode can be formed more accurately.
In order to further improve the pixel voltage holding capability, after the corresponding sub-electrodes and insulating blocks are formed in the process of manufacturing the array substrate, the method further comprises the following steps:
and etching each insulating block of the insulating layer to enable the edge block to form a retraction structure on one side close to the insulating medium, wherein the orthographic projection area of the insulating medium between the adjacent insulating blocks on the substrate is larger than that of the insulating medium between the corresponding adjacent sub-electrodes on the substrate.
In this embodiment, no matter the insulating block is formed first and then each sub-electrode of the second electrode layer is formed, or each sub-electrode is etched to form the insulating block as a mask plate, after the shapes of the insulating block and the sub-electrode are formed, wet etching is continuously performed on the insulating block to form the insulating block with the retraction structure as shown in fig. 5, on one hand, the insulating block with the retraction structure ensures that each sub-electrode of the pixel electrode is insulated from the common electrode without short circuit, and simultaneously, more PI solutions are filled, so that the storage capacitance of each pixel is effectively increased to further stabilize the pixel voltage, and the overall display effect of the display substrate is improved.
In an alternative embodiment, as shown in fig. 7b, a driving circuit layer is formed on the substrate 10, the driving circuit layer includes a first switching transistor T1 and a second switching transistor T1' of a multiplexing circuit, the multiplexing circuit is connected to one data transmission line and is connected to at least three data lines, the first switching transistor T1 and the second switching transistor T1' each include a control terminal 24, a first terminal 26 and a second terminal 27, wherein the control terminal of the first switching transistor T1 is connected to a first control signal, the first terminal 27 of the first switching transistor T1 is connected to the data transmission line, the second terminal 26 of the first switching transistor T1 is connected to the first terminal 27 of the second switching transistor T1', the second terminal 26 of the second switching transistor T1' and the data line, and the first switching transistor T1 is connected to the data transmission line in response to an input first control signal and is transmitted to the data line through the first terminal of the second switching transistor T1 '; the control terminal 24 of the second switching transistor T1 'receives a second control signal, and the second switching transistor T1' compensates the received data signal in response to the received second control signal and transmits the compensated data signal to the data line.
In the present embodiment, a buffer layer 21 is formed on a substrate 10, a semiconductor material layer including an active layer 22 and a conductive auxiliary conductive layer 22' is formed on the buffer layer 21, a gate insulating layer 23 covering the active layer 22 and the auxiliary conductive layer 22' is formed, a gate electrode 24 is formed on the gate insulating layer 23, an interlayer dielectric layer 25 covering the gate electrode 24 and the exposed gate insulating layer, and source and drain electrodes, such as a source electrode 27 and a drain electrode 26, are formed on the interlayer dielectric layer 25, wherein the drain electrode 26 of the first switching transistor T1 is electrically connected to the source electrode 27 and the drain electrode 26 of the second switching transistor T1 '. In this embodiment, the first switch transistor and the second switch transistor are arranged, and the second switch transistor is controlled to be turned on according to a preset time sequence to compensate for data signal jitter caused by turning off the first switch transistor and invalidating the Gate signal, so that the pixel voltage is further kept stable, and the display effect is improved.
Corresponding to the array substrate provided in the foregoing embodiment, an embodiment of the present application further provides a manufacturing method for manufacturing the array substrate, which specifically includes: the array substrate comprises a substrate, and is characterized in that a first electrode layer, an insulating layer and a second electrode layer are formed on the substrate in a stacking mode, wherein the second electrode layer comprises a plurality of sub-electrodes arranged at intervals, the insulating layer comprises insulating blocks arranged in one-to-one correspondence with the sub-electrodes, orthographic projections of the sub-electrodes on the substrate cover orthographic projections of the corresponding insulating blocks on the substrate, and the array substrate further comprises insulating media filled between adjacent sub-electrodes and between adjacent insulating blocks.
Aiming at the problem that the transmittance is affected by covering the whole insulating layer on the opening area in the related art, in the embodiment, firstly, the insulating blocks are used for insulating the first electrode layer and the second electrode layer so as to ensure the normal operation of the array substrate, the insulating medium with the transmittance higher than that of the insulating blocks is filled between the adjacent insulating blocks so as to improve the transmittance of the array substrate, and the dielectric constant of the insulating medium is higher than that of the insulating blocks so as to further increase the storage capacitance of each pixel of the array substrate so as to ensure the stability of the pixel voltage, so that the problems in the related art can be solved. Since the manufacturing method provided by the embodiments of the present application corresponds to the array substrate provided by the above embodiments, the previous embodiments are also applicable to the manufacturing method provided by the present embodiment, and detailed description is not provided in the present embodiment.
In an optional embodiment, the forming of the first electrode layer, the insulating layer, and the second electrode layer on the substrate in a stack further comprises: forming a first electrode layer on the substrate; forming an insulating material layer on the first electrode layer; patterning the insulating material layer to form an insulating layer, wherein the insulating layer comprises a plurality of insulating blocks arranged at intervals; forming a second electrode layer on the insulating layer, wherein the second electrode layer comprises sub-electrodes formed on the insulating blocks, and the orthographic projections of the sub-electrodes on the substrate cover the orthographic projections of the corresponding insulating blocks on the substrate; and filling the insulating medium between the adjacent sub-electrodes and between the adjacent insulating blocks.
In the embodiment, the first electrode layer, the insulating block, the sub-electrodes of the second electrode layer and the filling insulating medium are sequentially formed to form the array substrate, so that the overall transmittance can be improved, and the pixel voltage can be stabilized. For the specific implementation, reference is made to the foregoing embodiments, which are not described in detail herein.
In another alternative embodiment, the forming of the first electrode layer, the insulating layer, and the second electrode layer stacked on the substrate further includes: forming a first electrode layer on the substrate; forming an insulating material layer on the first electrode layer; forming a second electrode layer on the insulating material layer, wherein the second electrode layer comprises a plurality of sub-electrodes arranged at intervals; patterning the insulating material layer to form an insulating layer, wherein the insulating material layer is etched by using the plurality of sub-electrodes as mask plates to form a plurality of insulating blocks, and the orthographic projections of the sub-electrodes on the substrate cover the orthographic projections of the corresponding insulating blocks on the substrate; and filling the insulating medium between the adjacent sub-electrodes and between the adjacent insulating blocks.
In the embodiment, each sub-electrode of the second electrode layer is formed on the whole insulating material layer, so that the requirement of alignment precision of a mask plate of the second electrode layer is eliminated, and meanwhile, the sub-electrodes of the second electrode layer are used as the mask plate to etch the insulating material layer, so that the insulating blocks of the insulator electrode and the common electrode can be formed more accurately. For specific implementation, reference is made to the foregoing embodiments, which are not described herein again.
In another optional embodiment, after forming the corresponding sub-electrodes and the insulating blocks, the manufacturing method further includes: and etching each insulating block of the insulating layer to form a retraction structure on one side of the edge block close to the insulating medium, wherein the orthographic projection area of the insulating medium between the adjacent insulating blocks on the substrate is larger than that of the insulating medium between the corresponding adjacent sub-electrodes on the substrate.
In this embodiment, the insulating block having the retraction structure is formed to ensure insulation between each sub-electrode of the pixel electrode and the common electrode and prevent short circuit, and more PI solution is filled, so that the storage capacitance of each pixel is effectively increased to further stabilize the pixel voltage, and the overall display effect of the display substrate is improved. For specific implementation, reference is made to the foregoing embodiments, which are not described herein again.
In order to further implement the narrow bezel design, in an optional embodiment, the forming a first electrode layer, an insulating layer, and a second electrode layer on the substrate in a stacking manner further includes: forming a driving circuit layer on the substrate, wherein the driving circuit layer comprises a first switching transistor and a second switching transistor of a multiplexing circuit, the multiplexing circuit is connected with one data transmission line and is connected with at least three data lines, the first switching transistor and the second switching transistor both comprise a control end, a first end and a second end, the control end of the first switching transistor is connected with a first control signal, the first end of the first switching transistor is connected with the data transmission line, the second end of the first switching transistor is connected with the first end of the second switching transistor, the second end of the second switching transistor is connected with the data line, and the first switching transistor is connected with a data signal transmitted by the data transmission line in response to an input first control signal and is transmitted to the data line through the first end of the second switching transistor; and the control end of the second switching transistor is connected with a second control signal, and the second switching transistor responds to the input second control signal to compensate the connected data signal and transmit the data signal to the data line.
In this embodiment, on one hand, the number of data transmission lines is reduced through the formed multiplexing circuit to realize a narrow frame design, and on the other hand, through the formed first switching transistor and the second switching transistor, the second switching transistor is controlled according to a preset time sequence to compensate for instability of a data signal caused by the first switching transistor, so that the pixel voltage is further kept stable, and the display effect is improved. For specific implementation, reference is made to the foregoing embodiments, which are not described herein again.
Based on the foregoing array substrate, another embodiment of the present invention provides a display panel, which includes the foregoing array substrate, and the display panel is a liquid crystal display panel, and can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, or a navigator.
Aiming at the existing problems, the invention provides an array substrate, a manufacturing method and a display panel, wherein the array substrate of one embodiment improves the transmittance of the array substrate by filling an insulating medium with a transmittance larger than that of an insulating block between adjacent insulating blocks on the basis of insulating a first electrode layer and a second electrode layer by using the insulating block to ensure the normal work of the array substrate, and further increases the storage capacitance of each pixel of the array substrate by using the insulating medium with a dielectric constant larger than that of the insulating block to ensure the stability of the pixel voltage, so that the problems in the related technology can be solved, and the array substrate has practical application value.
It should be understood that the above-described embodiments of the present invention are examples for clearly illustrating the invention, and are not to be construed as limiting the embodiments of the present invention, and it will be obvious to those skilled in the art that various changes and modifications can be made on the basis of the above description, and it is not intended to exhaust all embodiments, and obvious changes and modifications can be made on the basis of the technical solutions of the present invention.
Claims (12)
1. The array substrate is characterized by comprising a first electrode layer, an insulating layer and a second electrode layer which are stacked on a substrate, wherein the first electrode layer, the insulating layer and the second electrode layer are arranged on the substrate in a stacked mode
The second electrode layer comprises a plurality of sub-electrodes arranged at intervals;
the insulating layer comprises insulating blocks which are arranged in one-to-one correspondence with the sub-electrodes, and the orthographic projection of the sub-electrodes on the substrate covers the orthographic projection of the corresponding insulating blocks on the substrate;
the array substrate further comprises insulating media filled between the adjacent sub-electrodes and between the adjacent insulating blocks, the transmittance of the insulating media is greater than that of the insulating blocks, and the dielectric constant of the insulating media is greater than that of the insulating blocks.
2. The array substrate of claim 1, wherein the insulating block forms a retraction structure on a side close to the insulating medium;
the orthographic projection area of the insulating medium between the adjacent insulating blocks on the substrate is larger than that of the insulating medium between the corresponding adjacent sub-electrodes on the substrate.
3. The array substrate of claim 1 or 2, wherein the array substrate comprises a plurality of sub-pixels arranged in an array, a plurality of data lines connected to the sub-pixels in each column, a plurality of data lines for receiving input data signals, and a plurality of multiplexing circuits, each multiplexing circuit connected to one data line and connected to at least three data lines, wherein
And each multiplexing circuit transmits the data signals transmitted by the data transmission lines to the corresponding data lines in time slots according to a preset time sequence.
4. The array substrate of claim 3, wherein the multiplexing circuits comprise multiplexing sub-circuits in one-to-one correspondence with the connected data lines, each multiplexing sub-circuit comprising a first switching transistor connected to the corresponding data transmission line and a second switching transistor connected to the data line, wherein,
the first switch transistor responds to an input first control signal, accesses a data signal transmitted by the data transmission line and transmits the data signal to the data line through the second switch transistor;
the second switching transistor compensates the accessed data signal in response to an input second control signal and transmits the compensated data signal to the data line.
5. The array substrate of claim 4, wherein the first switch transistor and the second switch transistor each comprise a control terminal, a first terminal, and a second terminal, wherein
A control end of the first switch transistor is connected to the first control signal, a first end of the first switch transistor is connected with the data transmission line, and a second end of the first switch transistor is connected with a first end of the second switch transistor, a second end of the second switch transistor and the data line;
and the control end of the second switching transistor is connected to the second control signal.
6. The array substrate of claim 5, wherein the first switch transistor has a same length to width ratio as the second switch transistor.
7. A display panel comprising the array substrate according to any one of claims 1 to 6.
8. A method for fabricating the array substrate according to any one of claims 1 to 6, comprising:
the array substrate comprises a substrate, and is characterized in that a first electrode layer, an insulating layer and a second electrode layer are formed on the substrate in a stacking mode, wherein the second electrode layer comprises a plurality of sub-electrodes arranged at intervals, the insulating layer comprises insulating blocks arranged in one-to-one correspondence with the sub-electrodes, orthographic projections of the sub-electrodes on the substrate cover orthographic projections of the corresponding insulating blocks on the substrate, and the array substrate further comprises insulating media filled between adjacent sub-electrodes and between adjacent insulating blocks.
9. The method of claim 8, wherein the step of forming a first electrode layer, an insulating layer, and a second electrode layer on a substrate in a stacked manner further comprises:
forming a first electrode layer on the substrate;
forming an insulating material layer on the first electrode layer;
patterning the insulating material layer to form an insulating layer, wherein the insulating layer comprises a plurality of insulating blocks arranged at intervals;
forming a second electrode layer on the insulating layer, wherein the second electrode layer comprises sub-electrodes formed on the insulating blocks, and orthographic projections of the sub-electrodes on the substrate cover orthographic projections of the corresponding insulating blocks on the substrate;
and filling the insulating medium between the adjacent sub-electrodes and between the adjacent insulating blocks.
10. The method of claim 8, wherein the step of forming a first electrode layer, an insulating layer, and a second electrode layer on the substrate further comprises:
forming a first electrode layer on the substrate;
forming an insulating material layer on the first electrode layer;
forming a second electrode layer on the insulating material layer, wherein the second electrode layer comprises a plurality of sub-electrodes arranged at intervals;
patterning the insulating material layer to form an insulating layer, wherein the insulating material layer is etched by using the plurality of sub-electrodes as mask plates to form a plurality of insulating blocks, and the orthographic projections of the sub-electrodes on the substrate cover the orthographic projections of the corresponding insulating blocks on the substrate;
and filling the insulating medium between the adjacent sub-electrodes and between the adjacent insulating blocks.
11. The fabrication method according to any one of claims 8 to 10, further comprising, after forming the corresponding sub-electrodes and insulating blocks:
and etching each insulating block of the insulating layer to enable the edge block to form a retraction structure on one side close to the insulating medium, wherein the orthographic projection area of the insulating medium between the adjacent insulating blocks on the substrate is larger than that of the insulating medium between the corresponding adjacent sub-electrodes on the substrate.
12. The method of manufacturing according to claim 8, wherein the forming of the first electrode layer, the insulating layer, and the second electrode layer on the substrate in a stacked manner further comprises: forming a driving circuit layer on the substrate, wherein the driving circuit layer comprises a first switching transistor and a second switching transistor of a multiplexing circuit, the multiplexing circuit is connected with one data transmission line and is connected with at least three data lines, the first switching transistor and the second switching transistor both comprise a control end, a first end and a second end, and the first end and the second end are connected with the first end and the second end of the multiplexing circuit respectively
A control end of the first switching transistor is connected with a first control signal, a first end of the first switching transistor is connected with the data transmission line, a second end of the first switching transistor is connected with a first end of the second switching transistor, a second end of the second switching transistor and the data line, and the first switching transistor responds to the input first control signal, is connected with the data signal transmitted by the data transmission line and is transmitted to the data line through the first end of the second switching transistor;
and the control end of the second switching transistor is connected with a second control signal, and the second switching transistor responds to the input second control signal to compensate the connected data signal and transmit the data signal to the data line.
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Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030085406A1 (en) * | 2001-11-06 | 2003-05-08 | Jia-Shyong Cheng | Process for producing inductor |
| CN101625491A (en) * | 2008-07-11 | 2010-01-13 | 乐金显示有限公司 | Liquid crystal display device and method for fabricating the same |
| CN103488004A (en) * | 2013-09-26 | 2014-01-01 | 京东方科技集团股份有限公司 | Array substrate, liquid crystal panel and display device |
| CN103489922A (en) * | 2013-09-30 | 2014-01-01 | 京东方科技集团股份有限公司 | Thin film transistor and preparation method thereof, array substrate and preparation method thereof and display device |
| JP2014013312A (en) * | 2012-07-04 | 2014-01-23 | Mitsubishi Electric Corp | Liquid crystal display device and manufacturing method |
| CN103824865A (en) * | 2014-02-14 | 2014-05-28 | 京东方科技集团股份有限公司 | Array substrate, preparation method thereof and display device |
| CN104155814A (en) * | 2014-08-29 | 2014-11-19 | 昆山龙腾光电有限公司 | Liquid crystal display device and manufacturing method thereof |
| CN104698630A (en) * | 2015-03-30 | 2015-06-10 | 合肥京东方光电科技有限公司 | Array substrate and display device |
| CN104714343A (en) * | 2015-03-18 | 2015-06-17 | 昆山龙腾光电有限公司 | Fringe-field switching mode thin film transistor array substrate and manufacturing method thereof |
| CN105572980A (en) * | 2015-12-18 | 2016-05-11 | 武汉华星光电技术有限公司 | Liquid crystal display panel and pixel structure thereof |
| CN106647059A (en) * | 2017-01-04 | 2017-05-10 | 京东方科技集团股份有限公司 | Array substrate, display panel and manufacturing methods of array substrate and display panel |
| CN107219694A (en) * | 2017-07-28 | 2017-09-29 | 京东方科技集团股份有限公司 | A kind of array base palte and preparation method thereof, display device |
| US20190072796A1 (en) * | 2017-09-01 | 2019-03-07 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Organic thin film transistor having perpendicular channels in pixel structure and method for manufacturing same |
| CN111458940A (en) * | 2020-05-14 | 2020-07-28 | 京东方科技集团股份有限公司 | Display panel and display device |
-
2022
- 2022-11-15 CN CN202211423457.4A patent/CN115755470A/en active Pending
Patent Citations (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030085406A1 (en) * | 2001-11-06 | 2003-05-08 | Jia-Shyong Cheng | Process for producing inductor |
| CN101625491A (en) * | 2008-07-11 | 2010-01-13 | 乐金显示有限公司 | Liquid crystal display device and method for fabricating the same |
| JP2010020277A (en) * | 2008-07-11 | 2010-01-28 | Lg Display Co Ltd | Liquid crystal display device, and method of manufacturing the same |
| JP2014013312A (en) * | 2012-07-04 | 2014-01-23 | Mitsubishi Electric Corp | Liquid crystal display device and manufacturing method |
| CN103488004A (en) * | 2013-09-26 | 2014-01-01 | 京东方科技集团股份有限公司 | Array substrate, liquid crystal panel and display device |
| CN103489922A (en) * | 2013-09-30 | 2014-01-01 | 京东方科技集团股份有限公司 | Thin film transistor and preparation method thereof, array substrate and preparation method thereof and display device |
| CN103824865A (en) * | 2014-02-14 | 2014-05-28 | 京东方科技集团股份有限公司 | Array substrate, preparation method thereof and display device |
| CN104155814A (en) * | 2014-08-29 | 2014-11-19 | 昆山龙腾光电有限公司 | Liquid crystal display device and manufacturing method thereof |
| CN104714343A (en) * | 2015-03-18 | 2015-06-17 | 昆山龙腾光电有限公司 | Fringe-field switching mode thin film transistor array substrate and manufacturing method thereof |
| CN104698630A (en) * | 2015-03-30 | 2015-06-10 | 合肥京东方光电科技有限公司 | Array substrate and display device |
| CN105572980A (en) * | 2015-12-18 | 2016-05-11 | 武汉华星光电技术有限公司 | Liquid crystal display panel and pixel structure thereof |
| WO2017101185A1 (en) * | 2015-12-18 | 2017-06-22 | 武汉华星光电技术有限公司 | Liquid crystal panel and pixel structure thereof |
| CN106647059A (en) * | 2017-01-04 | 2017-05-10 | 京东方科技集团股份有限公司 | Array substrate, display panel and manufacturing methods of array substrate and display panel |
| US20180188623A1 (en) * | 2017-01-04 | 2018-07-05 | Boe Technology Group Co., Ltd. | Array substrate, display panel, display device and method of manufacturing the same |
| CN107219694A (en) * | 2017-07-28 | 2017-09-29 | 京东方科技集团股份有限公司 | A kind of array base palte and preparation method thereof, display device |
| WO2019019610A1 (en) * | 2017-07-28 | 2019-01-31 | 京东方科技集团股份有限公司 | Array substrate and method for manufacturing same, and display device |
| US20190072796A1 (en) * | 2017-09-01 | 2019-03-07 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Organic thin film transistor having perpendicular channels in pixel structure and method for manufacturing same |
| CN111458940A (en) * | 2020-05-14 | 2020-07-28 | 京东方科技集团股份有限公司 | Display panel and display device |
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