CN115754971A - Radar data acquisition and storage method and system based on discrete DMA technology - Google Patents
Radar data acquisition and storage method and system based on discrete DMA technology Download PDFInfo
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Abstract
The invention discloses a radar data acquisition and storage method and system based on a discrete DMA (direct memory access) technology, and belongs to the technical field of radar signal processing. Generating radar data and storing descriptors of all the subdata segments through FIFO; the upper computer controls the two channels of the DMA to sequentially perform time-first storage and channel-first storage on the descriptor to obtain a target storage structure which is stored through FIFO; and combining all the descriptors with the corresponding sub-data segments to obtain target storage data, and discretely storing the target storage data through FIFO according to a target storage structure. The upper computer is used as an initiator of transmission transactions, the two channels of the DMA are controlled to realize tree structure discrete storage of multichannel radar data, the access mechanism of the DMA is fundamentally changed, the dependence on the memory is greatly reduced, the transmission rate is increased, the communication bandwidth and efficiency are improved, and the data are transmitted through the asynchronous FIFO, so that the problems of packet loss and error codes caused by asynchronous transmission among different modules can be effectively solved.
Description
Technical Field
The invention relates to the technical field of radar signal processing, in particular to a radar data acquisition and storage method and system based on a discrete DMA (direct memory access) technology.
Background
The radar imaging technology is developed rapidly, the real-time imaging speed is higher and higher, and the real-time imaging precision is higher and higher; the phased array radar system comprises a plurality of data channels, and data transmission of the channels is carried out simultaneously, so that the multichannel radar is high in acquisition speed, large in data volume and vital in real-time storage.
Patent document CN113611102A discloses a method for transmitting multi-channel radar echo signals based on FPGA, which alleviates the technical problems of low data transmission rate of radar signals, uncontrollable data sending frequency, incompatible device interfaces, and the like
The traditional radar data storage mode in the prior art has the defects that the system performance is unstable due to the fact that the transmission rate is low, massive data exist in large-capacity on-chip cache, the efficiency is low, time sequence problems or mistransmission often occur, and the data storage requirements of a multi-channel radar are difficult to meet.
Disclosure of Invention
The present invention aims to solve the problems of the background art, and provides a method and a system for radar data acquisition and storage based on a discrete DMA technique.
The purpose of the invention can be realized by the following technical scheme:
in a first aspect of the embodiments of the present invention, a method for acquiring and storing radar data based on a discrete DMA technology is provided, where the method includes:
generating radar data according to echo signals acquired by a multi-channel radar, storing the radar data into a first cache unit through a first asynchronous FIFO, and generating a first descriptor of each sub data segment of the radar data; the first descriptor includes metadata and a location pointer for each sub data segment;
sequentially performing time-first storage (TFS) and channel-first storage (CFS) on the first descriptor of each subdata segment of the radar data through a dual channel of a host computer (host computer) control Direct Memory Access (DMA), so as to obtain a target storage structure, and storing the target storage structure in a second cache unit through a second asynchronous first-in first-out (FIFO); the first layer of the target storage structure is a root node, the second layer is a time node, the third layer is a channel node, and the storage nodes of all the subdata segments are leaf nodes;
reading each first descriptor to obtain a corresponding subdata segment in the first cache unit, and combining all the first descriptors with the corresponding subdata segments to obtain target storage data;
and performing discrete storage on each sub-data segment of the target storage data through a third asynchronous FIFO according to the target storage structure.
Optionally, generating radar data according to an echo signal collected by the multichannel radar, and storing the radar data in the first buffer unit through the first asynchronous FIFO, includes:
performing photoelectric conversion on echo signals acquired by a multi-channel radar to obtain binary echo data;
adding corresponding time tags and channel tags in each subdata segment of the binary echo data to obtain radar data, and storing the radar data into a first cache unit through a first asynchronous FIFO; the sub-data segment time labels collected in the same time period are the same, and the sub-data segment channel labels collected in the same channel are the same.
Optionally, the step of sequentially performing time-first storage TFS and channel-first storage CFS on the first descriptor of each sub-data segment of the radar data through a dual channel of a DMA controlled by an upper computer, to obtain a target storage structure, and storing the target storage structure into a second cache unit through a second asynchronous FIFO includes:
controlling a first channel of the DMA through an upper computer to perform time-first storage TFS according to the acquisition time node of each subdata segment recorded by the first descriptor, and storing the obtained first storage structure in a third cache unit through a fourth asynchronous FIFO;
and controlling a second channel of the DMA through the upper computer, and performing channel priority storage CFS according to the subdata segments of the same acquisition time node on the basis of the first storage structure to obtain a target storage structure which is stored in a second cache unit through a second asynchronous FIFO.
Optionally, before discretely storing each sub-data segment of the target storage data through a third asynchronous FIFO according to the target storage structure, the method further includes:
creating a time array and a channel array to generate an adjacency list; the lengths of the time array and the channel array are respectively the same as the types of the time labels and the channel labels of the subdata segments in the target storage data;
and connecting the addresses of the time array and the channel array according to the position pointer of each subdata segment, and updating the position pointer to enable the storage structure of the adjacency list to be the target storage structure.
Optionally, after discretely storing each sub-data segment of the target storage data through a third asynchronous FIFO according to the target storage structure, the method further includes;
respectively generating a second descriptor, a third descriptor and a fourth descriptor of the root node, the time node and the channel node, and storing the second descriptor, the third descriptor and the fourth descriptor in each node position; the second descriptor comprises the number of time nodes, the data volume of the target storage data and a tree number; the third descriptor comprises the number of channel nodes, the total stored data volume under the time node and a node number; the fourth descriptor includes the number of leaf nodes, the total data storage amount under the channel node, and a node number.
In a second aspect of the embodiments of the present invention, a radar data acquisition and storage system based on a discrete DMA technology is further provided, where the system includes a data acquisition module, a DMA module, a first cache unit, a second cache unit, a first asynchronous FIFO, a second asynchronous FIFO, a third asynchronous FIFO, a combination module, and a storage module; wherein:
the data acquisition module is used for generating radar data according to echo signals acquired by a multi-channel radar, storing the radar data into a first cache unit through a first asynchronous FIFO, and generating first descriptors of all subdata segments of the radar data; the first descriptor includes metadata and a location pointer for each sub data segment;
the DMA module is used for sequentially performing time-first storage (TFS) and channel-first storage (CFS) on the first descriptors of the sub-data segments of the radar data through a dual channel of the upper computer for controlling DMA, so as to obtain a target storage structure which is stored in a second cache unit through a second asynchronous FIFO; the first layer of the target storage structure is a root node, the second layer is a time node, the third layer is a channel node, and the storage nodes of all the subdata segments are leaf nodes;
the combination module is used for reading each first descriptor to obtain a corresponding subdata segment in the first cache unit, and combining all the first descriptors with the corresponding subdata segments to obtain target storage data;
and the storage module is used for discretely storing each subdata segment of the target storage data through a third asynchronous FIFO according to the target storage structure.
Optionally, the data acquisition module comprises a photoelectric conversion module and a tag insertion module, wherein:
the photoelectric conversion module is used for performing photoelectric conversion on echo signals acquired by the multi-channel radar to obtain binary echo data;
the tag insertion module is used for adding corresponding time tags and channel tags in each subdata segment of the binary echo data to obtain radar data, and storing the radar data into a first cache unit through a first asynchronous FIFO; the sub data segment time labels collected in the same time segment are the same, and the sub data segment channel labels collected in the same channel are the same.
Optionally, the DMA module includes an upper computer, a first channel and a second channel; the system also comprises a third cache unit and a fourth asynchronous FIFO; wherein
The upper computer is used for controlling the first channel to perform time-first storage TFS according to the acquisition time node of each subdata segment recorded by the first descriptor, and the obtained first storage structure is stored in the third cache unit through the fourth asynchronous FIFO;
and the upper computer is also used for controlling the second channel to perform channel priority storage CFS according to the subdata segments of the same acquisition time node on the basis of the first storage structure, so that the obtained target storage structure is stored in a second cache unit through a second asynchronous FIFO.
Optionally, the system further includes an adjacency list generation module and a connection module:
the adjacency list generating module is used for creating a time array and a channel array to generate an adjacency list; the lengths of the time array and the channel array are respectively the same as the types of the time labels and the channel labels of the subdata segments in the target storage data;
and the connecting module is used for connecting the addresses of the time array and the channel array according to the position pointer of each subdata segment, updating the position pointer and enabling the storage structure of the adjacency list to be the target storage structure.
Optionally, the system further comprises a descriptor generation module;
the descriptor generation module is used for respectively generating a second descriptor, a third descriptor and a fourth descriptor of a root node, a time node and a channel node and storing the second descriptor, the third descriptor and the fourth descriptor to each node position; the second descriptor comprises the number of time nodes, the data volume of the target storage data and a tree number; the third descriptor comprises the number of channel nodes, the total stored data volume under the time node and a node number; the fourth descriptor includes the number of leaf nodes, the total data storage amount under the channel node, and the node number.
In a third aspect of the embodiments of the present invention, an electronic device is further provided, including a processor, a communication interface, a memory, and a communication bus, where the processor and the communication interface complete communication between the memory and the processor through the communication bus;
a memory for storing a computer program;
and the processor is used for realizing the steps of the method when executing the program stored in the memory.
In a fourth aspect of the embodiments of the present invention, a computer-readable storage medium is further provided, in which a computer program is stored, and the computer program, when being executed by a processor, implements the method steps described above.
The invention has the beneficial effects that:
the embodiment of the invention provides a radar data acquisition and storage method based on a discrete DMA (direct memory access) technology, which comprises the steps of generating radar data according to echo signals acquired by a multi-channel radar, storing the radar data into a first cache unit through a first asynchronous FIFO (first-in-first-out) and generating a first descriptor of each sub-data segment of the radar data; the first descriptor includes metadata and a location pointer for each sub data segment; sequentially performing time-first storage TFS and channel-first storage CFS on the first descriptor of each subdata segment of the radar data through a dual channel of the host computer controlling the DMA to obtain a target storage structure, and storing the target storage structure in a second cache unit through a second asynchronous FIFO; the first layer of the target storage structure is a root node, the second layer is a time node, the third layer is a channel node, and the storage nodes of all the subdata segments are leaf nodes; reading each first descriptor to obtain a corresponding subdata segment in the first cache unit, and combining all the first descriptors with the corresponding subdata segments to obtain target storage data; performing discrete storage on each subdata segment of the target storage data through a third asynchronous FIFO according to a target storage structure; the upper computer is used as an initiator of transmission transactions, the dual channels of the DMA are controlled to realize the tree structure discrete storage of the multichannel radar data, the access mechanism of the DMA is fundamentally changed, the dependence on the memory is greatly reduced, the transmission rate is improved, the communication bandwidth and the efficiency are improved, the data are transmitted through the asynchronous FIFO, and the problems of packet loss and error codes caused by asynchronous transmission among different modules can be effectively solved.
Drawings
The invention will be further described with reference to the accompanying drawings.
Fig. 1 is a flowchart of a radar data acquisition and storage method based on a discrete DMA technique according to an embodiment of the present invention;
fig. 2 is a system block diagram of a radar data acquisition and storage method based on a discrete DMA technique according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments; all other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides a radar data acquisition and storage method based on a discrete DMA technology, referring to fig. 1, fig. 1 is a flowchart of a radar data acquisition and storage method based on a discrete DMA technology provided in an embodiment of the present invention; the method comprises the following steps:
s101, radar data are generated according to echo signals collected by the multichannel radar and stored in a first cache unit through a first asynchronous FIFO, and first descriptors of sub data segments of the radar data are generated.
And S102, sequentially performing time-first storage (TFS) and channel-first storage (CFS) on the first descriptors of the sub-data segments of the radar data through the two channels of the upper computer control Direct Memory Access (DMA), so as to obtain a target storage structure, and storing the target storage structure in a second cache unit through a second asynchronous FIFO.
S103, reading each first descriptor to obtain a corresponding subdata segment in the first cache unit, and combining all the first descriptors with the corresponding subdata segments to obtain target storage data;
and S104, discretely storing each sub-data segment of the target storage data through a third asynchronous FIFO according to a target storage structure.
The first descriptor includes metadata and a location pointer for each sub data segment; the first layer of the target storage structure is a root node, the second layer is a time node, the third layer is a channel node, and the storage nodes of all the subdata segments are leaf nodes.
According to the radar data acquisition and storage method based on the discrete DMA technology, provided by the embodiment of the invention, the tree structure storage of multi-channel radar data is realized through the two channels of the DMA, the communication bandwidth and efficiency are improved, and the data are transmitted through the asynchronous FIFO, so that the problems of packet loss and error codes caused by asynchronous transmission among different modules can be effectively solved.
In one implementation, the TFS method preferentially stores data collected by each channel at the same detection time; the CFS method preferentially stores data acquired by the same detection channel at different detection times; by combining two data traversal methods, the storage of the radar data in a tree structure is realized.
In one implementation, radar data is stored in a tree structure, the data can be effectively classified and sorted, each storage node has a unique address, subtrees are independent of one another, and the operations of the subtrees are not affected by one another.
In one implementation, data reading and writing are performed in a descriptor (descriptors) manner, the downlink data adopts a write descriptor, the uplink data adopts a read descriptor, and a conventional transmission manner (source address + target address + length) of the traditional DMA is changed; the full duplex link in the true sense is realized by read-write descriptor separation.
Compared with the traditional DMA mode, the host computer needs to open up a storage space which is at least equal to or larger than the data to be transmitted in advance, so that the use efficiency of the memory resource is reduced to a certain extent; the descriptor uses the concept of a linked list, and the memory space is divided without pre-opening, namely, the descriptor is used after being transmitted; and the use of discrete memories is supported, large-batch data does not need to be stored in the whole memory space, and the use efficiency can be improved by utilizing fragmented memories.
In one embodiment, step S101 includes:
performing photoelectric conversion on echo signals acquired by a multi-channel radar to obtain binary echo data;
adding corresponding time tags and channel tags in each sub-data segment of the binary echo data to obtain radar data, and storing the radar data into a first cache unit through a first asynchronous FIFO; the sub-data segment time labels collected in the same time period are the same, and the sub-data segment channel labels collected in the same channel are the same.
In one embodiment, step S102 includes:
step one, a first channel of a DMA is controlled by an upper computer to perform time-first storage TFS according to acquisition time nodes of all sub-data segments recorded by a first descriptor, and a first storage structure is obtained and stored in a third cache unit through a fourth asynchronous FIFO;
and step two, controlling a second channel of the DMA through the upper computer, performing channel priority storage CFS according to the subdata segments of the same acquisition time node on the basis of the first storage structure, and storing the obtained target storage structure into a second cache unit through a second asynchronous FIFO.
In one embodiment, before step S104, the method further comprises:
step one, creating a time array and a channel array to generate an adjacency list; the lengths of the time array and the channel array are respectively the same as the types of the time labels and the channel labels of each subdata segment in the target storage data;
and step two, connecting the addresses of the time array and the channel array according to the position pointer of each subdata segment, and updating the position pointer to enable the storage structure of the adjacency list to be a target storage structure.
In one implementation mode, the adjacency list is a shared storage mode of a graph, and an adjacency list structure is adopted to represent a tree structure of multi-channel radar data; nodes of a tree structure can be quickly retrieved through subscripts of the adjacency list array and addresses of the linked list, and multichannel radar data can be quickly inquired.
In one embodiment, after step S104, the method further comprises:
respectively generating a second descriptor, a third descriptor and a fourth descriptor of the root node, the time node and the channel node, and storing the second descriptor, the third descriptor and the fourth descriptor in each node position; the second descriptor comprises the number of time nodes, the data volume of target storage data and a tree number; the third descriptor comprises the number of channel nodes, the total stored data volume under the time node and a node number; the fourth descriptor includes the number of leaf nodes, the total data amount stored under the channel node, and the node number.
Based on the same inventive concept, an embodiment of the present invention provides a radar data acquisition and storage system based on a discrete DMA technology, referring to fig. 2, fig. 2 is a system block diagram of a radar data acquisition and storage method based on a discrete DMA technology according to an embodiment of the present invention; the system comprises a data acquisition module, a DMA module, a first cache unit, a second cache unit, a first asynchronous FIFO, a second asynchronous FIFO, a third asynchronous FIFO, a combination module and a storage module; wherein:
the data acquisition module is used for generating radar data according to echo signals acquired by the multichannel radar, storing the radar data into the first cache unit through the first asynchronous FIFO and generating first descriptors of sub-data segments of the radar data; the first descriptor comprises metadata and a position pointer of each subdata segment;
the DMA module is used for controlling the DMA double channels through the upper computer to sequentially perform time-first storage (TFS) and channel-first storage (CFS) on the first descriptors of the sub-data segments of the radar data, so that a target storage structure is obtained and stored in the second cache unit through the second asynchronous FIFO; the first layer of the target storage structure is a root node, the second layer is a time node, the third layer is a channel node, and the storage nodes of all the subdata segments are leaf nodes;
the combination module is used for reading each first descriptor to obtain a corresponding subdata segment in the first cache unit, and combining all the first descriptors with the corresponding subdata segments to obtain target storage data;
and the storage module is used for discretely storing each subdata segment of the target storage data through the third asynchronous FIFO according to the target storage structure.
According to the radar data acquisition and storage method based on the discrete DMA technology, the tree structure storage of the multi-channel radar data is realized through the double channels of the DMA, the communication bandwidth and the efficiency are improved, the data are transmitted through the asynchronous FIFO, and the problems of packet loss and error codes caused by asynchronous transmission among different modules can be effectively solved.
In one embodiment, the data acquisition module comprises a photoelectric conversion module and a tag insertion module, wherein:
the photoelectric conversion module is used for performing photoelectric conversion on the echo signals acquired by the multi-channel radar to obtain binary echo data;
the tag insertion module is used for adding corresponding time tags and channel tags in each sub-data segment of the binary echo data to obtain radar data and storing the radar data into the first cache unit through the first asynchronous FIFO; the sub data segment time labels collected in the same time segment are the same, and the sub data segment channel labels collected in the same channel are the same.
In one embodiment, the DMA module comprises an upper computer, a first channel and a second channel; the system also comprises a third cache unit and a fourth asynchronous FIFO; wherein
The upper computer is used for controlling the first channel to perform time-first storage TFS according to the acquisition time node of each subdata segment recorded by the first descriptor, and the obtained first storage structure is stored in the third cache unit through the fourth asynchronous FIFO;
and the upper computer is also used for controlling the second channel to perform channel priority storage CFS according to the subdata segments of the same acquisition time node on the basis of the first storage structure, so that the obtained target storage structure is stored in the second cache unit through the second asynchronous FIFO.
In one embodiment, the system further comprises an adjacency list generation module and a connection module:
the adjacency list generating module is used for creating a time array and a channel array to generate an adjacency list; the lengths of the time array and the channel array are respectively the same as the types of the time labels and the channel labels of each subdata segment in the target storage data;
and the connecting module is used for connecting the addresses of the time array and the channel array according to the position pointer of each subdata segment, updating the position pointer and enabling the storage structure of the adjacency list to be a target storage structure.
In one embodiment, the system further comprises a header information generation module;
the descriptor generation module is used for respectively generating a second descriptor, a third descriptor and a fourth descriptor of the root node, the time node and the channel node and storing the second descriptor, the third descriptor and the fourth descriptor to each node position; the second descriptor comprises the number of time nodes, the data volume of target storage data and a tree number; the third descriptor comprises the number of channel nodes, the total stored data volume under the time node and a node number; the fourth descriptor includes the number of leaf nodes, the total data amount stored under the channel node, and the node number.
The embodiment of the present invention further provides an electronic device, as shown in fig. 3, which includes a processor 301, a communication interface 302, a memory 303, and a communication bus 304, where the processor 301, the communication interface 302, and the memory 303 complete mutual communication through the communication bus 304,
a memory 303 for storing a computer program;
the processor 301, when executing the program stored in the memory 303, implements the following steps:
generating radar data according to echo signals acquired by a multi-channel radar, storing the radar data into a first cache unit through a first asynchronous FIFO, and generating a first descriptor of each sub data segment of the radar data; the first descriptor includes metadata and a location pointer for each sub data segment;
sequentially performing time-first storage (TFS) and channel-first storage (CFS) on the first descriptor of each subdata segment of the radar data through a dual channel of a host computer (host computer) control Direct Memory Access (DMA), so as to obtain a target storage structure, and storing the target storage structure in a second cache unit through a second asynchronous first-in first-out (FIFO); the first layer of the target storage structure is a root node, the second layer is a time node, the third layer is a channel node, and the storage nodes of all the subdata segments are leaf nodes;
reading each first descriptor to obtain a corresponding subdata segment in the first cache unit, and combining all the first descriptors with the corresponding subdata segments to obtain target storage data;
and performing discrete storage on each sub data segment of the target storage data through a third asynchronous FIFO according to the target storage structure.
The communication bus mentioned in the electronic device may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus; the communication bus can be divided into an address bus, a data bus, a control bus and the like; for ease of illustration, only one thick line is shown, but this does not mean that there is only one bus or one type of bus.
The communication interface is used for communication between the electronic equipment and other equipment.
The Memory may include a Random Access Memory (RAM) or a Non-Volatile Memory (NVM), such as at least one disk Memory; optionally, the memory may also be at least one memory device located remotely from the processor.
The Processor may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but also Digital Signal Processors (DSPs), application Specific Integrated Circuits (ASICs), field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components.
In yet another embodiment of the present invention, a computer-readable storage medium is further provided, in which a computer program is stored, and the computer program, when executed by a processor, implements the steps of any of the above-mentioned radar data acquisition and storage methods based on discrete DMA technology.
In yet another embodiment of the present invention, there is also provided a computer program product containing instructions, which when run on a computer, causes the computer to execute any of the above-mentioned radar data acquisition and storage methods based on discrete DMA technology.
In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof; when implemented in software, may be implemented in whole or in part in the form of a computer program product; the computer program product includes one or more computer instructions; when loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the invention to occur, in whole or in part; the computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device; the computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, e.g., the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wire (e.g., coaxial cable, fiber optic, digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.); the computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that includes one or more of the available media; the usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid State Disk (SSD)), among others.
It is to be noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions; also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus; without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.
All the embodiments in the specification are described in a related manner, and the same and similar parts among the embodiments can be referred to each other, and each embodiment is mainly described as different from other embodiments; in particular, for the apparatus, the electronic device, and the computer-readable storage medium, and the computer program product embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and in relation to them, reference may be made to the partial description of the method embodiments.
While one embodiment of the present invention has been described in detail, the description is only a preferred embodiment of the present invention and should not be taken as limiting the scope of the invention; all equivalent changes and modifications made within the scope of the present invention shall fall within the scope of the present invention.
Claims (10)
1. A radar data acquisition and storage method based on a discrete DMA technology is characterized by comprising the following steps:
generating radar data according to echo signals acquired by a multi-channel radar, storing the radar data into a first cache unit through a first asynchronous FIFO, and generating a first descriptor of each sub data segment of the radar data; the first descriptor comprises metadata and a position pointer of each subdata segment;
sequentially performing time-first storage (TFS) and channel-first storage (CFS) on the first descriptors of the sub-data segments of the radar data through a dual channel of a host computer controlling a Direct Memory Access (DMA), so as to obtain a target storage structure, and storing the target storage structure into a second cache unit through a second asynchronous first-in first-out (FIFO); the first layer of the target storage structure is a root node, the second layer is a time node, the third layer is a channel node, and the storage nodes of all the subdata segments are leaf nodes;
reading each first descriptor to obtain a corresponding subdata segment in the first cache unit, and combining all the first descriptors with the corresponding subdata segments to obtain target storage data;
and performing discrete storage on each sub data segment of the target storage data through a third asynchronous FIFO according to the target storage structure.
2. The method for acquiring and storing radar data based on the discrete DMA technology according to claim 1, wherein the radar data generated according to the echo signals acquired by the multichannel radar is stored in the first buffer unit through the first asynchronous FIFO, and the method comprises:
performing photoelectric conversion on echo signals acquired by a multi-channel radar to obtain binary echo data;
adding corresponding time tags and channel tags in each sub-data segment of the binary echo data to obtain radar data, and storing the radar data into a first cache unit through a first asynchronous FIFO; the sub-data segment time labels collected in the same time period are the same, and the sub-data segment channel labels collected in the same channel are the same.
3. The method of claim 2, wherein the obtaining of the target storage structure by sequentially performing time-first storage TFS and channel-first storage CFS on the first descriptor of each sub-data segment of the radar data through a dual channel of the upper computer controlling DMA to store the target storage structure in the second cache unit through the second asynchronous FIFO comprises:
controlling a first channel of the DMA through an upper computer to perform time-first storage TFS according to the acquisition time node of each subdata segment recorded by the first descriptor, and storing the obtained first storage structure in a third cache unit through a fourth asynchronous FIFO;
and on the basis of the first storage structure, a second channel of the DMA is controlled by the upper computer, and the CFS is preferentially stored in the channel according to the subdata segments of the same acquisition time node, so that the obtained target storage structure is stored in a second cache unit through a second asynchronous FIFO.
4. The method for collecting and storing radar data based on the discrete DMA technology as claimed in claim 3, wherein before the sub-data segments of the target storage data are discretely stored through a third asynchronous FIFO according to the target storage structure, the method further comprises:
creating a time array and a channel array to generate an adjacency list; the lengths of the time array and the channel array are respectively the same as the types of the time labels and the channel labels of the subdata segments in the target storage data;
and connecting the addresses of the time array and the channel array according to the position pointer of each subdata segment, and updating the position pointer to enable the storage structure of the adjacency list to be the target storage structure.
5. The radar data acquisition and storage method based on the discrete DMA technology as claimed in claim 4, wherein after the sub-data segments of the target storage data are discretely stored through a third asynchronous FIFO according to the target storage structure, the method further comprises;
respectively generating a second descriptor, a third descriptor and a fourth descriptor of the root node, the time node and the channel node, and storing the second descriptor, the third descriptor and the fourth descriptor to the positions of all nodes; the second descriptor comprises the number of time nodes, the data volume of the target storage data and a tree number; the third descriptor comprises the number of channel nodes, the total data storage amount under the time node and a node number; the fourth descriptor includes the number of leaf nodes, the total data storage amount under the channel node, and the node number.
6. A radar data acquisition and storage system based on a discrete DMA technology is characterized by comprising a data acquisition module, a DMA module, a first cache unit, a second cache unit, a first asynchronous FIFO, a second asynchronous FIFO, a third asynchronous FIFO, a combination module and a storage module; wherein:
the data acquisition module is used for generating radar data according to echo signals acquired by a multi-channel radar, storing the radar data into a first cache unit through a first asynchronous FIFO and generating a first descriptor of each subdata segment of the radar data; the first descriptor includes metadata and a location pointer for each sub data segment;
the DMA module is used for sequentially performing time-first storage (TFS) and channel-first storage (CFS) on the first descriptors of the sub-data segments of the radar data through a dual channel of the upper computer for controlling DMA, so as to obtain a target storage structure which is stored in a second cache unit through a second asynchronous FIFO; the first layer of the target storage structure is a root node, the second layer is a time node, the third layer is a channel node, and the storage nodes of all the subdata segments are leaf nodes;
the combination module is used for reading each first descriptor to obtain a corresponding subdata segment in the first cache unit, and combining all the first descriptors with the corresponding subdata segments to obtain target storage data;
and the storage module is used for discretely storing each subdata segment of the target storage data through a third asynchronous FIFO according to the target storage structure.
7. The radar data acquisition and storage system based on the discrete DMA technology as claimed in claim 6, wherein the data acquisition module comprises a photoelectric conversion module and a tag insertion module, and wherein:
the photoelectric conversion module is used for performing photoelectric conversion on echo signals acquired by the multi-channel radar to obtain binary echo data;
the tag insertion module is used for adding corresponding time tags and channel tags in each subdata segment of the binary echo data to obtain radar data, and storing the radar data into a first cache unit through a first asynchronous FIFO; the sub data segment time labels collected in the same time segment are the same, and the sub data segment channel labels collected in the same channel are the same.
8. The radar data acquisition and storage system based on the discrete DMA technology as claimed in claim 7, wherein the DMA module comprises an upper computer, a first channel and a second channel; the system also comprises a third cache unit and a fourth asynchronous FIFO; wherein
The upper computer is used for controlling the first channel to perform time-first storage TFS according to the acquisition time node of each subdata segment recorded by the first descriptor to obtain a first storage structure and store the first storage structure into a third cache unit through a fourth asynchronous FIFO;
and the upper computer is also used for controlling the second channel to perform channel priority storage CFS according to the subdata segments of the same acquisition time node on the basis of the first storage structure, so that the obtained target storage structure is stored in a second cache unit through a second asynchronous FIFO.
9. The radar data acquisition and storage system based on the discrete DMA technology as claimed in claim 8, wherein the system further comprises an adjacency list generation module and a connection module:
the adjacency list generating module is used for creating a time array and a channel array to generate an adjacency list; the lengths of the time array and the channel array are respectively the same as the types of the time labels and the channel labels of the subdata segments in the target storage data;
and the connecting module is used for connecting the addresses of the time array and the channel array according to the position pointer of each subdata segment, and updating the position pointer to enable the storage structure of the adjacency list to be the target storage structure.
10. The radar data acquisition and storage system based on the discrete DMA technology as claimed in claim 9, wherein the system further comprises a descriptor generation module;
the descriptor generation module is used for respectively generating a second descriptor, a third descriptor and a fourth descriptor of a root node, a time node and a channel node and storing the second descriptor, the third descriptor and the fourth descriptor to each node position; the second descriptor comprises the number of time nodes, the data volume of the target storage data and a tree number; the third descriptor comprises the number of channel nodes, the total stored data volume under the time node and a node number; the fourth descriptor includes the number of leaf nodes, the total data storage amount under the channel node, and the node number.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5302956A (en) * | 1992-08-14 | 1994-04-12 | Vorad Safety Systems, Inc. | Multi-frequency, multi-target vehicular radar system using digital signal processing |
| US5835788A (en) * | 1996-09-18 | 1998-11-10 | Electronics For Imaging | System for transferring input/output data independently through an input/output bus interface in response to programmable instructions stored in a program memory |
| US6026443A (en) * | 1992-12-22 | 2000-02-15 | Sun Microsystems, Inc. | Multi-virtual DMA channels, multi-bandwidth groups, host based cellification and reassembly, and asynchronous transfer mode network interface |
| US20030110325A1 (en) * | 2001-12-10 | 2003-06-12 | Bradley Roach | Direct memory access (DMA) transfer buffer processor |
| CN101178434A (en) * | 2007-02-02 | 2008-05-14 | 上海易罗信息科技有限公司 | Radar data collection system and collection method thereof |
| CN109766296A (en) * | 2019-01-08 | 2019-05-17 | 郑州云海信息技术有限公司 | A kind of data processing method, device, system and dma controller |
| CN112000628A (en) * | 2020-08-21 | 2020-11-27 | 西安理工大学 | Multi-channel laser radar data storage method and device and electronic equipment |
-
2023
- 2023-01-10 CN CN202310036154.5A patent/CN115754971B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5302956A (en) * | 1992-08-14 | 1994-04-12 | Vorad Safety Systems, Inc. | Multi-frequency, multi-target vehicular radar system using digital signal processing |
| US6026443A (en) * | 1992-12-22 | 2000-02-15 | Sun Microsystems, Inc. | Multi-virtual DMA channels, multi-bandwidth groups, host based cellification and reassembly, and asynchronous transfer mode network interface |
| US5835788A (en) * | 1996-09-18 | 1998-11-10 | Electronics For Imaging | System for transferring input/output data independently through an input/output bus interface in response to programmable instructions stored in a program memory |
| US20030110325A1 (en) * | 2001-12-10 | 2003-06-12 | Bradley Roach | Direct memory access (DMA) transfer buffer processor |
| CN101178434A (en) * | 2007-02-02 | 2008-05-14 | 上海易罗信息科技有限公司 | Radar data collection system and collection method thereof |
| CN109766296A (en) * | 2019-01-08 | 2019-05-17 | 郑州云海信息技术有限公司 | A kind of data processing method, device, system and dma controller |
| CN112000628A (en) * | 2020-08-21 | 2020-11-27 | 西安理工大学 | Multi-channel laser radar data storage method and device and electronic equipment |
Non-Patent Citations (3)
| Title |
|---|
| CHAO XIA等: ""Implementation of DMA driver development under Linux"", 《2021 IEEE 2ND INTERNATIONAL CONFERENCE ON INFORMATION TECHNOLOGY, BIG DATA AND ARTIFICIAL INTELLIGENCE 》, pages 721 - 724 * |
| 沈洋等: ""多功能相控阵雷达多通道DMA传输系统设计"", vol. 42, no. 9, pages 2 - 3 * |
| 迟乐军等, 北京航空航天大学出版社 * |
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