CN115754816A - Electronic device and cable connection detection method - Google Patents
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Abstract
The embodiment of the application provides an electronic device and a cable connection detection method, wherein the electronic device comprises a main board and an auxiliary board, a plurality of first connectors are arranged on the main board, a plurality of second connectors are arranged on the auxiliary board, and the plurality of first connectors correspond to the plurality of second connectors one to one; a Complex Programmable Logic Device (CPLD) is arranged on the mainboard, and one or more signal distinguishing components are arranged on the auxiliary board; signal discriminating means for obtaining different types of signals, the types comprising frequency and/or duty cycle; the signal distinguishing component is used for respectively outputting different types of signals to the plurality of second connectors, wherein the types of the signals accessed by the different second connectors are different; the CPLD is used for determining whether the cable between the main board and the auxiliary board is correctly connected according to the type of the signal of each first connector in the plurality of first connectors. By adopting the embodiment of the application, whether the cable connection is correct can be conveniently and quickly detected.
Description
Technical Field
The present application relates to the field of computer technologies, and in particular, to an electronic device and a cable connection detection method.
Background
Along with the continuous development of the computing industry, the speed of data communication is faster and faster, and in order to satisfy higher signal transmission speed requirement, the high-speed cable that uses between inside mainboard of server and backplate, mainboard and the Riser card is more and more, because the interface keeps unanimous mostly, the equipment link connects the cable mistake very easily, leads to data transmission to go wrong.
Therefore, how to detect whether the cable is connected in a wrong way is a technical problem to be solved by those skilled in the art.
Disclosure of Invention
The embodiment of the application discloses an electronic device and a cable connection detection method, which can conveniently and quickly detect whether cable connection is correct.
In a first aspect, an embodiment of the present application provides an electronic device, which includes a main board and a sub-board, where a plurality of first connectors are configured on the main board, a plurality of second connectors are configured on the sub-board, and the plurality of first connectors correspond to the plurality of second connectors one to one; a Complex Programmable Logic Device (CPLD) is arranged on the main board, and one or more signal distinguishing components are arranged on the auxiliary board;
the signal differentiating component is configured to obtain different types of signals, wherein the types include a frequency and/or a duty cycle;
the signal distinguishing component is used for respectively outputting the different types of signals to the plurality of second connectors, wherein the types of the signals accessed by the different second connectors are different;
the CPLD is used for determining whether the cable between the main board and the auxiliary board is correctly connected according to the type of the signal of each first connector in the plurality of first connectors.
By adopting the method, the signal distinguishing component is arranged on the auxiliary board, signals of different types corresponding to different second connectors can be distinguished, the CPLD on the main board can determine the signal type which is received by the corresponding first connector based on the signal type corresponding to the different second connectors, the CPLD compares the signal type which is received by each first connector with the signal type which is actually received by the first connector, if the signal types are different, the cable connected between the main board and the auxiliary board can be determined to belong to wrong connection, and if the signal types are the same, the cable connected between the main board and the auxiliary board can be determined to belong to correct connection. Based on the thought, whether the cable is connected correctly or not can be detected quickly and accurately.
With reference to the first aspect, in a possible implementation manner of the first aspect, a situation of a type of a signal accessed by the second connector corresponding to each of the plurality of first connectors is set in the CPLD; if the type of the signal of the first connector is detected to be a target type, the cable connected to the auxiliary board on the first connector is correctly connected, wherein the target type is the type of the signal accessed by the second connector corresponding to the first connector.
With reference to the first aspect, or any one of the foregoing possible implementations of the first aspect, in yet another possible implementation of the first aspect, the secondary board includes a backplane and/or a Riser card.
With reference to the first aspect, or any one of the foregoing possible implementations of the first aspect, in a further possible implementation of the first aspect, the type is specifically a frequency, and the auxiliary plate further includes a crystal oscillator; in terms of obtaining different types of signals, the signal distinguishing component is specifically configured to perform frequency division processing on the fundamental frequency signal of the crystal oscillator to obtain signals of different frequencies.
With reference to the first aspect, or any one of the foregoing possible implementations of the first aspect, in a further possible implementation of the first aspect, the fundamental frequency signal of the crystal oscillator is further configured to be output to one of the second connectors. It can be understood that the fundamental frequency signal of the crystal oscillator is also used as a path of input, which can reduce the pressure of the signal distinguishing component, thereby compressing the deployment number of the signal distinguishing component to the maximum extent and being beneficial to saving space and cost.
With reference to the first aspect, or any one of the foregoing possible implementations of the first aspect, in a further possible implementation of the first aspect, the signal distinguishing unit includes a D flip-flop, and a D pin of the D flip-flop is connected to a D pin of the D flip-flop
And (7) a pin. By means of such a connection, theThe double-D trigger can realize a frequency division function, and the design complexity is reduced.
With reference to the first aspect, or any one of the foregoing possible implementations of the first aspect, in a further possible implementation of the first aspect, the D flip-flop is specifically a dual D flip-flop, the sub-board is specifically disposed with a signal distinguishing component, the signal distinguishing component is a first dual D flip-flop, a 1CP pin of the first dual D flip-flop is configured to receive a fundamental frequency signal of the crystal oscillator, one branch of a frequency-divided signal output by a 1Q pin of the first dual D flip-flop is configured to be output to one of the second connectors, another branch of the frequency-divided signal output by the 1Q pin of the first dual D flip-flop is configured to be output to a 2CP pin of the first dual D flip-flop, and a frequency-divided signal output by a 2Q pin of the first dual D flip-flop is configured to be output to one of the second connectors.
With reference to the first aspect, or any one of the foregoing possible implementations of the first aspect, in a further possible implementation of the first aspect, the D flip-flop is specifically a dual D flip-flop, the sub-board is specifically disposed with a plurality of signal distinguishing components, the plurality of signal distinguishing components are specifically a plurality of dual D flip-flops, the plurality of dual D flip-flops includes a second dual D flip-flop and a third dual D flip-flop, and the second dual D flip-flop and the third dual D flip-flop are connected in a cascade manner;
the 1CP pin of the second dual-D flip-flop is used for receiving a fundamental frequency signal of the crystal oscillator, one branch of a frequency division signal output by the 1Q pin of the second dual-D flip-flop is used for being output to one second connector of the plurality of second connectors, the other branch of the frequency division signal output by the 1Q pin of the second dual-D flip-flop is used for being output to the 2CP pin of the second dual-D flip-flop, and the frequency division signal output by the 2Q pin of the second dual-D flip-flop is used for being output to one second connector of the plurality of second connectors;
the 1CP pin of the third dual D flip-flop is configured to be connected to the 2Q pin of the second dual D flip-flop, one branch of the frequency-divided signal output by the 1Q pin of the third dual D flip-flop is configured to be output to one of the second connectors, another branch of the frequency-divided signal output by the 1Q pin of the third dual D flip-flop is configured to be output to the 2CP pin of the third dual D flip-flop, and the frequency-divided signal output by the 2Q pin of the third dual D flip-flop is configured to be output to one of the second connectors.
It will be appreciated that any desired number of different frequency signals may be divided in a cascaded manner.
With reference to the first aspect, or any one of the foregoing possible implementation manners of the first aspect, in yet another possible implementation manner of the first aspect, the electronic device further includes a baseboard management controller BMC, the CPLD is further configured to report a detection result of whether the cable is correctly connected to the BMC, and the BMC is configured to output a prompt message to prompt that the cable between the motherboard and the slave board is connected incorrectly. It can be understood that through this kind of suggestion mechanism, can let the user discover the problem fast and in time remedy to correct the wrong connection of cable between mainboard and the subplate as early as possible.
In a second aspect, an embodiment of the present application provides a secondary board, where a plurality of second connectors are configured on the secondary board, and the plurality of second connectors are in one-to-one correspondence with a plurality of first connectors on a main board, where:
the signal differentiating component is configured to obtain different types of signals, wherein the types include a frequency and/or a duty cycle;
the signal distinguishing component is used for respectively outputting the different types of signals to the plurality of second connectors, wherein the types of the signals accessed by the different second connectors are different;
the plurality of second connectors are used for transmitting signals to the plurality of first connectors of the mainboard through cables.
By adopting the method, the signal distinguishing component is arranged on the auxiliary board, signals of different types corresponding to different second connectors can be distinguished, the CPLD on the main board can determine the signal type which is received by the corresponding first connector based on the signal type corresponding to the different second connectors, the CPLD compares the signal type which is received by each first connector with the signal type which is actually received by the first connector, if the signal types are different, the cable connected between the main board and the auxiliary board can be determined to belong to wrong connection, and if the signal types are the same, the cable connected between the main board and the auxiliary board can be determined to belong to correct connection. Based on the thought, whether the cable is connected correctly can be detected quickly and accurately.
With reference to the second aspect, in a possible implementation manner of the second aspect, the sub board includes a back board and/or a Riser card.
With reference to the second aspect or any one of the foregoing possible implementation manners of the second aspect, in yet another possible implementation manner of the second aspect, the type is specifically a frequency, and the secondary plate further includes a crystal oscillator; in terms of obtaining different types of signals, the signal distinguishing component is specifically configured to perform frequency division processing on the fundamental frequency signal of the crystal oscillator to obtain signals of different frequencies.
With reference to the second aspect or any one of the foregoing possible implementations of the second aspect, in a further possible implementation of the second aspect, the fundamental frequency signal of the crystal oscillator is further configured to be output to one of the second connectors. It can be understood that the fundamental frequency signal of the crystal oscillator is also used as one input, so that the pressure of the signal distinguishing component can be reduced, the number of the signal distinguishing components can be reduced to the maximum extent, and the space and the cost can be saved.
With reference to the second aspect or any one of the foregoing possible implementations of the second aspect, in a further possible implementation of the second aspect, the signal distinguishing component includes a D flip-flop, and a D pin of the D flip-flop is connected to a D pin of the D flip-flop
And (7) a pin. Through the connection mode, the double-D trigger can realize the frequency division function, and the complexity of design is reduced.
With reference to the second aspect or any one of the foregoing possible implementations of the second aspect, in a further possible implementation of the second aspect, the D flip-flop is specifically a dual D flip-flop, and a signal distinguishing component is specifically disposed on the sub-board, the signal distinguishing component is a first dual D flip-flop, the 1CP pin of the first dual D flip-flop is configured to receive the fundamental frequency signal of the crystal oscillator, one branch of the frequency-divided signal output by the 1Q pin of the first dual D flip-flop is configured to be output to one of the second connectors, the other branch of the frequency-divided signal output by the 1Q pin of the first dual D flip-flop is configured to be output to the 2CP pin of the first dual D flip-flop, and the frequency-divided signal output by the 2Q pin of the first dual D flip-flop is configured to be output to one of the second connectors.
With reference to the second aspect or any one of the foregoing possible implementations of the second aspect, in a further possible implementation of the second aspect, the D flip-flop is specifically a dual D flip-flop, the sub-board is specifically disposed with a plurality of signal distinguishing components, the plurality of signal distinguishing components are specifically a plurality of dual D flip-flops, the plurality of dual D flip-flops includes a second dual D flip-flop and a third dual D flip-flop, and the second dual D flip-flop is connected to the third dual D flip-flop in a cascade manner;
the 1CP pin of the second dual-D flip-flop is used for receiving a fundamental frequency signal of the crystal oscillator, one branch of a frequency division signal output by the 1Q pin of the second dual-D flip-flop is used for being output to one second connector of the plurality of second connectors, the other branch of the frequency division signal output by the 1Q pin of the second dual-D flip-flop is used for being output to the 2CP pin of the second dual-D flip-flop, and the frequency division signal output by the 2Q pin of the second dual-D flip-flop is used for being output to one second connector of the plurality of second connectors;
the 1CP pin of the third dual D flip-flop is configured to be connected to the 2Q pin of the second dual D flip-flop, one branch of the frequency-divided signal output by the 1Q pin of the third dual D flip-flop is configured to be output to one of the second connectors, another branch of the frequency-divided signal output by the 1Q pin of the third dual D flip-flop is configured to be output to the 2CP pin of the third dual D flip-flop, and the frequency-divided signal output by the 2Q pin of the third dual D flip-flop is configured to be output to one of the second connectors.
It will be appreciated that any desired number of different frequency signals may be divided in a cascaded manner.
In a third aspect, an embodiment of the present application provides a cable connection detection method, which is applied to an electronic device, where the electronic device includes a main board and a sub-board, the main board is configured with a plurality of first connectors, the sub-board is configured with a plurality of second connectors, and the plurality of first connectors correspond to the plurality of second connectors one to one; the method comprises the following steps that a Complex Programmable Logic Device (CPLD) is deployed on the main board, one or more signal distinguishing components are deployed on the auxiliary board, and the method comprises the following steps:
obtaining different types of signals through the signal distinguishing component, wherein the types comprise frequencies and/or duty ratios, the different types of signals are respectively used for being output to the plurality of second connectors, and the types of the signals accessed by the different second connectors are different;
determining, by the CPLD, whether the cable between the main board and the secondary board is properly connected according to the type of the signal of each of the plurality of first connectors.
By adopting the method, the signal distinguishing component is arranged on the auxiliary board, signals of different types corresponding to different second connectors can be distinguished, the CPLD on the main board can determine the signal type which is received by the corresponding first connector based on the signal type corresponding to the different second connectors, the CPLD compares the signal type which is received by each first connector with the signal type which is actually received by the first connector, if the signal types are different, the cable connected between the main board and the auxiliary board can be determined to belong to wrong connection, and if the signal types are the same, the cable connected between the main board and the auxiliary board can be determined to belong to correct connection. Based on the thought, whether the cable is connected correctly can be detected quickly and accurately.
With reference to the third aspect or any one of the foregoing possible implementations of the third aspect, in a further possible implementation of the third aspect, a case of a type of a signal that is accessed by the second connector corresponding to each of the plurality of first connectors is set in the CPLD; if the type of the signal of the first connector is detected to be a target type, the cable connected to the auxiliary board on the first connector is correctly connected, wherein the target type is the type of the signal accessed by the second connector corresponding to the first connector.
With reference to the third aspect, in a possible implementation manner of the third aspect, the secondary board includes a backplane and/or a Riser card.
With reference to the third aspect or any one of the foregoing possible implementation manners of the third aspect, in a further possible implementation manner of the third aspect, the type is specifically a frequency, and the auxiliary plate further includes a crystal oscillator; in terms of obtaining different types of signals, the signal distinguishing component is specifically configured to perform frequency division processing on the fundamental frequency signal of the crystal oscillator to obtain signals of different frequencies.
With reference to the third aspect or any one of the foregoing possible implementation manners of the third aspect, in a further possible implementation manner of the third aspect, the fundamental frequency signal of the crystal oscillator is further configured to be output to one of the second connectors. It can be understood that the fundamental frequency signal of the crystal oscillator is also used as a path of input, which can reduce the pressure of the signal distinguishing component, thereby compressing the deployment number of the signal distinguishing component to the maximum extent and being beneficial to saving space and cost.
With reference to the third aspect or any one of the foregoing possible implementation manners of the third aspect, in a further possible implementation manner of the third aspect, the signal distinguishing component includes a D flip-flop, and a D pin of the D flip-flop is connected to a D pin of the D flip-flop
And (6) a pin. Through the connection mode, the double-D trigger can realize the frequency division function, and the design complexity is reduced.
With reference to the third aspect or any one of the foregoing possible implementations of the third aspect, in a further possible implementation of the third aspect, the D flip-flop is specifically a dual D flip-flop, the sub-board is specifically disposed with a signal distinguishing component, the signal distinguishing component is a first dual D flip-flop, a 1CP pin of the first dual D flip-flop is configured to receive a fundamental frequency signal of the crystal oscillator, one branch of a frequency-divided signal output by a 1Q pin of the first dual D flip-flop is configured to be output to one of the second connectors, another branch of the frequency-divided signal output by the 1Q pin of the first dual D flip-flop is configured to be output to a 2CP pin of the first dual D flip-flop, and a frequency-divided signal output by a 2Q pin of the first dual D flip-flop is configured to be output to one of the second connectors.
With reference to the third aspect or any one of the foregoing possible implementations of the third aspect, in a further possible implementation of the third aspect, the D flip-flop is specifically a dual D flip-flop, the sub-board is specifically disposed with a plurality of signal distinguishing components, the plurality of signal distinguishing components are specifically a plurality of dual D flip-flops, the plurality of dual D flip-flops include a second dual D flip-flop and a third dual D flip-flop, and the second dual D flip-flop and the third dual D flip-flop are connected in a cascade manner;
the 1CP pin of the second dual-D flip-flop is used for receiving a fundamental frequency signal of the crystal oscillator, one branch of a frequency division signal output by the 1Q pin of the second dual-D flip-flop is used for being output to one second connector of the plurality of second connectors, the other branch of the frequency division signal output by the 1Q pin of the second dual-D flip-flop is used for being output to the 2CP pin of the second dual-D flip-flop, and the frequency division signal output by the 2Q pin of the second dual-D flip-flop is used for being output to one second connector of the plurality of second connectors;
the 1CP pin of the third dual D flip-flop is configured to be connected to the 2Q pin of the second dual D flip-flop, one branch of the frequency-divided signal output by the 1Q pin of the third dual D flip-flop is configured to be output to one of the second connectors, another branch of the frequency-divided signal output by the 1Q pin of the third dual D flip-flop is configured to be output to the 2CP pin of the third dual D flip-flop, and the frequency-divided signal output by the 2Q pin of the third dual D flip-flop is configured to be output to one of the second connectors.
It will be appreciated that any desired number of different frequency signals may be divided in a cascaded manner.
With reference to the third aspect, or any one of the foregoing possible implementation manners of the third aspect, in yet another possible implementation manner of the third aspect, the electronic device further includes a baseboard management controller BMC, the CPLD is further configured to report a detection result of whether the cable is correctly connected to the BMC, and the BMC is configured to output a prompt message to prompt that the cable connection between the main board and the sub-board is incorrect.
It can be understood that through this kind of suggestion mechanism, can let the user discover the problem fast and in time remedy to correct the wrong connection of cable between mainboard and the subplate as early as possible.
In a fourth aspect, an embodiment of the present application provides a cable connection detection method, where the method is applied to a secondary board, where a plurality of second connectors are configured on the secondary board, and the plurality of second connectors correspond to a plurality of first connectors on a main board one to one, where:
obtaining, by the signal discrimination unit, different types of signals, wherein the types comprise frequency and/or duty cycle;
outputting the different types of signals to the plurality of second connectors respectively, wherein the types of the signals accessed by the different second connectors are different;
a plurality of first connectors for transmitting signals to the main board through the plurality of second connectors via cables.
By adopting the method, the signal distinguishing component is arranged on the auxiliary board, signals of different types corresponding to different second connectors can be distinguished, the CPLD on the main board can determine the signal type which is received by the corresponding first connector based on the signal type corresponding to the different second connectors, the CPLD compares the signal type which is received by each first connector with the signal type which is actually received by the first connector, if the signal types are different, the cable connected between the main board and the auxiliary board can be determined to belong to wrong connection, and if the signal types are the same, the cable connected between the main board and the auxiliary board can be determined to belong to correct connection. Based on the thought, whether the cable is connected correctly can be detected quickly and accurately.
With reference to the fourth aspect, in a possible implementation manner of the fourth aspect, the sub board includes a back board and/or a Riser card.
With reference to the fourth aspect or any one of the foregoing possible implementations of the fourth aspect, in a further possible implementation of the fourth aspect, the type is specifically a frequency, and the secondary plate further includes a crystal oscillator; in terms of obtaining different types of signals, the signal distinguishing component is specifically configured to perform frequency division processing on the fundamental frequency signal of the crystal oscillator to obtain signals of different frequencies.
With reference to the fourth aspect or any one of the foregoing possible implementation manners of the fourth aspect, in a further possible implementation manner of the fourth aspect, the fundamental frequency signal of the crystal oscillator is further used for being output to one of the second connectors. It can be understood that the fundamental frequency signal of the crystal oscillator is also used as a path of input, which can reduce the pressure of the signal distinguishing component, thereby compressing the deployment number of the signal distinguishing component to the maximum extent and being beneficial to saving space and cost.
With reference to the fourth aspect or any one of the foregoing possible implementation manners of the fourth aspect, in a further possible implementation manner of the fourth aspect, the signal distinguishing component includes a D flip-flop, and a D pin of the D flip-flop is connected to a D pin of the D flip-flop
And (6) a pin. Through the connection mode, the double-D trigger can realize the frequency division function, and the complexity of design is reduced.
Drawings
The drawings used in the embodiments of the present application are described below.
Fig. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of another electronic device provided in the embodiment of the present application;
fig. 3 is a flowchart of a method for detecting a cable connection according to an embodiment of the present disclosure.
Detailed Description
The embodiments of the present application are described below with reference to the drawings.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an electronic device 10 according to an embodiment of the present disclosure, where the electronic device 10 includes a main board 11 and a sub-board 12, a plurality of first connectors 110 are disposed on the main board 11, a plurality of second connectors 120 are disposed on the sub-board, and the plurality of first connectors 110 and the plurality of second connectors 120 correspond to one another one by one; for example, if the main board 11 sequentially has 4 first connectors A1, B1, C1, and D1, and the sub-board 12 sequentially has 4 second connectors A2, B2, C2, and D2, the interface specifications of the different first connectors may be the same or different, and the interface specifications of the different second connectors may be the same or different. The first connector A1 corresponds to the second connector A2, the first connector B1 corresponds to the second connector B2, the first connector C1 corresponds to the second connector C2, and the first connector D1 corresponds to the second connector D2. It should be noted that, the correspondence between the first connector A1 and the second connector A2 specifically means that A1 is used to connect with A2 through a cable, although B1 may also connect with A2 through a cable under the condition that the interface specifications of the first connector A1 and the first connector B1 are the same, since B1 and A2 are not preset to have a correspondence relationship, such a connection cannot achieve an intended function, generally speaking, if a certain first connector does not correspond to a certain second connector, and the certain first connector and the certain second connector establish a connection through a cable, the cable is considered to be connected incorrectly, that is, only the corresponding first connector and the corresponding second connector establish a connection through a cable, the cable is considered to be connected correctly. According to the above example, the connection cables between the first connector A1 and the non-corresponding second connector B2 or C2 are all connected incorrectly, the connection cables between the first connector A1 and the corresponding second connector A2 are connected correctly, and the rest are analogized in turn.
The first connector 110 and the second connector 120 having a corresponding relationship are illustrated in fig. 1 as being connected by a broken line.
One or more Complex Programmable Logic Devices (CPLDs) 112 are disposed on the motherboard 11; one or more signal discrimination elements 122 are disposed on the sub-panel 12.
In the embodiment of the present application, the signal differentiating component on the sub-board 12 is used to obtain different types of signals, wherein the types include frequency and/or duty cycle; the signal distinguishing component is further configured to output the different types of signals to the plurality of second connectors, respectively, where the different types of signals accessed by the second connectors are different; for example, the signal distinguishing component obtains signals of type 1, type 2, type 3 and type 4, and in combination with the above-mentioned examples, the signal of type 1 is used for outputting to the second connector A2, the signal of type 2 is used for outputting to the second connector B2, the signal of type 3 is used for outputting to the second connector C2, and the signal of type 4 is used for outputting to the second connector D2.
The CPLD on the main board 11 is used to determine whether the cable between the main board and the secondary board is correctly connected according to the type of the signal of each of the plurality of first connectors. It should be noted that the type of the signal accessed by each of the second connectors is stored in the CPLD, for example, in the form shown in table 1.
TABLE 1
| Second connector | Type of signal | |
| Second | Type | 1 |
| Second | Type | 2 |
| Second | Type | 3 |
| Second | Type | 4 |
Since the CPLD already knows which second connector corresponds to each first connector and also knows which type of signal on each second connector, it can also be determined what type of signal each first connector should receive in the case of correct cable connection, and therefore, the CPLD can determine whether the cable between the main board and the sub board is correctly connected according to the type of signal each first connector of the plurality of first connectors should receive and the type of signal actually received.
For example, if it is detected that the type of the signal of the first connector A1 (i.e., the type of the signal actually received) is a target type (i.e., the type of the signal that should be received), the cable connected to the sub board on the first connector A1 is correctly connected, where the target type is the type of the signal accessed by the second connector A2 corresponding to the first connector A2.
Similarly, if it is detected that the type of the signal of the first connector B1 (i.e., the type of the signal actually received) is a target type (i.e., the type of the signal that should be received), the cable connected to the sub board on the first connector B1 is correctly connected, where the target type is the type of the signal accessed by the second connector B2 corresponding to the first connector B2.
The determination of the type of signal of the other first connector can be analogized to the above.
It will be appreciated that when a cable connection error between one or more corresponding sets of first and second connectors is determined, a cable connection error between the main board 11 and the secondary board 12 may be determined.
In this embodiment of the present application, the sub board 12 may be a backplane and/or a Riser card, and optionally, the backplane may be used to connect a hard disk, and the Riser card refers to a function expansion card or a Riser card inserted into a PCI-Express (peripheral component interconnect Express) interface. Of course, the back board may also be other types of circuit boards, as long as the circuit board can be connected with the main board through a connector and a cable, which is not limited herein.
For ease of understanding, the above-mentioned types are exemplified as the frequencies.
Optionally, in the case that the type is frequency, the sub-board 12 may further include a crystal oscillator, and in terms of obtaining different types of signals, the signal distinguishing component is specifically configured to perform frequency division processing on a fundamental frequency signal of the crystal oscillator to obtain signals with different frequencies. For example, the signal distinguishing component takes the fundamental frequency signal as input, and outputs signals of various other frequencies after processing, for example, 1/2 fundamental frequency signal, 1/4 fundamental frequency signal, 1/8 fundamental frequency signal, etc., and the frequency of the output signal may be greater than the fundamental frequency or smaller than the fundamental frequency.
Optionally, the fundamental frequency signal of the crystal oscillator is further used for being output to one of the second connectors. Also by way of example, the signal differentiating component may differentiate 1/2 baseband signals, 1/4 baseband signals, and 1/8 baseband signals, where the 3 signals are input to only 3 second connectors of the second connector A2, the second connector B2, the second connector C2, and the second connector D2, and the other 1 second connector has no signal corresponding thereto, and if the baseband signal of the crystal oscillator is also input as 1, exactly 4 signals correspond to the 4 second connectors, and each second connector may respectively receive signals with different frequencies.
In the examples of this application, theThe signal differentiation component may be an integrated circuit or a chip, for example, a CPLD, or a D flip-flop, such as a single D flip-flop, a dual D flip-flop, a triple D flip-flop, or the like. When the signal distinguishing component is a D trigger, the D pin of the D trigger is connected with the D trigger
And (7) a pin.
For the sake of understanding, the D flip-flop is exemplified as 74LVC74A (belonging to a kind of dual D flip-flop) in the following.
In case 1, as shown in fig. 2, a signal distinguishing component 122 is specifically disposed on the daughter board 12, the signal distinguishing component 122 is a dual D flip-flop, which may be referred to as a first dual D flip-flop for convenience of description, the 1CP pin of the first dual D flip-flop is used for receiving the baseband signal of the crystal oscillator 123, one branch of the frequency-divided signal (i.e., 1/2 baseband signal) output by the 1Q pin of the first dual D flip-flop is used for outputting to one of the second connectors, the other branch of the frequency-divided signal output by the 1Q pin of the first dual D flip-flop is used for outputting to the 2CP pin of the first dual D flip-flop, that is, the 1/2 baseband signal output by the 1Q pin of the first dual D flip-flop is used as an input of the 2CP pin of the first dual D flip-flop, and the frequency-divided signal (i.e., 1/4 signal) output by the 2Q pin of the first dual D flip-flop is used for outputting to one of the second connectors. It can be seen that the frequency division based on a dual D flip-flop can at least divide 1/2 baseband signal and 1/4 baseband signal, and in addition to the original baseband signal of the crystal 123, there are at least 3 frequency signals in total, so that the frequency signals can be used as the inputs of 3 second connectors, for example, as the inputs of the second connectors A2, B2, and C2, respectively.
In case 2, a plurality of signal distinguishing components are specifically disposed on the sub-board, and the plurality of signal distinguishing components are specifically a plurality of dual D flip-flops, where the plurality of dual D flip-flops may be two or more than two, and specifically how many of the plurality of dual D flip-flops may be set according to the number of different frequency signals required, regardless of how many of the plurality of dual D flip-flops are specifically described below by taking two dual D flip-flops included therein as an example, for convenience of description, the two dual D flip-flops are referred to as a second dual D flip-flop and a third dual D flip-flop, and the second dual D flip-flop and the third dual D flip-flop are connected in a cascade manner.
The 1CP pin of the second dual D flip-flop is configured to receive a baseband signal of the crystal oscillator, one branch of a frequency-divided signal (i.e., a 1/2 baseband signal) output by the 1Q pin of the second dual D flip-flop is configured to be output to one of the second connectors, another branch of the frequency-divided signal output by the 1Q pin of the second dual D flip-flop is configured to be output to the 2CP pin of the second dual D flip-flop, that is, the 1/2 baseband signal output by the 1Q pin of the second dual D flip-flop is used as an input of the 2CP pin of the second dual D flip-flop, and the frequency-divided signal (i.e., a 1/4 baseband signal) output by the 2Q pin of the second dual D flip-flop is configured to be output to one of the second connectors.
The 1CP pin of the third dual D flip-flop is used for connecting to the 2Q pin of the second dual D flip-flop, that is, the 1/4 baseband signal output by the 2Q pin of the second dual D flip-flop is also used as the input of the 1CP pin of the third dual D flip-flop, one branch of the frequency-divided signal (i.e., the frequency-divided-1/8 signal) output by the 1Q pin of the third dual D flip-flop is used for outputting to one of the plurality of second connectors, the other branch of the frequency-divided signal (i.e., the frequency-divided-1/8 signal) output by the 1Q pin of the third dual D flip-flop is used for outputting to the 2CP pin of the third dual D flip-flop, that is, the 1/8 baseband signal output by the 1Q pin of the third dual D flip-flop is used as the input of the 2CP pin of the third dual D flip-flop, and the frequency-divided signal (i.e., the frequency-divided-1/16 signal) output by the 2Q pin of the third dual D flip-flop is used for outputting to one of the plurality of second connectors.
It can be seen that at least 1/2 baseband signal, 1/4 baseband signal, 1/8 baseband signal, 1/16 baseband signal can be separated by performing frequency division based on 2 dual D flip-flops, and in addition to the original baseband signal of the crystal oscillator, there are at least 5 frequency signals in total, so that the signals can be used as inputs of 5 second connectors, and if the number of the dual D flip-flops is greater, the types of the signal frequencies that can be provided are also greater, and the number of the second connectors that can be connected is also greater.
Of course, the dual D flip-flop may be other devices besides the 74LVC 74A.
In this embodiment, the electronic device 10 may further include a Baseboard Management Controller (BMC) 13, where the CPLD is further configured to report a detection result of whether the cable is correctly connected to the BMC, and when the BMC learns from the CPLD that the cable between the motherboard and the daughter board is incorrectly connected, the BMC is configured to output a prompt message to prompt that the cable between the motherboard and the daughter board is incorrectly connected, for example, the BMC sends a prompt to a user using the electronic device through text, animation, voice, or other manners, so that the user may learn that the cable between the motherboard and the daughter board is incorrectly connected or missed.
Optionally, as shown in fig. 3, fig. 3 illustrates a process of detecting whether a CPLD on the motherboard, a dual D flip-flop on the secondary board, and a crystal oscillator cooperate with each other to detect whether a cable is connected between the motherboard and the secondary board, in general, a fundamental frequency signal, i.e., a baseband signal, is provided by the crystal oscillator, and is input to the dual D flip-flop, and is subjected to frequency division processing by the dual D flip-flop to output one or more frequency division signals, and the one or more frequency division signals are output to the first connector of the motherboard through a cable via the second connector of the dual D flip-flop, while the CPLD on the motherboard detects a frequency of a signal of each first connector, and determines whether to notify the BMC of an alarm by determining whether a frequency of the detected signal (i.e., an actual signal frequency) is consistent with a frequency of a preset signal (i.e., a signal frequency that should be detected), and if so, does not notify the BMC of the alarm (i.e., the cable is correctly connected), notifies the BMC of the alarm (i.e., a cable connection error).
The electronic device in the embodiment of the present application may be an electronic device such as a server, a computer, a vehicle-mounted device (e.g., an automobile, a bicycle, an electric vehicle, an airplane, a ship, etc.), a smart home device (e.g., a refrigerator, a television, an air conditioner, an electric meter, etc.), a smart robot, a workshop device, etc., or a component (or a module or a component) in the electronic device.
By adopting the method, different types of signals respectively corresponding to different second connectors can be divided by arranging the signal distinguishing component on the auxiliary board, the CPLD on the main board can determine the type of the signal which is received by the corresponding first connector based on the type of the signal which is corresponding to different second connectors, the CPLD compares the type of the signal which is received by each first connector with the type of the signal which is actually received by the first connector, if the types of the signal which is received by each first connector are different, the cable which is connected between the main board and the auxiliary board can be determined to be in wrong connection, and if the types of the signal which is received by each first connector are the same, the cable which is connected between the main board and the auxiliary board can be determined to be in correct connection. Based on the thought, whether the cable is connected correctly or not can be detected quickly and accurately.
It should be noted that, in the case where the signal distinguishing part is a part having a size smaller than that of the CPLD, the signal distinguishing part does not need to occupy a large space when being disposed on the sub-board, and in the case where the signal distinguishing part is a part having a cost smaller than that of the CPLD, the disposing of the signal distinguishing part on the sub-board can save a capital cost. Especially when the signal discrimination section is a D flip-flop, it is possible to significantly reduce the space occupied by the deployment and to significantly reduce the capital cost required for the deployment.
Those skilled in the art can understand that all or part of the processes in the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer readable storage medium, and can be implemented by hardware related to the computer program. And the aforementioned storage medium includes: various media that can store computer program code, such as ROM or RAM, magnetic or optical disks, etc.
Claims (30)
1. An electronic device is characterized by comprising a main board and a secondary board, wherein a plurality of first connectors are arranged on the main board, a plurality of second connectors are arranged on the secondary board, and the plurality of first connectors correspond to the plurality of second connectors one to one; a Complex Programmable Logic Device (CPLD) is arranged on the main board, and one or more signal distinguishing components are arranged on the auxiliary board;
the signal discriminating means is for obtaining different types of signals, wherein the types comprise frequency and/or duty cycle;
the signal distinguishing component is used for respectively outputting the different types of signals to the plurality of second connectors, wherein the types of the signals accessed by the different second connectors are different;
the CPLD is used for determining whether the cable between the main board and the auxiliary board is correctly connected according to the type of the signal of each first connector in the plurality of first connectors.
2. The electronic device according to claim 1, wherein the condition of the type of the signal accessed by the second connector corresponding to each of the plurality of first connectors is set in the CPLD; if the type of the signal of the first connector is detected to be a target type, the cable connected to the auxiliary board on the first connector is correctly connected, wherein the target type is the type of the signal accessed by the second connector corresponding to the first connector.
3. The electronic device of claim 1, wherein the sub-board comprises a backplane and/or a Riser card.
4. An electronic device according to any of claims 1-3, characterized in that the type is in particular frequency, the subplate further comprising a crystal oscillator; in terms of obtaining different types of signals, the signal distinguishing component is specifically configured to perform frequency division processing on the fundamental frequency signal of the crystal oscillator to obtain signals of different frequencies.
5. The electronic device of claim 4, wherein the fundamental frequency signal of the crystal oscillator is further configured to be output to one of the plurality of second connectors.
6. Electronic device according to claim 4 or 5, characterized in that the signal discrimination means comprise a D flip-flop, the D pin of which is connected to the D flip-flop
And (7) a pin.
7. The electronic device according to claim 6, wherein the D flip-flop is a dual D flip-flop, and the sub-board is disposed with a signal distinguishing component, the signal distinguishing component is a first dual D flip-flop, the 1CP pin of the first dual D flip-flop is configured to receive a fundamental frequency signal of the crystal oscillator, one branch of the frequency-divided signal output from the 1Q pin of the first dual D flip-flop is configured to be output to one of the second connectors, the other branch of the frequency-divided signal output from the 1Q pin of the first dual D flip-flop is configured to be output to the 2CP pin of the first dual D flip-flop, and the frequency-divided signal output from the 2Q pin of the first dual D flip-flop is configured to be output to one of the second connectors.
8. The electronic device according to claim 6, wherein the D flip-flop is a dual D flip-flop, and the sub-board has a plurality of signal distinguishing components disposed thereon, and the plurality of signal distinguishing components are a plurality of dual D flip-flops, and the plurality of dual D flip-flops includes a second dual D flip-flop and a third dual D flip-flop, and the second dual D flip-flop and the third dual D flip-flop are connected in a cascade manner;
the 1CP pin of the second dual D flip-flop is configured to receive a fundamental frequency signal of the crystal oscillator, one branch of a frequency-divided signal output from the 1Q pin of the second dual D flip-flop is configured to be output to one of the second connectors, another branch of the frequency-divided signal output from the 1Q pin of the second dual D flip-flop is configured to be output to the 2CP pin of the second dual D flip-flop, and a frequency-divided signal output from the 2Q pin of the second dual D flip-flop is configured to be output to one of the second connectors;
the 1CP pin of the third dual D flip-flop is configured to be connected to the 2Q pin of the second dual D flip-flop, one branch of the frequency-divided signal output by the 1Q pin of the third dual D flip-flop is configured to be output to one of the second connectors, another branch of the frequency-divided signal output by the 1Q pin of the third dual D flip-flop is configured to be output to the 2CP pin of the third dual D flip-flop, and the frequency-divided signal output by the 2Q pin of the third dual D flip-flop is configured to be output to one of the second connectors.
9. The electronic device according to any one of claims 1 to 8, wherein the electronic device further includes a Baseboard Management Controller (BMC), the CPLD is further configured to report a detection result of whether the cable is correctly connected to the BMC, and the BMC is configured to output a prompt message to prompt that the cable between the motherboard and the daughter board is incorrectly connected.
10. A sub-board, wherein a plurality of second connectors are configured on the sub-board, and the plurality of second connectors are in one-to-one correspondence with a plurality of first connectors on a main board, wherein:
the signal differentiating component is configured to obtain different types of signals, wherein the types include a frequency and/or a duty cycle;
the signal distinguishing component is used for respectively outputting the different types of signals to the plurality of second connectors, wherein the types of the signals accessed by the different second connectors are different;
the plurality of second connectors are used for transmitting signals to the plurality of first connectors of the mainboard through cables.
11. A sub-panel according to claim 10, wherein the sub-panel comprises a back panel and/or a Riser card.
12. A secondary plate according to any one of claims 10-11, wherein the type is in particular frequency, the secondary plate further comprising a crystal oscillator; in terms of obtaining different types of signals, the signal distinguishing component is specifically configured to perform frequency division processing on the fundamental frequency signal of the crystal oscillator to obtain signals of different frequencies.
13. The sub board according to claim 12, wherein the fundamental frequency signal of the crystal oscillator is further used for output to one of the plurality of second connectors.
14. The subplate according to claim 12 or 13, characterized in that the signal discrimination means comprises a D flip-flop, the D pin of which is connected to the D flip-flop
And (7) a pin.
15. The slave board according to claim 14, wherein the D flip-flop is a dual D flip-flop, and a signal distinguishing component is disposed on the slave board, the signal distinguishing component is a first dual D flip-flop, the 1CP pin of the first dual D flip-flop is used for receiving a fundamental frequency signal of the crystal oscillator, one branch of a frequency-divided signal output from the 1Q pin of the first dual D flip-flop is used for outputting to one of the second connectors, another branch of the frequency-divided signal output from the 1Q pin of the first dual D flip-flop is used for outputting to the 2CP pin of the first dual D flip-flop, and a frequency-divided signal output from the 2Q pin of the first dual D flip-flop is used for outputting to one of the second connectors.
16. The slave board according to claim 14, wherein the D flip-flop is a dual D flip-flop, and a plurality of signal distinguishing components are disposed on the slave board, and the plurality of signal distinguishing components are a plurality of dual D flip-flops, and the plurality of dual D flip-flops includes a second dual D flip-flop and a third dual D flip-flop, and the second dual D flip-flop and the third dual D flip-flop are connected in a cascade manner;
the 1CP pin of the second dual-D flip-flop is used for receiving a fundamental frequency signal of the crystal oscillator, one branch of a frequency division signal output by the 1Q pin of the second dual-D flip-flop is used for being output to one second connector of the plurality of second connectors, the other branch of the frequency division signal output by the 1Q pin of the second dual-D flip-flop is used for being output to the 2CP pin of the second dual-D flip-flop, and the frequency division signal output by the 2Q pin of the second dual-D flip-flop is used for being output to one second connector of the plurality of second connectors;
the 1CP pin of the third dual D flip-flop is configured to be connected to the 2Q pin of the second dual D flip-flop, one branch of the frequency-divided signal output by the 1Q pin of the third dual D flip-flop is configured to be output to one of the second connectors, another branch of the frequency-divided signal output by the 1Q pin of the third dual D flip-flop is configured to be output to the 2CP pin of the third dual D flip-flop, and the frequency-divided signal output by the 2Q pin of the third dual D flip-flop is configured to be output to one of the second connectors.
17. A cable connection detection method is characterized by being applied to an electronic device, wherein the electronic device comprises a main board and an auxiliary board, a plurality of first connectors are arranged on the main board, a plurality of second connectors are arranged on the auxiliary board, and the first connectors correspond to the second connectors one by one; a Complex Programmable Logic Device (CPLD) is arranged on the main board, one or more signal distinguishing components are arranged on the auxiliary board, and the method comprises the following steps:
obtaining different types of signals through the signal distinguishing component, wherein the types comprise frequencies and/or duty ratios, the different types of signals are respectively used for being output to the plurality of second connectors, and the types of the signals accessed by the different second connectors are different;
determining, by the CPLD, whether the cable between the main board and the secondary board is properly connected according to the type of the signal of each of the plurality of first connectors.
18. The method of claim 17, wherein the condition of the type of signal accessed by the second connector corresponding to each of the plurality of first connectors is set in the CPLD; if the type of the signal of the first connector is detected to be a target type, the cable connected to the auxiliary board on the first connector is correctly connected, wherein the target type is the type of the signal accessed by the second connector corresponding to the first connector.
19. The method of claim 17, wherein the sub-board comprises a backplane and/or a Riser card.
20. The method according to any of claims 17-19, wherein the type is in particular frequency, the secondary plate further comprising a crystal oscillator; in terms of obtaining different types of signals, the signal distinguishing component is specifically configured to perform frequency division processing on the fundamental frequency signal of the crystal oscillator to obtain signals of different frequencies.
21. The method of claim 20, wherein the fundamental frequency signal of the crystal oscillator is further used for outputting to one of the plurality of second connectors.
22. Method according to claim 20 or 21, characterized in that the signal discrimination means comprise a D flip-flop, the D pin of which is connected to the D flip-flop
And (6) a pin.
23. The method as claimed in claim 22, wherein the D flip-flop is a dual D flip-flop, and the sub-board has a signal distinguishing component disposed thereon, the signal distinguishing component is a first dual D flip-flop, the 1CP pin of the first dual D flip-flop is used for receiving the fundamental frequency signal of the crystal oscillator, one branch of the frequency-divided signal output from the 1Q pin of the first dual D flip-flop is used for outputting to one of the second connectors, the other branch of the frequency-divided signal output from the 1Q pin of the first dual D flip-flop is used for outputting to the 2CP pin of the first dual D flip-flop, and the frequency-divided signal output from the 2Q pin of the first dual D flip-flop is used for outputting to one of the second connectors.
24. The method according to claim 22, wherein the D flip-flop is a dual D flip-flop, and the sub-board has a plurality of signal distinguishing components disposed thereon, and the plurality of signal distinguishing components is a plurality of dual D flip-flops, and the plurality of dual D flip-flops includes a second dual D flip-flop and a third dual D flip-flop, and the second dual D flip-flop and the third dual D flip-flop are connected in a cascade manner;
the 1CP pin of the second dual D flip-flop is configured to receive a fundamental frequency signal of the crystal oscillator, one branch of a frequency-divided signal output from the 1Q pin of the second dual D flip-flop is configured to be output to one of the second connectors, another branch of the frequency-divided signal output from the 1Q pin of the second dual D flip-flop is configured to be output to the 2CP pin of the second dual D flip-flop, and a frequency-divided signal output from the 2Q pin of the second dual D flip-flop is configured to be output to one of the second connectors;
the 1CP pin of the third dual D flip-flop is configured to be connected to the 2Q pin of the second dual D flip-flop, one branch of the frequency-divided signal output by the 1Q pin of the third dual D flip-flop is configured to be output to one of the second connectors, another branch of the frequency-divided signal output by the 1Q pin of the third dual D flip-flop is configured to be output to the 2CP pin of the third dual D flip-flop, and the frequency-divided signal output by the 2Q pin of the third dual D flip-flop is configured to be output to one of the second connectors.
25. The method according to any one of claims 17 to 24, wherein the electronic device further includes a baseboard management controller BMC, the CPLD is further configured to report a detection result of whether the cable is correctly connected to the BMC, and the BMC is configured to output a prompt message to prompt that the cable between the motherboard and the subplate is incorrectly connected.
26. A cable connection detection method is characterized in that the method is applied to a secondary board, a plurality of second connectors are configured on the secondary board, the second connectors correspond to a plurality of first connectors on a main board one by one, and the method comprises the following steps:
obtaining, by the signal discrimination means, different types of signals, wherein the types comprise frequency and/or duty cycle;
outputting the different types of signals to the plurality of second connectors respectively, wherein the types of the signals accessed by the different second connectors are different;
a plurality of first connectors for transmitting signals to the main board through the plurality of second connectors via cables.
27. The method of claim 26, wherein the sub-panel comprises a backplane and/or a Riser card.
28. The method according to claim 26 or 27, wherein the type is in particular frequency, the secondary plate further comprising a crystal oscillator; in terms of obtaining different types of signals, the signal distinguishing component is specifically configured to perform frequency division processing on the fundamental frequency signal of the crystal oscillator to obtain signals of different frequencies.
29. The method of claim 28, wherein the fundamental frequency signal of the crystal oscillator is further used for output to one of the plurality of second connectors.
30. According to the rightThe method of claim 28 or 29, wherein the signal differentiation component comprises a D flip-flop having a D pin connected to the D flip-flop
And (6) a pin.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117667818A (en) * | 2024-01-31 | 2024-03-08 | 苏州元脑智能科技有限公司 | Signal transmission structure, server and signal transmission method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117667818A (en) * | 2024-01-31 | 2024-03-08 | 苏州元脑智能科技有限公司 | Signal transmission structure, server and signal transmission method |
| CN117667818B (en) * | 2024-01-31 | 2024-05-14 | 苏州元脑智能科技有限公司 | Signal transmission structure, server and signal transmission method |
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