CN115754816A - Electronic device and cable connection detection method - Google Patents
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Abstract
Description
技术领域technical field
本申请涉及计算机技术领域,尤其涉及一种电子装置及线缆连接检测方法。The present application relates to the field of computer technology, in particular to an electronic device and a cable connection detection method.
背景技术Background technique
随着计算产业的不断发展,数据通信的速率越来越快,为了满足更高的信号传输速率要求,服务器内部主板与背板、主板与Riser卡之间使用的高速线缆越来越多,由于接口大多保持一致,组装环节很容易将线缆接错,导致数据传输出现问题。With the continuous development of the computing industry, the rate of data communication is getting faster and faster. In order to meet the higher signal transmission rate requirements, more and more high-speed cables are used between the main board and the backplane inside the server, and between the main board and the riser card. Since the interfaces are mostly consistent, it is easy to connect the wrong cables during the assembly process, resulting in problems in data transmission.
因此,如何检测线缆是否接错是本领域技术人员需要解决的技术问题。Therefore, how to detect whether the cables are connected incorrectly is a technical problem to be solved by those skilled in the art.
发明内容Contents of the invention
本申请实施例公开了一种电子装置及线缆连接检测方法,能够方便、快捷地检测线缆连接是否正确。The embodiment of the present application discloses an electronic device and a cable connection detection method, which can conveniently and quickly detect whether the cable connection is correct.
第一方面,本申请实施例提供一种电子装置,该电子装置包括主板和副板,所述主板上配置有多个第一连接器,所述副板上配置有多个第二连接器,所述多个第一连接器与所述多个第二连接器一一对应;所述主板上部署有复杂可编程逻辑器件CPLD,所述副板上部署有一个或多个信号区分部件;In a first aspect, an embodiment of the present application provides an electronic device, the electronic device includes a main board and a sub-board, a plurality of first connectors are arranged on the main board, and a plurality of second connectors are arranged on the sub-board, The plurality of first connectors correspond to the plurality of second connectors one by one; a complex programmable logic device CPLD is disposed on the main board, and one or more signal distinguishing components are disposed on the sub-board;
所述信号区分部件用于获得不同类型的信号,其中,所述类型包括频率和/或占空比;The signal distinguishing component is used to obtain different types of signals, wherein the types include frequency and/or duty cycle;
所述信号区分部件用于将所述不同类型的信号分别输出至所述多个第二连接器,其中,不同的第二连接器接入的信号的类型不同;The signal distinguishing component is configured to respectively output the signals of different types to the plurality of second connectors, wherein the types of signals connected to different second connectors are different;
所述CPLD用于根据所述多个第一连接器中每个第一连接器的信号的类型,确定所述主板与所述副板之间的线缆是否正确连接。The CPLD is used to determine whether the cable between the main board and the sub-board is correctly connected according to the signal type of each first connector in the plurality of first connectors.
采用上述方法,通过在该副板上设置信号区分部件,能够划分出不同类型的分别与不同第二连接器对应的信号,而该主板上的CPLD可以基于不同第二连接器对应的信号类型确定出相应的第一连接器应该接收到的信号类型,该CPLD将每个第一连接器应该收到的信号的类型与该第一连接器实际收到的信号类型进行比较,如果两者不同则可以确定主板与副板之间连接的线缆属于错误连接,如果两者相同则可以确定主板与副板之间连接的线缆属于正确连接。基于这种思路,可以快速、准确地检测出线缆是否正确连接。Using the above method, by setting the signal distinguishing component on the sub-board, different types of signals corresponding to different second connectors can be divided, and the CPLD on the main board can be determined based on the signal types corresponding to different second connectors The signal type that should be received by the corresponding first connector, the CPLD compares the signal type that each first connector should receive with the signal type actually received by the first connector, if the two are different then It can be determined that the cable connected between the main board and the sub-board is a wrong connection, and if the two are the same, it can be determined that the cable connected between the main board and the sub-board is a correct connection. Based on this idea, it is possible to quickly and accurately detect whether the cable is connected correctly.
结合第一方面,在第一方面的一种可能的实现方式中,所述多个第一连接器中每个第一连接器对应的第二连接器接入的信号的类型的情况设置在了所述CPLD中;若检测到所述第一连接器的信号的类型为目标类型,则所述第一连接器上连接到所述副板的线缆连接正确,其中,所述目标类型为所述第一连接器对应的第二连接器接入的信号的类型。With reference to the first aspect, in a possible implementation manner of the first aspect, the type of signal connected to the second connector corresponding to each first connector among the plurality of first connectors is set in the In the CPLD; if it is detected that the signal type of the first connector is the target type, then the cable connected to the sub-board on the first connector is connected correctly, wherein the target type is the target type The type of signal connected to the second connector corresponding to the first connector.
结合第一方面,或者第一方面的上述任一种可能的实现方式中,在第一方面的又一种可能的实现方式中,所述副板包括背板和/或Riser卡。With reference to the first aspect, or any of the foregoing possible implementation manners of the first aspect, in yet another possible implementation manner of the first aspect, the subboard includes a backplane and/or a riser card.
结合第一方面,或者第一方面的上述任一种可能的实现方式中,在第一方面的又一种可能的实现方式中,所述类型具体为频率,所述副板还包括晶振;在获得不同类型的信号方面,所述信号区分部件具体用于对所述晶振的基频信号进行分频处理得到不同频率的信号。In combination with the first aspect, or any of the above possible implementations of the first aspect, in another possible implementation of the first aspect, the type is specifically frequency, and the sub-board further includes a crystal oscillator; In terms of obtaining different types of signals, the signal distinguishing component is specifically configured to perform frequency division processing on the fundamental frequency signal of the crystal oscillator to obtain signals of different frequencies.
结合第一方面,或者第一方面的上述任一种可能的实现方式中,在第一方面的又一种可能的实现方式中,所述晶振的基频信号还用于输出至所述多个第二连接器中的一个第二连接器。可以理解,将晶振的基频信号也作为一路输入,可以减少信号区分部件的压力,从而最大限度的压缩了信号区分部件的部署数量,有利于节省空间和成本。In combination with the first aspect, or any of the above possible implementations of the first aspect, in another possible implementation of the first aspect, the fundamental frequency signal of the crystal oscillator is also used to output to the multiple A second connector of the second connectors. It can be understood that using the fundamental frequency signal of the crystal oscillator as an input can reduce the pressure on the signal distinguishing components, thereby reducing the number of deployed signal distinguishing components to the greatest extent, which is beneficial to save space and cost.
结合第一方面,或者第一方面的上述任一种可能的实现方式中,在第一方面的又一种可能的实现方式中,所述信号区分部件包括D触发器,所述D触发器的D引脚连接了所述D触发器的引脚。通过这种连接方式,使得双D触发器能够实现分频功能,降低了设计的复杂度。In combination with the first aspect, or any of the above possible implementation manners of the first aspect, in yet another possible implementation manner of the first aspect, the signal distinguishing component includes a D flip-flop, and the D flip-flop The D pin is connected to the D flip-flop's pin. Through this connection mode, the double D flip-flop can realize the frequency division function, which reduces the complexity of the design.
结合第一方面,或者第一方面的上述任一种可能的实现方式中,在第一方面的又一种可能的实现方式中,所述D触发器具体为双D触发器,所述副板上具体部署有一个信号区分部件,所述一个信号区分部件为第一双D触发器,所述第一双D触发器1CP引脚用于接所述晶振的基频信号,所述第一双D触发器的1Q引脚输出的分频信号的一个支路用于输出至所述多个第二连接器中的一个第二连接器,所述第一双D触发器的1Q引脚输出的分频信号的另一个支路用于输出至所述第一双D触发器的2CP引脚,所述第一双D触发器的2Q引脚输出的分频信号用于输出至所述多个第二连接器中的一个第二连接器。In combination with the first aspect, or any of the above possible implementations of the first aspect, in yet another possible implementation of the first aspect, the D flip-flop is specifically a double D flip-flop, and the sub-board A signal distinguishing component is specifically deployed on the board, and the signal distinguishing component is a first dual D flip-flop, and the 1CP pin of the first dual D flip-flop is used to connect the fundamental frequency signal of the crystal oscillator, and the first dual D flip-flop A branch of the frequency division signal output by the 1Q pin of the D flip-flop is used to output to a second connector in the plurality of second connectors, and the output of the 1Q pin of the first double D flip-flop Another branch of the frequency division signal is used to output to the 2CP pin of the first double D flip-flop, and the frequency division signal output by the 2Q pin of the first double D flip-flop is used to output to the multiple A second connector of the second connectors.
结合第一方面,或者第一方面的上述任一种可能的实现方式中,在第一方面的又一种可能的实现方式中,所述D触发器具体为双D触发器,所述副板上具体部署有多个信号区分部件,所述多个信号区分部件具体为多个双D触发器,所述多个双D触发器包括第二双D触发器和第三双D触发器,所述第二双D触发器与所述第三双D触发器以级联的方式连接;In combination with the first aspect, or any of the above possible implementations of the first aspect, in yet another possible implementation of the first aspect, the D flip-flop is specifically a double D flip-flop, and the sub-board A plurality of signal distinguishing components are specifically deployed, and the plurality of signal distinguishing components are specifically a plurality of double-D flip-flops, and the plurality of double-D flip-flops include a second double-D flip-flop and a third double-D flip-flop, so The second double D flip-flop is connected in cascade with the third double D flip-flop;
所述第二双D触发器1CP引脚用于接所述晶振的基频信号,所述第二双D触发器的1Q引脚输出的分频信号的一个支路用于输出至所述多个第二连接器中的一个第二连接器,所述第二双D触发器的1Q引脚输出的分频信号的另一个支路用于输出至所述第二双D触发器的2CP引脚,所述第二双D触发器的2Q引脚输出的分频信号用于输出至所述多个第二连接器中的一个第二连接器;The 1CP pin of the second double D flip-flop is used to connect the base frequency signal of the crystal oscillator, and a branch of the frequency division signal output by the 1Q pin of the second double D flip-flop is used to output to the multiple One of the second connectors, the other branch of the frequency division signal output by the 1Q pin of the second double D flip-flop is used to output to the 2CP pin of the second double D flip-flop Pin, the frequency division signal output by the 2Q pin of the second double D flip-flop is used to output to a second connector in the plurality of second connectors;
所述第三双D触发器1CP引脚用于接所述第二双D触发器的2Q引脚,所述第三双D触发器的1Q引脚输出的分频信号的一个支路用于输出至所述多个第二连接器中的一个第二连接器,所述第三双D触发器的1Q引脚输出的分频信号的另一个支路用于输出至所述第三双D触发器的2CP引脚,所述第三双D触发器的2Q引脚输出的分频信号用于输出至所述多个第二连接器中的一个第二连接器。The 1CP pin of the third double D flip-flop is used to connect the 2Q pin of the second double D flip-flop, and a branch of the frequency division signal output by the 1Q pin of the third double D flip-flop is used for output to one of the plurality of second connectors, and another branch of the frequency division signal output by the 1Q pin of the third dual D flip-flop is used to output to the third dual D The 2CP pin of the flip-flop, the frequency division signal output by the 2Q pin of the third dual D flip-flop is used to output to one second connector among the plurality of second connectors.
可以理解,通过级联的方式可以分频出任意所需数量的不同频率的信号。It can be understood that any required number of signals with different frequencies can be divided by cascading.
结合第一方面,或者第一方面的上述任一种可能的实现方式中,在第一方面的又一种可能的实现方式中,所述电子装置还包括基板管理控制器BMC,所述CPLD还用于将所述线缆是否正确连接的检测结果上报给所述BMC,所述BMC用于输出提示信息,以提示所述主板与所述副板之间的线缆连接错误。可以理解,通过这种提示机制,可以让用户快速发现问题并及时补救,从而尽早纠正主板与副板之间线缆的错误连接。With reference to the first aspect, or any of the foregoing possible implementation manners of the first aspect, in yet another possible implementation manner of the first aspect, the electronic device further includes a baseboard management controller BMC, and the CPLD further It is used for reporting the detection result of whether the cable is connected correctly to the BMC, and the BMC is used for outputting prompt information to prompt that the cable connection between the main board and the sub-board is wrong. It can be understood that through this prompt mechanism, the user can quickly discover the problem and remedy it in time, so as to correct the wrong connection of the cable between the main board and the sub board as early as possible.
第二方面,本申请实施例提供一种副板,所述副板上配置有多个第二连接器,所述多个第二连接器与主板上的多个第一连接器一一对应,其中:In the second aspect, the embodiment of the present application provides a sub-board, the sub-board is configured with a plurality of second connectors, and the plurality of second connectors correspond to the plurality of first connectors on the main board one by one. in:
所述信号区分部件用于获得不同类型的信号,其中,所述类型包括频率和/或占空比;The signal distinguishing component is used to obtain different types of signals, wherein the types include frequency and/or duty cycle;
所述信号区分部件用于将所述不同类型的信号分别输出至所述多个第二连接器,其中,不同的第二连接器接入的信号的类型不同;The signal distinguishing component is configured to respectively output the signals of different types to the plurality of second connectors, wherein the types of signals connected to different second connectors are different;
所述多个第二连接器用于将信号通过线缆传输至所述主板的多个第一连接器。The plurality of second connectors are used to transmit signals to the plurality of first connectors of the motherboard through cables.
采用上述方法,通过在该副板上设置信号区分部件,能够划分出不同类型的分别与不同第二连接器对应的信号,而该主板上的CPLD可以基于不同第二连接器对应的信号类型确定出相应的第一连接器应该接收到的信号类型,该CPLD将每个第一连接器应该收到的信号的类型与该第一连接器实际收到的信号类型进行比较,如果两者不同则可以确定主板与副板之间连接的线缆属于错误连接,如果两者相同则可以确定主板与副板之间连接的线缆属于正确连接。基于这种思路,可以快速、准确地检测出线缆是否正确连接。Using the above method, by setting the signal distinguishing component on the sub-board, different types of signals corresponding to different second connectors can be divided, and the CPLD on the main board can be determined based on the signal types corresponding to different second connectors The signal type that should be received by the corresponding first connector, the CPLD compares the signal type that each first connector should receive with the signal type actually received by the first connector, if the two are different then It can be determined that the cable connected between the main board and the sub-board is a wrong connection, and if the two are the same, it can be determined that the cable connected between the main board and the sub-board is a correct connection. Based on this idea, it is possible to quickly and accurately detect whether the cable is connected correctly.
结合第二方面,在第二方面的一种可能的实现方式中,所述副板包括背板和/或Riser卡。With reference to the second aspect, in a possible implementation manner of the second aspect, the subboard includes a backplane and/or a riser card.
结合第二方面,或者第二方面的上述任一种可能的实现方式,在第二方面的又一种可能的实现方式中,所述类型具体为频率,所述副板还包括晶振;在获得不同类型的信号方面,所述信号区分部件具体用于对所述晶振的基频信号进行分频处理得到不同频率的信号。In combination with the second aspect, or any of the above-mentioned possible implementation manners of the second aspect, in another possible implementation manner of the second aspect, the type is specifically frequency, and the sub-board further includes a crystal oscillator; In terms of different types of signals, the signal distinguishing component is specifically configured to perform frequency division processing on the fundamental frequency signal of the crystal oscillator to obtain signals of different frequencies.
结合第二方面,或者第二方面的上述任一种可能的实现方式,在第二方面的又一种可能的实现方式中,所述晶振的基频信号还用于输出至所述多个第二连接器中的一个第二连接器。可以理解,将晶振的基频信号也作为一路输入,可以减少信号区分部件的压力,从而最大限度的压缩了信号区分部件的部署数量,有利于节省空间和成本。With reference to the second aspect, or any of the above possible implementation manners of the second aspect, in yet another possible implementation manner of the second aspect, the fundamental frequency signal of the crystal oscillator is also used to output to the multiple first A second connector of the two connectors. It can be understood that using the fundamental frequency signal of the crystal oscillator as an input can reduce the pressure on the signal distinguishing components, thereby reducing the number of deployed signal distinguishing components to the greatest extent, which is beneficial to save space and cost.
结合第二方面,或者第二方面的上述任一种可能的实现方式,在第二方面的又一种可能的实现方式中,所述信号区分部件包括D触发器,所述D触发器的D引脚连接了所述D触发器的引脚。通过这种连接方式,使得双D触发器能够实现分频功能,降低了设计的复杂度。With reference to the second aspect, or any of the above possible implementation manners of the second aspect, in yet another possible implementation manner of the second aspect, the signal distinguishing component includes a D flip-flop, and the D flip-flop of the D flip-flop pin connected to the D flip-flop's pin. Through this connection mode, the double D flip-flop can realize the frequency division function, which reduces the complexity of the design.
结合第二方面,或者第二方面的上述任一种可能的实现方式,在第二方面的又一种可能的实现方式中,所述D触发器具体为双D触发器,所述副板上具体部署有一个信号区分部件,所述一个信号区分部件为第一双D触发器,所述第一双D触发器1CP引脚用于接所述晶振的基频信号,所述第一双D触发器的1Q引脚输出的分频信号的一个支路用于输出至所述多个第二连接器中的一个第二连接器,所述第一双D触发器的1Q引脚输出的分频信号的另一个支路用于输出至所述第一双D触发器的2CP引脚,所述第一双D触发器的2Q引脚输出的分频信号用于输出至所述多个第二连接器中的一个第二连接器。With reference to the second aspect, or any of the above possible implementation manners of the second aspect, in yet another possible implementation manner of the second aspect, the D flip-flop is specifically a double D flip-flop, and the sub-board A signal distinguishing component is specifically deployed, and the signal distinguishing component is a first double D flip-flop, and the 1CP pin of the first double D flip-flop is used to connect the fundamental frequency signal of the crystal oscillator, and the first double D A branch of the frequency-division signal output by the 1Q pin of the flip-flop is used to output to a second connector in the plurality of second connectors, and the divided signal output by the 1Q pin of the first double D flip-flop The other branch of the frequency signal is used to output to the 2CP pin of the first double D flip-flop, and the frequency division signal output by the 2Q pin of the first double D flip-flop is used to output to the plurality of first A second connector of the two connectors.
结合第二方面,或者第二方面的上述任一种可能的实现方式,在第二方面的又一种可能的实现方式中,所述D触发器具体为双D触发器,所述副板上具体部署有多个信号区分部件,所述多个信号区分部件具体为多个双D触发器,所述多个双D触发器包括第二双D触发器和第三双D触发器,所述第二双D触发器与所述第三双D触发器以级联的方式连接;With reference to the second aspect, or any of the above possible implementation manners of the second aspect, in yet another possible implementation manner of the second aspect, the D flip-flop is specifically a double D flip-flop, and the sub-board A plurality of signal distinguishing components are specifically deployed, and the plurality of signal distinguishing components are specifically a plurality of double D flip-flops, and the plurality of double D flip-flops include a second double D flip-flop and a third double D flip-flop, the The second double D flip-flop is connected in cascade with the third double D flip-flop;
所述第二双D触发器1CP引脚用于接所述晶振的基频信号,所述第二双D触发器的1Q引脚输出的分频信号的一个支路用于输出至所述多个第二连接器中的一个第二连接器,所述第二双D触发器的1Q引脚输出的分频信号的另一个支路用于输出至所述第二双D触发器的2CP引脚,所述第二双D触发器的2Q引脚输出的分频信号用于输出至所述多个第二连接器中的一个第二连接器;The 1CP pin of the second double D flip-flop is used to connect the base frequency signal of the crystal oscillator, and a branch of the frequency division signal output by the 1Q pin of the second double D flip-flop is used to output to the multiple One of the second connectors, the other branch of the frequency division signal output by the 1Q pin of the second double D flip-flop is used to output to the 2CP pin of the second double D flip-flop Pin, the frequency division signal output by the 2Q pin of the second double D flip-flop is used to output to a second connector in the plurality of second connectors;
所述第三双D触发器1CP引脚用于接所述第二双D触发器的2Q引脚,所述第三双D触发器的1Q引脚输出的分频信号的一个支路用于输出至所述多个第二连接器中的一个第二连接器,所述第三双D触发器的1Q引脚输出的分频信号的另一个支路用于输出至所述第三双D触发器的2CP引脚,所述第三双D触发器的2Q引脚输出的分频信号用于输出至所述多个第二连接器中的一个第二连接器。The 1CP pin of the third double D flip-flop is used to connect the 2Q pin of the second double D flip-flop, and a branch of the frequency division signal output by the 1Q pin of the third double D flip-flop is used for output to one of the plurality of second connectors, and another branch of the frequency division signal output by the 1Q pin of the third dual D flip-flop is used to output to the third dual D The 2CP pin of the flip-flop, the frequency division signal output by the 2Q pin of the third dual D flip-flop is used to output to one second connector among the plurality of second connectors.
可以理解,通过级联的方式可以分频出任意所需数量的不同频率的信号。It can be understood that any required number of signals with different frequencies can be divided by cascading.
第三方面,本申请实施例提供一种线缆连接检测方法,应用于电子装置,所述电子装置包括主板和副板,所述主板上配置有多个第一连接器,所述副板上配置有多个第二连接器,所述多个第一连接器与所述多个第二连接器一一对应对应;所述主板上部署有复杂可编程逻辑器件CPLD,所述副板上部署有一个或多个信号区分部件,所述方法包括:In a third aspect, the embodiment of the present application provides a cable connection detection method, which is applied to an electronic device, and the electronic device includes a main board and a sub-board, the main board is configured with a plurality of first connectors, and the sub-board A plurality of second connectors are configured, and the plurality of first connectors are in one-to-one correspondence with the plurality of second connectors; a complex programmable logic device CPLD is deployed on the main board, and a complex programmable logic device CPLD is deployed on the sub-board. There are one or more signal distinguishing components, the method comprising:
通过所述信号区分部件获得不同类型的信号,所述类型包括频率和/或占空比所述不同类型的信号分别用于输出至所述多个第二连接器,不同的第二连接器接入的信号的类型不同;Different types of signals are obtained by the signal distinguishing component, and the types include frequency and/or duty cycle. The different types of signals are respectively used to be output to the plurality of second connectors, and different second connectors are connected to The type of incoming signal is different;
通过所述CPLD根据所述多个第一连接器中每个第一连接器的信号的类型,确定所述主板与所述副板之间的线缆是否正确连接。Whether the cable between the main board and the sub-board is correctly connected is determined by the CPLD according to the signal type of each first connector in the plurality of first connectors.
采用上述方法,通过在该副板上设置信号区分部件,能够划分出不同类型的分别与不同第二连接器对应的信号,而该主板上的CPLD可以基于不同第二连接器对应的信号类型确定出相应的第一连接器应该接收到的信号类型,该CPLD将每个第一连接器应该收到的信号的类型与该第一连接器实际收到的信号类型进行比较,如果两者不同则可以确定主板与副板之间连接的线缆属于错误连接,如果两者相同则可以确定主板与副板之间连接的线缆属于正确连接。基于这种思路,可以快速、准确地检测出线缆是否正确连接。Using the above method, by setting the signal distinguishing component on the sub-board, different types of signals corresponding to different second connectors can be divided, and the CPLD on the main board can be determined based on the signal types corresponding to different second connectors The signal type that should be received by the corresponding first connector, the CPLD compares the signal type that each first connector should receive with the signal type actually received by the first connector, if the two are different then It can be determined that the cable connected between the main board and the sub-board is a wrong connection, and if the two are the same, it can be determined that the cable connected between the main board and the sub-board is a correct connection. Based on this idea, it is possible to quickly and accurately detect whether the cable is connected correctly.
结合第三方面,或者第三方面的上述任一种可能的实现方式,在第三方面的又一种可能的实现方式中,所述多个第一连接器中每个第一连接器对应的第二连接器接入的信号的类型的情况设置在了所述CPLD中;若检测到所述第一连接器的信号的类型为目标类型,则所述第一连接器上连接到所述副板的线缆连接正确,其中,所述目标类型为所述第一连接器对应的第二连接器接入的信号的类型。With reference to the third aspect, or any of the above possible implementation manners of the third aspect, in yet another possible implementation manner of the third aspect, each of the multiple first connectors corresponds to The type of the signal connected to the second connector is set in the CPLD; if it is detected that the type of the signal of the first connector is the target type, then the first connector is connected to the secondary The cable connection of the board is correct, wherein the target type is the type of the signal connected to the second connector corresponding to the first connector.
结合第三方面,在第三方面的一种可能的实现方式中,所述副板包括背板和/或Riser卡。With reference to the third aspect, in a possible implementation manner of the third aspect, the subboard includes a backplane and/or a riser card.
结合第三方面,或者第三方面的上述任一种可能的实现方式,在第三方面的又一种可能的实现方式中,所述类型具体为频率,所述副板还包括晶振;在获得不同类型的信号方面,所述信号区分部件具体用于对所述晶振的基频信号进行分频处理得到不同频率的信号。In combination with the third aspect, or any of the above-mentioned possible implementation manners of the third aspect, in another possible implementation manner of the third aspect, the type is specifically frequency, and the sub-board further includes a crystal oscillator; In terms of different types of signals, the signal distinguishing component is specifically configured to perform frequency division processing on the fundamental frequency signal of the crystal oscillator to obtain signals of different frequencies.
结合第三方面,或者第三方面的上述任一种可能的实现方式,在第三方面的又一种可能的实现方式中,所述晶振的基频信号还用于输出至所述多个第二连接器中的一个第二连接器。可以理解,将晶振的基频信号也作为一路输入,可以减少信号区分部件的压力,从而最大限度的压缩了信号区分部件的部署数量,有利于节省空间和成本。With reference to the third aspect, or any of the above possible implementation manners of the third aspect, in yet another possible implementation manner of the third aspect, the fundamental frequency signal of the crystal oscillator is also used to output to the multiple first A second connector of the two connectors. It can be understood that using the fundamental frequency signal of the crystal oscillator as an input can reduce the pressure on the signal distinguishing components, thereby reducing the number of deployed signal distinguishing components to the greatest extent, which is beneficial to save space and cost.
结合第三方面,或者第三方面的上述任一种可能的实现方式,在第三方面的又一种可能的实现方式中,所述信号区分部件包括D触发器,所述D触发器的D引脚连接了所述D触发器的引脚。通过这种连接方式,使得双D触发器能够实现分频功能,降低了设计的复杂度。With reference to the third aspect, or any of the above possible implementation manners of the third aspect, in yet another possible implementation manner of the third aspect, the signal distinguishing component includes a D flip-flop, and the D of the D flip-flop pin connected to the D flip-flop's pin. Through this connection mode, the double D flip-flop can realize the frequency division function, which reduces the complexity of the design.
结合第三方面,或者第三方面的上述任一种可能的实现方式,在第三方面的又一种可能的实现方式中,所述D触发器具体为双D触发器,所述副板上具体部署有一个信号区分部件,所述一个信号区分部件为第一双D触发器,所述第一双D触发器1CP引脚用于接所述晶振的基频信号,所述第一双D触发器的1Q引脚输出的分频信号的一个支路用于输出至所述多个第二连接器中的一个第二连接器,所述第一双D触发器的1Q引脚输出的分频信号的另一个支路用于输出至所述第一双D触发器的2CP引脚,所述第一双D触发器的2Q引脚输出的分频信号用于输出至所述多个第二连接器中的一个第二连接器。With reference to the third aspect, or any of the above possible implementation manners of the third aspect, in another possible implementation manner of the third aspect, the D flip-flop is specifically a double D flip-flop, and the sub-board A signal distinguishing component is specifically deployed, and the signal distinguishing component is a first double D flip-flop, and the 1CP pin of the first double D flip-flop is used to connect the fundamental frequency signal of the crystal oscillator, and the first double D A branch of the frequency-division signal output by the 1Q pin of the flip-flop is used to output to a second connector in the plurality of second connectors, and the divided signal output by the 1Q pin of the first double D flip-flop The other branch of the frequency signal is used to output to the 2CP pin of the first double D flip-flop, and the frequency division signal output by the 2Q pin of the first double D flip-flop is used to output to the plurality of first A second connector of the two connectors.
结合第三方面,或者第三方面的上述任一种可能的实现方式,在第三方面的又一种可能的实现方式中,所述D触发器具体为双D触发器,所述副板上具体部署有多个信号区分部件,所述多个信号区分部件具体为多个双D触发器,所述多个双D触发器包括第二双D触发器和第三双D触发器,所述第二双D触发器与所述第三双D触发器以级联的方式连接;With reference to the third aspect, or any of the above possible implementation manners of the third aspect, in another possible implementation manner of the third aspect, the D flip-flop is specifically a double D flip-flop, and the sub-board A plurality of signal distinguishing components are specifically deployed, and the plurality of signal distinguishing components are specifically a plurality of double D flip-flops, and the plurality of double D flip-flops include a second double D flip-flop and a third double D flip-flop, the The second double D flip-flop is connected in cascade with the third double D flip-flop;
所述第二双D触发器1CP引脚用于接所述晶振的基频信号,所述第二双D触发器的1Q引脚输出的分频信号的一个支路用于输出至所述多个第二连接器中的一个第二连接器,所述第二双D触发器的1Q引脚输出的分频信号的另一个支路用于输出至所述第二双D触发器的2CP引脚,所述第二双D触发器的2Q引脚输出的分频信号用于输出至所述多个第二连接器中的一个第二连接器;The 1CP pin of the second double D flip-flop is used to connect the base frequency signal of the crystal oscillator, and a branch of the frequency division signal output by the 1Q pin of the second double D flip-flop is used to output to the multiple One of the second connectors, the other branch of the frequency division signal output by the 1Q pin of the second double D flip-flop is used to output to the 2CP pin of the second double D flip-flop Pin, the frequency division signal output by the 2Q pin of the second double D flip-flop is used to output to a second connector in the plurality of second connectors;
所述第三双D触发器1CP引脚用于接所述第二双D触发器的2Q引脚,所述第三双D触发器的1Q引脚输出的分频信号的一个支路用于输出至所述多个第二连接器中的一个第二连接器,所述第三双D触发器的1Q引脚输出的分频信号的另一个支路用于输出至所述第三双D触发器的2CP引脚,所述第三双D触发器的2Q引脚输出的分频信号用于输出至所述多个第二连接器中的一个第二连接器。The 1CP pin of the third double D flip-flop is used to connect the 2Q pin of the second double D flip-flop, and a branch of the frequency division signal output by the 1Q pin of the third double D flip-flop is used for output to one of the plurality of second connectors, and another branch of the frequency division signal output by the 1Q pin of the third dual D flip-flop is used to output to the third dual D The 2CP pin of the flip-flop, the frequency division signal output by the 2Q pin of the third dual D flip-flop is used to output to one second connector among the plurality of second connectors.
可以理解,通过级联的方式可以分频出任意所需数量的不同频率的信号。It can be understood that any required number of signals with different frequencies can be divided by cascading.
结合第三方面,或者第三方面的上述任一种可能的实现方式,在第三方面的又一种可能的实现方式中,所述电子装置还包括基板管理控制器BMC,所述CPLD还用于将所述线缆是否正确连接的检测结果上报给所述BMC,所述BMC用于输出提示信息,以提示所述主板与所述副板之间的线缆连接错误。With reference to the third aspect, or any of the foregoing possible implementation manners of the third aspect, in yet another possible implementation manner of the third aspect, the electronic device further includes a baseboard management controller BMC, and the CPLD also uses In order to report the detection result of whether the cable is connected correctly to the BMC, the BMC is used to output prompt information to prompt that the cable connection between the main board and the sub-board is wrong.
可以理解,通过这种提示机制,可以让用户快速发现问题并及时补救,从而尽早纠正主板与副板之间线缆的错误连接。It can be understood that through this prompt mechanism, the user can quickly discover the problem and remedy it in time, so as to correct the wrong connection of the cable between the main board and the sub board as early as possible.
第四方面,本申请实施例提供一种线缆连接检测方法,该方法应用于副板,所述副板上配置有多个第二连接器,所述多个第二连接器与主板上的多个第一连接器一一对应,其中:In a fourth aspect, the embodiment of the present application provides a cable connection detection method, the method is applied to the sub-board, the sub-board is configured with a plurality of second connectors, and the plurality of second connectors are connected to the main board. Multiple first connectors correspond one to one, wherein:
通过所述信号区分部件获得不同类型的信号,其中,所述类型包括频率和/或占空比;Obtaining different types of signals through the signal distinguishing component, wherein the types include frequency and/or duty cycle;
将所述不同类型的信号分别输出至所述多个第二连接器,其中,不同的第二连接器接入的信号的类型不同;Outputting the different types of signals to the plurality of second connectors respectively, wherein the types of signals connected to different second connectors are different;
通过所述多个第二连接器用于将信号经过线缆传输至所述主板的多个第一连接器。The plurality of second connectors are used to transmit signals to the plurality of first connectors of the motherboard through cables.
采用上述方法,通过在该副板上设置信号区分部件,能够划分出不同类型的分别与不同第二连接器对应的信号,而该主板上的CPLD可以基于不同第二连接器对应的信号类型确定出相应的第一连接器应该接收到的信号类型,该CPLD将每个第一连接器应该收到的信号的类型与该第一连接器实际收到的信号类型进行比较,如果两者不同则可以确定主板与副板之间连接的线缆属于错误连接,如果两者相同则可以确定主板与副板之间连接的线缆属于正确连接。基于这种思路,可以快速、准确地检测出线缆是否正确连接。Using the above method, by setting the signal distinguishing component on the sub-board, different types of signals corresponding to different second connectors can be divided, and the CPLD on the main board can be determined based on the signal types corresponding to different second connectors The signal type that should be received by the corresponding first connector, the CPLD compares the signal type that each first connector should receive with the signal type actually received by the first connector, if the two are different then It can be determined that the cable connected between the main board and the sub-board is a wrong connection, and if the two are the same, it can be determined that the cable connected between the main board and the sub-board is a correct connection. Based on this idea, it is possible to quickly and accurately detect whether the cable is connected correctly.
结合第四方面,在第四方面的一种可能的实现方式中,所述副板包括背板和/或Riser卡。With reference to the fourth aspect, in a possible implementation manner of the fourth aspect, the subboard includes a backplane and/or a riser card.
结合第四方面,或者第四方面的上述任一种可能的实现方式,在第四方面的又一种可能的实现方式中,所述类型具体为频率,所述副板还包括晶振;在获得不同类型的信号方面,所述信号区分部件具体用于对所述晶振的基频信号进行分频处理得到不同频率的信号。In combination with the fourth aspect, or any of the above-mentioned possible implementation manners of the fourth aspect, in another possible implementation manner of the fourth aspect, the type is specifically frequency, and the sub-board further includes a crystal oscillator; In terms of different types of signals, the signal distinguishing component is specifically configured to perform frequency division processing on the fundamental frequency signal of the crystal oscillator to obtain signals of different frequencies.
结合第四方面,或者第四方面的上述任一种可能的实现方式,在第四方面的又一种可能的实现方式中,所述晶振的基频信号还用于输出至所述多个第二连接器中的一个第二连接器。可以理解,将晶振的基频信号也作为一路输入,可以减少信号区分部件的压力,从而最大限度的压缩了信号区分部件的部署数量,有利于节省空间和成本。With reference to the fourth aspect, or any of the above possible implementation manners of the fourth aspect, in yet another possible implementation manner of the fourth aspect, the fundamental frequency signal of the crystal oscillator is also used to output to the multiple first A second connector of the two connectors. It can be understood that using the fundamental frequency signal of the crystal oscillator as an input can reduce the pressure on the signal distinguishing components, thereby reducing the number of deployed signal distinguishing components to the greatest extent, which is beneficial to save space and cost.
结合第四方面,或者第四方面的上述任一种可能的实现方式,在第四方面的又一种可能的实现方式中,所述信号区分部件包括D触发器,所述D触发器的D引脚连接了所述D触发器的引脚。通过这种连接方式,使得双D触发器能够实现分频功能,降低了设计的复杂度。With reference to the fourth aspect, or any of the above possible implementation manners of the fourth aspect, in yet another possible implementation manner of the fourth aspect, the signal distinguishing component includes a D flip-flop, and the D flip-flop of the D flip-flop pin connected to the D flip-flop's pin. Through this connection mode, the double D flip-flop can realize the frequency division function, which reduces the complexity of the design.
附图说明Description of drawings
以下对本申请实施例用到的附图进行介绍。The accompanying drawings used in the embodiments of the present application are introduced below.
图1是本申请实施例提供的一种电子装置的结构示意图;FIG. 1 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;
图2是本申请实施例提供的又一种电子装置的结构示意图;FIG. 2 is a schematic structural diagram of another electronic device provided by an embodiment of the present application;
图3是本申请实施例提供的一种线缆连接检测的方法流程图。Fig. 3 is a flow chart of a method for cable connection detection provided by an embodiment of the present application.
具体实施方式Detailed ways
下面结合本申请实施例中的附图对本申请实施例进行描述。Embodiments of the present application are described below with reference to the drawings in the embodiments of the present application.
请参见图1,图1是本申请实施例提供的一种电子装置10的结构示意图,该电子装置10包括主板11和副板12,所述主板11上配置有多个第一连接器110,所述副板上配置有多个第二连接器120,所述多个第一连接器110与所述多个第二连接器一一对应120;比如,假若主板11上依次有A1、B1、C1、D1共4个第一连接器,副板12上依次有A2、B2、C2、D2共4个第二连接器,其中,不同的第一连接器的接口规格可以相同也可以不同,不同的第二连接器的接口规格可以相同也可以不同。另外,第一连接器A1与第二连接器A2对应,第一连接器B1与第二连接器B2对应,第一连接器C1与第二连接器C2对应,第一连接器D1与第二连接器D2对应。需要说明的是,第一连接器A1与第二连接器A2对应具体是指A1是用来与A2通过线缆相连的,虽然在第一连接器A1与第一连接器B1的接口规格相同的情况下,B1也可以与A2通过线缆连接,但是由于B1与A2并未预先设置为对应关系,因此这种连接无法实现预期功能,总的来说,如果某个第一连接器与某个第二连接器并不对应,而该某个第一连接器和该某个第二连接器又通过线缆建立了连接,则认为该线缆连接错误,即只有相对应的第一连接器与第二连接器之间通过线缆建立连接才认为该线缆是正确连接。按照前面所举例子,第一连接器A1与非对应的第二连接器B2或C2之间连接线缆均为错误连接,第一连接器A1与对应的第二连接器A2之间连接线缆为正确连接,其余依次类推。Please refer to FIG. 1. FIG. 1 is a schematic structural diagram of an electronic device 10 provided by an embodiment of the present application. The electronic device 10 includes a main board 11 and a sub-board 12. The main board 11 is provided with a plurality of
具有对应关系的第一连接器110和第二连接器120图1中通过虚线进行了连接示意。The
所述主板11上部署有一个或多个复杂可编程逻辑器件(Complex programmablelogic device,CPLD)112;所述副板12上部署有一个或多个信号区分部件122。One or more complex programmable logic devices (Complex programmable logic devices, CPLDs) 112 are deployed on the main board 11 ; one or more
本申请实施例中,所述副板12上的信号区分部件用于获得不同类型的信号,其中,所述类型包括频率和/或占空比;所述信号区分部件还用于将所述不同类型的信号分别输出至所述多个第二连接器,其中,不同的第二连接器接入的信号的类型不同;比如,信号区分部件获得了类型1、类型2、类型3、类型4的信号,结合以上所举例子,类型1的信号用于输出至第二连接器A2、类型2的信号用于输出至第二连接器B2、类型3的信号用于输出至第二连接器C2、类型4的信号用于输出至第二连接器D2。In the embodiment of the present application, the signal distinguishing component on the sub-board 12 is used to obtain different types of signals, wherein the types include frequency and/or duty cycle; Types of signals are respectively output to the plurality of second connectors, wherein the types of signals connected to different second connectors are different; for example, the signal distinguishing component obtains the Signals, combined with the above example, the signal of
所述主板11上的所述CPLD用于根据所述多个第一连接器中每个第一连接器的信号的类型,确定所述主板与所述副板之间的线缆是否正确连接。需要说明的是,上述多个第二连接器中每个第二连接器接入的信号的类型在该CPLD中存储好了,例如以表1所示的形式存储。The CPLD on the main board 11 is used to determine whether the cable between the main board and the sub-board is properly connected according to the signal type of each first connector in the plurality of first connectors. It should be noted that, the type of signal connected to each second connector among the plurality of second connectors is stored in the CPLD, for example, in the form shown in Table 1.
表1Table 1
由于CPLD已经知道每个第一连接器对应的第二连接器是哪个,也知道每个第二连接器上的信号类型是哪种,因此,在线缆连接正确的情况下,每个第一连接器分别应该收到什么类型的信号也是可以确定的,因此,该CPLD根据该多个第一连接器中每个第一连接器应该接收到的信号的类型和实际接收的信号的类型,可确定主板与副板之间的线缆是否正确连接。Since the CPLD already knows which second connector each first connector corresponds to, and also knows what type of signal is on each second connector, therefore, when the cable is connected correctly, each first What types of signals should be received by the connectors can also be determined. Therefore, the CPLD can determine the type of signals that each first connector in the plurality of first connectors should receive and the type of signals actually received. Make sure the cables between the main board and the sub board are properly connected.
举例来说,若检测到所述第一连接器A1的信号的类型(即实际接收的信号的类型)为目标类型(即应该接收到的信号的类型),则所述第一连接器A1上连接到所述副板的线缆连接正确,其中,所述目标类型为所述第一连接器A2对应的第二连接器A2接入的信号的类型。For example, if it is detected that the type of the signal on the first connector A1 (that is, the type of the signal actually received) is the target type (that is, the type of the signal that should be received), then on the first connector A1 The cable connected to the sub-board is correctly connected, wherein the target type is the type of the signal connected to the second connector A2 corresponding to the first connector A2.
同理,若检测到所述第一连接器B1的信号的类型(即实际接收的信号的类型)为目标类型(即应该接收到的信号的类型),则所述第一连接器B1上连接到所述副板的线缆连接正确,其中,所述目标类型为所述第一连接器B2对应的第二连接器B2接入的信号的类型。Similarly, if it is detected that the type of the signal of the first connector B1 (that is, the type of the signal actually received) is the target type (that is, the type of the signal that should be received), then the connection on the first connector B1 The cable connection to the sub-board is correct, wherein the target type is the type of the signal connected to the second connector B2 corresponding to the first connector B2.
对其他第一连接器的信号的类型的判断可以依此类推。The determination of the signal types of other first connectors can be deduced in the same way.
可以理解,当确定出一组或多组对应的第一连接器和第二连接器之间的线缆连接错误,就可以确定该主板11与该副板12之间的线缆连接错误。It can be understood that when it is determined that one or more groups of corresponding first connectors and second connectors are connected incorrectly, it can be determined that the cable connections between the main board 11 and the sub-board 12 are incorrect.
本申请实施例中,该副板12可以为背板和/或Riser卡,可选的,该背板可以用于接硬盘等,该Riser卡是指插在高速串行计算机扩展总线标准(peripheral componentinterconnect express,PCI-Express)接口上的功能扩展卡或转接卡。当然,该背板还可以为其他类型的电路板,只要能够通过连接器和线缆与主板进行连接的电路板均可以,此处不做限定。In the embodiment of the present application, the
为了便于理解,下面以上述类型为频率为例进行举例说明。For ease of understanding, the following uses the above-mentioned type as an example for illustration.
可选的,在该类型为频率的情况下,上述副板12还可以包括晶振,在获得不同类型的信号方面,该信号区分部件具体用于对晶振的基频信号进行分频处理得到不同频率的信号。比如,该信号区分部件以该基频信号为输入,经过处理后输出多种其他频率的信号,比如,1/2基频信号、1/4基频信号、1/8基频信号等,输出的信号的频率可以比基频大也可以比基频小。Optionally, in the case where the type is frequency, the above-mentioned
可选的,所述晶振的基频信号还用于输出至所述多个第二连接器中的一个第二连接器。同样以上述例子来说明,该信号区分部件可以划分出1/2基频信号、1/4基频信号、1/8基频信号,这3个信号只能对应输入到第二连接器A2、第二连接器B2、第二连接器C2和第二连接器D2中的3个第二连接器,还有1个第二连接器是没有信号与之对应的,而如果将晶振的基频信号也作为1个输入,则刚好有4个信号与4个第二连接器对应,各个第二连接器可以分别接入不同频率的信号。Optionally, the fundamental frequency signal of the crystal oscillator is also used to be output to one of the plurality of second connectors. Also using the above example to illustrate, the signal distinguishing component can divide 1/2 base frequency signal, 1/4 base frequency signal, 1/8 base frequency signal, these 3 signals can only be input to the second connector A2, There are three second connectors among the second connector B2, the second connector C2 and the second connector D2, and there is one second connector that has no signal corresponding to it, and if the fundamental frequency signal of the crystal oscillator Also as one input, there are exactly 4 signals corresponding to 4 second connectors, and each second connector can respectively receive signals of different frequencies.
本申请实施例中,该信号区分部件可以为集成电路,或者芯片,比如,可以为CPLD,还可以为D触发器,比如单D触发器、双D触发器、三D触发器等等。当该信号区分部件为D触发器时,该D触发器的D引脚连接了所述D触发器的引脚。In the embodiment of the present application, the signal distinguishing component may be an integrated circuit or a chip, such as a CPLD, or a D flip-flop, such as a single D flip-flop, a double D flip-flop, a triple D flip-flop, and the like. When the signal distinguishing component is a D flip-flop, the D pin of the D flip-flop is connected to the D flip-flop pin.
为了便于理解,下面以该D触发器为74LVC74A(属于一种双D触发器)为例进行说明。In order to facilitate understanding, the D flip-flop is 74LVC74A (belonging to a double D flip-flop) as an example for illustration below.
案例1,如图2所示,所述副板12上具体部署有一个信号区分部件122,所述一个信号区分部件122为一个双D触发器,为了便于描述可以称为第一双D触发器,所述第一双D触发器1CP引脚用于接所述晶振123的基频信号,所述第一双D触发器的1Q引脚输出的分频信号(即1/2基频信号)的一个支路用于输出至所述多个第二连接器中的一个第二连接器,所述第一双D触发器的1Q引脚输出的分频信号的另一个支路用于输出至所述第一双D触发器的2CP引脚,也就是将第一双D触发器的1Q引脚输出的1/2基频信号作为第一双D触发器的2CP引脚的输入,所述第一双D触发器的2Q引脚输出的分频信号(即1/4基频信号)用于输出至所述多个第二连接器中的一个第二连接器。可以看出,基于一个双D触发器进行分频至少可以分出1个1/2基频信号、1个1/4基频信号,再加上晶振123原始的基频信号,总共至少有3种频率的信号,因此可以作为3个第二连接器的输入,比如分别作为第二连接器A2、B2、C2的输入。
案例2,所述副板上具体部署有多个信号区分部件,所述多个信号区分部件具体为多个双D触发器,该多个双D触发器可能为两个也可能不止两个,具体是多少个可以根据所需的不同频率信号的数量来设置,不管该多个双D触发器的具体是多少个双D触发器,下面均以其中包括的两个双D触发器为例进行介绍,为例便于描述,称这两个双D触发器为第二双D触发器和第三双D触发器,所述第二双D触发器与所述第三双D触发器以级联的方式连接。In
所述第二双D触发器1CP引脚用于接所述晶振的基频信号,所述第二双D触发器的1Q引脚输出的分频信号(即1/2基频信号)的一个支路用于输出至所述多个第二连接器中的一个第二连接器,所述第二双D触发器的1Q引脚输出的分频信号的另一个支路用于输出至所述第二双D触发器的2CP引脚,也就是将第二双D触发器的1Q引脚输出的1/2基频信号作为第二双D触发器的2CP引脚的输入,所述第二双D触发器的2Q引脚输出的分频信号(即1/4基频信号)用于输出至所述多个第二连接器中的一个第二连接器。The 1CP pin of the second double D flip-flop is used to connect the base frequency signal of the crystal oscillator, and one of the frequency division signals (
第三双D触发器1CP引脚用于接第二双D触发器的2Q引脚,也即是说,该第二双D触发器的2Q引脚输出的1/4基频信号还用于作为该第三双D触发器的1CP引脚的输入,第三双D触发器的1Q引脚输出的分频信号(即1/8分频信号)的一个支路用于输出至所述多个第二连接器中的一个第二连接器,第三双D触发器的1Q引脚输出的分频信号(即1/8分频信号)的另一个支路用于输出至第三双D触发器的2CP引脚,也就是将第三双D触发器的1Q引脚输出的1/8基频信号作为第三双D触发器的2CP引脚的输入,第三双D触发器的2Q引脚输出的分频信号(即1/16基频信号)用于输出至多个第二连接器中的一个第二连接器。The 1CP pin of the third double D flip-flop is used to connect the 2Q pin of the second double D flip-flop, that is to say, the 1/4 base frequency signal output by the 2Q pin of the second double D flip-flop is also used for As the input of the 1CP pin of the third double D flip-flop, a branch of the frequency division signal (ie 1/8 frequency division signal) output by the 1Q pin of the third double D flip-flop is used to output to the multiple One of the second connectors in the second connector, the other branch of the frequency division signal (that is, the 1/8 frequency division signal) output by the 1Q pin of the third double D flip-flop is used to output to the third double D The 2CP pin of the flip-flop, that is, the 1/8 base frequency signal output by the 1Q pin of the third double D flip-flop is used as the input of the 2CP pin of the third double D flip-flop, and the 2Q of the third double D flip-flop The frequency-divided signal (that is, the 1/16 base frequency signal) output by the pin is used to be output to a second connector among the plurality of second connectors.
可以看出,基于2个双D触发器进行分频至少可以分出1个1/2基频信号、1个1/4基频信号、1个1/8基频信号、1个1/16基频信号,再加上晶振原始的基频信号,总共至少有5种频率的信号,因此可以作为5个第二连接器的输入,如果双D触发器数量更多,那么能够提供的信号频率种类也更多,能够连接的第二连接器的数量也更多。It can be seen that the frequency division based on two double D flip-flops can at least separate a 1/2 base frequency signal, a 1/4 base frequency signal, a 1/8 base frequency signal, and a 1/16 base frequency signal. The base frequency signal, plus the original base frequency signal of the crystal oscillator, has a total of at least 5 kinds of frequency signals, so it can be used as the input of 5 second connectors. If there are more double D flip-flops, then the signal frequency that can be provided There are also more types, and the number of second connectors that can be connected is also larger.
当然,双D触发器除了可以具体为74LVC74A外,还可以是其他器件。Certainly, besides being 74LVC74A specifically, the double D flip-flop can also be other devices.
本申请实施例中,所述电子装置10还可以包括基板管理控制器(BaseboardManagement Controller,BMC)13,所述CPLD还用于将所述线缆是否正确连接的检测结果上报给BMC,该BMC从该CPLD获知所述主板与所述副板之间的线缆连接错误的情况下,BMC用于输出提示信息,以提示所述主板与所述副板之间的线缆连接错误,例如,该BMC通过文字、或者动画、或者语音、或者其他方式来向使用该电子装置的用户发出提示,以便用户可以获知所述主板与所述副板之间的线缆连接错误或者漏接。In the embodiment of the present application, the electronic device 10 may further include a Baseboard Management Controller (BMC) 13, and the CPLD is also used to report the detection result of whether the cable is connected correctly to the BMC, and the BMC receives from When the CPLD learns that the cable connection between the main board and the sub-board is wrong, the BMC is used to output prompt information to prompt that the cable connection between the main board and the sub-board is wrong, for example, the The BMC sends a prompt to the user using the electronic device through text, or animation, or voice, or other methods, so that the user can learn that the cable connection between the main board and the sub-board is wrong or missed.
可选的,如图3所示,图3示意了主板上的CPLD、副板上的双D触发器、晶振互相配合,检测主板与副板之间线缆连接与否的流程,总的来说,首先由晶振提供基础频率的信号,即基频信号,该基频信号作为双D触发器的输入,经过该双D触发器进行分频处理后输出一个或多个分频信号,该一个或多个分频信号经由双D触发器的第二连接器通过线缆输出至主板的第一连接器,而主板上的CPLD检测每个第一连接器的信号的频率,通过判断检测到的信号的频率(即实际信号频率)与预设信号的频率(即应该的信号频率)是否一致来确定是否通知BMC进行告警,若是一致(即线缆连接正确)则不通知BMC进行告警(表示为PASS),若一致(即线缆连接错误)则通知BMC进行告警。Optionally, as shown in Figure 3, Figure 3 shows the CPLD on the main board, the double D flip-flop on the sub-board, and the crystal oscillator cooperate with each other to detect whether the cable is connected between the main board and the sub-board. Said, firstly, the crystal oscillator provides the basic frequency signal, that is, the base frequency signal. The base frequency signal is used as the input of the double D flip-flop. After the double D flip-flop performs frequency division processing, it outputs one or more frequency division signals. The one or a plurality of frequency division signals are output to the first connector of the main board through the second connector of the double D flip-flop through the cable, and the CPLD on the main board detects the frequency of the signal of each first connector, and judges the detected Whether the frequency of the signal (that is, the actual signal frequency) is consistent with the frequency of the preset signal (that is, the expected signal frequency) determines whether to notify the BMC for an alarm, and if it is consistent (that is, the cable connection is correct), then the BMC is not notified for an alarm (expressed as PASS), if they are consistent (that is, the cable connection is wrong), the BMC will be notified to give an alarm.
本申请实施例中的电子装置可以为服务器、电脑、车载设备(例如,汽车、自行车、电动车、飞机、船舶等)、智能家居设备(例如,冰箱、电视、空调、电表等)、智能机器人、车间设备等电子设备,或者为该电子设备中的器件(或者说模块,或者说部件)。The electronic devices in the embodiments of the present application can be servers, computers, vehicle-mounted equipment (such as automobiles, bicycles, electric vehicles, airplanes, ships, etc.), smart home equipment (such as refrigerators, TVs, air conditioners, electric meters, etc.), intelligent robots , workshop equipment and other electronic equipment, or devices (or modules, or components) in the electronic equipment.
采用上述方法,通过在该副板上设置信号区分部件,能够划分出不同类型的分别与不同第二连接器对应的信号,而该主板上的CPLD可以基于不同第二连接器对应的信号类型确定出相应的第一连接器应该接收到的信号类型,该CPLD将每个第一连接器应该收到的信号的类型与该第一连接器实际收到的信号类型进行比较,如果两者不同则可以确定主板与副板之间连接的线缆属于错误连接,如果两者相同则可以确定主板与副板之间连接的线缆属于正确连接。基于这种思路,可以快速、准确地检测出线缆是否正确连接。Using the above method, by setting the signal distinguishing component on the sub-board, different types of signals corresponding to different second connectors can be divided, and the CPLD on the main board can be determined based on the signal types corresponding to different second connectors The signal type that should be received by the corresponding first connector, the CPLD compares the signal type that each first connector should receive with the signal type actually received by the first connector, if the two are different then It can be determined that the cable connected between the main board and the sub-board is a wrong connection, and if the two are the same, it can be determined that the cable connected between the main board and the sub-board is a correct connection. Based on this idea, it is possible to quickly and accurately detect whether the cable is connected correctly.
需要说明的是,当该信号区分部件为相比CPLD尺寸小的部件的情况下,该信号区分部件部署在副板上不需要占用太大空间,当该信号区分部件为相比CPLD成本更小的部件的情况下,在副板上部署该信号区分部件能够节省资金成本。尤其当该信号区分部件为D触发器时,能够显著减少部署所占用的空间,以及显著减小部署所需的资金成本。It should be noted that, when the signal distinguishing component is a component smaller in size than the CPLD, the signal distinguishing component does not need to occupy too much space when it is deployed on the sub-board, and when the signal distinguishing component is less expensive than the CPLD In the case of a single component, deploying the signal differentiation component on the sub-board can save capital costs. Especially when the signal distinguishing component is a D flip-flop, the space occupied by the deployment can be significantly reduced, and the capital cost required for the deployment can be significantly reduced.
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程,该流程可以由计算机程序来计算机程序相关的硬件完成,该计算机程序可存储于计算机可读取存储介质中,该计算机程序在执行时,可包括如上述各方法实施例的流程。而前述的存储介质包括:ROM或随机存储记忆体RAM、磁碟或者光盘等各种可存储计算机程序代码的介质。Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments are realized. The processes can be completed by computer programs or hardware related to the computer programs. The computer programs can be stored in computer-readable storage media. The computer programs During execution, it may include the processes of the foregoing method embodiments. The aforementioned storage medium includes: ROM or random access memory RAM, magnetic disk or optical disk, and other various media that can store computer program codes.
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