CN115754471A - Impedance test structure and design method thereof - Google Patents
Impedance test structure and design method thereof Download PDFInfo
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- CN115754471A CN115754471A CN202111026198.7A CN202111026198A CN115754471A CN 115754471 A CN115754471 A CN 115754471A CN 202111026198 A CN202111026198 A CN 202111026198A CN 115754471 A CN115754471 A CN 115754471A
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Abstract
The embodiment of the invention belongs to the technical field of printed circuit board design and manufacture, and particularly relates to an impedance test structure and a design method of the impedance test structure, which are used for solving the problem that manual test of a printed circuit board is time-consuming and labor-consuming in the related technology. The impedance test structure is provided with a plurality of circuit layers which are stacked, each circuit layer is provided with an impedance line, the impedance lines are located in the detection area of the circuit layer, and the impedance values of the two impedance lines in the adjacent circuit layers are unequal. When the impedance test structure is tested, the impedance tester is used for detecting the impedance of the detection area, different detection signals can be obtained according to different impedance values, and the detection efficiency is improved and the labor is saved by distinguishing the detection signals and waveforms to test whether the printed circuit board has layer dislocation.
Description
Technical Field
The embodiment of the invention relates to the technical field of printed circuit board design and manufacture, in particular to an impedance test structure and a design method of the impedance test structure.
Background
With the development of printed circuit board technology, multilayer printed circuit boards are used more and more. In manufacturing a printed circuit board structure, generally, a layer number label is etched on each circuit layer, and then the circuit layers are sequentially stacked and pressed to form a multi-layer printed circuit board. In the related art, the number of layers of each circuit layer is usually manually compared to test whether the printed circuit board has layer misalignment. However, this method of using manual testing is time consuming and labor intensive.
Disclosure of Invention
The embodiment of the invention provides an impedance test structure and a design method of the impedance test structure, which are used for solving the problems of time and labor waste caused by manual testing of a printed circuit board in the related technology.
In a first aspect, an embodiment of the present invention provides an impedance testing structure, which includes a plurality of stacked circuit layers, each circuit layer is provided with an impedance line, the impedance line is located in a detection area of the circuit layer, and impedance values of two impedance lines in adjacent circuit layers are not equal to each other.
In one possible implementation, the impedance value of each of the impedance lines is different from the impedance values of the other impedance lines.
In one possible implementation, a plurality of signal holes are included, the signal holes penetrate through the circuit layer, and any impedance line is located between two adjacent signal holes, so that the impedance lines are connected in series.
In a possible implementation manner, the signal connector further comprises a ground hole, and a preset distance is reserved between the ground hole and the signal hole.
In one possible implementation, a plurality of the signal holes are arrayed on the impedance testing structure.
In a second aspect, an embodiment of the present invention further provides a method for designing an impedance test structure, including:
designing the length and the width of an impedance test structure, wherein the impedance test structure is provided with a plurality of circuit layers which are arranged in a stacked mode;
designing a signal hole in the impedance test structure, wherein the signal hole penetrates through the circuit layer to form a detection area for detecting impedance;
designing impedance lines in each circuit layer so that the impedance lines are located in the detection area, and the impedance values of the two impedance lines in the adjacent circuit layers are not equal;
and designing a grounding hole in the impedance test structure.
In one possible implementation, designing an impedance line in each of the circuit layers includes: the impedance value of each impedance line is different from the impedance values of the other impedance lines.
In one possible implementation manner, each of the impedance lines has a different line width and line length, so that the impedance value of each of the impedance lines is different from the impedance values of the other impedance lines.
In one possible implementation, any of the impedance lines is designed to be located between two adjacent signal holes so that the impedance lines are connected in series.
In one possible implementation, designing a signal hole in the impedance testing structure includes: and designing a plurality of signal holes to be arrayed in the impedance test structure.
The embodiment of the invention provides an impedance test structure and a design method of the impedance test structure. When testing the impedance test structure, use the impedance tester to carry out impedance detection to the detection area, because different impedance value can obtain different detected signal, thereby test printed circuit board whether take place the layer and do not misplace the phenomenon through distinguishing detected signal, improved detection efficiency, use manpower sparingly.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a first schematic structural diagram of an impedance testing structure according to an embodiment of the present invention;
FIG. 2 isbase:Sub>A cross-sectional view A-A of the impedance testing structure of FIG. 1;
FIG. 3 isbase:Sub>A cross-sectional view A-A of the impedance test structure of FIG. 1;
FIG. 4 is a second schematic structural diagram of an impedance testing structure according to an embodiment of the present invention;
fig. 5 is a flowchart of a method for designing an impedance test structure according to an embodiment of the present invention.
Description of reference numerals:
10. an impedance test structure; 101. a first circuit layer; 102. a second circuit layer; 103. a third circuit layer; 104. a fourth circuit layer; 105. a fifth circuit layer;
11. a signal aperture; 111. a first signal aperture; 112. a second signal aperture; 113. a third signal aperture; 114. a fourth signal aperture; 115. a fifth signal aperture;
12. a ground hole;
13. positioning holes;
14. an impedance line; 141. a first impedance line; 142. a second impedance line; 143. a third impedance line; 144. a fourth impedance line; 145. a fifth impedance line; 146. a sixth impedance line.
Detailed Description
With the development of printed circuit board technology, multilayer printed circuit boards are used more and more. In the manufacture of printed circuit board structures, generally, a layer number is etched on each circuit layer, and the circuit layers are sequentially stacked and pressed to form a multi-layer printed circuit board. In the related art, the number of layers of each circuit layer is usually manually compared to test whether the printed circuit board has layer misalignment. However, this method of using manual testing is time consuming and labor intensive.
In view of this, an embodiment of the present invention provides an impedance testing structure and a design method of the impedance testing structure, where the impedance testing structure has a plurality of circuit layers stacked one on another, each circuit layer is provided with an impedance line, the impedance lines are located in a detection area of the circuit layer, and impedance values of two impedance lines in adjacent circuit layers are not equal. When testing the impedance test structure, use the impedance tester to carry out impedance detection to the detection area, because different impedance value can obtain different detected signal, thereby test printed circuit board whether take place the layer and do not misplace the phenomenon through distinguishing detected signal, improved detection efficiency, use manpower sparingly.
While several alternative implementations of the invention will be described in conjunction with the appended drawings, it should be understood by those skilled in the art that the following implementations are illustrative only and not exhaustive, and that certain features or certain examples may be substituted, combined, or combined by those skilled in the art based on these implementations and still be considered a disclosure of the invention.
Referring to fig. 1, 2 and 3, an impedance testing structure 10 provided by the embodiment of the present invention is located at a production patterning edge of a circuit board, and specifically includes a plurality of circuit layers stacked one on another. It should be noted that the number of the circuit layers in the impedance testing structure 10 is the same as the number of the circuit layers in the circuit board, so that the circuit board and the impedance testing structure 10 are formed by a synchronous process in the subsequent production process.
Illustratively, each circuit layer is provided with an impedance line 14, and the impedance line 14 is located in the detection area of the circuit layer. In this embodiment, the impedance testing structure 10 has a testing plane, the testing plane is a side surface of the outermost circuit layer away from the adjacent circuit layer, and the detection area is located in the testing plane, so that the impedance tester can perform a testing operation in the detection area in the testing plane, so as to test the impedance values of the impedance lines 14 in the plurality of circuit layers.
It should be noted that the impedance tester is a tester that inputs a current signal to a structure to be tested and determines an impedance value by detecting a response signal of the input signal. In this embodiment, after the current signal is input to the impedance line 14, a corresponding TDR (Time Domain reflector) waveform curve may be obtained, and the impedance value of the impedance line 14 may be determined according to the TDR waveform curve. In particular, impedance testers typically include test probes, through which the impedance tester is typically connected to the structure under test.
In a possible implementation manner, a plurality of through conductive holes may be disposed on the circuit layer, the center lines of the conductive holes are perpendicular to the plane of the circuit layer, so that the two ends of the impedance line 14 are respectively connected to the conductive holes, the plurality of conductive holes may form a detection area of the circuit layer, and the impedance value of the impedance line 14 between the conductive holes may be detected by contacting the impedance tester with the conductive holes.
In another possible implementation manner, a set of conductive leads may be disposed on the surface of each circuit layer, so that two ends of the impedance line 14 are connected to the conductive leads, respectively, and the other ends of the conductive leads may be exposed in the testing plane of the impedance testing structure 10. The conductive leads exposed in the test plane of the impedance test structure 10 may form a detection area of the circuit layer, and the impedance value of the impedance lines 14 between the conductive holes may be detected by contacting the impedance tester with the conductive leads.
In this embodiment, the impedance values of the two impedance lines 14 in the adjacent circuit layers are not equal, so that when the impedance is detected by the impedance tester, whether the layer-level dislocation phenomenon occurs in the adjacent circuit layer can be determined according to the impedance values of the adjacent circuit layers, and whether the layer-level dislocation phenomenon occurs in the printed circuit board can be determined.
The embodiment of the invention provides an impedance test structure 10, which comprises a plurality of stacked circuit layers, wherein each circuit layer is provided with an impedance line 14, the impedance lines 14 are positioned in a detection area of the circuit layer, and the impedance values of the two impedance lines 14 in the adjacent circuit layers are unequal. When the impedance test structure 10 is tested, the impedance tester is used for detecting the impedance of the detection area, different detection signals can be obtained due to different impedance values, and the detection efficiency is improved and the labor is saved by distinguishing the detection signals and waveforms to test whether the printed circuit board has layer dislocation.
Further, the impedance test structure 10 can also determine whether the line impedance of the circuit board is qualified by testing the impedance value of the impedance line 14, so as to realize quality control and detection of the manufacturing process of the circuit board, and further improve the yield of products. In the related art, an impedance test strip for implementing line impedance quality control is also generally provided. Compared with the impedance test strip in the related art, the impedance test structure 10 in the embodiment can realize quality control of line impedance in the circuit board, and can also realize detection of whether the circuit board has layer dislocation, thereby improving the integration of the impedance test structure 10.
Optionally, the impedance value of each impedance line 14 is different from the impedance values of the other impedance lines 14, so that each impedance line 14 has a different impedance value, and accordingly, when the impedance tester is used to test the impedance lines 14, each impedance line 14 can obtain a different TDR curve, which is beneficial to further judging whether the layer-level dislocation phenomenon occurs in the circuit layer corresponding to the impedance line 14.
Illustratively, the impedance value of the impedance line 14 may be set by setting the line length and the line width of the impedance line 14. For example, each of the impedance lines 14 may be provided with a different line width or line length so that the impedance value of each of the impedance lines 14 is different from the impedance values of the other impedance lines 14. It should be noted that the line length and the line width of the impedance line 14 are also set according to the equipment capability of the impedance tester. For example, when the line length of the measurement impedance line 14 of the impedance tester ranges from 0.1inch to 1inch, the line length of the impedance line 14 may be set to 0.1inch, 0.5inch, or 1inch.
In this embodiment, in addition to the line length and the line width of the impedance line 14, the impedance value of the impedance line 14 may be set by setting the material of the circuit layer.
Furthermore, the impedance value of the impedance line 14 can be set to test the impedance of different lines in the circuit board, so that the test capability of the impedance test structure 10 is improved, and the test requirements of different products are met.
Optionally, the impedance testing structure 10 further includes a plurality of signal holes 11, the signal holes 11 are disposed through the circuit layer, and any impedance line 14 is located between two adjacent signal holes 11, so that all the impedance lines 14 are connected in series. As shown in fig. 2 and 3, each circuit layer is provided with one impedance line 14, and two ends of the impedance line 14 are respectively connected to two adjacent signal holes 11. The inner wall of the signal hole 11 has a conductive layer so that the impedance line 14 located in a different circuit layer can be electrically connected through the signal hole 11, and the conductive layer may be made of a metal such as copper, for example.
In one possible implementation, the series arrangement of the impedance lines 14 may be a step-like arrangement. Illustratively, with continued reference to FIG. 2, the impedance testing structure 10 is shown to include a first circuit layer 101, a second circuit layer 102, a third circuit layer 103, a fourth circuit layer 104, and a fifth circuit layer 105, which are sequentially stacked, wherein the first circuit layer 101 is at the topmost level in the illustrated position. Accordingly, one resistance line 14 is provided for each circuit layer. A first signal hole 111, a second signal hole 112, a third signal hole 113, a fourth signal hole 114 and a fifth signal hole 115 are sequentially arranged along the extending direction of the impedance testing structure 10, wherein the first signal hole 111 is located at the left end of the position shown in the figure. One end of the first resistance line 141 on the first circuit layer 101 is connected to the first signal hole 111; one end of the second impedance line 142 on the second circuit layer 102 is connected to the first signal hole 111, and the other end is connected to the second signal hole 112; the impedance lines 14 of the circuit layers of other layers are arranged according to the above rule to form a series connection manner in which the impedance lines 14 are arranged in a ladder shape, which is not described herein again.
In another possible implementation manner, the series arrangement of the impedance lines 14 may also be concave-convex. Illustratively, referring to FIG. 3, the impedance testing structure 10 is shown as in FIG. 2, except for the arrangement of the impedance lines 14. One end of the first resistance line 141 on the first circuit layer 101 is connected to the first signal hole 111; one end of the second impedance line 142 on the second circuit layer 102 is connected to the fifth signal hole 115, and the other end is connected to the fourth signal hole 114; one end of the third impedance line 143 on the third circuit layer 103 is connected to the third signal hole 113, and the other end is connected to the fourth signal hole 114; one end of the fourth impedance line 144 on the fourth circuit layer 104 is connected to the first signal hole 111, and the other end is connected to the second signal hole 112; the fifth resistance line 145 on the fifth circuit layer 105 has one end connected to the third signal via 113 and the other end connected to the second signal via 112. By the above connection method, a series connection method in which the impedance lines 14 are arranged in a concave-convex shape is formed.
The process of testing the impedance testing structure 10 using the impedance tester is briefly described below by taking fig. 2 as an example. For example, when the test probe contacts the third signal hole 113, since the impedance line 14 is connected in series, the impedance tester may apply the same current signal to the first impedance line 141, the second impedance line 142, and the third impedance line 143, and since the signal hole 11 also has a certain impedance, the obtained TDR curve includes two curves with significant fluctuation, and the two curves with significant fluctuation respectively correspond to the impedance of the first signal hole 111 and the impedance of the second signal hole 112, and further the TDR curve can be sequentially divided into a first line segment, a second line segment, and a third line segment, which respectively correspond to the impedance of the first impedance line 141, the impedance of the second impedance line 142, and the impedance of the third impedance line 143, so that whether the layer-level-dislocation phenomenon occurs between the first impedance line 141, the second impedance line 142, and the third impedance line 143 can be determined, and whether the line impedance of the circuit board is qualified can be determined.
It should be noted that when the test probe contacts the third signal hole 113, the third circuit layer 103 is a reference layer in the impedance test structure 10, and metal copper needs to be laid on the surface of the third circuit layer 103 to shield the impedance line 14 of other circuit layers.
Optionally, the impedance testing structure 10 further includes a ground hole 12, and a predetermined distance is provided between the ground hole 12 and the signal hole 11. Illustratively, a ground hole 12 is disposed through the impedance testing structure 10, one end of the ground hole 12 is exposed in the testing plane, and the other end of the ground hole 12 is connected to the shielding layer of the circuit board. The preset distance is reserved between the grounding hole 12 and the signal hole 11 so as to adapt to the distance between the test probes of the impedance tester, and further when the impedance tester tests the impedance, one of the test probes is connected with the grounding hole 12, and the other test probe is in contact with the signal hole 11.
Taking fig. 1 as an example, one ground hole 12 may be disposed at one side of the first signal hole 111, and a predetermined distance may be provided between the ground hole 12 and the first signal hole 111. Of course, in some other examples, a plurality of ground holes 12 may be provided, one ground hole 12 is corresponding to one side of each signal hole 11, and a preset distance is provided between a ground hole 12 and its corresponding signal hole 11.
Optionally, the plurality of impedance lines 14 are arranged in an array on the impedance testing structure 10, so that on the premise of not increasing the length of the impedance testing structure 10, the plurality of signal holes 11 are further arranged on the impedance testing structure 10, and the integration of the impedance testing structure 10 is improved. As shown in fig. 4, two rows of signal holes 11 are disposed on the impedance testing structure 10, and each row of signal holes 11 includes 5 signal holes 11 spaced apart along the extending direction of the impedance testing structure 10. Correspondingly, the impedance test structure 10 shown in fig. 4 includes 11 circuit layers arranged in a stacked manner, each circuit layer is provided with one impedance line 14, and the projection of the impedance line 14 on the impedance test structure 10 is a zigzag shape, so that the impedance lines 14 are connected in series.
With continued reference to fig. 1 and 4, the impedance testing structure 10 is further provided with positioning holes 13, and the positioning holes 13 are used to prevent the impedance testing structure 10 from moving during testing. During testing, after the positioning holes 13 are aligned with the matching holes on the fixture for fixing the impedance testing structure 10, the probes are inserted to fix the impedance testing structure 10 on the fixture.
The embodiment of the present invention further provides a design method of the impedance test structure 10, which is used for designing the impedance test structure 10 in the above embodiment. The testing principle of the over-impedance tester has been briefly described above, and is not described in detail in this embodiment.
As shown in fig. 5, the method for designing the impedance testing structure 10 provided in this embodiment includes the following steps:
step S101, designing the length and the width of an impedance test structure, wherein the impedance test structure is provided with a plurality of circuit layers which are arranged in a stacked mode.
Illustratively, the length and width of the impedance testing structure 10 are designed according to the process capability of manufacturing circuit board equipment and the equipment capability of the impedance tester. The process capability of the circuit board may include, for example, the hole diameter of the drilled hole, the line width and the line length of the etched line. The device capabilities of the impedance tester may include, for example, the spacing between test probes, the line length and line width of the impedance line 14 that can be measured, and the like.
It should be noted that the number of the circuit layers is the same as that of the circuit layers in the circuit board, so that the circuit board and the impedance testing structure 10 are formed by a synchronous process in the subsequent production process.
And S102, designing a signal hole in the impedance test structure, wherein the signal hole penetrates through the circuit layer to form a detection area for detecting impedance.
Illustratively, the impedance testing structure 10 includes a plurality of signal holes 11, and the plurality of signal holes 11 may form a detection area for detecting impedance. The inner wall of the signal hole 11 has a conductive layer so that the impedance line 14 located in a different circuit layer can be electrically connected through the signal hole 11, and the conductive layer may be made of a metal such as copper, for example.
Step S103, designing an impedance line in each circuit layer, so that the impedance line is located in the detection area, and the impedance values of two impedance lines in adjacent circuit layers are not equal.
In this embodiment, the impedance values of the two impedance lines 14 in the adjacent circuit layers are not equal, so that when the impedance tester detects the impedance, whether the layer-by-layer dislocation phenomenon occurs in the adjacent circuit layer can be determined according to the impedance values of the adjacent circuit layers, and whether the layer-by-layer dislocation phenomenon occurs in the printed circuit board can be determined.
And step S104, designing a grounding hole in the impedance test structure.
Illustratively, a ground hole 12 is disposed through the impedance testing structure 10, one end of the ground hole 12 is exposed in the testing plane, and the other end of the ground hole 12 is connected to the shielding layer of the circuit board. The preset distance is reserved between the grounding hole 12 and the signal hole 11 so as to adapt to the distance between the test probes of the impedance tester, and when the impedance tester tests the impedance, one test probe is connected with the grounding hole 12, and the other test probe is contacted with the signal hole 11.
The design method of the impedance test structure 10 provided by the embodiment of the invention comprises the steps of designing the length and the width of the impedance test structure 10, wherein the impedance test structure 10 is provided with a plurality of circuit layers which are arranged in a stacking mode; designing a signal hole 11 in the impedance test structure 10, wherein the signal hole 11 penetrates through the circuit layer to form a detection area for detecting impedance; designing an impedance line 14 in each circuit layer, so that the impedance line 14 is located in the detection area, and the impedance values of the two impedance lines 14 in the adjacent circuit layers are not equal; a ground hole 12 is designed into the impedance test structure 10. When testing the impedance test structure 10 designed by this embodiment, the impedance tester is used to perform impedance detection on the detection area, and different detection signals can be obtained by different impedance values, so that whether layer dislocation occurs in the printed circuit board is tested by distinguishing the detection signals and waveforms, thereby improving the detection efficiency and saving manpower.
Further, the impedance test structure 10 designed in this embodiment can also determine whether the line impedance of the circuit board is qualified by testing the impedance value of the impedance line 14, thereby implementing quality control and detection in the manufacturing process of the circuit board, and further improving the yield of products. In the related art, an impedance test strip for implementing line impedance quality control is also generally provided. Compared with the impedance test strip in the related art, the impedance test structure 10 designed in this embodiment can realize quality control of the line impedance in the circuit board, and can also realize detection of whether the circuit board has layer dislocation, thereby improving the integration of the impedance test structure 10.
In this embodiment, the step of designing the impedance line 14 in each circuit layer includes: the impedance value of each impedance line 14 is different from the impedance values of the other impedance lines 14, so that each impedance line 14 has a different impedance value, and accordingly, when the impedance tester is used for testing the impedance lines 14, each impedance line 14 can obtain different TDR curves, which is beneficial to further judging whether the layer-level dislocation phenomenon occurs in the circuit layer corresponding to the impedance line 14.
Alternatively, each of the impedance lines 14 may have a different line width and line length, so that the impedance value of each of the impedance lines 14 is different from the impedance values of the other impedance lines 14. For example, each of the impedance lines 14 may be provided with a different line width or line length so that the impedance value of each of the impedance lines 14 is different from the impedance values of the other impedance lines 14. It should be noted that the line length and the line width of the impedance line 14 are also set according to the equipment capability of the impedance tester. For example, when the line length of the measurement impedance line 14 of the impedance tester ranges from 0.1inch to 1inch, the line length of the impedance line 14 may be set to 0.1inch, 0.5inch, or 1inch.
In this embodiment, in addition to the line length and the line width of the impedance line 14, the impedance value of the impedance line 14 may be set by setting the material of the circuit layer.
Furthermore, the impedance value of the impedance line 14 can be set to test the impedance of different lines in the circuit board, so that the test capability of the impedance test structure 10 is improved, and the test requirements of different products are met.
In this embodiment, any impedance line 14 is designed to be located between two adjacent signal holes 11, so that the impedance lines 14 are connected in series.
In one possible implementation, the series arrangement of the impedance lines 14 may be a step-like arrangement. Illustratively, referring to fig. 2, the impedance testing structure 10 shown therein includes a first circuit layer 101, a second circuit layer 102, a third circuit layer 103, a fourth circuit layer 104, a fifth circuit layer 105 and a sixth circuit layer, which are sequentially stacked, wherein the first circuit layer 101 is located at the topmost layer in the illustrated position. Accordingly, one resistance line 14 is provided for each circuit layer. A first signal hole 111, a second signal hole 112, a third signal hole 113, a fourth signal hole 114 and a fifth signal hole 115 are sequentially arranged along the extending direction of the impedance testing structure 10, wherein the first signal hole 111 is located at the left end of the position shown in the figure. One end of the first resistance line 141 on the first circuit layer 101 is connected to the first signal hole 111; one end of the second impedance line 142 on the second circuit layer 102 is connected to the first signal hole 111, and the other end is connected to the second signal hole 112; the impedance lines 14 of the circuit layers of other layers are arranged according to the above rule to form a series connection manner in which the impedance lines 14 are arranged in a ladder shape, which is not described herein again.
In another possible implementation manner, the arrangement of the impedance lines 14 in series may also be concave-convex. Illustratively, referring to FIG. 3, the impedance testing structure 10 is shown as in FIG. 2, except for the arrangement of the impedance lines 14. One end of the first resistance line 141 on the first circuit layer 101 is connected to the first signal hole 111; one end of the second impedance line 142 on the second circuit layer 102 is connected to the fifth signal hole 115, and the other end is connected to the fourth signal hole 114; one end of the third impedance line 143 on the third circuit layer 103 is connected to the third signal hole 113, and the other end is connected to the fourth signal hole 114; one end of the fourth impedance line 144 on the fourth circuit layer 104 is connected to the first signal hole 111, and the other end is connected to the second signal hole 112; the fifth resistance line 145 on the fifth circuit layer 105 has one end connected to the third signal hole 113 and the other end connected to the second signal hole 112. By the above connection method, a series connection method in which the impedance lines 14 are arranged in a concave-convex shape is formed.
Of course, the two arrangements shown in fig. 2 and 3 are merely examples, and the impedance lines 14 may be arranged in series.
The process of testing the impedance testing structure 10 using the impedance tester is briefly described below by taking fig. 2 as an example. For example, when the test probe contacts the third signal hole 113, since the impedance line 14 is connected in series, the impedance tester may apply the same current signal to the first impedance line 141, the second impedance line 142, and the third impedance line 143, and since the signal hole 11 also has a certain impedance, the obtained TDR curve includes two curves with significant fluctuation, and the two curves with significant fluctuation respectively correspond to the impedance of the first signal hole 111 and the impedance of the second signal hole 112, and further the TDR curve can be sequentially divided into a first line segment, a second line segment, and a third line segment, which respectively correspond to the impedance of the first impedance line 141, the impedance of the second impedance line 142, and the impedance of the third impedance line 143, so that whether the layer-level-dislocation phenomenon occurs between the first impedance line 141, the second impedance line 142, and the third impedance line 143 can be determined, and whether the line impedance of the circuit board is qualified can be determined.
It should be noted that, when the test probe contacts the third signal hole 113, the third circuit layer 103 is a reference layer in the impedance test structure 10, and a metal copper layer needs to be designed on the surface of the third circuit layer 103 to shield the impedance line 14 of other circuit layers.
In this embodiment, the step of designing the signal hole 11 in the impedance testing structure 10 further includes: a plurality of signal holes 11 are designed to be arranged in an array in the impedance testing structure 10, so that on the premise of not increasing the length of the impedance testing structure 10, the plurality of signal holes 11 are further arranged on the impedance testing structure 10, and the integration of the impedance testing structure 10 is improved. As shown in fig. 4, two rows of signal holes 11 are disposed on the impedance testing structure 10, and each row of signal holes 11 includes 5 signal holes 11 spaced apart along the extending direction of the impedance testing structure 10. Correspondingly, the impedance test structure 10 shown in fig. 4 includes 11 circuit layers arranged in a stacked manner, each circuit layer is provided with one impedance line 14, and the projection of the impedance line 14 on the impedance test structure 10 is a zigzag shape, so that the impedance lines 14 are connected in series.
In the description of the embodiments of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicate orientations or positional relationships based on those shown in the drawings, and are used merely for convenience of description and for simplicity of description, but do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be considered as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the embodiments of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the embodiments of the present invention, unless otherwise explicitly specified or limited, the terms "mounted," "connected," "fixed," and the like are to be construed broadly, e.g., as being fixedly connected, detachably connected, or integrated; they may be directly connected or indirectly connected through intervening media, or they may be interconnected within two elements or in a relationship where two elements interact with each other unless otherwise specifically limited. The specific meanings of the above terms in the present invention can be understood according to specific situations by those of ordinary skill in the art.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. The impedance test structure is characterized by comprising a plurality of stacked circuit layers, wherein each circuit layer is provided with an impedance line, the impedance lines are positioned in a detection area of the circuit layer, and the impedance values of two adjacent impedance lines in the circuit layers are unequal.
2. The impedance test structure of claim 1, wherein each of the impedance lines has an impedance value that is different from the impedance values of the other impedance lines.
3. The impedance testing structure according to claim 2, comprising a plurality of signal holes extending through the circuit layer, any of the impedance lines being located between two adjacent signal holes so that the impedance lines are connected in series.
4. The impedance testing structure of claim 3, further comprising a ground via having a predetermined distance from the signal via.
5. The impedance test structure of claim 3, wherein a plurality of the signal vias are arrayed on the impedance test structure.
6. A method of designing an impedance test structure, comprising:
designing the length and the width of an impedance test structure, wherein the impedance test structure is provided with a plurality of circuit layers which are arranged in a stacked mode;
designing a signal hole in the impedance test structure, wherein the signal hole penetrates through the circuit layer to form a detection area for detecting impedance;
designing impedance lines in each circuit layer so that the impedance lines are located in the detection area, and the impedance values of the two impedance lines in the adjacent circuit layers are not equal;
and designing a grounding hole in the impedance test structure.
7. The method of designing an impedance testing structure according to claim 6, wherein designing an impedance line in each of the circuit layers comprises: the impedance value of each impedance line is different from the impedance values of the other impedance lines.
8. The method for designing an impedance test structure according to claim 7, wherein each of the impedance lines has a different line width and a different line length, so that the impedance value of each of the impedance lines is different from the impedance values of the other impedance lines.
9. The method of claim 8, wherein any of the impedance lines is designed to be located between two adjacent signal holes so that the impedance lines are connected in series.
10. The method of designing an impedance test structure according to any one of claims 6 to 9, wherein designing a signal hole in the impedance test structure comprises: and designing a plurality of signal holes to be arranged in an array in the impedance test structure.
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